MAX9867_10 [MAXIM]
Ultra-Low Power Stereo Audio Codec; 超低功耗立体声音频编解码器
| 型号： | MAX9867_10 |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Ultra-Low Power Stereo Audio Codec |
| 文件： | 总55页 (文件大小：789K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-4573; Rev 1; 5/10
Ultra-Low Power Stereo Audio Codec
MAX9867
General Description
The MAX9867 is an ultra-low power stereo audio codec
designed for portable consumer devices such as
mobile phones and portable gaming consoles.
Features
o 1.8V Single-Supply Operation
o 6.7mW Playback Power Consumption
o 90dB Stereo DAC, 8kHz ≤ fs ≤ 48kHz
o 85dB Stereo ADC, 8kHz ≤ fs ≤ 48kHz
o Battery-Measurement Auxiliary ADC
The device features stereo differential microphone inputs
that can be connected to either analog or digital micro-
phones. The single-ended line inputs, with configurable
preamplifier, can be sent to the ADC for record or routed
directly to the headphone amplifier for playback. An aux-
iliary ADC path can be used to track any DC voltage.
o Support for Any Master Clock Between 10MHz to
60MHz
o Stereo Digital Microphone Input Support
The stereo headphone amplifiers support differential,
single-ended, and capacitorless output configurations.
Using the capacitorless output configuration, the
device can output 10mW into 32Ω headphones.
Comprehensive click-and-pop circuitry suppresses
audible clicks and pops during volume changes and
startup or shutdown.
o Stereo Analog Differential Microphone Inputs
o Stereo Headphone Amplifiers: Differential,
Single-Ended, or Capacitorless
o Stereo Line Inputs
o Voiceband Filter with a Stopband Attenuation
Greater than 70dB
Utilizing Maxim’s proprietary digital circuitry, the device
can accept any available 10MHz to 60MHz system
clock. This architecture eliminates the need for an
external PLL and multiple crystal oscillators. The stereo
ADC and DAC paths provide user-configurable voice-
band or audioband digital filters. Voiceband filters pro-
vide extra attenuation at the GSM packet frequency
o 1.65V to 3.6V Digital Interface Supply Voltage
o I2S/TDM-Compatible Digital Audio Bus
o 30-Bump, 2.2mm x 2.7mm 0.4mm-Pitch WLP
Applications
Cell Phones
and greater than 70dB stopband attenuation at f
.
S/2
Portable Gaming Devices
Portable Navigation Devices
Portable Multimedia Players
Wireless Headsets
The MAX9867 operates from a single 1.8V supply, and
2
supports a 1.65V to 3.6V logic level. An I C 2-wire seri-
al interface provides control for volume levels, signal
mixing, and general operating modes.
Ordering Information
The MAX9867 is available in a tiny 2.2mm x 2.7mm,
0.4mm-ball-pitch, WLP package. A 32-pin 5mm x 5mm
TQFN package is also available.
PART
TEMP RANGE
-40°C to +85°C
-40°C to +85°C
PIN-PACKAGE
MAX9867EWV+
MAX9867ETJ+
30 WLP
32 TQFN-EP*
+Denotes lead(Pb)-free/RoHS-compliant package.
*EP = Exposed pad.
Simplified Block Diagram
2
2
I S/PCM
I C
CONTROL
INTERFACE
LEFT MIC AMP
DIGITAL AUDIO INTERFACE
MAX9867
DIGITAL MICROPHONE
ADC
ADC
DAC
DAC
MIX
INTERFACE
HEADPHONE
AMP
AUDIO DIGITAL
FILTERS
RIGHT MIC AMP
MIX
LEFT PREAMP
LINEIN 1
RIGHT PREAMP
HEADPHONE
AMP
LINEIN 2
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
Ultra-Low Power Stereo Audio Codec
ABSOLUTE MAXIMUM RATINGS
(Voltages with respect to AGND.)
Continuous Power Dissipation (T = +70°C)
A
DVDD, AVDD, and PVDD.........................................-0.3V to +2V
DVDDIO.................................................................-0.3V to +3.6V
DGND and PGND..................................................-0.1V to +0.1V
PREG, REF, REG, MICBIAS ....................-0.3V to (AVDD + 0.3V)
MCLK, LRCLK, BCLK
SDOUT, SDIN .................................-0.3V to (DVDDIO + 0.3V)
SDA, SCL, IRQ ......................................................-0.3V to +3.6V
LOUTP, LOUTN, ROUTP,
30-Bump WLP (derate 12.5mW/°C above +70°C)....1000mW
32-Pin TQFN-EP (derate 34.5mW/°C above +70°C).2759mW
Junction-to-Ambient Thermal Resistance (θ ) (Note 1)
JA
30-Bump WLP .............................................................80°C/W
32-Pin TQFN-EP ..........................................................29°C/W
Operating Temp Range.......................................-40°C to +85°C
Storage Temp Range ........................................-65°C to +150°C
Lead Temperature (TQFN only, 10s) ...............................+300°C
Soldering Temperature (reflow) .......................................+260°C
MAX9867
ROUTN.................................(PGND - 0.3V) to (PVDD + 0.3V)
LINL, LINR, JACKSNS/AUX, MICLP/DIGMICDATA,
MICLN/DIGMICCLK, MICRP, MICRN..-0.3V to (AVDD + 0.3V)
Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-
layer board. For detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V
= V
REF
= V
= 2.2µF, C
= V
MICBIAS
= +1.8V, R = ∞, headphone load (R ) connected between _OUTP and _OUTN in differential
AVDD
PVDD
DVDD
DVDDIO
= C
L
L
mode, C
= C
= 1µF, AV
= +20dB, AV
= 0dB, AV
= 0dB, AV
= +20dB, AV
=
PREG
REG
PRE
PGAM
DAC
LINE
VOL
0dB, MCLK = 13MHz, T = T
to T
, unless otherwise noted. Typical values are at T = +25°C.) (Note 2)
MAX A
A
MIN
PARAMETER
SYMBOL
CONDITIONS
PVDD, DVDD, AVDD
MIN
1.65
1.65
TYP
MAX
1.95
3.6
UNITS
1.8
1.8
Supply Voltage Range
V
DVDDIO
Analog (AVDD +
PVDD)
4.65
0.96
3.28
1.40
8.0
7
1.5
5
Full-duplex 8kHz
mono (voice mode)
(Note 3)
Digital (DVDD +
DVDDIO)
Analog (AVDD +
PVDD)
DAC playback 48kHz
stereo (audio mode)
(Note 3)
Digital (DVDD +
DVDDIO)
2
Total Supply Current
I
mA
VDD
Analog (AVDD +
PVDD)
12
3
Full-duplex 48kHz
stereo (audio mode)
(Note 3)
Digital (DVDD +
DVDDIO)
2.0
Analog (AVDD +
PVDD)
3.8
6
Stereo line-in only
Digital (DVDD +
DVDDIO)
0.004
1
0.05
5
Analog (AVDD +
PVDD)
Shutdown Supply Current
T
= +25°C
µA
A
Digital (DVDD +
DVDDIO)
1
5
2
_______________________________________________________________________________________
Ultra-Low Power Stereo Audio Codec
MAX9867
ELECTRICAL CHARACTERISTICS (continued)
(V
= V
REF
= V
= 2.2µF, C
= V
MICBIAS
= +1.8V, R = ∞, headphone load (R ) connected between _OUTP and _OUTN in differential
AVDD
PVDD
DVDD
DVDDIO
= C
L
L
mode, C
= C
= 1µF, AV
= +20dB, AV
= 0dB, AV
= 0dB, AV
= +20dB, AV
=
PREG
REG
PRE
PGAM
DAC
LINE
VOL
0dB, MCLK = 13MHz, T = T
to T
, unless otherwise noted. Typical values are at T = +25°C.) (Note 2)
MAX A
A
MIN
PARAMETER
Shutdown to Full Operation
Soft-Start/-Stop Time
DAC (Note 4)
SYMBOL
CONDITIONS
Excludes PLL lock time
MIN
TYP
MAX
UNITS
ms
10
10
ms
Master or slave
mode
90
f = 48kHz, AV
=
S
VOL
Dynamic Range (Note 5)
Full-Scale Output
DR
dB
0dB, T = +25°C
A
Slave mode
84
Differential mode
1
V
/V
= 0x09
V
OLL OLR
RMS
%
Capacitorless and
single-ended modes
0.56
DC accuracy, measured with respect to
full-scale output
Gain Error
1
5
f = 1kHz, 0dBFS, HP
filter disabled, digital
input to analog output
f = 8kHz
1.2
S
Voice Path Phase Delay
P
ms
dB
DLY
f = 16kHz
S
0.59
MCLK = 12.288MHz, f = 48kHz, 0dBFS,
S
measured at headphone outputs
Total Harmonic Distortion
THD
-80
DAC Attenuation Range
DAC Gain Adjust
AV
DACA = 0xF to 0x0
DACG = 00 to 11
-15
0
0
dB
dB
DAC
AV
+18
GAIN
V
= V
= 1.65V to 1.95V
PVDD
60
78
78
AVDD
f = 217Hz, V
AV
= 100mV
,
RIPPLE
P-P
= 0dB
VOL
Power-Supply Rejection Ratio
PSRR
dB
f = 1kHz, V
= 100mV
,
RIPPLE
P-P
75
62
AV
= 0dB
VOL
f = 10kHz, V
= 100mV
P-P
,
RIPPLE
AV
= 0dB
VOL
DAC VOICE MODE DIGITAL IIR LOWPASS FILTER
With respect to f within ripple; f = 8kHz to
0.448 x
S
S
48kHz
f
S
Passband Cutoff
f
f
Hz
PLP
SLP
0.451 x
-3dB cutoff
f
S
Passband Ripple
Stopband Cutoff
f < f
0.1
dB
Hz
dB
PLP
0.476 x
With respect to f ; f = 8kHz to 48kHz
S
S
f
S
Stopband Attenuation
f > f
, f = 20Hz to 20kHz
75
SLP
_______________________________________________________________________________________
3
Ultra-Low Power Stereo Audio Codec
ELECTRICAL CHARACTERISTICS (continued)
(V
= V
REF
= V
= 2.2µF, C
= V
MICBIAS
= +1.8V, R = ∞, headphone load (R ) connected between _OUTP and _OUTN in differential
AVDD
PVDD
DVDD
DVDDIO
= C
L
L
mode, C
= C
= 1µF, AV
= +20dB, AV
= 0dB, AV
= 0dB, AV
= +20dB, AV
=
PREG
REG
PRE
PGAM
DAC
LINE
VOL
0dB, MCLK = 13MHz, T = T
to T
, unless otherwise noted. Typical values are at T = +25°C.) (Note 2)
MAX A
A
MIN
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DAC VOICE MODE DIGITAL 5th ORDER IIR HIGHPASS FILTER
DVFLT = 0x1
(elliptical tuned for 16kHz GSM + 217Hz
notch)
0.0161
x f
MAX9867
S
DVFLT = 0x2
(500Hz Butterworth tuned for 16kHz)
0.0312
x f
S
5th Order Passband Cutoff
(-3dB from Peak, I2C Register
Programmable)
DVFLT = 0x3
(elliptical tuned for 8kHz GSM + 217Hz
notch)
f
Hz
DHPPB
0.0321
x f
S
DVFLT = 0x4
(500Hz Butterworth tuned for 8kHz)
0.0625
x f
S
DVFLT = 0x5
(f /240 Butterworth)
S
0.0042
x f
S
DVFLT = 0x1
(elliptical tuned for 16kHz GSM + 217Hz
notch)
0.0139
x f
S
DVFLT = 0x2
(500Hz Butterworth tuned for 16kHz)
0.0156
x f
S
5th Order Stopband Cutoff
(-30dB from Peak, I2C Register
Programmable)
DVFLT = 0x3
(elliptical tuned for 8kHz GSM + 217Hz
notch)
f
Hz
DHPSB
0.0279
x f
S
DVFLT = 0x4
(500Hz Butterworth tuned for 8kHz)
0.0312
x f
S
DVFLT = 0x5
(f /240 Butterworth)
S
0.0021
x f
S
DC Attenuation
DC
DVFLT ≠ 000
90
dB
Hz
ATTEN
DAC STEREO AUDIO MODE DIGITAL FIR LOWPASS FILTER
With respect to f within ripple;
f = 8kHz to 48kHz
S
0.43 x
f
S
S
0.47 x
Passband Cutoff
f
f
-3dB cutoff
PLP
SLP
f
S
0.50 x
-6.02dB cutoff
f
S
Passband Ripple
Stopband Cutoff
f < f
0.1
dB
Hz
dB
PLP
0.58 x
With respect to f ; f = 8kHz to 48kHz
S
S
f
S
Stopband Attenuation
60
4
_______________________________________________________________________________________
Ultra-Low Power Stereo Audio Codec
MAX9867
ELECTRICAL CHARACTERISTICS (continued)
(V
= V
REF
= V
= 2.2µF, C
= V
MICBIAS
= +1.8V, R = ∞, headphone load (R ) connected between _OUTP and _OUTN in differential
AVDD
PVDD
DVDD
DVDDIO
= C
L
L
mode, C
= C
= 1µF, AV
= +20dB, AV
= 0dB, AV
= 0dB, AV
= +20dB, AV
=
PREG
REG
PRE
PGAM
DAC
LINE
VOL
0dB, MCLK = 13MHz, T = T
to T
, unless otherwise noted. Typical values are at T = +25°C.) (Note 2)
MAX A
A
MIN
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DAC STEREO AUDIO MODE DIGITAL DC BLOCKING HIGHPASS FILTER
Passband Cutoff
(-3dB from Peak)
0.000625
x f
f
DVFLT = 0x1
DVFLT = 0x1
Hz
dB
DHPPB
S
DC Attenuation
DC
90
ATTEN
ADC (Note 6)
f = 8kHz, MODE = 0 (IIR voice)
75
84
85
S
Dynamic Range (Note 5)
Full-Scale Input
DR
dB
f = 8kHz to 48kHz, MODE = 1 (FIR audio)
S
Differential MIC input or stereo-line inputs,
1
1
V
P-P
AV
= 0dB, AV
= 0dB
PRE
PGAM
DC accuracy, measured with respect to
80% of full-scale output
Gain Error (Note 7)
5
%
f = 1kHz, 0dBFS, HP
f = 8kHz
1.2
S
filter disabled,
analog input to
digital output
Voice Path Phase Delay
P
ms
DLY
f = 16kHz
S
0.61
-81
Total Harmonic Distortion
ADC Level Adjust Range
THD
AV
f = 1kHz, f = 8kHz, T = +25°C, 0dBFS
-70
+3
dB
dB
S
A
AVL/AVR = 0xF to 0x0
= 1.65V to 1.95V, input referred
-12
60
ADC
V
85
85
AVDD
f = 217Hz, V
= 100mV, AV
= 0dB,
RIPPLE
ADC
input referred
Power-Supply Rejection Ratio
PSRR
dB
f = 1kHz, V
input referred
= 100mV, AV
= 0dB,
RIPPLE
ADC
80
80
f = 10kHz, V
= 100mV, AV
= 0dB,
RIPPLE
ADC
input referred
ADC VOICE MODE DIGITAL IIR LOWPASS FILTER
With respect to f within ripple;
0.445 x
S
f = 8kHz to 48kHz
S
f
S
Passband Cutoff
f
Hz
PLP
0.449 x
-3dB cutoff
f
S
Passband Ripple
Stopband Cutoff
f < f
0.1
dB
Hz
dB
PLP
0.469 x
f
With respect to f ; f = 8kHz to 48kHz
SLP
S
S
f
S
Stopband Attenuation
f > f
, f = 20Hz to 20kHz
74
SLP
_______________________________________________________________________________________
5
Ultra-Low Power Stereo Audio Codec
ELECTRICAL CHARACTERISTICS (continued)
(V
= V
REF
= V
= 2.2µF, C
= V
MICBIAS
= +1.8V, R = ∞, headphone load (R ) connected between _OUTP and _OUTN in differential
AVDD
PVDD
DVDD
DVDDIO
= C
L
L
mode, C
= C
= 1µF, AV
= +20dB, AV
= 0dB, AV
= 0dB, AV
= +20dB, AV
=
PREG
REG
PRE
PGAM
DAC
LINE
VOL
0dB, MCLK = 13MHz, T = T
to T
, unless otherwise noted. Typical values are at T = +25°C.) (Note 2)
MAX A
A
MIN
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
ADC VOICE MODE DIGITAL 5th ORDER IIR HIGHPASS FILTER
AVFLT = 0x1
(elliptical tuned for 16kHz GSM + 217Hz
notch)
0.0161
x f
MAX9867
S
AVFLT = 0x2
(500Hz Butterworth tuned for 16kHz)
0.0312
x f
S
5th Order Passband Cutoff
(-3dB from Peak, I2C Register
Programmable)
AVFLT = 0x3
(elliptical tuned for 8kHz GSM + 217Hz
notch)
f
Hz
AHPPB
0.0321
x f
S
AVFLT = 0x4
(500Hz Butterworth tuned for 8kHz)
0.0625
x f
S
AVFLT = 0x5
(f /240 Butterworth)
S
0.0042
x f
S
AVFLT = 0x1
(elliptical tuned for 16kHz GSM + 217Hz
notch)
0.0139
x f
S
AVFLT = 0x2
(500Hz Butterworth tuned for 16kHz)
0.0156
x f
S
Stopband Cutoff (-30dB from
Peak)
AVFLT = 0x3
(elliptical tuned for 8kHz GSM + 217Hz
notch)
f
Hz
AHPSB
0.0279
x f
S
AVFLT = 0x4
(500Hz Butterworth tuned for 8kHz)
0.0312
x f
S
AVFLT = 0x5
(f /240 Butterworth)
S
0.0021
x f
S
DC Attenuation
DC
AVFLT ≠ 000
90
dB
Hz
ATTEN
ADC STEREO AUDIO MODE DIGITAL FIR LOWPASS FILTER
With respect to f within ripple;
f = 8kHz to 48kHz
S
0.43 x
f
S
S
Passband Cutoff
f
f
PLP
SLP
0.48 x
-3dB cutoff
f
S
-6.02dB cutoff
0.5 x f
0.1
S
Passband Ripple
Stopband Cutoff
f < f
dB
Hz
dB
PLP
0.58 x
With respect to f ; f = 8kHz to 48kHz
S
S
f
S
Stopband Attenuation
f > f , f = 20Hz to 20kHz
SLP
60
6
_______________________________________________________________________________________
Ultra-Low Power Stereo Audio Codec
MAX9867
ELECTRICAL CHARACTERISTICS (continued)
(V
= V
REF
= V
= 2.2µF, C
= V
MICBIAS
= +1.8V, R = ∞, headphone load (R ) connected between _OUTP and _OUTN in differential
AVDD
PVDD
DVDD
DVDDIO
= C
L
L
mode, C
= C
= 1µF, AV
= +20dB, AV
= 0dB, AV
= 0dB, AV
= +20dB, AV
=
PREG
REG
PRE
PGAM
DAC
LINE
VOL
0dB, MCLK = 13MHz, T = T
to T
, unless otherwise noted. Typical values are at T = +25°C.) (Note 2)
MAX A
A
MIN
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
ADC STEREO AUDIO MODE DIGITAL DC BLOCKING HIGHPASS FILTER
Passband Cutoff
(-3dB from Peak)
0.000625
x f
f
AVFLT = 0x1
AVFLT = 0x1
Hz
dB
AHPPB
S
DC Attenuation
DC
90
ATTEN
OUTPUT VOLUME CONTROL
VOLL/VOLR = 0x00
VOLL/VOLR = 0x01
VOLL/VOLR = 0x02
VOLL/VOLR = 0x04
VOLL/VOLR = 0x08
VOLL/VOLR = 0x10
VOLL/VOLR = 0x20
14.55
14.1
14.9
14.4
13.9
12.9
9.9
15.15
14.6
13.6
14.1
Line Input to Output Volume
Control
AV
12.6
13.1
dB
VOL
9.35
10.35
1.35
0.35
0.9
-50.15
-49.2
-48.15
VOLL/VOLR = 0x00 to 0x06 (+6dB to +3dB)
VOLL/VOLR = 0x06 to 0x0F (+3dB to -6dB)
VOLL/VOLR = 0x0F to 0x17 (-6dB to -22dB)
VOLL/VOLR = 0x17 to 0x3F (-22dB to mute)
0.5
1
Output Volume Control Step Size
dB
dB
2
4
Output Volume Control Mute
Attenuation
f = 1kHz
100
HEADPHONE AMPLIFIER (Note 8)
R = 16Ω
30
8
52
32
19
10
-76
L
Output Power per Channel
(Differential Mode)
f = 1kHz, THD <
1%, T = +25°C
A
P
P
mW
mW
OUT
OUT
R = 32Ω
L
R = 16Ω
L
Output Power per Channel
(Capacitorless Mode)
f = 1kHz, THD <
1%, T = +25°C
A
R = 32Ω
L
R = 16Ω, P
= 25mW, f = 1kHz
L
OUT
MCLK = 13MHz,
f = 8kHz
S
Total Harmonic Distortion + Noise
(Differential Mode)
-77
-70
-65
-65
THD+N
THD+N
dB
dB
R = 32Ω, P
25mW, f = 1kHz
=
L
OUT
MCLK = 12.288MHz,
f = 48kHz
S
-80
-72
-74
R = 16Ω, P
= 6.25mW, f = 1kHz
L
OUT
MCLK = 13MHz,
f = 8kHz
S
Total Harmonic Distortion + Noise
(Capacitorless Mode)
R = 32Ω, P
=
L
OUT
6.25mW, f = 1kHz
MCLK = 12.288MHz,
f = 48kHz
S
-74
-74
-74
R = 16Ω, P
= 6.25mW, f = 1kHz
L
OUT
MCLK = 13MHz,
f = 8kHz
S
Total Harmonic Distortion + Noise
(SE Mode)
THD+N
DR
dB
dB
R = 32Ω, P
=
L
OUT
6.25mW, f = 1kHz
MCLK = 12.288MHz,
f = 48kHz
S
-76
90
Dynamic Range
AV
= +6dB (Notes 5, 7)
76
VOL
_______________________________________________________________________________________
7
Ultra-Low Power Stereo Audio Codec
ELECTRICAL CHARACTERISTICS (continued)
(V
= V
REF
= V
= 2.2µF, C
= V
MICBIAS
= +1.8V, R = ∞, headphone load (R ) connected between _OUTP and _OUTN in differential
AVDD
PVDD
DVDD
DVDDIO
= C
L
L
mode, C
= C
= 1µF, AV
= +20dB, AV
= 0dB, AV
= 0dB, AV
= +20dB, AV
=
PREG
REG
PRE
PGAM
DAC
LINE
VOL
0dB, MCLK = 13MHz, T = T
to T
, unless otherwise noted. Typical values are at T = +25°C.) (Note 2)
MAX A
A
MIN
PARAMETER
SYMBOL
CONDITIONS
= 1.65V to 1.95V
PVDD
MIN
TYP
MAX
UNITS
V
= V
60
78
AVDD
f = 217Hz, V
= 100mV
,
RIPPLE
P-P
78
AV
= 0dB
MAX9867
VOL
Power-Supply Rejection Ratio
(Note 7)
PSRR
dB
f = 1kHz, V
= 100mV
,
RIPPLE
P-P
75
62
AV
= 0dB
VOL
f = 10kHz, V
= 100mV
P-P
,
RIPPLE
AV
= 0dB
VOL
(LOUTP–LOUTN,
ROUTP–ROUTN),
AV
= -84dB
VOL
0.2
0.8
differential mode
T
A
= +25°C
Output Offset Voltage
V
mV
dB
OS
AV = -84dB
(LOUTP–LOUTN,
ROUTP–LOUTN),
VOL
capacitorless
mode
T
A
= +25°C
Differential mode, P
= 5mW, f = 1kHz
87
55
OUT
Capacitorless
mode,
TQFN
WLP
R = 32Ω
Crosstalk
X
TALK
P
= 5mW,
OUT
60
f = 1kHz
500
100
L
No sustained
oscillations
Capacitive Drive
pF
R = ∞
L
Peak voltage,
A-weighted, 32
samples per
second
Into shutdown
Out of shutdown
Into shutdown
Out of shutdown
-80
-69
-75
-75
Click-and-Pop Level
(Differential, Capacitorless
Modes)
dBV
Peak voltage,
A-weighted, 32
samples per
second
Click-and-Pop Level
(SE Mode)
dBV
MICROPHONE AMPLIFIER
PALEN/PAREN = 01
PALEN/PAREN = 10
PALEN/PAREN = 11
-0.5
19.5
29.5
-0.6
19.3
0
20
+0.5
20.5
30.5
+0.4
20.3
Preamplifier Gain
AV
dB
dB
PRE
30
PGAML/PGAMR = 0x1F
PGAML/PGAMR = 0x00
-0.1
19.75
50
MIC PGA Gain
AV
PGAM
Common-Mode Rejection Ratio
MIC Input Resistance
CMRR
V
= 100mV , f = 217Hz
dB
IN
P-P
R
All gain settings
30
50
kΩ
IN_MIC
8
_______________________________________________________________________________________
Ultra-Low Power Stereo Audio Codec
MAX9867
ELECTRICAL CHARACTERISTICS (continued)
(V
= V
REF
= V
= 2.2µF, C
= V
MICBIAS
= +1.8V, R = ∞, headphone load (R ) connected between _OUTP and _OUTN in differential
AVDD
PVDD
DVDD
DVDDIO
= C
L
L
mode, C
= C
= 1µF, AV
= +20dB, AV
= 0dB, AV
= 0dB, AV
= +20dB, AV
=
PREG
REG
PRE
PGAM
DAC
LINE
VOL
0dB, MCLK = 13MHz, T = T
to T
, unless otherwise noted. Typical values are at T = +25°C.) (Note 2)
MAX A
A
MIN
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
AV
= 0dB,
= 1V , f = 1kHz
P-P
PRE
-80
V
IN
Total Harmonic Distortion + Noise
THD+N
dB
AV
= +30dB,
PRE
V
= 32mV , f = 1kHz,
P-P
-67
IN
(1V
at ADC input)
P-P
V
= 1.65V to 1.95V, input referred
60
85
85
AVDD
f = 217Hz, V
AV
= 100mV,
RIPPLE
= 0dB, input referred
ADC
Power-Supply Rejection Ratio
PSRR
dB
f = 1kHz, V
= 100mV,
RIPPLE
80
80
AV
= 0dB, input referred
ADC
f = 10kHz, V
= 100mV,
RIPPLE
AV
= 0dB, input referred
ADC
MICROPHONE BIAS
Output Voltage
V
V
= 1.8V, I = 1mA
LOAD
1.5
1.525
0.2
10
1.55
10
V
MICBIAS
PSRR
AVDD
Load Regulation
Line Regulation
I
= 1mA to 2mA
V/A
µV/V
LOAD
V
= 1.65V to 1.95V
AVDD
f = 217Hz, V
f = 10kHz, V
A-weighted
= 100mV
85
RIPPLE
RIPPLE
P-P
Power-Supply Rejection Ratio
dB
= 100mV
81
P-P
Noise Voltage
9.1
µV
RMS
LINE INPUT
Full-Scale Input
V
AV
= 0dB
1.0
100
-83
V
IN
LINE
P-P
Line Input Level Adjust Range
Line Input Mute Attenuation
Input Resistance
AV
LIGL/LIGR = 0xF to 0x0
f = 1kHz
-6.5
20
+24.5
dB
dB
kΩ
dB
LINE
R
AV
= +24dB
IN_LINE
LINE
Total Harmonic Distortion + Noise
AUXIN INPUT
THD+N
V
= 0.1V , f = 1kHz, differential output
IN P-P
Input DC Voltage Range
AUXIN Input Resistance
JACK SENSE OPERATION
AUXEN = 1
0
0.738
0.98 x
V
R
AUXEN = 1, 0V ≤ AUXIN ≤ 0.738V
10
40
MΩ
IN
0.92 x
0.95 x
JDETEN = 1, SHDN = 1, JACKSNS
MICBIAS MICBIAS MICBIAS
Threshold
V
V
TH
JDETEN = 1, SHDN = 0, JACKSNS,
AVDD - AVDD - AVDD -
LOUTP
0.8
0.4
4
0.15
20
JDETEN = 1, SHDN = 1,
JACKSNS = GND
Pullup Current
Pullup Voltage
I
µA
V
PU
JDETEN = 1, SHDN = 0,
JACKSNS = LOUTP = GND
4
JDETEN = 1, JACKSNS, LOUTP
AVDD
_______________________________________________________________________________________
9
Ultra-Low Power Stereo Audio Codec
ELECTRICAL CHARACTERISTICS (continued)
(V
= V
REF
= V
= 2.2µF, C
= V
MICBIAS
= +1.8V, R = ∞, headphone load (R ) connected between _OUTP and _OUTN in differential
AVDD
PVDD
DVDD
DVDDIO
= C
L
L
mode, C
= C
= 1µF, AV
= +20dB, AV
= 0dB, AV
= 0dB, AV
= +20dB, AV
=
PREG
REG
PRE
PGAM
DAC
LINE
VOL
0dB, MCLK = 13MHz, T = T
to T
, unless otherwise noted. Typical values are at T = +25°C.) (Note 2)
MAX A
A
MIN
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DIGITAL SIDETONE
Differential output mode,
DVST = 0x1F to 0x01
Sidetone Gain Adjust Range
Voice Path Phase Delay
AV
P
-60
0
dB
ms
STGA
MAX9867
MIC input to headphone output, f = 1kHz,
HP filter disabled, f = 8kHz
S
2.2
DLY
INPUT CLOCK CHARACTERISTICS
MCLK Input Frequency
f
For any LRCLK sample rate
Prescaler = /1 mode
/2 or /4 modes
10
40
30
60
60
70
MHz
%
MCLK
MCLK Input Duty Cycle
Maximum allowable RMS for performance
limits
Maximum MCLK Input Jitter
LRCLK Sample Rate Range
100
ps
RMS
8
48
7
kHz
Rapid lock mode
2
Any allowable LRCLK
LRCLK PLL Lock Time
and PCLK rate, slave
mode
ms
Nonrapid lock
mode
12
25
Allowable LRCLK period change from
nominal for slave PLL mode at any
allowable LRCLK and PCLK rates
LRCLK Acceptable Jitter for
Maintaining PLL Lock
100
ns
%
FREQ = 0x8 through 0xF
0
0
0
0
LRCLK Average Frequency Error
(Master and Slave Modes)
(Note 9)
PCLK = 192xf , 256xf , 384xf , 512xf ,
S
S
S
S
768xf , and 1024xf
S
S
All other modes
-0.025
+0.025
DIGITAL INPUT (MCLK)
Input High Voltage
V
1.2
V
V
IH
Input Low Voltage
V
0.6
1
IL
Input Leakage Current
Input Capacitance
I
, I
IH IL
T
A
= +25°C
µA
pF
10
DIGITAL INPUTS (SDIN, BCLK, LRCLK)
0.7 x
DVDDIO
Input High Voltage
Input Low Voltage
V
V
V
IH
0.3 x
DVDDIO
V
IL
Input Hysteresis
200
10
mV
µA
pF
Input Leakage Current
Input Capacitance
I
, I
IH IL
T
A
= +25°C
1
10 ______________________________________________________________________________________
Ultra-Low Power Stereo Audio Codec
MAX9867
ELECTRICAL CHARACTERISTICS (continued)
(V
= V
REF
= V
= 2.2µF, C
= V
MICBIAS
= +1.8V, R = ∞, headphone load (R ) connected between _OUTP and _OUTN in differential
AVDD
PVDD
DVDD
DVDDIO
= C
L
L
mode, C
= C
= 1µF, AV
= +20dB, AV
= 0dB, AV
= 0dB, AV
= +20dB, AV
=
PREG
REG
PRE
PGAM
DAC
LINE
VOL
0dB, MCLK = 13MHz, T = T
to T
, unless otherwise noted. Typical values are at T = +25°C.) (Note 2)
MAX A
A
MIN
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DIGITAL INPUTS (SDA, SCL)
0.7 x
DVDD
Input High Voltage
V
V
V
IH
0.3 x
DVDD
Input Low Voltage
V
IL
Input Hysteresis
200
10
mV
µA
pF
Input Leakage Current
Input Capacitance
I
, I
IH IL
T
A
= +25°C
1
DIGITAL INPUT (DIGMICDATA)
0.65 x
DVDD
Input High Voltage
V
V
V
IH
0.35 x
DVDD
Input Low Voltage
V
IL
Input Hysteresis
100
10
mV
µA
pF
Input Leakage Current
Input Capacitance
I
, I
IH IL
T
A
= +25°C
35
CMOS DIGITAL OUTPUTS (BCLK, LRCLK, SDOUT)
Output Low Voltage
V
I
= 3mA
0.4
V
V
OL
OL
DVDDIO
- 0.4
Output High Voltage
V
I
= 3mA
OH
OH
CMOS DIGITAL OUTPUT (DIGMICCLK)
Output Low Voltage
V
I
I
= 1mA
= 1mA
0.4
1
V
V
OL
OL
DVDD -
0.4
Output High Voltage
V
OH
OH
OPEN-DRAIN DIGITAL OUTPUTS (SDA, IRQ)
Output High Current
I
V
= V , T = +25°C
DVDD A
µA
V
OH
OUT
0.2 x
DVDD
Output Low Voltage
V
I
= 3mA
OL
OL
DIGITAL MICROPHONE TIMING CHARACTERISTICS (V
= 1.65V)
DVDD
MICCLK = 00
MICCLK = 01
PCLK/8
PCLK/6
DIGMICCLK Divide Ratio
f
MHz
ns
MICCLK
DIGMICDATA to DIGMICCLK
Setup Time
t
Either clock edge
Either clock edge
20
0
SU, MIC
HD, MIC
DIGMICDATA to DIGMICCLK
Hold Time
t
ns
DIGITAL AUDIO INTERFACE TIMING CHARACTERISTICS (V
= 1.65V)
DVDD
t
Slave operation
Master operation
75
ns
ns
BCLKS
Minimum BCLK Cycle Time
t
325
BCLKM
______________________________________________________________________________________ 11
Ultra-Low Power Stereo Audio Codec
ELECTRICAL CHARACTERISTICS (continued)
(V
= V
REF
= V
= 2.2µF, C
= V
MICBIAS
= +1.8V, R = ∞, headphone load (R ) connected between _OUTP and _OUTN in differential
AVDD
PVDD
DVDD
DVDDIO
= C
L
L
mode, C
= C
= 1µF, AV
= +20dB, AV
= 0dB, AV
= 0dB, AV
= +20dB, AV
=
PREG
REG
PRE
PGAM
DAC
LINE
VOL
0dB, MCLK = 13MHz, T = T
to T
, unless otherwise noted. Typical values are at T = +25°C.) (Note 2)
MAX A
A
MIN
PARAMETER
Minimum BCLK High Time
Minimum BCLK Low Time
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
ns
t
Slave operation
Slave operation
30
30
7
BCLKH
t
ns
BCLKL
BCLK or LRCLK Rise and Fall
8
t , t
Master operation, C = 15pF
ns
R
F
L
SDIN or LRCLK to BCLK Setup
Time
t
20
0
ns
ns
ns
SU
SDIN or LRCLK to BCLK Hold
Time
t
HD
SDOUT Delay Time from BCLK
Rising Edge
t
C = 30pF
L
0
40
DLY
I2C TIMING CHARACTERISTICS (V
= 1.65V)
DVDD
Serial-Clock Frequency
f
0
400
kHz
µs
SCL
Bus Free Time Between STOP
and START Conditions
t
1.3
BUF
Hold Time (REPEATED) START
Condition
t
t
0.6
µs
HD, STA
SCL Pulse-Width Low
SCL Pulse-Width High
t
1.3
0.6
µs
µs
LOW
t
HIGH
Setup Time for a REPEATED
START Condition
0.6
µs
SU, STA
Data Hold Time
Data Setup Time
t
R
= 475Ω
= 475Ω
0
900
ns
ns
HD, DAT
PU, SDA
t
100
SU, DAT
SDA and SCL Receiving Rise
Time
20 +
0.1C
t
R
(Note 10)
(Note 10)
300
300
250
ns
ns
ns
B
SDA and SCL Receiving Fall
Time
20 +
0.1C
t
F
F
B
R
20 +
0.1C
PU, SDA
SDA Transmitting Fall Time
t
(Note 10)
B
Setup Time for STOP Condition
Bus Capacitance
t
0.6
µs
pF
ns
SU, STO
C
400
50
B
Pulse Width of Suppressed Spike
t
0
SP
Note 2: The MAX9867 is 100% production tested at T = +25°C. Specifications over temperature limits are guaranteed by design.
A
Note 3: Clocking all zeros into the DAC, master mode, and differential headphone mode.
Note 4: DAC performance measured at the headphone outputs.
Note 5: Dynamic range measured using the EIAJ method. -60dBFS 1kHz output signal, A-weighted, and normalized to 0dBFS.
f = 20Hz to 20kHz.
Note 6: Performance measured using microphone inputs, unless otherwise stated.
Note 7: Performance measured using line inputs.
Note 8: Performance measured using DAC, unless otherwise stated. LRCLK = 8kHz, unless otherwise stated.
Note 9: In master-mode operation, the accuracy of the MCLK input proportionally determines the accuracy of the sample clock rate.
Note 10:C is in pF.
B
12 ______________________________________________________________________________________
Ultra-Low Power Stereo Audio Codec
MAX9867
Typical Operating Characteristics
(V
= V
= V
= +1.8V, C
= 2.2µF, C
= C
= C
= 1µF, AV
= 0dB, MCLK = 13MHz, LRCLK =
AVDD
DVDD
PVDD
REF
MICBIAS
PREG
REG
MICPGA
8kHz, BW = 20Hz to f /2, T = +25°C, unless otherwise noted.)
S
A
TOTAL HARMONIC DISTORTION + NOISE
vs. POWER OUT (DAC TO HEADPHONE)
TOTAL HARMONIC DISTORTION + NOISE
vs. POWER OUT (DAC TO HEADPHONE)
TOTAL HARMONIC DISTORTION + NOISE
vs. POWER OUT (DAC TO HEADPHONE)
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
MCLK = 13MHz
LRCLK = 8kHz
MCLK = 13MHz
LRCLK = 8kHz
MCLK = 12.288MHz
LRCLK = 48kHz
R
= 32Ω
R
LOAD
= 16Ω
R
LOAD
= 32Ω
LOAD
DIFFERENTIAL MODE
DIFFERENTIAL MODE
DIFFERENTIAL MODE
3kHz
3kHz
6kHz
1kHz
1kHz
25
1kHz
20Hz
20Hz
20Hz
0
5
10
15
20
30
35
0
10
20
30
40
50
60
0
5
10
15
20
25
30
35
POWER OUT (mW)
POWER OUT (mW)
POWER OUT (mW)
TOTAL HARMONIC DISTORTION + NOISE
vs. POWER OUT (DAC TO HEADPHONE)
TOTAL HARMONIC DISTORTION + NOISE
vs. FREQUENCY (DAC TO HEADPHONE)
TOTAL HARMONIC DISTORTION + NOISE
vs. FREQUENCY (DAC TO HEADPHONE)
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
MCLK = 12.288MHz
LRCLK = 48kHz
MCLK = 13MHz
LRCLK = 8kHz
MCLK = 13MHz
LRCLK = 8kHz
R
= 16Ω
R
LOAD
= 32Ω
R
LOAD
= 16Ω
LOAD
DIFFERENTIAL MODE
DIFFERENTIAL MODE
DIFFERENTIAL MODE
6kHz
5mW
100
1kHz
40
5mW
100
20mW
20mW
20Hz
0
10
20
30
50
60
10
1000
10,000
10
1000
10,000
POWER OUT (mW)
FREQUENCY (Hz)
FREQUENCY (Hz)
TOTAL HARMONIC DISTORTION + NOISE
vs. FREQUENCY (DAC TO HEADPHONE)
TOTAL HARMONIC DISTORTION + NOISE
vs. FREQUENCY (DAC TO HEADPHONE)
TOTAL HARMONIC DISTORTION + NOISE
vs. POWER OUT (DAC TO HEADPHONE)
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
MCLK = 12.288MHz
LRCLK = 48kHz
MCLK = 12.288MHz
LRCLK = 48kHz
MCLK = 13MHz
LRCLK = 8kHz
R
= 32Ω
R
LOAD
= 16Ω
R
LOAD
= 32Ω
LOAD
DIFFERENTIAL MODE
DIFFERENTIAL MODE
CAPACITORLESS MODE
3kHz
1kHz
5mW
5mW
20Hz
20mW
20mW
10,000
10
100
1000
FREQUENCY (Hz)
100,000
10
100
1000
10,000
100,000
0
2
4
6
8
10
FREQUENCY (Hz)
POWER OUT (mW)
______________________________________________________________________________________ 13
Ultra-Low Power Stereo Audio Codec
Typical Operating Characteristics (continued)
(V
= V
= V
= +1.8V, C
= 2.2µF, C
= C
= C
= 1µF, AV
= 0dB, MCLK = 13MHz, LRCLK =
AVDD
DVDD
PVDD
REF
MICBIAS
PREG
REG
MICPGA
8kHz, BW = 20Hz to f /2, T = +25°C, unless otherwise noted.)
S
A
TOTAL HARMONIC DISTORTION + NOISE
vs. POWER OUT (DAC TO HEADPHONE)
TOTAL HARMONIC DISTORTION + NOISE
vs. FREQUENCY (DAC TO HEADPHONE)
TOTAL HARMONIC DISTORTION + NOISE
vs. FREQUENCY (DAC TO HEADPHONE)
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
MCLK = 12.288MHz
LRCLK = 48kHz
MCLK = 13MHz
LRCLK = 8kHz
MCLK = 12.288MHz
LRCLK = 48kHz
R
= 32Ω
R
LOAD
= 32Ω
R
LOAD
= 32Ω
LOAD
MAX9867
CAPACITORLESS MODE
CAPACITORLESS MODE
CAPACITORLESS MODE
6kHz
1mW
5mW
1kHz
1mW
5mW
20Hz
0
2
4
6
8
10
12
10
100
1000
10,000
10
100
1000
FREQUENCY (Hz)
10,000
100,000
POWER OUT (mW)
FREQUENCY (Hz)
TOTAL HARMONIC DISTORTION + NOISE
vs. POWER OUT (DAC TO HEADPHONE)
TOTAL HARMONIC DISTORTION + NOISE
vs. POWER OUT (DAC TO HEADPHONE)
TOTAL HARMONIC DISTORTION + NOISE
vs. FREQUENCY (DAC TO HEADPHONE)
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
MCLK = 13MHz
LRCLK = 8kHz
MCLK = 12.288MHz
LRCLK = 48kHz
MCLK = 13MHz
LRCLK = 8kHz
R
= 32Ω, C
= 220µF
R
LOAD
= 32Ω, C
= 220µF
R
LOAD
= 32Ω, C
= 220µF
LOAD
OUT
OUT
OUT
SINGLE-ENDED MODE
SINGLE-ENDED MODE
SINGLE-ENDED MODE
SPECIFIED AT 1kHz
P
OUT
20Hz
20Hz
3kHz
6kHz
1mW
1kHz
5mW
1kHz
0
2
4
6
8
10
0
2
4
6
8
10
12
10
100
1000
10,000
POWER OUT (mW)
POWER OUT (mW)
FREQUENCY (Hz)
TOTAL HARMONIC DISTORTION + NOISE
vs. FREQUENCY (DAC TO HEADPHONE)
TOTAL HARMONIC DISTORTION + NOISE
vs. POWER OUT (LINE IN TO HEADPHONE)
TOTAL HARMONIC DISTORTION + NOISE
vs. POWER OUT (LINE IN TO HEADPHONE)
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
0
-10
-20
-30
-40
-50
-60
-70
-80
0
-10
-20
MCLK = 13MHz
LRCLK = 8kHz
LINE IN PREAMP = +18dB
LINE IN PREAMP = 0dB
R
LOAD
= 32Ω
R
LOAD
= 32Ω
R
= 32Ω, C
= 220µF
DIFFERENTIAL MODE
DIFFERENTIAL MODE
LOAD
OUT
SINGLE-ENDED MODE
SPECIFIED AT 1kHz
P
OUT
-30
-40
-50
-60
-70
-80
-90
1mW
6kHz
20Hz
1kHz
6kHz
20Hz
5mW
1kHz
10
100
1000
FREQUENCY (Hz)
10,000
100,000
0
5
10 15 20 25 30 35 40 45 50
POWER OUT (mW)
0
5
10 15 20 25 30 35 40
POWER OUT (mW)
14 ______________________________________________________________________________________
Ultra-Low Power Stereo Audio Codec
MAX9867
Typical Operating Characteristics (continued)
(V
= V
= V
= +1.8V, C
= 2.2µF, C
= C
= C
= 1µF, AV
= 0dB, MCLK = 13MHz, LRCLK =
AVDD
DVDD
PVDD
REF
MICBIAS
PREG
REG
MICPGA
8kHz, BW = 20Hz to f /2, T = +25°C, unless otherwise noted.)
S
A
TOTAL HARMONIC DISTORTION + NOISE
vs. FREQUENCY (LINE IN TO HEADPHONE)
TOTAL HARMONIC DISTORTION + NOISE
vs. FREQUENCY (LINE IN TO HEADPHONE)
POWER OUT vs. HEADPHONE LOAD
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
60
50
40
30
20
10
0
LINE IN PREAMP = +18dB
LINE IN PREAMP = +18dB
MCLK = 12.288MHz
LRCLK = 48kHz
THD+N = < 0.1%
DIFFERENTIAL MODE
R
= 32Ω
R
LOAD
= 32Ω
LOAD
DIFFERENTIAL MODE
DIFFERENTIAL MODE
5mW
5mW
20mW
20mW
10
100
1000
FREQUENCY (Hz)
10,000
100,000
10
100
1000
10,000
100,000
1
10
100
1000
FREQUENCY (Hz)
HEADPHONE LOAD (Ω)
TOTAL HARMONIC DISTORTION + NOISE
vs. FREQUENCY (MICROPHONE TO ADC)
POWER OUT vs. HEADPHONE LOAD
POWER OUT vs. HEADPHONE LOAD
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
30
25
20
15
10
5
25
20
15
10
5
MCLK = 13MHz
LRCLK = 8kHz
MICPRE = 0dB
MCLK = 12.288MHz
LRCLK = 48kHz
THD+N = < 0.1%
MCLK = 12.288MHz
LRCLK = 48kHz
THD+N = < 0.1%
V
IN
= 1V
CAPACITORLESS MODE
SINGLE-ENDED MODE
P-P
0
0
10
100
1000
10,000
1
10
100
1000
1
10
100
1000
FREQUENCY (Hz)
HEADPHONE LOAD (Ω)
HEADPHONE LOAD (Ω)
TOTAL HARMONIC DISTORTION + NOISE
vs. FREQUENCY (MICROPHONE TO ADC)
TOTAL HARMONIC DISTORTION + NOISE
vs. FREQUENCY (MICROPHONE TO ADC)
POWER-SUPPLY REJECTION RATIO
vs. FREQUENCY (DAC TO HEADPHONE)
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
MCLK = 13MHz
LRCLK = 8kHz
MICPRE = 20dB
MCLK = 13MHz
LRCLK = 8kHz
MICPRE = 30dB
V = 100mV
RIPPLE P-P
MCLK = 13MHz
LRCLK = 8kHz
V
= 0.11V
V = 0.032V
IN P-P
IN
P-P
10
100
1000
10,000
10
100
1000
10,000
10
100
1000
FREQUENCY (Hz)
10,000
100,000
FREQUENCY (Hz)
FREQUENCY (Hz)
______________________________________________________________________________________ 15
Ultra-Low Power Stereo Audio Codec
Typical Operating Characteristics (continued)
(V
= V
= V
= +1.8V, C
= 2.2µF, C
= C
= C
= 1µF, AV
= 0dB, MCLK = 13MHz, LRCLK =
AVDD
DVDD
PVDD
REF
MICBIAS
PREG
REG
MICPGA
8kHz, BW = 20Hz to f /2, T = +25°C, unless otherwise noted.)
S
A
POWER-SUPPLY REJECTION RATIO
vs. FREQUENCY (MIC TO ADC)
POWER-SUPPLY REJECTION RATIO
vs. FREQUENCY (MICBIAS)
FFT, DAC TO HEADPHONE,
0dBFS, MCLK = 13MHz, LRCLK = 8kHz
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
20
0
V
= 100mV
V
= 100mV
P-P
FREQ = 0xA
RIPPLE
P-P
RIPPLE
MCLK = 13MHz
LRCLK = 8kHz
MAX9867
-20
-40
-60
-80
-100
-120
-140
10
100
FREQUENCY (Hz)
1000
10
100
FREQUENCY (Hz)
1000
0
2
4
6
8
10 12 14 16 18 20
FREQUENCY (kHz)
FFT, DAC TO HEADPHONE,
-60dBFS, MCLK = 13MHz, LRCLK = 8kHz
FFT, DAC TO HEADPHONE,
0dBFS, MCLK = 12.288MHz, LRCLK = 48kHz
FFT, DAC TO HEADPHONE,
-60dBFS, MCLK = 12.288MHz, LRCLK = 48kHz
20
0
20
20
FREQ = 0xA
NI = 6000
NI = 6000
0
-20
0
-20
-40
-60
-80
-100
-120
-140
-20
-40
-40
-60
-60
-80
-80
-100
-120
-140
-100
-120
-140
0
2
4
6
8
10 12 14 16 18 20
0
2
4
6
8
10 12 14 16 18 20
0
2
4
6
8
10 12 14 16 18 20
FREQUENCY (kHz)
FREQUENCY (kHz)
FREQUENCY (kHz)
FFT, DAC TO HEADPHONE,
0dBFS, MCLK = 13MHz, LRCLK = 48kHz
FFT, DAC TO HEADPHONE,
-60dBFS, MCLK = 13MHz, LRCLK = 48kHz
FFT, DAC TO HEADPHONE,
0dBFS, MCLK = 13MHz, LRCLK = 44.1kHz
20
0
20
0
20
0
PLL MODE
PLL MODE
PLL MODE
-20
-40
-60
-80
-100
-120
-140
-20
-40
-60
-80
-100
-120
-140
-20
-40
-60
-80
-100
-120
-140
0
2
4
6
8
10 12 14 16 18 20
0
2
4
6
8
10 12 14 16 18 20
0
2
4
6
8
10 12 14 16 18 20
FREQUENCY (kHz)
FREQUENCY (kHz)
FREQUENCY (kHz)
16 ______________________________________________________________________________________
Ultra-Low Power Stereo Audio Codec
MAX9867
Typical Operating Characteristics (continued)
(V
= V
= V
= +1.8V, C
= 2.2µF, C
= C
= C
= 1µF, AV
= 0dB, MCLK = 13MHz, LRCLK =
AVDD
DVDD
PVDD
REF
MICBIAS
PREG
REG
MICPGA
8kHz, BW = 20Hz to f /2, T = +25°C, unless otherwise noted.)
S
A
FFT, DAC TO HEADPHONE, -60dBFS,
MCLK = 13MHz, LRCLK = 44.1kHz
FFT, MICROPHONE TO ADC,
0dBFS, MCLK = 13MHz, LRCLK = 8kHz
FFT, MICROPHONE TO ADC,
-60dBFS, MCLK = 13MHz, LRCLK = 8kHz
20
0
20
0
20
0
PLL MODE
FREQ = 0xA
FREQ = 0xA
-20
-40
-60
-80
-100
-120
-140
-20
-40
-60
-80
-100
-120
-140
-20
-40
-60
-80
-100
-120
-140
0
2
4
6
8
10 12 14 16 18 20
0
500 1000 1500 2000 2500 3000 3500 4000
FREQUENCY (Hz)
0
500 1000 1500 2000 2500 3000 3500 4000
FREQUENCY (Hz)
FREQUENCY (kHz)
FFT, MICROPHONE TO ADC,
0dBFS, MCLK = 12.288MHz, LRCLK = 48kHz
FFT, MICROPHONE TO ADC,
-60dBFS, MCLK = 12.288MHz, LRCLK = 48kHz
FFT, MICROPHONE TO ADC,
0dBFS, MCLK = 13MHz, LRCLK = 48kHz
20
20
20
0
NI = 6000
NI = 6000
PLL MODE
0
-20
0
-20
-20
-40
-60
-80
-100
-120
-140
-40
-40
-60
-60
-80
-80
-100
-120
-140
-100
-120
-140
0
2
4
6
8
10 12 14 16 18 20
0
2
4
6
8
10 12 14 16 18 20
0
2
4
6
8
10 12 14 16 18 20
FREQUENCY (kHz)
FREQUENCY (kHz)
FREQUENCY (kHz)
FFT, MICROPHONE TO ADC,
-60dBFS, MCLK = 13MHz, LRCLK = 48kHz
WIDEBAND FFT, DAC TO HEADPHONE,
0dBFS, MCLK = 13MHz, LRCLK = 8kHz
WIDEBAND FFT, DAC TO HEADPHONE,
-60dBFS, MCLK = 13MHz, LRCLK = 8kHz
20
0
0
-20
20
0
PLL MODE
FREQ = 0xA
FREQ = 0xA
-20
-40
-60
-80
-100
-120
-140
-20
-40
-60
-80
-100
-120
-140
-40
-60
-80
-100
-120
-140
0
2
4
6
8
10 12 14 16 18 20
0
20
40
60
80
100
120
0
20
40
60
80
100
120
FREQUENCY (kHz)
FREQUENCY (kHz)
FREQUENCY (kHz)
______________________________________________________________________________________ 17
Ultra-Low Power Stereo Audio Codec
Typical Operating Characteristics (continued)
(V
= V
= V
= +1.8V, C
= 2.2µF, C
= C
= C
= 1µF, AV
= 0dB, MCLK = 13MHz, LRCLK =
AVDD
DVDD
PVDD
REF
MICBIAS
PREG
REG
MICPGA
8kHz, BW = 20Hz to f /2, T = +25°C, unless otherwise noted.)
S
A
DAC IIR HIGHPASS FILTER
FREQUENCY RESPONSE, MODE = 0
DAC IIR HIGHPASS FILTER
FREQUENCY RESPONSE, MODE = 0
DAC IIR/FIR LOWPASS FILTER
FREQUENCY RESPONSE (8kHz)
20
0
20
0
20
10
DVFLT = 0
DVFLT = 3
AVFLT = 0
AVFLT = 3
LRCLK = 8kHz
MODE = 0
LRCLK = 8kHz
MODE = 1
0
MAX9867
-10
-20
-30
-40
-50
-60
-70
-80
-20
-40
-60
-80
-100
-20
-40
-60
-80
-100
MODE = 0
DVFLT = 4
AVFLT = 4
20
120
220
320
420
520
20
120
220
320
420
520
3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 4.0
FREQUENCY (kHz)
FREQUENCY (Hz)
FREQUENCY (Hz)
ADC IIR/FIR LOWPASS FILTER
FREQUENCY RESPONSE (8kHz)
SHUTDOWN TO DAC FULL OPERATION
(CAPACITORLESS OR DIFFERENTIAL MODE)
20
10
MODE = 1
-20
MODE = 0
-40
-60
-80
-100
3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 4.0
FREQUENCY (kHz)
TIME (4ms/div)
SHUTDOWN TO DAC FULL OPERATION
(CLICKLESS SINGLE-ENDED MODE)
SHUTDOWN TO DAC FULL OPERATION
(FAST TURN-ON SINGLE-ENDED MODE)
TIME (40ms/div)
TIME (4ms/div)
18 ______________________________________________________________________________________
Ultra-Low Power Stereo Audio Codec
MAX9867
Typical Operating Characteristics (continued)
(V
= V
= V
= +1.8V, C
= 2.2µF, C
= C
= C
= 1µF, AV
= 0dB, MCLK = 13MHz, LRCLK =
MICPGA
AVDD
DVDD
PVDD
REF
MICBIAS
PREG
REG
8kHz, BW = 20Hz to f /2, T = +25°C, unless otherwise noted.)
S
A
FULL OPERATION TO SHUTDOWN (DAC)
ADC SOFT-START
TIME (1ms/div)
TIME (4ms/div)
TOTAL HARMONIC DISTORTION + NOISE
vs. MCLK FREQUENCY, 0dBFS
DYNAMIC RANGE vs. MCLK FREQUENCY
0
120
LRCLK = 48kHz
PLL MODE
V
= -60dBFS
IN
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
LRCLK = 48kHz
PLL MODE
A-WEIGHTED
110
100
90
80
70
60
10 15 20 25 30 35 40 45 50 55 60
MCLK FREQUENCY (MHz)
10
100
MCLK FREQUENCY (MHz)
LINE INPUT RESISTANCE vs. GAIN SETTING
AUX CODE vs. INPUT VOLTAGE
270
220
170
120
70
30,000
25,000
20,000
15,000
10,000
5000
0
20
-5000
-6
-1
4
9
14
19
24
-0.4 -0.2
0
0.2 0.4 0.6 0.8 1.0 1.2
INPUT VOLTAGE (V)
GAIN SETTING (dB)
______________________________________________________________________________________ 19
Ultra-Low Power Stereo Audio Codec
Pin Description
PIN/BUMP
NAME
FUNCTION
TQFN-EP
WLP
A2
1
2
3
DGND
SCL
Digital Ground
2
B3
I C Serial-Clock Input. Connect a pullup resistor to a 1.7V to 3.3V supply.
2
A3
SDA
I C Serial-Data Input/Output. Connect a pullup resistor to a 1.7V to 3.3V supply.
Hardware Interrupt Output. IRQ can be programmed to pull low when bits in
status register 0x00 are set. Read status register 0x00 to clear IRQ once set.
Repeat faults have no effect on IRQ until it is cleared by reading register 0x00.
Connect a 10kΩ pullup resistor to a 1.7V to 3.3V supply.
MAX9867
4
C3
IRQ
5
6
A4
B4
AVDD
REF
Analog Power Supply. Bypass to AGND with a 1µF capacitor.
Converter Reference. Bypass to AGND with a 2.2µF capacitor (1.23V nominal).
Positive Internal Regulated Supply. Bypass to AGND with a 1µF capacitor (1.6V
nominal).
7
A5
PREG
8
9
B5
A6
REG
PREG/2 Voltage Reference. Bypass to AGND with a 1µF capacitor (0.8V nominal).
Analog Ground
AGND
Low-Noise Microphone Bias. Connect a 2.2kΩ to 470Ω resistor to the positive
output of a microphone (1.525V nominal). Bypass to AGND with a 1µF capacitor.
10
B6
MICBIAS
Left Negative Differential Microphone Input or Digital Microphone Clock Output.
For analog microphones, AC-couple to the negative output of a microphone with a
1µF capacitor. For digital microphones, connect to the clock input of the
microphone.
MICLN/
DIGMICCLK
11
C5
Left Positive Differential Microphone Input or Digital Microphone Data Input. For
analog microphones, AC-couple to the positive output of a microphone with a 1µF
capacitor. For digital microphones, connect to the data output of the
microphone(s). Up to two digital microphones can be connected.
MICLP/
DIGMICDATA
12
C6
Right Positive Differential Microphone Input. AC-couple to the positive output of a
microphone with a 1µF capacitor.
13
14
C4
D6
MICRP
MICRN
Right Negative Differential Microphone Input. AC-couple to the negative output of
a microphone with a 1µF capacitor.
15
16
D5
E6
LINL
LINR
Left-Line Input. AC-couple analog audio signal to LINL with a 1µF capacitor.
Right-Line Input. AC-couple analog audio signal to LINR with a 1µF capacitor.
Jack Sense or Auxiliary ADC Input. When configured for jack detection, JACKSNS
detects the presence or absence of a jack. See the Mode Configuration section
for details. When configured as an auxiliary ADC input, AUX is used to measure
DC voltages.
17
D4
JACKSNS/AUX
18
19
E5
D3
PGND
Headphone Power Ground
Positive Right-Channel Headphone Output. Connect directly to the load in
differential and capacitorless mode. AC-couple to the load in single-ended mode.
ROUTP
Negative Right-Channel Headphone Output. Inverting output in differential mode.
Leave unconnected in capacitorless and fast turn-on single-ended mode. Bypass
with a 1µF capacitor to AGND in clickless, single-ended mode.
20
21
E4
D2
ROUTN
LOUTN
Negative Left-Channel Headphone Output. Noninverting output in differential
mode. Common headphone return in capacitorless mode. Leave unconnected in
fast turn-on single-ended mode. Bypass with a 1µF capacitor to AGND in clickless
single-ended mode.
20 ______________________________________________________________________________________
Ultra-Low Power Stereo Audio Codec
MAX9867
Pin Description (continued)
PIN/BUMP
NAME
FUNCTION
TQFN-EP
WLP
Positive Left-Channel Headphone Output. Connect directly to the load in
differential and capacitorless mode. AC-couple to the load in single-ended mode.
22
E3
LOUTP
23
24, 25
26
E2
—
PVDD
N.C.
Headphone Power Supply. Bypass to PGND with a 1µF capacitor.
No Connection
E1
D1
C2
DVDDIO
SDOUT
SDIN
Digital Audio Interface Power Supply. Bypass to DGND with a 1µF capacitor.
Digital Audio Serial-Data ADC Output
27
28
Digital Audio Serial-Data DAC Input
Digital Audio Left-Right Clock Input/Output. LRCLK is the audio sample rate clock
and determines whether the audio data on SDIN is routed to the left or right
channel. In TDM mode, LRCLK is a frame synchronization pulse. LRCLK is an
input when the MAX9867 is in slave mode and an output when in master mode.
29
C1
LRCLK
Digital Audio Bit Clock Input/Output. BCLK is an input when the MAX9867 is in
slave mode and an output when in master mode.
30
31
32
—
B1
B2
A1
—
BCLK
MCLK
DVDD
EP
Master Clock Input. Acceptable input frequency range: 10MHz to 60MHz.
Digital Power Supply. Supply for the digital circuitry and I2C interface. Bypass to
DGND with a 1µF capacitor.
Exposed Pad. Connect the exposed thermal pad to AGND.
transmission noise. The digital filtering provides attenuation
Detailed Description
The MAX9867 is a low-power stereo audio codec
designed for portable applications requiring minimum
power consumption.
of out-of-band energy by over 70dB, eliminating audi-
ble aliasing. A digital sidetone function allows audio
from the record path to be summed into the playback
path after digital filtering.
The stereo playback path accepts digital audio through
a flexible interface compatible with I2S, TDM, and left-
justified signals. An oversampling sigma-delta DAC
converts the incoming digital data stream to analog
audio and outputs the audio through the stereo head-
phone amplifier. The headphone amplifier can be con-
figured in differential, single-ended, and capacitorless
output modes.
The MAX9867 also includes two stereo, single-ended
line inputs with gain adjustment, which can be record-
ed by the ADCs and/or output by the headphone ampli-
fiers. An auxiliary ADC accurately measures a DC
voltage by utilizing the right audio ADC and reporting
the DC voltage through the I2C interface. A jack detec-
tion function allows the detection of headphone, micro-
phone, and headset jacks. Insertion and removal
events can be programmed to trigger a hardware inter-
rupt and flag an I2C register bit.
The stereo record path has two analog microphone
inputs with selectable gain. An integrated microphone
bias can be used to power the microphones. The left
analog microphone inputs can also accept data from
up to two digital microphones. An oversampling sigma-
delta ADC converts the microphone signals and out-
puts the digital bit stream over the digital audio
interface.
The MAX9867’s flexible clock circuitry utilizes a program-
mable clock divider and a digital PLL, allowing the DAC
and ADC to operate at maximum dynamic range for all
combinations of master clock (MCLK) and sample rate
(LRCLK) without consuming extra supply current. Any
master clock between 10MHz and 60MHz is supported
as are all sample rates from 8kHz to 48kHz. Master and
slave modes are supported for maximum flexibility.
Integrated digital filtering provides a range of notch and
highpass filters for both the playback and record paths
to limit undesirable low-frequency signals and GSM
______________________________________________________________________________________ 21
Ultra-Low Power Stereo Audio Codec
2
I2C Registers
I C Slave Address
The MAX9867 responds to the slave address 0x30 for
all write commands and 0x31 for all read operations.
The MAX9867 audio codec is completely controlled
through software using an I2C interface. The power-on
default setting is complete shutdown, requiring that the
internal registers be programmed to activate the device.
See Table 1 for the device’s complete register map.
2
Table 1. I C Register Map
MAX9867
POWER-
ON RESET
STATE
REGISTER
ADDRESS
REGISTER
B7
B6
B5
B4
B3
B2
B1
B0
STATUS
Status (Read Only)
Jack Sense (Read Only)
AUX High (Read Only)
AUX Low (Read Only)
Interrupt Enable
CLD
SLD
ULK
0
0
0
0
0
0
JDET
0
0
0
0x00
0x01
0x02
0x03
0x04
—
—
LSNS
JKSNS
JKMIC
AUX[15:8]
AUX[7:0]
—
—
ICLD
ISLD
0
IULK
0
0
SDODLY
IJDET
0
0x00
CLOCK CONTROL
System Clock
0
PSCLK
FREQ
0x05
0x06
0x00
0x00
Stereo Audio Clock
Control High
PLL
NI[14:8]
Stereo Audio Clock
Control Low
RLK/
NI[0]
NI[7:1]
DLY
0x07
0x00
DIGITAL AUDIO INTERFACE
Interface Mode
Interface Mode
DIGITAL FILTERING
Codec Filters
MAS
WCI
0
BCI
0
HIZOFF
TDM
0
0
0x08
0x09
0x00
0x00
0
LVOLFIX DMONO
BSEL
MODE
AVFLT
0
0
DVFLT
0x0A
0x00
LEVEL CONTROL
Sidetone
DSTS
DVST
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
0x11
0x12
0x13
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
DAC Level
0
DACM
DACG
DACA
ADC Level
AVL
AVR
LIGL
LIGR
Left-Line Input Level
Right-Line Input Level
Left Volume Control
Right Volume Control
Left Microphone Gain
Right Microphone Gain
CONFIGURATION
ADC Input
0
0
0
0
0
0
LILM
LIRM
0
0
0
0
VOLLM
VOLL
VOLR
PGAML
PGAMR
VOLRM
PALEN
PAREN
MXINL
MICCLK
MXINR
DIGMICL DIGMICR
AUXCAP AUXGAIN AUXCAL AUXEN
0x14
0x15
0x16
0x00
0x00
0x00
Microphone
0
0
0
0
Mode
DSLEW
VSEN
ZDEN
0
JDETEN
HPMODE
POWER MANAGEMENT
System Shutdown
Revision
SHDN
LNLEN
LNREN
0
DALEN
DAREN
ADLEN
ADREN
0x17
0xFF
0x00
0x42
REV
22 ______________________________________________________________________________________
Ultra-Low Power Stereo Audio Codec
MAX9867
register and are set the next time the event occurs.
Registers 0x02 and 0x03 report the DC level applied to
AUX. See the ADC section for more details and Table 2.
Device Status
Status registers 0x00 and 0x01 are read-only registers
that report the status of various device functions. The
status register bits are cleared upon reading the status
Table 2. Status Registers
REGISTER
ADDRESS
REGISTER
B7
B6
B5
B4
B3
B2
B1
B0
Status (Read Only)
CLD
SLD
ULK
0
0
0
0
0
0
JDET
0
0
0
0x00
0x01
0x02
0x03
Jack Sense (Read Only)
AUX High (Read Only)
AUX Low (Read Only)
LSNS
JKSNS
JKMIC
AUX[15:8]
AUX[7:0]
BITS
FUNCTION
Clip Detect Flag
CLD
Indicates that a signal has reached or exceeded full scale in the ADC or DAC.
Slew Level Detect Flag
When volume or gain changes are made, the slewing circuitry smoothly steps through all intermediate
settings. When SLD is set high, all slewing has completed and the volume or gain is at its final value. SLD
is also set when soft-start or stop is complete.
SLD
Digital PLL Unlock Flag
Indicates that the digital audio PLL has become unlocked and digital signal data is not reliable.
ULK
Headset Configuration Change Flag
JDET is set whenever there is a change in register 0x01, indicating that the headset configuration has
changed.
JDET
LOUTP State (Valid if SHDN = 0, JDETEN = 1)
LSNS is set when the voltage at LOUTP exceeds AVDD - 0.4V. An internal pullup from AVDD to LOUTP
causes this condition whenever there is no load on LOUTP. LSNS is only valid in differential and
capacitorless output modes.
LSNS
JACKSNS State (Valid if JDETEN = 1)
JKSNS is set when the voltage at JACKSNS exceeds AVDD - 0.4V. An internal pullup from AVDD to
JACKSNS causes this condition whenever there is no load on JACKSNS.
JKSNS
JKMIC
Microphone Detection (Valid if PALEN or PAREN ≠ 00 and JDETEN = 1)
JKMIC is set when JACKSNS exceeds 0.95 x V
.
MICBIAS
Auxiliary Input Measurement
AUX is a 16-bit signed two’s complement number representing the voltage measured at JACKSNS/AUX.
Before reading a value from AUX, set AUXCAP to 1 to ensure a stable reading. After reading the value,
set AUXCAP to 0.
AUX
Use the following formula to convert the AUX value into an equivalent JACKSNS/AUX voltage:
AUX
K
⎛
⎝
⎞
⎠
Voltage = 0.738V ×
⎜
⎟
K = AUX value when AUXGAIN = 1. See the ADC section for complete details.
______________________________________________________________________________________ 23
Ultra-Low Power Stereo Audio Codec
accommodate a wide range of system architectures,
Hardware Interrupts
Hardware interrupts are reported on the open-drain IRQ
pin. When an interrupt occurs, IRQ remains low until the
interrupt is serviced by reading the status register 0x00.
If a flag is set, it is reported as a hardware interrupt only
if the corresponding interrupt enable is set. Each bit
enables interrupts for the status flag in the respective
bit location in register 0x00. See Table 3.
the MAX9867 supports three main clocking modes:
• Normal: This mode uses a 15-bit clock divider coeffi-
cient to set the sample rate relative to the prescaled
MCLK input (PCLK). This allows high flexibility in both
the MCLK and LRCLK frequencies and can be used
in either master or slave mode.
• Exact Integer: In both master and slave mode, com-
mon MCLK frequencies (12MHz, 13MHz, 16MHz,
and 19.2MHz) can be programmed to operate in
exact integer mode for both 8kHz and 16kHz sample
rates. In these modes, the MCLK and LRCLK rates
are selected by using the FREQ bits instead of the NI
and PLL control bits.
SDODLY is used to control the SDOUT timing. See the
Digital Audio Interface section for a detailed description.
MAX9867
Clock Control
The MAX9867 can work with a master clock (MCLK)
supplied from any system clock within the 10MHz-to-
60MHz range. Internally, the MAX9867 requires a
10MHz-to-20MHz clock. A prescaler divides MCLK by
1, 2, or 4 to create the internal clock (PCLK). PCLK is
used to clock all portions of the MAX9867. See Table 4.
• PLL: When operating in slave mode, a PLL can be
enabled to lock onto externally generated LRCLK
signals that are not integer related to PCLK. Prior to
enabling the interface, program NI to the nearest
desired ratio and set the NI[0] = 1 to enable the
PLL’s rapid lock mode. If NI[0] = 0, then NI is ignored
and PLL lock time is slower.
The MAX9867 is capable of supporting any sample rate
from 8kHz to 48kHz, including all common sample rates
(8kHz, 16kHz, 24kHz, 32kHz, 44.1kHz, and 48kHz). To
Table 3. Interrupt Register
REGISTER
ADDRESS
REGISTER
B7
B6
B5
B4
B3
B2
B1
B0
Interrupt Enable
ICLD
ISLD
IULK
0
0
SDODLY
IJDET
0
0x04
Table 4. Clock Control Registers
REGISTER
REGISTER
System Clock
B7
B6
B5
B4
B3
B2
B1
B0
0
0
PSCLK
FREQ
0x05
Stereo Audio Clock
Control High
PLL
NI[14:8]
0x06
0x07
Stereo Audio Clock
Control Low
NI[7:1]
NI[0]
BITS
FUNCTION
MCLK Prescaler
Divides MCLK to generate a PCLK between 10MHz and 20MHz.
00 = Disable clock for low-power shutdown.
01 = Select if MCLK is between 10MHz and 20MHz.
10 = Select if MCLK is between 20MHz and 40MHz.
11 = Select if MCLK is between 40MHz and 60MHz.
PSCLK
24 ______________________________________________________________________________________
Ultra-Low Power Stereo Audio Codec
MAX9867
Table 4. Clock Control Registers (continued)
BITS
FUNCTION
Exact Integer Modes
Allows integer sampling for specific PCLK (prescaled MCLK) frequencies and 8kHz or 16kHz sample rates.
FREQ[3:0]
0x00
PCLK (MHz)
LRCLK (kHz)
Normal or PLL mode
Reserved
PCLK/LRCLK
0x1–0x7
Reserved
Reserved
0x8
0x9
0xA
0xB
0xC
0xD
0xE
0xF
12
12
13
13
16
16
19.2
19.2
8
16
8
16
8
16
8
16
1500
750
FREQ
1625
812.5
2000
1000
2400
1200
Modes 0x8–0xF are available in either master or slave mode. In slave mode, if the indicated PCLK/LRCLK ratio
cannot be guaranteed, use PLL mode instead.
PLL Mode Enable
0 = Valid for slave and master mode. The frequency of LRCLK is set by the NI divider bits. In master mode, the
MAX9867 generates LRCLK using the specified divide ratio. In slave mode, the MAX9867 expects an
LRCLK as specified by the divide ratio.
PLL
1 = Valid for slave mode only. A digital PLL locks on to any externally supplied LRCLK signal.
Rapid Lock Mode
To enable rapid lock mode, set NI to the nearest desired ratio and set NI[0] = 1 before enabling the interface.
Normal Mode LRCLK Divider
When PLL = 0, the frequency of LRCLK is determined by NI. See Table 5 for common NI values.
NI = (65536 x 96 x f
)/f
LRCLK PCLK
NI
f
f
= LRCLK frequency
= Prescaled MCLK internal clock frequency (PCLK)
LRCLK
PCLK
LRCLK > 24kHz is only valid for MODE = 0 (stereo audio mode). MODE = 1 (voice mode) requires LRCLK ≤
24kHz.
Table 5. Common NI Values
LRCLK (kHz)
24
MCLK (MHz)
PSCLK
8
16
32
44.1
48
11.2896
12
01
01
01
01
01
10
10
10
0x116A
0x1062
0x1000
0x0F20
0x0A3D
0x1062
0x0F20
0x0E90
0x22D4
0x20C5
0x2000
0x1E3F
0x147B
0x20C5
0x1E3F
0x1D21
0x343F
0x3127
0x3000
0x2D5F
0x1EB8
0x1893
0x16AF
0x15D8
0x45A9
0x4189
0x4000
0x3C7F
0x28F6
0x4189
0x3C7F
0x3A41
0x6000
0x5A51
0x5833
0x535F
0x3873
0x5A51
0x535F
0x5048
0x687D
0x624E
0x6000
0x5ABE
0x3D71
0x624E
0x5ABE
0x5762
12.288
13
19.2
24
26
27
Note: Bolded values are exact integers that provide maximum full-scale performance.
______________________________________________________________________________________ 25
Ultra-Low Power Stereo Audio Codec
mode, BCLK can be configured in a number of ways to
Digital Audio Interface
The MAX9867’s digital audio interface supports a wide
range of operating modes to ensure maximum compati-
bility. See Figures 1–4 for timing diagrams. In master
mode, the MAX9867 outputs LRCLK and BCLK, while in
slave mode they are inputs. When operating in master
ensure compatiblity with other audio devices.
LVOLFIX is used to fix the line input playback volume to
0dB regardless of VOLL and VOLR. See the Line Inputs
section for complete details and Table 6.
Table 6. Digital Audio Interface Registers
MAX9867
REGISTER
ADDRESS
REGISTER
B7
B6
B5
B4
B3
B2
B1
B0
Interface Mode
Interface Mode
MAS
0
WCI
0
BCI
0
DLY
HIZOFF
TDM
0
0
0x08
0x09
LVOLFIX DMONO
BSEL
BITS
FUNCTION
Master Mode
MAS
0 = The MAX9867 operates in slave mode with LRCLK and BCLK configured as inputs.
1 = The MAX9867 operates in master mode with LRCLK and BCLK configured as outputs.
LRCLK Invert
0 = Left-channel data is input and output while LRCLK is low.
1 = Right-channel data is input and output while LRCLK is low.
Note: WCI is ignored when TDM = 1.
BCLK Invert
In master and slave modes:
0 = SDIN is latched into the part on the rising edge of BCLK.
SDOUT transitions after the rising edge of BCLK as determined by SDODLY.
1 = SDIN is latched into the part on the falling edge of BCLK.
SDOUT transitions after the falling edge of BCLK as determined by SDODLY.
In master mode:
WCI
BCI
0 = LRCLK changes state immediately after the rising edge of BCLK.
1 = LRCLK changes state immediately after the falling edge of BCLK.
SDOUT Delay
0 = SDOUT transitions one half BCLK cycle after SDIN is latched into the part.
1 = SDOUT transitions on the same BCLK edge as SDIN is latched into the part.
See Figures 1–4 for complete details. See Register 0x04 (interrupt registers).
Delay Mode
SDODLY
0 = SDIN/SDOUT data is latched on the first BCLK edge following an LRCLK edge.
DLY
1 = SDIN/SDOUT data is assumed to be delayed one BCLK cycle so that it is latched on the 2nd BCLK edge
following an LRCLK edge (I2S-compatible mode).
Note: DLY is ignored when TDM = 1.
SDOUT High-Impedance Mode
0 = SDOUT goes to a high-impedance state after all data bits have been transferred out of the MAX9867,
allowing SDOUT to be shared by other devices.
HIZOFF
1 = SDOUT is set either high or low after all data bits have been transferred out of the MAX9867.
Note: High-impedance mode is intended for use when TDM = 1.
LVOLFIX
See the Line Inputs section.
26 ______________________________________________________________________________________
Ultra-Low Power Stereo Audio Codec
MAX9867
Table 6. Digital Audio Interface Registers (continued)
BITS
FUNCTION
TDM Mode Select
0 = LRCLK signal polarity indicates left and right audio.
1 = LRCLK is a framing pulse that transitions polarity to indicate the start of a frame of audio data consisting
TDM
of multiple channels.
When operating in TDM mode, the left channel is output immediately following the frame sync pulse. If right-
channel data is being transmitted, the 2nd channel of data immediately follows the 1st channel data.
Mono Playback Mode
DMONO
0 = Stereo data input on SDIN is processed separately.
1 = Stereo data input on SDIN is mixed to a single channel and routed to both the left and right DAC.
BCLK Select
Configures BCLK when operating in master mode. BSEL has no effect in slave mode. Set BSEL = 010, unless
sharing the bus with multiple devices:
000 = Off
001 = 64x LRCLK (192x internal clock divided by 3)
010 = 48x LRCLK (192x internal clock divided by 4)
011 = Reserved for future use.
100 = PCLK/2
BSEL
101 = PCLK/4
110 = PCLK/8
111 = PCLK/16
______________________________________________________________________________________ 27
Ultra-Low Power Stereo Audio Codec
AUDIO MASTER MODES:
LEFT JUSTIFIED: WCI = 0, BCI = 0, DLY = 0, SDODLY = 0
7ns (typ)
7ns (typ)
LRCLK
LEFT
RIGHT
1/f
S
RELATIVE TO PCLK (SEE NOTE)
D15
D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
D15
D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
SDOUT
BCLK
40ns (max)
0ns (min)
MAX9867
7ns (typ)
7ns (typ)
CONFIGURED BY BSEL
25ns (min)
0ns (min)
SDIN
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
LEFT JUSTIFIED + LRCLK INVERT: WCI = 1, BCI = 0, DLY = 0, SDODLY = 0
7ns (typ)
7ns (typ)
LRCLK
RIGHT
LEFT
1/f
S
RELATIVE TO PCLK (SEE NOTE)
SDOUT
BCLK
D15
D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
D15
D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
40ns (max)
0ns (min)
7ns (typ)
7ns (typ)
CONFIGURED BY BSEL
25ns (min)
0ns (min)
SDIN
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
LEFT JUSTIFIED + BCLK INVERT: WCI = 0, BCI = 1, DLY = 0, SDODLY = 0
7ns (typ)
7ns (typ)
LRCLK
LEFT
RIGHT
1/f
S
RELATIVE TO PCLK (SEE NOTE)
SDOUT
BCLK
D15
D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
D15
D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
40ns (max)
0ns (min)
7ns (typ)
7ns (typ)
CONFIGURED BY BSEL
25ns (min)
0ns (min)
SDIN
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
NOTE: THE DELAY FROM A BCLK EDGE AND AN LRCLK EDGE IS DETERMINED BY LENGTH OF TIME THAT PCLK (THE INTERNALLY DIVIDED DOWN VERSION OF MCLK AS DEFINED BY THE PSCLK BITS) IS HIGH DURING ONE PERIOD OF
MCLK PLUS THE INTERNAL DELAY. FOR EXAMPLE: IF PCLK = 12.288MHZ, THEN THE DELAY BETWEEN BCLK AND LRCLK IS TYPICALLY 45ns.
Figure 1. Digital Audio Interface Audio Master Mode Example (Sheet 1 of 2)
28 ______________________________________________________________________________________
Ultra-Low Power Stereo Audio Codec
MAX9867
2
I S: WCI = 0, BCI = 0, DLY = 1, SDODLY = 0
7ns (typ)
7ns (typ)
LRCLK
LEFT
RIGHT
1/f
S
RELATIVE TO PCLK (SEE NOTE)
SDOUT
BCLK
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
40ns (max)
0ns (min)
7ns (typ)
7ns (typ)
CONFIGURED BY BSEL
25ns (min)
0ns (min)
SDIN
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
LEFT JUSTIFIED: WCI = 0, BCI = 0, DLY = 0, SDODLY = 1
7ns (typ)
7ns (typ)
LRCLK
SDOUT
BCLK
LEFT
RIGHT
1/f
S
RELATIVE TO PCLK (SEE NOTE)
D15
D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
D15
D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
40ns (max)
0ns (min)
7ns (typ)
7ns (typ)
CONFIGURED BY BSEL
25ns (min)
0ns (min)
SDIN
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
NOTE: THE DELAY FROM A BCLK EDGE AND AN LRCLK EDGE IS DETERMINED BY LENGTH OF TIME THAT PCLK (THE INTERNALLY DIVIDED DOWN VERSION OF MCLK AS DEFINED BY THE PSCLK BITS) IS HIGH DURING ONE PERIOD OF
MCLK PLUS THE INTERNAL DELAY. FOR EXAMPLE: IF PCLK = 12.288MHZ, THEN THE DELAY BETWEEN BCLK AND LRCLK IS TYPICALLY 45ns.
Figure 1. Digital Audio Interface Audio Master Mode Example (Sheet 2 of 2)
______________________________________________________________________________________ 29
Ultra-Low Power Stereo Audio Codec
VOICE (TDM, PCM) MASTER MODES:
BCI = 0, HIZOFF = 0, SDODLY = 0
7ns (typ)
7ns (typ)
LRCLK
1/f
S
RELATIVE TO PCLK (SEE NOTE)
SDOUT
BCLK
L15 L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0 R15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0
40ns (max)
0ns (min)
7ns (typ)
7ns (typ)
MAX9867
CONFIGURED BY BSEL
25ns (min)
0ns (min)
SDIN
L15 L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0 R15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0
BCI = 1, HIZOFF = 0, SDODLY = 0
7ns (typ)
7ns (typ)
LRCLK
1/f
S
RELATIVE TO PCLK (SEE NOTE)
SDOUT
BCLK
L15 L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0 R15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0
40ns (max)
0ns (min)
7ns (typ)
7ns (typ)
CONFIGURED BY BSEL
25ns (min)
0ns (min)
SDIN
L15 L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0 R15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0
BCI = 0, HIZOFF = 1, SDODLY = 0
7ns (typ)
7ns (typ)
LRCLK
1/f
S
RELATIVE TO PCLK (SEE NOTE)
SDOUT
BCLK
L15 L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0 R15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0
40ns (max)
0ns (min)
7ns (typ)
7ns (typ)
CONFIGURED BY BSEL
25ns (min)
0ns (min)
SDIN
L15 L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0 R15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0
BCI = 0, HIZOFF = 0, SDODLY = 1
7ns (typ)
7ns (typ)
LRCLK
1/f
S
RELATIVE TO PCLK (SEE NOTE)
SDOUT
BCLK
L15 L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0 R15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0
40ns (max)
0ns (min)
7ns (typ)
7ns (typ)
CONFIGURED BY BSEL
25ns (min)
0ns (min)
SDIN
L15 L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0 R15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0
Figure 2. Digital Audio Interface Voice Master Mode Examples
30 ______________________________________________________________________________________
Ultra-Low Power Stereo Audio Codec
MAX9867
AUDIO SLAVE MODES:
LEFT JUSTIFIED: WCI = 0, BCI = 0, DLY = 0, SDODLY = 0
LRCLK
LEFT
RIGHT
1/f
S
0ns (min)
25ns (min)
D15
D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
40ns (max)
D15
D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
SDOUT
BCLK
0ns (min)
30ns (min)
75ns (min)
0ns (min)
30ns (min)
25ns (min)
SDIN
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
LEFT JUSTIFIED + LRCLK INVERT: WCI = 1, BCI = 0, DLY = 0, SDODLY = 0
LRCLK
RIGHT
LEFT
1/f
S
0ns (min)
25ns (min)
SDOUT
BCLK
D15
D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
40ns (max)
D15
D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
0ns (min)
30ns (min)
75ns (min)
0ns (min)
30ns (min)
25ns (min)
SDIN
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
LEFT JUSTIFIED + BCLK INVERT: WCI = 0, BCI = 1, DLY = 0, SDODLY = 0
LRCLK
LEFT
RIGHT
1/f
S
0ns (min)
25ns (min)
SDOUT
BCLK
D15
D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
40ns (max)
D15
D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
0ns (min)
30ns (min)
75ns (min)
0ns (min)
30ns (min)
25ns (min)
SDIN
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Figure 3. Digital Audio Interface Audio Slave Mode Examples (Sheet 1 of 2)
______________________________________________________________________________________ 31
Ultra-Low Power Stereo Audio Codec
2
I S: WCI = 0, BCI = 0, DLY = 1, SDODLY = 0
LRCLK
SDOUT
LEFT
RIGHT
1/f
S
0ns (min)
25ns (min)
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
40ns (max)
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
0ns (min)
30ns (min)
MAX9867
BCLK
75ns (min)
30ns (min)
25ns (min)
0ns (min)
SDIN
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
LEFT JUSTIFIED: WCI = 0, BCI = 0, DLY = 0, SDODLY = 1
LEFT
LRCLK
RIGHT
1/f
S
0ns (min)
25ns (min)
SDOUT
BCLK
D15
D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
40ns (max)
D15
D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
0ns (min)
30ns (min)
75ns (min)
0ns (min)
30ns (min)
25ns (min)
SDIN
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Figure 3. Digital Audio Interface Audio Slave Mode Examples (Sheet 2 of 2)
32 ______________________________________________________________________________________
Ultra-Low Power Stereo Audio Codec
MAX9867
VOICE (TDM, PCM) SLAVE MODES:
BCI = 0, HIZOFF = 0, SDODLY = 0
LRCLK
1/f
S
0ns (min)
25ns (min)
0ns (min)
0ns (min)
0ns (min)
0ns (min)
SDOUT
BCLK
L15 L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0 R15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0
40ns (max)
0ns (min)
30ns (min)
75ns (min)
30ns (min)
25ns (min)
25ns (min)
25ns (min)
25ns (min)
0ns (min)
SDIN
L15 L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0 R15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0
BCI = 1, HIZOFF = 0, SDODLY = 0
LRCLK
1/f
S
0ns (min)
25ns (min)
SDOUT
BCLK
L15 L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0 R15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0
40ns (max)
0ns (min)
30ns (min)
75ns (min)
30ns (min)
0ns (min)
SDIN
L15 L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0 R15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0
BCI = 0, HIZOFF = 1, SDODLY = 0
LRCLK
1/f
S
0ns (min)
25ns (min)
SDOUT
BCLK
L15 L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0 R15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0
40ns (max)
0ns (min)
30ns (min)
75ns (min)
30ns (min)
0ns (min)
SDIN
L15 L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0 R15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0
BCI = 0, HIZOFF = 0, SDODLY = 1
LRCLK
1/f
S
0ns (min)
25ns (min)
SDOUT
BCLK
L15 L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0 R15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0
40ns (max)
0ns (min)
30ns (min)
75ns (min)
30ns (min)
0ns (min)
SDIN
L15 L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0 R15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0
Figure 4. Digital Audio Interface Voice Slave Mode Examples
______________________________________________________________________________________ 33
Ultra-Low Power Stereo Audio Codec
stopband attenuation as well as selectable highpass fil-
Digital Filtering
The MAX9867 incorporates both IIR (voice) and FIR
(audio) digital filters to accomodate a wide range of
audio sources. The IIR fiilters provide over 70dB of
ters. The FIR filters provide low-power consumption and
are linear phase to maintain stereo imaging. Table 7 is
the digital filtering register.
Table 7. Digital Filtering Register
REGISTER
ADDRESS
REGISTER
Codec Filters
B7
B6
B5
B4
B3
B2
B1
B0
MAX9867
MODE
AVFLT
0
DVFLT
0x0A
BITS
FUNCTION
Digital Audio Filter Mode
0 = IIR Voice Filters
MODE
1 = FIR Audio Filters
ADC Digital Audio Filter
MODE = 0
Select the desired digital filter response from Table 8. See the Frequency Response graph in the Typical
Operating Characteristics section for details on each filter.
MODE = 1
AVFLT
DVFLT
0x0 = DC-blocking filter is disabled. Any other setting = DC-blocking filter is enabled.
DAC Digital Audio Filter
MODE = 0
Select the desired digital filter response from Table 8. See the Frequency Response graph in the Typical
Operating Characteristics section for details on each filter.
MODE = 1
0x0 = DC-blocking filter is disabled. Any other setting = DC-blocking filter is enabled.
Table 8. IIR Highpass Digital Filters
INTENDED SAMPLE
RATE (kHz)
HIGHPASS CORNER
FREQUENCY (Hz)
CODE
FILTER TYPE
217Hz NOTCH
0x0
0x1
Disabled
Elliptical
Butterworth
Elliptical
16
256
500
256
500
Yes
No
0x2
16
0x3
8
8
Yes
No
0x4
Butterworth
Butterworth
0x5
8 to 24
f /240
S
No
0x6 to 0x7
Reserved
34 ______________________________________________________________________________________
Ultra-Low Power Stereo Audio Codec
MAX9867
gain adjustment is also provided to set the sidetone
level relative to the playback level. Table 9 is the digital
gain registers.
Digital Gain Control
The MAX9867 includes digital gain adjustment for the
playback and record paths. Independent gain adjust-
ment is provided for the two record channels. Sidetone
Table 9. Digital Gain Registers
REGISTER
ADDRESS
REGISTER
B7
B6
B5
B4
B3
B2
B1
B0
Sidetone
DSTS
DACM
0
DVST
0x0B
0x0C
0x0D
DAC Level
ADC Level
0
DACG
DACA
AVR
AVL
BITS
FUNCTION
Digital Sidetone Source Mixer
00 = No sidetone is selected.
01 = Left ADC
DSTS
10 = Right ADC
11 = Left + right ADC
Digital Sidetone Level Control
All gain settings are relative to the ADC input voltage.
Differential Headphone Output Mode
SETTING
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
GAIN (dB)
SETTING
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
0x11
0x12
0x13
GAIN (dB)
-20
SETTING
GAIN (dB)
-42
Off
0
-2
-4
-6
0x16
0x17
0x18
0x19
0x1A
0x1B
0x1C
0x1D
0x1E
0x1F
—
-22
-24
-26
-28
-30
-32
-34
-36
-44
-46
-48
-50
-52
-54
-56
-58
-8
-10
-12
-14
-16
-18
0x14
-38
-60
DVST
0x15
-40
—
Capacitorless and Single-Ended Headphone Output Mode
SETTING
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
GAIN (dB)
Off
SETTING
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
0x11
0x12
0x13
GAIN (dB)
-25
SETTING
0x16
0x17
0x18
0x19
0x1A
0x1B
0x1C
0x1D
0x1E
0x1F
—
GAIN (dB)
-47
-5
-7
-9
-11
-13
-15
-17
-19
-21
-23
-27
-29
-31
-33
-35
-37
-39
-41
-49
-51
-53
-55
-57
-59
-61
-63
0x14
-43
-65
0x15
-45
—
DAC Mute Enable
0 = No mute
1 = Mute
DACM
______________________________________________________________________________________ 35
Ultra-Low Power Stereo Audio Codec
Table 9. Digital Gain Registers (continued)
BITS
FUNCTION
DAC Gain
00 = 0dB
01 = +6dB
10 = +12dB
11 = +18dB
DACG
Note: DACG is only used when MODE = 0. If MODE = 1, the DAC level is only set by DACA.
MAX9867
DAC Level Control
DACA works in all modes.
SETTING
GAIN (dB)
SETTING
0x8
GAIN (dB)
0x0
0
-8
0x1
0x2
0x3
0x4
0x5
0x6
0x7
-1
-2
-3
-4
-5
-6
-7
0x9
0xA
0xB
0xC
0xD
0xE
0xF
-9
DACA
-10
-11
-12
-13
-14
-15
ADC Left/Right Level Control
SETTING
0x0
GAIN (dB)
SETTING
0x8
GAIN (dB)
+3
+2
+1
0
-5
-6
-7
0x1
0x2
0x3
0x9
0xA
0xB
AVL/AVR
-8
0x4
0x5
0x6
0x7
-1
-2
-3
-4
0xC
0xD
0xE
0xF
-9
-10
-11
-12
to the headphone amplifier and can be optionally con-
nected to the ADC for recording. Table 10 lists the line
input registers.
Line Inputs
The MAX9867 includes one pair of single-ended line
inputs. When enabled, the line inputs connect directly
Table 10. Line Input Registers
REGISTER
ADDRESS
REGISTER
B7
B6
B5
B4
B3
B2
B1
B0
Left-Line Input Level
Right-Line Input Level
0
0
LILM
LIRM
0
0
0
0
LIGL
LIGR
0x0E
0x0F
36 ______________________________________________________________________________________
Ultra-Low Power Stereo Audio Codec
MAX9867
Table 10. Line Input Registers (continued)
BITS
FUNCTION
Line-Input Left/Right Playback Mute
LILM/LIRM
0 = Line input is connected to the headphone amplifiers.
1 = Line input is disconnected from the headphone amplifiers.
Line-Input Left/Right Gain
SETTING
0x0
GAIN (dB)
+24
SETTING
0x8
GAIN (dB)
+8
+6
+4
+2
0
0x1
+22
0x9
0x2
+20
0xA
LIGL/LIGR
0x3
+18
0xB
0x4
+16
0xC
0x5
+14
0xD
-2
0x6
+12
0xE
-4
0x7
+10
0xF
-6
Fix Line Input Volume
0 = Line input to headphone output volume tracks VOLL and VOLR bits.
1 = Line input to headphone output volume fixed at VOLL and VOLR bits.
See the Digital Audio Interface section.
LVOLFIX
registers 0x10 and 0x11 to set the desired volume. See
Table 11.
Playback Volume
The MAX9867 incorporates volume and mute control to
allow level control for the playback audio path. Program
Table 11. Playback Volume Registers
REGISTER
ADDRESS
REGISTER
B7
B6
B5
B4
B3
B2
B1
B0
Left Volume Control
Right Volume Control
0
0
VOLLM
VOLRM
VOLL
VOLR
0x10
0x11
______________________________________________________________________________________ 37
Ultra-Low Power Stereo Audio Codec
Table 11. Playback Volume Registers (continued)
BITS
FUNCTION
Left/Right Playback Mute
VOLLM and VOLRM mute both the DAC and line input audio signals.
0 = Audio playback is unmuted.
1 = Audio playback is muted
VOLLM/VOLRM
Note: VSEN has no effect on the mute function. When VOLLM or VOLRM is set, the output is muted
immediately (ZDEN = 1) or at the next zero-crossing (ZDEN = 0).
MAX9867
Left/Right Playback Volume
VOLL and VOLR control the playback volume for both the DAC and line input audio signals.
SETTING
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
GAIN (dB)
SETTING
0x0E
0x0F
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x18
0x19
0x1A
0x1B
GAIN (dB)
-5
SETTING
0x1C
0x1D
0x1E
0x1F
0x20
0x21
0x22
0x23
0x24
0x25
0x26
0x27
GAIN (dB)
-42
+6
+5.5
+5
+4.5
+4
+3.5
+3
+2
+1
0
-6
-8
-46
-50
-54
-58
-62
-66
-70
-74
-10
-12
-14
-16
-18
-20
-22
-26
-30
-34
-38
VOLL/VOLR
-78
-82
-84
-1
-2
-3
-4
0x28 to 0x3F
MUTE
Note: Gain settings apply when the headphone amplifier is configured in differential mode. In the single-
ended and capacitorless modes, the actual gain is 5dB lower for each setting.
the ADCs. The first stage offers selectable 0dB, 20dB,
or 30dB settings. The second stage is a programmable
gain amplifier (PGA) adjustable from 0dB to 20dB in
1dB steps. Zero-crossing detection is included on the
PGA to minimize zipper noise while making gain
changes. See Figure 5 for a detailed diagram of the
microphone input structure. Table 12 is the microphone
input register.
Microphone Inputs
Two differential microphone inputs and a low-noise micro-
phone bias for powering the microphones are provided
by the MAX9867. In typical applications, the left micro-
phone records a voice signal and the right microphone
records a background noise signal. In applications that
require only one microphone, use the left microphone
input and disable the right ADC. The microphone signals
are amplified by two stages of gain and then routed to
Table 12. Microphone Input Register
REGISTER
ADDRESS
REGISTER
B7
B6
B5
B4
B3
B2
B1
B0
Left Microphone Gain
Right Microphone Gain
0
0
PALEN
PAREN
PGAML
PGAMR
0x12
0x13
38 ______________________________________________________________________________________
Ultra-Low Power Stereo Audio Codec
MAX9867
Table 12. Microphone Input Register (continued)
BITS
FUNCTION
Left/Right Microphone Preamplifier Gain
Enables the microphone circuitry and sets the preamplifier gain.
00 = Disabled
01 = 0dB
PALEN/PAREN
10 = +20dB
11 = +30dB
Left/Right Microphone Programmable Gain Amplifier
SETTING
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
GAIN (dB)
+20
SETTING
0x0B
0x0C
0x0D
0x0E
0x0F
GAIN (dB)
+9
+8
+7
+6
+5
+4
+3
+2
+1
+19
+18
+17
PGAML/PGAMR
+16
+15
0x10
+14
0x11
+13
0x12
+12
0x13
+10
0x14
to 0x1F
0
+11
MAX9867
1.5V
MICBIAS
0/20/30dB
V
REG
0dB TO +20dB
MICLP
MICLN
ADC
L
PREAMP
-
PGA
0/20/30dB
V
REG
0dB TO +20dB
PGA
MICRP
MICRN
ADC
R
PREAMP
Figure 5. Microphone Input Signal Path
______________________________________________________________________________________ 39
Ultra-Low Power Stereo Audio Codec
ADC
Table 13. AUX ADC Wait Times
The MAX9867 includes two 16-bit ADCs. The first ADC
is used to record left-channel microphone and line-input
audio signals. The second ADC can be used to record
right-channel microphone and line-input signals, or it
can be configured to accurately measure DC voltages.
WAIT TIMES
LRCLK (kHz)
WAIT TIME (ms)
48
44.1
32
40
44
When measuring DC voltages, both the left and right
ADCs must be enabled by setting ADLEN and ADREN
in register 0x17. The input to the second ADC is JACK-
SNS/AUX and the output is reported in AUX (registers
0x02 and 0x03). Since the audio ADC is used to per-
form the measurement, the digital audio interface must
be properly configured. If the left ADC is being used to
convert audio, the DC measurement is performed at the
same sample rate. When not using the left ADC, config-
ure the digital interface for a 48kHz sample rate to
ensure the fastest possible settling time.
60
24
80
MAX9867
22.05
16
90
120
160
175
240
12
11.025
8
1) Enable the AUX input (AUXEN = 1).
2) Enable the offset calibration (AUXCAL = 1).
3) Wait the appropriate time (see Table 13).
4) Complete calibration (AUXCAL = 0).
To ensure accurate results, the MAX9867 includes two
calibration routines. Calibrate the ADC each time the
MAX9867 is powered on. Calibration settings are not
lost if the MAX9867 is placed in shutdown. When mak-
ing a measurement, set AUXCAP to 1 to prevent AUX
from changing while reading the registers.
Gain Calibration Procedure
Perform the following steps the first time a DC measure-
ment is taken after applying power to the MAX9867 or if
the temperature changes significantly:
Setup Procedure
1) Ensure a valid MCLK signal is provided and config-
ure PSCLK appropriately.
1) Enable the AUX input (AUXEN = 1).
2) Choose a clocking mode. The following options are
possible:
2) Start gain calibration (AUXGAIN = 1).
3) Wait the appropriate time (see Table 13).
4) Freeze the measurement results (AUXCAP = 1).
• Slave mode with LRCLK and BCLK signals pro-
vided. The measurement sample rate is deter-
mined by the external clocks.
5) Read AUX and store the value in memory to correct
all future measurements (k = AUX[15:0], k is typical-
ly 19500).
• Slave mode with no LRCLK and BCLK signals
provided. Configure the device for normal clock
mode using the NI ratio. Select fS = 48kHz to allow
for the fastest settling times.
6) Complete calibration (AUXGAIN = AUXCAP = 0).
DC Measurement Procedure
Perform the following steps after offset and gain cali-
bration are complete:
• Master mode with audio. Configure the device in
normal mode using the NI ratio or exact integer
mode using FREQ as required by the audio signal.
1) Enable the AUX input (AUXEN = 1).
• Master mode without audio. Configure the
device in normal mode using the NI ratio. Select fS
= 48kHz to allow for the fastest settling times.
2) Wait the appropriate time (see Table 13).
3) Freeze the measurement results (AUXCAP = 1).
3) Ensure JACKSNS is disabled.
4) Read AUX and correct with the gain calibration
value:
4) Enable the left and right ADC; take the MAX9867 out
of shutdown.
AUX[15:0]
k
⎛
⎝
⎞
V
= 0.738
⎜
⎟
⎠
AUX
Offset Calibration Procedure
Perform the following steps before the first DC mea-
surement is taken after applying power to the
MAX9867:
5) Complete measurement (AUXCAP = 0).
40 ______________________________________________________________________________________
Ultra-Low Power Stereo Audio Codec
MAX9867
Complete DC Measurement Example
b. Wait 40ms.
MCLK = 13MHz, slave mode, BCLK and LRCLK not
externally supplied:
c. Freeze the measurement results (AUXCAP = 1).
d. Read AUX and store the value in memory to cor-
rect all future measurements (k = AUX[15:0]).
1) Configure the digital audio interface for fS = 48kHz
(PSCLK = 01, FREQ = 0x0, PLL = 0, NI = 0x5ABE,
MAS = 0).
e. Complete calibration (AUXGAIN = AUXCAP =
AUXEN = 0).
2) Disable JACKSNS (JDETEN = 0).
6) Measure the voltage on JACKSNS/AUX:
a. Enable the AUX input (AUXEN = 1).
b. Wait 40ms.
3) Enable the left and right ADC; take the MAX9867 out
of shutdown (ADLEN = ADREN = SHDN = 1).
4) Calibrate the offset:
c. Freeze the measurement results (AUXCAP = 1).
a. Enable the AUX input (AUXEN = 1).
b. Enable the offset calibration (AUXCAL = 1).
c. Wait 40ms.
d. Read AUX and correct with the gain calibration
value.
e. Complete measurement (AUXCAP = 0).
7) DC measurement complete.
d. Complete calibration (AUXCAL = 0).
5) Calibrate the gain:
a. Start gain calibration (AUXGAIN = 1).
Table 14. ADC Input Register
REGISTER
ADDRESS
REGISTER
ADC Input
B7
B6
B5
B4
B3
B2
B1
B0
MXINL
MXINR
AUXCAP AUXGAIN AUXCAL
AUXEN
0x14
BITS
FUNCTION
Left/Right ADC Audio Input Mixer
00 = No input is selected.
01 = Left/right analog microphone
10 = Left/right line input
11 = Left/right analog microphone + line input
MXINL/MXINR
Note: If the right-line input is disabled, then the left-line input is connected to both mixers. Enabling the
left and right digital microphones disables the left and right audio mixers, respectively. See DIGMICL/
DIGMICR in Table 15 for more details.
Auxiliary Input Capture
AUXCAP
0 = Update AUX with the voltage at JACKSNS/AUX.
1 = Hold AUX for reading.
Auxiliary Input Gain Calibration
0 = Normal operation
AUXGAIN
1 = The input buffer is disconnected from JACKSNS/AUX and connected to an internal voltage reference.
While in this mode, read the AUX register and store the value. Use the stored value as a gain
calibration factor, K, on subsequent readings.
Auxiliary Input Offset Calibration
0 = Normal operation
AUXCAL
AUXEN
1 = JACKSNS/AUX is disconnected from the input and the ADC automatically calibrates out any internal
offsets.
Auxiliary Input Enable
0 = Use JACKSNS/AUX for jack detection.
1 = Use JACKSNS/AUX for DC measurements.
Note: For AUXEN = 1, set MXINR = 00, ADLEN = 1, and ADREN = 1.
______________________________________________________________________________________ 41
Ultra-Low Power Stereo Audio Codec
phone input. The right analog microphone input is still
Digital Microphone Input
The MAX9867 can accept audio from up to two digital
microphones. When using digital microphones, the left
analog microphone input is retasked as a digital micro-
available to allow a combination of analog and digital
microphones to be used. Figure 6 shows the digital
microphone interface timing diagram. See Table 15.
Table 15. Digital Microphone Input Register
REGISTER
ADDRESS
REGISTER
Microphone
B7
B6
B5
B4
B3
B2
B1
B0
MAX9867
MICCLK
DIGMICL DIGMICR
0
0
0
0
0x15
BITS
FUNCTION
Digital Microphone Clock
00 = PCLK/8
MICCLK
01 = PCLK/6
10 = Reserved
11 = Reserved
Digital Left/Right Microphone Enable
DIGMICL
DIGMICR
Left ADC Input
Right ADC Input
0
0
ADC input mixer
ADC input mixer
Line input (left analog
microphone unavailable)
Left digital microphone
DIGMICL/DIGMICR
0
1
Right digital microphone
1
1
0
1
ADC input mixer
Left digital microphone Right digital microphone
Note: The left analog microphone input is never available when DIGMICL or DIGMICR = 1.
1/f
MICCLK
DIGMICCLK
t
t
t
t
SU, MIC
HD, MIC
SU, MIC
HD, MIC
DIGMICDATA
LEFT
RIGHT
LEFT
RIGHT
Figure 6. Digital Microphone Timing Diagram
42 ______________________________________________________________________________________
Ultra-Low Power Stereo Audio Codec
MAX9867
Powered-On Headset Detection
When the MAX9867 is in normal operation and the micro-
phone interface is enabled, jack insertion and removal can
be detected through the JACKSNS/AUX pin. As shown in
Figure 7, VMIC is pulled up by MICBIAS. When a micro-
phone is connected, VMIC is assumed to be between 0V
and 95% of VMICBIAS. If the jack is removed, VMIC increas-
es to VMICBIAS. This event causes JKMIC to be set, alert-
ing the system that the headset has been removed.
Alternatively, if the jack is inserted, VMIC decreases to
below 95% of VMICBIAS and JKMIC is cleared, alerting the
system that a jack has been inserted. The JKMIC bit can
be configured to create a hardware interrupt that alerts the
microcontroller of jack removal and insertion events.
Mode Configuration
The MAX9867 includes circuitry to minimize click-and-
pop during volume changes, detect headsets, and con-
figure the headphone amplifier mode. Both volume
slewing and zero-crossing detection are included to
ensure click-and-pop free volume transitions. Table 16
is the mode configuration register.
Headset Detection Overview
The MAX9867 features headset detection that can detect
the insertion and removal of a jack as well as the load
type. When a jack is detected, an interrupt on IRQ can be
triggered to alert the microcontroller of the event. Figure 7
shows the typical configuration for jack detection.
Sleep-Mode Headset Detection
When the MAX9867 is in shutdown and the power supply
is available, sleep-mode headset detection can be
enabled to detect jack insertion. Sleep mode applies a
4µA pullup current to JACKSNS/AUX and LOUTP that
forces the voltage on JACKSNS/AUX and LOUTP to
AVDD when no load is applied. When a jack is inserted,
either JACKSNS, LOUTP (assuming the headphone
amplifier is not configured in single-ended mode), or both
are loaded sufficiently to reduce the output voltage to
nearly 0V and clear the JKSNS or LSNS bits, respectively.
The change in the LSNS and JKSNS bits sets JDET and
triggers an interrupt on IRQ if IJDET is set. The interrupt
signals the microcontroller that a jack has been inserted,
allowing the microcontroller to respond as desired.
Headphone Modes
The headphone amplifier supports differential, single-
ended, and capacitorless output modes, as shown in
Figure 8. In each mode, the amplifier can be configured
for stereo or mono operation. The differential and
capacitorless modes are inherently click and pop free.
The single-ended mode optionally includes click-and-
pop reduction to eliminate the click and pop that would
normally be caused by the output coupling capacitor.
When click-and-pop reduction is not required in the sin-
gle-ended configuration, leave LOUTN and ROUTN
unconnected.
LOUTP
MICBIAS
GND
MIC
HPR
HPL
JACKSNS/AUX
ROUTP
MICLP
LOUTN
Figure 7. Typical Configuration for Headset Detection
DIFFERENTIAL
CAPACITORLESS
LOUTP
SINGLE ENDED
220µF
LOUTP
LOUTN
LOUTP
LOUTN
LOUTN
1µF
220µF
ROUTP
ROUTN
ROUTP
ROUTN
ROUTP
ROUTN
1µF
OPTIONAL COMPONENTS REQUIRED FOR CLICK AND POP SUPPRESSION ONLY
Figure 8. Headphone Amplifier Modes
______________________________________________________________________________________ 43
Ultra-Low Power Stereo Audio Codec
Table 16. Mode Configuration Register
REGISTER
ADDRESS
REGISTER
B7
B6
B5
B4
B3
B2
B1
B0
Mode
DSLEW
VSEN
ZDEN
0
JDETEN
HPMODE
0x16
BITS
FUNCTION
Digital Volume Slew Speed
MAX9867
DSLEW
0 = Digital volume changes are slewed over 10ms.
1 = Digital volume changes are slewed over 80ms.
Volume Change Smoothing
VSEN
ZDEN
0 = Volume changes slew through all intermediate values.
1 = Volume changes occur in one step.
Line Input Zero-Crossing Detection
0 = Line input volume changes occur at zero crossings in the audio waveform or after 62ms if no zero
crossing occurs.
1 = Line-input volume changes occur immediately.
Jack Detection Enable
SHDN = 0: Sleep Mode
Enables pullups on LOUTP and JACKSNS/AUX to detect jack insertion. LSNS and JKSNS are valid.
LOUTP detection is only valid in differential and capacitorless output modes.
SHDN = 1: Normal Mode
JDETEN
Enables the comparator circuitry on JACKSNS/AUX to detect voltage changes. JKMIC is valid if the
microphone circuitry is enabled.
Note: AUXEN must be set to 0 for jack detection to function.
Headphone Amplifier Mode
HPMODE
Mode
000
Stereo differential (clickless)
001
Mono (left) differential (clickless)
Stereo capacitorless (clickless)
Mono (left) capacitorless (clickless)
Stereo single-ended (clickless)
Mono (left) single-ended (clickless)
Stereo single-ended (fast turn-on)
Mono (left) single-ended (fast turn-on)
010
HPMODE
011
100
101
110
111
Note: In mono operation, the right amplifier is disabled.
44 ______________________________________________________________________________________
Ultra-Low Power Stereo Audio Codec
MAX9867
Power Management
The MAX9867 includes complete power management
control to minimize power usage. The DAC and both
ADC can be independently enabled so that only the
required circuitry is active. Toggle the SHDN bit when-
ever a configuration change is made. Table 17 is the
power-management register.
Table 17. Power-Management Register
REGISTER
ADDRESS
REGISTER
B7
B6
B5
B4
B3
B2
B1
B0
System Shutdown
SHDN
LNLEN
LNREN
0
DALEN
DAREN
ADLEN
ADREN
0x17
BITS
FUNCTION
Shutdown
SHDN
Places the device in low-power shutdown mode.
Left-Line Input Enable
Enables the left-line input preamp and automatically enables the left and right headphone amplifiers.
If LNREN = 0, the left-line input signal is also routed to the right ADC input mixer and right headphone
amplifier.
LNLEN
Note: Control of the right headphone amplifier can be overridden by HPMODE.
Right-Line Input Enable
LNREN
DALEN
Enables the right-line input preamp and automatically enables the right headphone amplifier.
Note: Control of the right headphone amplifier can be overridden by HPMODE.
Left DAC Enable
Enables the left DAC and automatically enables the left and right headphone amplifiers. If DAREN = 0, the
left DAC signal is also routed to the right headphone amplifier.
Note: Control of the right headphone amplifier can be overridden by HPMODE.
Right DAC Enable
2
DAREN
ADLEN
Enabling the right DAC must be done in the same I C write operation that enables the left DAC. Right
DAC operation requires DALEN = 1.
Left ADC Enable
Right ADC Enable
2
Enabling the right ADC must be done in the same I C write operation that enables the left ADC. The right
ADREN
ADC can be enabled while the left ADC is running if used for DC measurements. SHDN must be toggled
to disable the right ADC in this case. Right ADC operation requires ADLEN = 1.
Revision Code
The MAX9867 includes a revision code to allow easy
identification of the device revision. The revision code is
0x42. See Table 18 for the revision code register.
Table 18. Revision Code Register
REGISTER
ADDRESS
REGISTER
Revision
B7
B6
B5
B4
B3
B2
B1
B0
REV
0xFF
______________________________________________________________________________________ 45
Ultra-Low Power Stereo Audio Codec
2
required on SCL if there are multiple masters on the bus,
I C Serial Interface
The MAX9867 features an I2C/SMBus-compatible,
2-wire serial interface consisting of a serial-data line
(SDA) and a serial-clock line (SCL). SDA and SCL facili-
tate communication between the MAX9867 and the mas-
ter at clock rates up to 400kHz. Figure 9 shows the
2-wire interface timing diagram. The master generates
SCL and initiates data transfer on the bus. The master
device writes data to the MAX9867 by transmitting the
proper slave address followed by the register address
and then the data word. Each transmit sequence is
framed by a START (S) or REPEATED START (Sr) condi-
tion and a STOP (P) condition. Each word transmitted to
the MAX9867 is 8 bits long and is followed by an
acknowledge clock pulse. A master reading data from
the MAX9867 transmits the proper slave address
followed by a series of nine SCL pulses. The MAX9867
transmits data on SDA in sync with the master-generated
SCL pulses. The master acknowledges receipt of each
byte of data. Each read sequence is framed by a START
or REPEATED START condition, a not acknowledge, and
a STOP condition. SDA operates as both an input and an
open-drain output. A pullup resistor, typically greater
than 500Ω is required on SDA. SCL operates only as an
input. A pullup resistor, typically greater than 500Ω, is
or if the single master has an open-drain SCL output.
Series resistors in line with SDA and SCL are optional.
Series resistors protect the digital inputs of the
MAX9867 from high-voltage spikes on the bus lines, and
minimize crosstalk, and undershoot of the bus signals.
Bit Transfer
One data bit is transferred during each SCL cycle. The
data on SDA must remain stable during the high period
of the SCL pulse. Changes in SDA while SCL is high
are control signals. See the START and STOP
Conditions section.
MAX9867
START and STOP Conditions
SDA and SCL idle high when the bus is not in use. A
master initiates communication by issuing a START con-
dition. A START condition is a high-to-low transition on
SDA with SCL high. A STOP condition is a low-to-high
transition on SDA while SCL is high (Figure 10). A START
condition from the master signals the beginning of a
transmission to the MAX9867. The master terminates
transmission, and frees the bus, by issuing a STOP con-
dition. The bus remains active if a REPEATED START
condition is generated instead of a STOP condition.
SDA
t
BUF
t
SU, STA
t
SU, DAT
t
HD, STA
t
SP
t
LOW
t
SU, STO
t
HD, DAT
t
SCL
HIGH
t
HD, STA
t
R
t
F
START CONDITION
REPEATED START CONDITION
STOP
CONDITION
START
CONDITION
Figure 9. 2-Wire Interface Timing Diagram
S
Sr
P
SCL
SDA
Figure 10. START, STOP, and REPEATED START Conditions
46 ______________________________________________________________________________________
Ultra-Low Power Stereo Audio Codec
MAX9867
Early STOP Conditions
The MAX9867 recognizes a STOP condition at any
point during data transmission except if the STOP con-
dition occurs in the same high pulse as a START condi-
tion. For proper operation, do not send a STOP
condition during the same SCL high pulse as the
START condition.
down SDA during the entire master-generated 9th clock
pulse if the previous byte is successfully received.
Monitoring ACK allows for detection of unsuccessful
data transfers. An unsuccessful data transfer occurs if
a receiving device is busy or if a system fault has
occurred. In the event of an unsuccessful data transfer,
the bus master retries communication. The master pulls
down SDA during the 9th clock cycle to acknowledge
receipt of data when the MAX9867 is in read mode. An
acknowledge is sent by the master after each read byte
to allow data transfer to continue. A not acknowledge is
sent when the master reads the final byte of data from
the MAX9867, followed by a STOP condition.
Slave Address
The slave address is defined as the 7 most significant
bits (MSBs) followed by the read/write bit. For the
MAX9867, the 7 most significant bits are 0011000.
Setting the read/write bit to 1 (slave address = 0x31)
configures the MAX9867 for read mode. Setting the
read/write bit to 0 (slave address = 0x30) configures
the MAX9867 for write mode. The address is the first
byte of information sent to the MAX9867 after the
START condition.
Write Data Format
A write to the MAX9867 includes transmission of a
START condition, the slave address with the R/W bit set
to 0, 1 byte of data to configure the internal register
address pointer, 1 or more bytes of data, and a STOP
condition. Figure 12 illustrates the proper frame format
for writing 1 byte of data to the MAX9867. Figure 13
illustrates the frame format for writing n bytes of data to
the MAX9867.
Acknowledge
The acknowledge bit (ACK) is a clocked 9th bit that the
MAX9867 uses to handshake receipt each byte of data
when in write mode (see Figure 11). The MAX9867 pulls
CLOCK PULSE FOR
ACKNOWLEDGMENT
START
CONDITION
SCL
1
2
9
NOT ACKNOWLEDGE
SDA
ACKNOWLEDGE
Figure 11. Acknowledge
ACKNOWLEDGE FROM MAX9867
B7 B6 B5 B4 B3 B2 B1 B0
ACKNOWLEDGE FROM MAX9867
ACKNOWLEDGE FROM MAX9867
REGISTER ADDRESS
A
P
S
SLAVE ADDRESS
0
A
A
DATA BYTE
1 BYTE
R/W
AUTOINCREMENT INTERNAL
REGISTER ADDRESS POINTER
Figure 12. Writing 1 Byte of Data to the MAX9867
______________________________________________________________________________________ 47
Ultra-Low Power Stereo Audio Codec
The first byte transmitted from the MAX9867 is the con-
The slave address with the R/W bit set to 0 indicates
that the master intends to write data to the MAX9867.
The MAX9867 acknowledges receipt of the address
byte during the master-generated 9th SCL pulse.
tent of register 0x00. Transmitted data is valid on the
rising edge of SCL. The address pointer autoincre-
ments after each read data byte. This autoincrement
feature allows all registers to be read sequentially within
one continuous frame. A STOP condition can be issued
after any number of read data bytes. If a STOP condi-
tion is issued followed by another read operation, the
first data byte to be read is from register 0x00.
The second byte transmitted from the master config-
ures the MAX9867’s internal register address pointer.
The pointer tells the MAX9867 where to write the next
byte of data. An acknowledge pulse is sent by the
MAX9867 upon receipt of the address pointer data.
MAX9867
The address pointer can be preset to a specific register
before a read command is issued. The master presets
the address pointer by first sending the MAX9867’s
slave address with the R/W bit set to 0 followed by the
register address. A REPEATED START condition is then
sent followed by the slave address with the R/W bit set
to 1. The MAX9867 then transmits the contents of the
specified register. The address pointer autoincrements
after transmitting the first byte.
The third byte sent to the MAX9867 contains the data
that is written to the chosen register. An acknowledge
pulse from the MAX9867 signals receipt of the data byte.
The address pointer autoincrements to the next register
address after each received data byte. This autoincre-
ment feature allows a master to write to sequential regis-
ters within one continuous frame. Figure 13 illustrates
how to write to multiple registers with one frame. The
master signals the end of transmission by issuing a
STOP condition. Register addresses greater than 0x17
are reserved. Do not write to these addresses.
The master acknowledges receipt of each read byte
during the acknowledge clock pulse. The master must
acknowledge all correctly received bytes except the
last byte. The final byte must be followed by a not
acknowledge from the master and then a STOP condi-
tion. Figure 14 illustrates the frame format for reading 1
byte from the MAX9867. Figure 15 illustrates the frame
format for reading multiple bytes from the MAX9867.
Read Data Format
Send the slave address with the R/W bit set to 1 to initi-
ate a read operation. The MAX9867 acknowledges
receipt of its slave address by pulling SDA low during
the 9th SCL clock pulse. A START command followed
by a read command resets the address pointer to reg-
ister 0x00.
ACKNOWLEDGE FROM MAX9867
ACKNOWLEDGE FROM MAX9867
B7 B6 B5 B4 B3 B2 B1 B0
B7 B6 B5 B4 B3 B2 B1 B0
ACKNOWLEDGE FROM MAX9867
SLAVE ADDRESS
ACKNOWLEDGE FROM MAX9867
REGISTER ADDRESS
S
0
A
A
A
DATA BYTE 1
1 BYTE
DATA BYTE n
1 BYTE
A
P
R/W
AUTOINCREMENT INTERNAL
REGISTER ADDRESS POINTER
Figure 13. Writing n Bytes of Data to the MAX9867
NOT ACKNOWLEDGE FROM MASTER
ACKNOWLEDGE FROM MAX9867
SLAVE ADDRESS
ACKNOWLEDGE FROM MAX9867
REGISTER ADDRESS
REPEATED START
ACKNOWLEDGE FROM MAX9867
Sr SLAVE ADDRESS
A
P
S
0
A
A
1
A
DATA BYTE
1 BYTE
R/W
R/W
AUTOINCREMENT INTERNAL
REGISTER ADDRESS POINTER
Figure 14. Reading 1 Byte of Data from the MAX9867
48 ______________________________________________________________________________________
Ultra-Low Power Stereo Audio Codec
MAX9867
ACKNOWLEDGE FROM MAX9867
SLAVE ADDRESS
ACKNOWLEDGE FROM MAX9867
REGISTER ADDRESS
ACKNOWLEDGE FROM MAX9867
Sr SLAVE ADDRESS
A
P
S
0
A
A
1
A
DATA BYTE
1 BYTE
R/W
REPEATED START
R/W
AUTOINCREMENT INTERNAL
REGISTER ADDRESS POINTER
Figure 15. Reading n Bytes of Data from the MAX9867
Connect all digital I/O termination to the ground plane
with minimum path length to DGND. Bypass DVDD and
DVDDIO directly to DGND.
Applications Information
Proper layout and grounding are essential for optimum
performance. When designing a PCB for the MAX9867,
partition the circuitry so that the analog sections of the
MAX9867 are separated from the digital sections. This
ensures that the analog audio traces are not routed
near digital traces.
Route microphone signals from the microphone to the
MAX9867 as a differential pair, ensuring that the posi-
tive and negative signals follow the same path as close-
ly as possible with equal trace length. When using
single-ended microphones or other single-ended audio
sources, ground the negative microphone input as near
as possible to the audio source and then treat the posi-
tive and negative traces as differential pairs.
Use a large continuous ground plane on a dedicated
layer of the PCB to minimize loop areas. Connect
AGND and DGND directly to the ground plane using
the shortest trace length possible. Proper grounding
improves audio performance, minimizes crosstalk
between channels, and prevents any digital noise from
coupling into the analog audio signals.
The MAX9867 TQFN package features an exposed
thermal pad on its underside. Connect the exposed
thermal pad to AGND.
An evaluation kit (EV Kit) is available to provide an
example layout for the MAX9867. The EV kit allows
quick setup of the MAX9867 and includes easy-to-use
software, allowing all internal registers to be controlled.
Ground the bypass capacitors on MICBIAS, REG,
PREG, and REF directly to the ground plane with mini-
mum trace length. Also be sure to minimize the path
length to AGND. Bypass AVDD directly to AGND.
______________________________________________________________________________________ 49
Ultra-Low Power Stereo Audio Codec
Functional Diagram/Typical Operating Circuit
1.7V–3.6V
1.8V
1.8V
1.8V
SYSTEM
CLOCK
TO PROCESSOR
TO PROCESSOR
1µF
1µF
1µF
1µF
1µF
26
(E1)
4
(C3)
3
2
31
(B2)
30
(B1)
29
28
27
(D1)
32
(A1)
5
(A4)
7
(A5)
23
(E2)
(A3)
(B3)
(C1)
(C2)
DVDDIO
IRQ
SDA
SCL
MCLK
BCLK
LRCLK
SDIN SDOUT
DVDD
AVDD
PREG
PVDD
6
(B4)
2.2µF
1µF
REF
REG
REF
8
(B5)
CLOCK
GEN
DIGITAL AUDIO
INTERFACE
LINEAR
REG
2
I C
MAX9867
VCM
PREG
10
(B6)
DVST:
0dB TO -60dB
1µF
MICBIAS
DSTS
MAX9867
2.2kΩ
PALEN:
0/20/30dB
PGAML:
+20dB TO 0dB
12
(C6)
MICLP/
DIGMICDATA
0.22µF
0.22µF
AVL:
+3dB TO -12dB
DACG:
DACA:
VOLL:
+6dB TO -84dB
MXINL
0/6/12/18dB 0dB TO -15dB
22
LOUTP (E3)
DIGITAL
FILTERING
DIGITAL
FILTERING
ADCL
DACL
11 MICLN/
(C5) DIGMICCLK
2.2kΩ
2.2kΩ
LOUTN 21
(D2)
DMONO
DACG:
DACA:
VOLR:
+6dB TO -84dB
19
0/6/12/18dB 0dB TO -15dB
ROUTP (D3)
DIGITAL
FILTERING
DACR
PAREN:
0/20/30dB
PGAMR:
+20dB TO 0dB
13
(C4)
0.22µF
AVR:
+3dB TO -12dB
ROUTN 20
(E4)
MICRP
MXINR
DIGITAL
FILTERING
ADCR
14 MICRN
(D6)
0.22µF
0.47µF
2.2kΩ
LIGL:
+24dB TO -6dB
VOLL, LVOLFIX:
+6dB TO -84dB
15
JACKSNS/ 17
AUX (D4)
(D5)
LINL
LINR
JACK
DETECT
LIGR:
+24dB TO -6dB
VOLR, LVOLFIX:
+6dB TO -84dB
16
(E6)
0.47µF
DGND
AGND
9
PGND
18
1
(A2)
(A6)
(E5)
() WLP PACKAGE
50 ______________________________________________________________________________________
Ultra-Low Power Stereo Audio Codec
MAX9867
Pin Configurations
TOP VIEW
(BUMP SIDE DOWN)
MAX9867
TOP VIEW
1
2
3
4
5
6
24 23 22 21 20 19 18 17
DVDD
DGND
SDA
AVDD
PREG
AGND
16
15
N.C. 25
DVDDIO 26
LINR
LINL
A
B
C
D
E
BCLK
LRCLK
SDOUT
DVDDIO
MCLK
SDIN
SCL
IRQ
REF
REG
MICLN
LINL
MICBIAS
MICLP
MICRN
LINR
14 MICRN
27
28
29
30
31
32
SDOUT
SDIN
MICRP
13
12
MAX9867
LRCLK
BCLK
MICLP/DIGMICDATA
MICRP
11 MICLN/DIGMICCLK
*EP
10
9
MICBIAS
AGND
MCLK
DVDD
+
LOUTN
PVDD
ROUTP JACKSNS
1
2
3
4
5
6
7
8
LOUTP
ROUTN
PGND
THIN QFN
(5mm × 5mm)
WLP
(2.2mm x 2.7mm)
*EP = EXPOSED PAD
______________________________________________________________________________________ 51
Ultra-Low Power Stereo Audio Codec
Package Information
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in the
package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the
package regardless of RoHS status.
PACKAGE TYPE
30 WLP
PACKAGE CODE
W302A2+3
DOCUMENT NO.
21-0211
32 TQFN-EP
T3255+4
21-0140
MAX9867
52 ______________________________________________________________________________________
Ultra-Low Power Stereo Audio Codec
MAX9867
Package Information (continued)
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in the
package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the
package regardless of RoHS status.
______________________________________________________________________________________ 53
Ultra-Low Power Stereo Audio Codec
Package Information (continued)
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in the
package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the
package regardless of RoHS status.
MAX9867
54 ______________________________________________________________________________________
Ultra-Low Power Stereo Audio Codec
MAX9867
Revision History
REVISION
NUMBER
REVISION
DATE
PAGES
DESCRIPTION
CHANGED
0
1
4/09
5/10
Initial release
Added lead soldering and soldering temperatures, updated V specification
—
2, 8
OS
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 55
© 2010 Maxim Integrated Products
Maxim is a registered trademark of Maxim Integrated Products, Inc.
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