MAX9860ETG+ [MAXIM]
16-Bit Mono Audio Voice Codec; 16位单声道音频编解码器
| 型号： | MAX9860ETG+ |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | 16-Bit Mono Audio Voice Codec |
| 文件： | 总40页 (文件大小：922K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-4349; Rev 1; 9/09
16-Bit Mono Audio Voice Codec
MAX9860
General Description
Features
The MAX9860 is a low-power, voiceband, mono audio
codec designed to provide a complete audio solution
for wireless voice headsets and other mono voice audio
devices. Using an on-chip bridge-tied load mono head-
phone amplifier, the MAX9860 can output 30mW into a
32Ω earpiece while operating from a single 1.8V power
supply. Very low power consumption makes it an ideal
choice for battery-powered applications.
o 1.8V Single-Supply Operation
o Digital Highpass Elliptical Filters with Notch for
217Hz (GSM)
o Mono 30mW BTL Headphone Amplifier
o Dual Low-Noise Microphone Inputs
o Automatic Microphone Gain Control and Noise
The MAX9860’s flexible clocking circuitry utilizes com-
mon system clock frequencies ranging from 10MHz to
60MHz, eliminating the need for an external PLL and
multiple crystal oscillators. Both the ADC and DAC sup-
port sample rates of 8kHz to 48kHz in either synchro-
nous or asynchronous operation. Both master and slave
timing modes are supported.
Gate
o 90dB DAC DR (f = 48kHz)
S
o 81dB ADC DR (f = 48kHz)
S
o Supports Master Clock Frequencies from 10MHz
to 60MHz
o Supports Sample Rates from 8kHz to 48kHz
o Flexible Digital Audio Interface
Two differential microphone inputs are available with a
user-programmable preamplifier and programmable
gain amplifier. Automatic gain control with selectable
attack/release times and signal threshold allows maxi-
mum dynamic range. A noise gate with selectable
threshold provides a means to quiet the channel when
no signal is present. Both the DAC and ADC digital filters
provide full attenuation for out-of-band signals as well as
a 5th order GSM-compliant digital highpass filter. A digi-
tal side tone mixer provides loopback of the micro-
phones/ADC signal to the DAC/headphone output.
o Clickless/Popless Operation
o 2-Wire, I2C-Compatible Control Interface
o Available in 24-Pin, Thin QFN, 4mm x 4mm x
0.8mm Package
Ordering Information
Serial DAC and ADC data is transferred over a flexible
digital I2S-compatible interface that also supports TDM
mode. Mode settings, volume control, and shutdown are
programmed through a 2-wire, I2C-compatible interface.
PART
TEMP RANGE
PIN-PACKAGE
MAX9860ETG+
-40°C to +85°C
24 TQFN-EP*
+Denotes a lead-free/RoHS-compliant package.
*EP = Exposed pad.
The MAX9860 is fully specified over the -40°C to +85°C
extended temperature range and is available in a low-
profile, 4mm x 4mm, 24-pin thin QFN package.
Simplified Block Diagram
DVDDIO
1.7V TO 3.6V
AVDD AND DVDD
1.7V TO 1.9V
Applications
Audio Headsets
Portable Navigation Device
Mobile Phones
2
MAX9860
I C
INTERFACE
Smart Phones
DAC
VoIP Phones
DIGITAL
FILTERING
AND
DIGITAL
AUDIO
INTERFACE
Audio Accessories
DIGITAL AUDIO
INPUT/OUTPUT
DIFF
MIC
ADC
ADC
MIXERS
DIFF
MIC
CLOCK
CONTROL
Pin Configuration and Typical Operating Circuit appear at
end of data sheet.
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
16-Bit Mono Audio Voice Codec
ABSOLUTE MAXIMUM RATINGS
(Voltages referenced to AGND.)
Junction-to-Ambient Thermal Resistance (θ ) (Note 1)
JA
DVDDIO, SDA, SCL, IRQ.......................................-0.3V to +3.6V
AVDD, DVDD............................................................-0.3V to +2V
AGND, DGND, MICGND.......................................-0.3V to +0.3V
OUTP, OUTN, PREG, REF, MICBIAS......-0.3V to (AVDD + 0.3V)
MICLP, MICLN, MICRP, MICRN, REG ....-0.3V to (PREG + 0.3V)
MCLK, LRCLK, BCLK,
24-Pin TQFN (derate 27.8mW/°C above +70°C,
multilayer board) ........................................................36°C/W
Operating Temperature Range ...........................-40°C to +85°C
Storage Temperature Range.............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
SDOUT, SDIN..................................-0.3V to (DVDDIO + 0.3V)
Continuous Power Dissipation (T = +70°C)
A
MAX9860
24-Pin TQFN (derate 27.8mW/°C above +70°C,
multilayer board) ......................................................2222mW
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer
board. For detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial.
ELECTRICAL CHARACTERISTICS
(V
= V
= V
= +1.8V, R = ∞, headphone load (R ) connected between OUTP and OUTN, C
= 2.2µF, C
=
AVDD
DVDD
DVDDIO
L
L
REF
MICBIAS
C
PREG
= C
= 1µF, A
= +20dB, A
= 0dB, MCLK = 13MHz, LRCLK = 8kHz, T = T
to T , unless otherwise noted.
MAX
REG
VPRE
VMICPGA
A
MIN
Typical values are at T = +25°C.) (Note 2)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
AVDD (inferred from HP output PSRR)
1.7
1.8
1.9
DVDD (inferred from codec performance
tests)
Supply Voltage Range
1.7
1.7
1.8
1.9
V
DVDDIO
1.8
3.6
2.2
1.6
5.7
1.0
9.0
1.2
8.0
2.2
5
AVDD
DVDD
AVDD
DVDD
AVDD
DVDD
AVDD
DVDD
AVDD
1.46
1.05
4.08
0.78
6.17
0.8
DAC playback mode
(48kHz)
Full operation
8kHz mono ADC + DAC
Total Supply Current
(Note 3)
I
mA
AVDD+DVDD
Full operation
8kHz stereo ADC + DAC
5.38
1.68
0.56
Stereo ADC only (48kHz)
Shutdown Supply Current
Shutdown to Full Operation
I
T
A
= +25°C
µA
ms
SHDN
DVDD +
DVDDIO
1.65
10
5
DAC (Note 4)
Gain Error
1
5
%
+0dB volume setting, f = 8kHz,
S
Dynamic Range (Note 5)
DAC Full-Scale Output
DR
measured at headphone output,
84
90
dB
T
A
= +25°C
1
V
RMS
f = 1kHz, 0dBFS, HP
filter disabled, digital
input to analog output
f = 8kHz
1.2
S
DAC Path Phase Delay
ms
dB
f = 16kHz
S
0.59
-87
f = 1kHz, MCLK = 12.288MHz,
LRCLK = 48kHz
Total Harmonic Distortion + Noise
THD+N
2
_______________________________________________________________________________________
16-Bit Mono Audio Voice Codec
MAX9860
ELECTRICAL CHARACTERISTICS (continued)
(V
= V
= V
= +1.8V, R = ∞, headphone load (R ) connected between OUTP and OUTN, C
= 2.2µF, C
=
AVDD
DVDD
DVDDIO
L
L
REF
MICBIAS
C
PREG
= C
= 1µF, A
= +20dB, A
= 0dB, MCLK = 13MHz, LRCLK = 8kHz, T = T
to T , unless otherwise noted.
MAX
REG
VPRE
VMICPGA
A
MIN
Typical values are at T = +25°C.) (Note 2)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
f = 1kHz, V
= 100mV
,
RIPPLE
P-P
94
71
A
VPGA
= 0dB
Power-Supply Rejection Ratio
PSRR
dB
f = 10kHz, V
= 100mV
,
RIPPLE
P-P
A
VPGA
= 0dB
DAC LOWPASS DIGITAL FILTER
With respect to f within ripple; f = 8kHz
to 48kHz
0.448 x
S
S
Hz
f
S
Passband Cutoff
f
PLP
-3dB cutoff
0.451
0.1
f
S
Passband Ripple
Stopband Cutoff
f < f
dB
Hz
dB
PLP
0.476 x
f
With respect to f ; f = 8kHz to 48kHz
S S
SLP
f
S
Stopband Attenuation
f > f , f = 20Hz to 20kHz
SLP
75
DAC HIGHPASS DIGITAL FILTER
DVFLT = 0x1
0.0161
(elliptical for 16kHz GSM)
x f
S
DVFLT = 0x2
(500Hz Butterworth for 16kHz)
0.0312
x f
S
5th Order Passband Cutoff
(-3dB from Peak, I C Register
Programmable) (Note 6)
DVFLT = 0x3
(elliptical for 8kHz GSM)
0.0321
x f
2
f
Hz
DHPPB
S
DVFLT = 0x4
(500Hz Butterworth for 8kHz)
0.0625
x f
S
DVFLT = 0x5
(200Hz Butterworth for 48kHz)
0.0042
x f
S
DVFLT = 0x1
(elliptical for 16kHz GSM)
0.0139
x f
S
DVFLT = 0x2
(500Hz Butterworth for 16kHz)
0.0156
x f
S
5th Order Stopband Cutoff
(-30dB from Peak, I C Register
Programmable) (Note 6)
DVFLT = 0x3
(elliptical for 8kHz GSM)
0.0279
x f
2
f
Hz
dB
DHPSB
S
DVFLT = 0x4
(500Hz Butterworth for 8kHz)
0.0312
x f
S
DVFLT = 0x5
(200Hz Butterworth for 48kHz)
0.0021
x f
S
DC Blocking
DC
DVFLT ≠ 0x0
90
Atten
ADC
Differential MIC Input, A
= 0dB,
VPRE
Full-Scale Input Voltage
Channel Gain Mismatch
0dBFS
1
V
P-P
A
VPGA
= 0dB
0.3
%
_______________________________________________________________________________________
3
16-Bit Mono Audio Voice Codec
ELECTRICAL CHARACTERISTICS (continued)
(V
= V
= V
= +1.8V, R = ∞, headphone load (R ) connected between OUTP and OUTN, C
= 2.2µF, C
=
AVDD
DVDD
DVDDIO
L
L
REF
MICBIAS
C
PREG
= C
= 1µF, A
= +20dB, A
= 0dB, MCLK = 13MHz, LRCLK = 8kHz, T = T
to T , unless otherwise noted.
MAX
REG
VPRE
VMICPGA
A
MIN
Typical values are at T = +25°C.) (Note 2)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
f = 8kHz, A
A-weighted from 20Hz to f /2
= 0dB,
VPRE
S
81
Dynamic Range (Note 5)
DR
dB
S
MAX9860
f = 48kHz, A
S
= 0dB, T = +25°C
75
83
VPRE
A
f = 1kHz, 0dBFS, HP filter
disabled, analog input to
digital output
f = 8kHz
1.2
S
ADC Phase Delay
ms
dB
f = 16kHz
S
0.61
-75
Total Harmonic Distortion
THD
f = 1kHz, f = 48kHz, T = +25°C
-70
S
A
f = 1kHz, V
= 100mV
,
RIPPLE
P-P
82
A
VPGA
= 0dB
Power-Supply Rejection Ratio
PSRR
dB
dB
Hz
f = 10kHz, V
= 100mV
,
RIPPLE
P-P
76
A
VPGA
= 0dB
Channel Crosstalk
Driven channel at -1dBFS, f = 1kHz
-92
ADC LOWPASS DIGITAL FILTER
With respect to f within ripple;
S
f = 8kHz to 48kHz
S
0.445 x
f
S
Passband Cutoff
f
PLP
-3dB cutoff
0.449
0.1
f
S
Passband Ripple
Stopband Cutoff
f < f
dB
Hz
dB
PLP
0.469 x
f
With respect to f ; f = 8kHz to 48kHz
S S
SLP
f
S
Stopband Attenuation
f > f
74
SLP
ADC HIGHPASS DIGITAL FILTER
0.0161
AVFLT = 0x1 (elliptical for 16kHz GSM)
x f
S
AVFLT = 0x2 (500Hz Butterworth for
16kHz)
0.0312
x f
S
5th Order Passband Cutoff
(-3dB from Peak, I C Register
Programmable) (Note 6)
0.0321
x f
2
f
AVFLT = 0x3 (elliptical for 8kHz GSM)
Hz
AHPPB
S
AVFLT = 0x4
(500Hz Butterworth for 8kHz)
0.0625
x f
S
AVFLT = 0x5
(200Hz Butterworth for 48kHz)
0.0042
x f
S
4
_______________________________________________________________________________________
16-Bit Mono Audio Voice Codec
MAX9860
ELECTRICAL CHARACTERISTICS (continued)
(V
= V
= V
= +1.8V, R = ∞, headphone load (R ) connected between OUTP and OUTN, C
= 2.2µF, C
=
AVDD
DVDD
DVDDIO
L
L
REF
MICBIAS
C
PREG
= C
= 1µF, A
= +20dB, A
= 0dB, MCLK = 13MHz, LRCLK = 8kHz, T = T
to T , unless otherwise noted.
MAX
REG
VPRE
VMICPGA
A
MIN
Typical values are at T = +25°C.) (Note 2)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
0.0139
x f
MAX
UNITS
AVFLT = 0x1
(elliptical for 16kHz GSM)
S
AVFLT = 0x2
(500Hz Butterworth for 16kHz)
0.0156
x f
S
5th Order Stopband Cutoff
(-30dB from peak, I C Register
Programmable) (Note 6)
AVFLT = 0x3
(elliptical for 8kHz GSM)
0.0279
x f
2
f
Hz
AHPSB
S
AVFLT = 0x4
(500Hz Butterworth for 8kHz)
0.0312
x f
S
AVFLT = 0x5
(200Hz Butterworth for 48kHz)
0.0021
x f
S
DC Blocking
DC
AVFLT ≠ 0x0
90
dB
ATTEN
CLOCKING
MCLK is not required to be synchronous
or related to the desired LRCLK data rate
MCLK Input Frequency
10
40
60
60
MHz
%
MCLK Duty Cycle
50
Maximum MCLK Input Jitter
LRCLK Data Rate Frequency
LRCLK PLL Lock Time
For guaranteed performance limits
100
ps
RMS
8
48
25
kHz
12
20
ms
LRCLK Acceptable Jitter for
Maintaining PLL Lock
ns
MONO HEADPHONE AMPLIFIER
R = 16Ω
30
50
33
L
f = 1kHz, THD+N ≤ 1%
= +25°C
Output Power
P
mW
%
OUT
T
A
R = 32Ω
L
R = 32Ω, P
= 25mW, f = 1kHz
= 25mW, f = 1kHz
0.05
0.08
L
OUT
Total Harmonic Distortion + Noise
Dynamic Range (Note 5)
THD+N
DR
R = 16Ω, P
L
OUT
+0dB volume setting, DAC input at
90
dB
f = 8kHz to 48kHz
S
AVDD = 1.7V to 1.9V
60
84
86
Power-Supply Rejection Ratio
PSRR
V
V
V
= 100mV , f = 217Hz
dB
RIPPLE
RIPPLE
P-P
= 100mV , f = 20kHz
71
P-P
Output Offset Voltage
V
- V T =+25°C
OUTN, A
0.25
500
100
1
mV
pF
OS
OUTP
R = 32Ω
L
Capacitive Drive Capability
No sustained oscillations
R = ∞
L
Peak voltage into/out of shutdown, 32sps,
A-weighted
Click-and-Pop Level
-70
dBV
_______________________________________________________________________________________
5
16-Bit Mono Audio Voice Codec
ELECTRICAL CHARACTERISTICS (continued)
(V
= V
= V
= +1.8V, R = ∞, headphone load (R ) connected between OUTP and OUTN, C
= 2.2µF, C
=
AVDD
DVDD
DVDDIO
L
L
REF
MICBIAS
C
PREG
= C
= 1µF, A
= +20dB, A
= 0dB, MCLK = 13MHz, LRCLK = 8kHz, T = T
to T , unless otherwise noted.
MAX
REG
VPRE
VMICPGA
A
MIN
Typical values are at T = +25°C.) (Note 2)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
MICROPHONE AMPLIFIER
PAM = 00
PAM = 01
Off
0
-0.5
19
+0.5
21
MAX9860
Preamplifier Gain
MIC PGA Gain
A
T
= +25°C
dB
dB
VPRE
A
PAM = 10
PAM = 11
20
30
0
29
31
PGAM = 0x14–0x1F
PGAM = 0x00
A
VMICPGA
CMRR
+20
1
MIC PGA Gain Step Size
dB
dB
Common-Mode Rejection Ratio
V
= 100mV
at 217Hz
50
IN
P-P
All gain settings, measured at
MICLN/MICRN
MIC Input Resistance
MIC Input Bias Voltage
R
30
50
0.8
-75
kΩ
V
IN_MIC
0.7
0.9
A
VPRE
= 0dB, A
= 0dB,
VMICPGA
dB
V
= 1V , f = 1kHz
P-P
IN
Total Harmonic Distortion + Noise
THD+N
PSRR
A
VPRE
= +30dB, A
= 0dB,
VMICPGA
-66
dB
V
= 31mV , f = 1kHz
P-P
IN
AVDD = 1.7V to 1.9V
60
95
82
76
dB
dB
dB
MIC Power-Supply Rejection
Ratio
V
V
= 100mV at 1kHz, input referred
= 100mV at 10kHz, input referred
RIPPLE
RIPPLE
MICROPHONE BIAS
MICBIAS Output Voltage
Load Regulation
V
I
I
= 1mA, T = +25°C
A
1.5
1.55
0.2
82
1.6
10
V
MICBIAS
LRR
LOAD
= 1mA to 2mA
mV
dB
dB
LOAD
V
V
= 100mV
= 100mV
at 217Hz
at 10kHz
RIPPLE
RIPPLE
P-P
P-P
MICBIAS Line Ripple Rejection
81
MICBIAS Noise Voltage
AUTOMATIC GAIN CONTROL
AGC Hold Duration
A-weighted
9.5
µV
RMS
AGCHLD[1:0] setting range, FREQ ≠ 0
AGCATK[1:0] setting range, FREQ ≠ 0
AGCRLS[2:0] setting range, FREQ ≠ 0
AGCSTH[3:0] setting range, FREQ ≠ 0
50
3
400
200
10
ms
AGC Attack Time
ms
s
AGC Release Time
0.078
-3
AGC Threshold Level
NOISE GATE
-18
dB
NG Attack and Release Time
NG Threshold Level
Noise Gate Threshold Step Size
NG Attenuation
0.5
4
s
-72
0
-16
12
0
dB
dB
dB
DIGITAL SIDETONE
Sidetone Gain Adjust
DVST
PDLY
2dB steps
-60
dB
ms
MIC input to headphone
output, f = 1kHz, HP filter
disabled
8kHz
2.2
1.1
Sidetone Phase Delay
16kHz
6
_______________________________________________________________________________________
16-Bit Mono Audio Voice Codec
MAX9860
DIGITAL AUDIO INTERFACE ELECTRICAL CHARACTERISTICS
(V
= V
= 1.8V, unless otherwise noted.) (Note 2)
DVDDIO
DVDD
PARAMETER
SYMBOL
CONDITIONS
MIN
75
TYP
MAX
UNITS
ns
BCLK Cycle Time
BCLK High Time
BCLK Low Time
t
Slave operation
Slave operation
Slave operation
BCLKS
BCLKH
t
30
ns
t
30
ns
BCLKL
BCLK or LRCLK Rise and Fall
Time
t , t
Master operation
ABCI = DBCI = 0
ABCI = DBCI = 1
ABCI = DBCI = 0
ABCI = DBCI = 1
7
ns
ns
ns
ns
ns
ns
R
F
SDIN or LRCLK to BCLK Rising
Setup Time
t
t
25
25
0
SU
SDIN or LRCLK to BCLK Falling
Setup Time
SU
HD
HD
SDIN or LRCLK to BCLK Rising
Hold Time
t
t
SDIN or LRCLK to BCLK Falling
Hold Time
0
SDOUT Delay Time from BCLK
Rising Edge
t
ABCI = DBCI = 0, C = 30pF
0
40
DLY
L
2
I C INTERFACE ELECTRICAL CHARACTERISTICS
(V
= V
= 1.8V, unless otherwise noted.) (Note 2)
DVDDIO
DVDD
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Serial-Clock Frequency
f
0
400
kHz
SCL
Bus Free Time Between STOP
and START Conditions
t
1.3
0.6
µs
µs
BUF
Hold Time (Repeated) START
Condition
t
t
HD,STA
SCL Pulse Width Low
SCL Pulse Width High
t
1.3
0.6
µs
µs
LOW
t
HIGH
Setup Time for a Repeated
START Condition
0.6
µs
SU,STA
Data Hold Time
Data Setup Time
t
0
900
ns
ns
HD,DAT
t
100
SU,DAT
SDA and SCL Receiving
Rise Time
t
C
C
is in pF
is in pF
20 + 0.1C
300
300
ns
ns
R
B
B
B
SDA and SCL Receiving
Fall Time
t
20 + 0.1C
F
B
_______________________________________________________________________________________
7
16-Bit Mono Audio Voice Codec
2
I C INTERFACE ELECTRICAL CHARACTERISTICS (continued)
(V
= V
= 1.8V, unless otherwise noted.) (Note 2)
DVDDIO
DVDD
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
SDA Transmitting
Fall Time
t
C
is in pF
20 + 0.1C
0.6
250
ns
F
B
B
Setup Time for STOP Condition
Bus Capacitance
t
µs
pF
ns
SU,STO
C
400
50
B
MAX9860
Pulse Width of Suppressed Spike
t
0
SP
DIGITAL INPUTS (LRCLK, BCLK, SDIN, MCLK)
0.7
x DVDDIO
Input Voltage High
Input Voltage Low
V
V
V
IH
0.3
x DVDDIO
V
IL
MCLK Input Voltage High
MCLK Input Voltage Low
Input Leakage Current
Input Capacitance
1.4
-1
V
V
0.4
+1
I
, I
IH IL
T
A
= +25°C
µA
pF
3
DIGITAL INPUTS (SCL, SDA)
0.7
x DVDD
Input Voltage High
Input Voltage Low
V
V
V
IH
0.3
x DVDD
V
IL
Input Hysteresis
200
3
mV
µA
pF
Input Leakage Current
Input Capacitance
I
, I
IH IL
T
= +25oC
A
-1
+1
CMOS DIGITAL OUTPUTS (BCLK, LRCLK, SDOUT)
Output Low Voltage
V
I
= 3mA
0.4
V
V
OL
OL
DVDDIO
- 0.4
Output High Voltage
V
I
= 3mA
OH
OL
OPEN-DRAIN DIGITAL OUTPUTS (SDA, IRQ)
Output High Leakage Current
Output Low Voltage
I
V
= DVDDIO, T = +25°C
-1
+1
µA
V
OH
OUT
A
V
I
= 3mA
0.4
OL
OL
Note 2: All devices are 100% production tested at room temperature. All temperature limits are guaranteed by design.
Note 3: Supply current measurements taken with no applied signal at microphone inputs. A digital zero audio signal used for all dig-
ital serial audio inputs. Headphone outputs are loaded as stated in the global conditions.
Note 4: DAC performance is measured at headphone outputs.
Note 5: ADC, DAC, and headphone amplifier dynamic ranges are measured using the EIAJ method. -60dBV 1kHz input signal, A-weight-
ed and normalized to 0dBFS.
Note 6: Notch for GSM filters occurs at 217Hz.
8
_______________________________________________________________________________________
16-Bit Mono Audio Voice Codec
MAX9860
Typical Operating Characteristics
(V
= +1.8V, V
= V
= +1.8V, R = ∞, headphone load (R ) connected between OUTP and OUTN, C
= 2.2µF,
AVDD
DVDD
DVDDIO
L
L
REF
C
PREG
= C
= 1µF, C
= 1µF A
= 0dB, A
= +20dB, MCLK = 13MHz, T = +25°C, unless otherwise noted.)
VPRE A
REG
MICBIAS
VMICPGA
TOTAL HARMONIC DISTORTION + NOISE
vs. OUTPUT POWER (DAC TO HP)
TOTAL HARMONIC DISTORTION + NOISE
vs. OUTPUT POWER (DAC TO HP)
TOTAL HARMONIC DISTORTION + NOISE
vs. FREQUENCY (DAC TO HP)
10
1
10
1
10
R = 32Ω
L
R = 16Ω
L
R = 32Ω
L
1
0.1
f = 3.5kHz
f = 3.5kHz
P
= 5mW
OUT
0.1
0.1
f = 1kHz
f = 1kHz
0.01
0.001
0.01
0.001
0.01
0.001
P
= 20mW
OUT
f = 20kHz
f = 20kHz
0.01
0.1
1
10
0
5
10
15
20
25
30
0
10
20
30
40
50
60
FREQUENCY (kHz)
OUTPUT POWER (mW)
OUTPUT POWER (mW)
TOTAL HARMONIC DISTORTION + NOISE
vs. FREQUENCY (DAC TO HP)
TOTAL HARMONIC DISTORTION + NOISE
vs. FREQUENCY (MICL TO ADC)
TOTAL HARMONIC DISTORTION + NOISE
vs. FREQUENCY (MICL TO ADC)
10
1
10
1
10
1
R = 16Ω
L
MICPRE = +20dB
MICPRE = 0dB
V
= 100mV
V
= 1V
IN
P-P
IN
P-P
P
= 5mW
OUT
0.1
0.1
0.1
0.01
P
= 20mW
OUT
0.01
0.001
0.01
0.001
0.01
0.1
1
10
0.01
0.1
1
10
100
0.01
0.1
1
10
100
FREQUENCY (kHz)
FREQUENCY (kHz)
FREQUENCY (kHz)
TOTAL HARMONIC DISTORTION + NOISE
vs. FREQUENCY (MICL TO ADC)
HEADPHONE OUTPUT POWER
vs. LOAD RESISTANCE
POWER-SUPPLY REJECTION RATIO
vs. FREQUENCY (DAC TO HP)
0
-10
10
1
60
50
40
30
20
10
0
MICPRE = +30dB
V
= 31V
IN
P-P
-20
-30
-40
-50
-60
0.1
-70
-80
-90
0.01
0.001
-100
-110
-120
0.01
0.1
1
10
100
0.01
0.1
1
10
100
0
25
50
75
100
125
150
FREQUENCY (kHz)
FREQUENCY (kHz)
LOAD RESISTANCE (Ω)
_______________________________________________________________________________________
9
16-Bit Mono Audio Voice Codec
Typical Operating Characteristics (continued)
(V
= +1.8V, V
= V
= +1.8V, R = ∞, headphone load (R ) connected between OUTP and OUTN, C
= 2.2µF,
AVDD
DVDD
DVDDIO
L
L
REF
C
PREG
= C
= 1µF, C
= 1µF A
= 0dB, A
= +20dB, MCLK = 13MHz, T = +25°C, unless otherwise noted.)
VPRE A
REG
MICBIAS
VMICPGA
POWER-SUPPLY REJECTION RATIO
vs. FREQUENCY (MIC TO ADC)
0dBFS FFT (DAC TO HP)
-60dBFS FFT (DAC TO HP)
0
-10
20
20
0
MCLK = 13MHz
LRCLK = 8kHz
PLL DISABLED
MCLK = 13MHz
LRCLK = 8kHz
PLL DISABLED
0
-20
-20
8
-20
-40
-60
-80
-100
-120
-140
-30
-40
-40
-50
-60
-60
-70
-80
-80
-90
-100
-120
-140
-100
-110
-120
0.01
0.1
1
10
100
0
5
10
FREQUENCY (kHz)
15
20
0
5
10
FREQUENCY (kHz)
15
20
FREQUENCY (kHz)
0dBFS FFT (DAC TO HP)
-60dBFS FFT (DAC TO HP)
0dBFS FFT (DAC TO HP AMP)
20
0
20
0
20
0
MCLK = 13MHz
LRCLK = 8kHz
PLL ENABLED
MCLK = 12.288MHz
LRCLK = 48kHz
PLL DISABLED
MCLK = 13MHz
LRCLK = 8kHz
PLL ENABLED
-20
-40
-60
-80
-100
-120
-140
-20
-40
-60
-80
-100
-120
-140
-20
-40
-60
-80
-100
-120
-140
0
5
10
FREQUENCY (kHz)
15
20
0
5
10
FREQUENCY (kHz)
15
20
0
5
10
FREQUENCY (kHz)
15
20
-60dBFS FFT (DAC TO HP AMP)
0dBFS FFT (MICL TO ADC)
-60dBFS FFT (MICL TO ADC)
20
0
20
0
20
0
MCLK = 12.288MHz
LRCLK = 48kHz
PLL DISABLED
MCLK = 13MHz
LRCLK = 8kHz
PLL DISABLED
MCLK = 13MHz
LRCLK = 8kHz
PLL DISABLED
-20
-40
-60
-80
-100
-120
-140
-20
-40
-60
-80
-100
-120
-140
-20
-40
-60
-80
-100
-120
-140
0
5
10
15
20
0
1
2
3
4
0
1
2
3
4
FREQUENCY (kHz)
FREQUENCY (kHz)
FREQUENCY (kHz)
10 ______________________________________________________________________________________
16-Bit Mono Audio Voice Codec
MAX9860
Typical Operating Characteristics (continued)
(V
= +1.8V, V
= V
= +1.8V, R = ∞, headphone load (R ) connected between OUTP and OUTN, C
= 2.2µF,
AVDD
DVDD
DVDDIO
L
L
REF
C
PREG
= C
= 1µF, C
= 1µF A
= 0dB, A
= +20dB, MCLK = 13MHz, T = +25°C, unless otherwise noted.)
A
REG
MICBIAS
VMICPGA
VPRE
0dBFS FFT (MICL TO ADC)
-60dBFS FFT (MICL TO ADC)
0dBFS FFT (MICL TO ADC)
20
0
20
20
0
MCLK = 12.288MHz
LRCLK = 48kHz
PLL DISABLED
MCLK = 13MHz
LRCLK = 8kHz
PLL ENABLED
MCLK = 13MHz
LRCLK = 8kHz
PLL ENABLED
0
-20
-20
-40
-60
-80
-100
-120
-140
-20
-40
-60
-80
-100
-120
-140
-40
-60
-80
-100
-120
-140
0
1
2
3
4
0
1
2
3
4
0
5
10
FREQUENCY (kHz)
15
20
FREQUENCY (kHz)
FREQUENCY (kHz)
-60dBFS FFT (MICL TO ADC)
-5dBFS WIDEBAND FFT (DAC TO HP)
-60dBFS WIDEBAND FFT (DAC TO HP)
20
0
20
0
20
0
MCLK = 13MHz
LRCLK = 8kHz
PLL DISABLED
MCLK = 13MHz
LRCLK = 8kHz
PLL DISABLED
MCLK = 12.288MHz
LRCLK = 48kHz
PLL DISABLED
R = 32Ω
L
-20
-40
-60
-80
-100
-120
-140
R = 32Ω
L
-20
-40
-60
-80
-100
-20
-40
-60
-80
-100
0
5
10
FREQUENCY (kHz)
15
20
0.1
1
10
100
1000 10,000
0.1
1
10
100
1000 10,000
FREQUENCY (kHz)
FREQUENCY (kHz)
SUPPLY CURRENT
vs. SUPPLY VOLTAGE
DAC DIGITAL FILTER
FREQUENCY RESPONSE, 8kHz
ADC DIGITAL FILTER
FREQUENCY RESPONSE, 8kHz
10
0
10
0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-10
-20
-30
-40
-50
-60
-70
-80
-90
I
AVDD
FULL-DUPLEX 8kHz MODE
ELLIPTICAL FOR 8kHz GSM WITH
NOTCH AT 217Hz
ELLIPTICAL FOR 8kHz GSM WITH
NOTCH AT 217Hz
I
+ I
DVDD DVDDIO
0.01
0.1
1
10
0.01
0.1
1
10
1.65 1.70 1.75 1.80 1.85 1.90 1.95
SUPPLY VOLTAGE (V)
FREQUENCY (kHz)
FREQUENCY (kHz)
______________________________________________________________________________________ 11
16-Bit Mono Audio Voice Codec
Typical Operating Characteristics (continued)
(V
= +1.8V, V
= V
= +1.8V, R = ∞, headphone load (R ) connected between OUTP and OUTN, C
= 2.2µF,
AVDD
DVDD
DVDDIO
L
L
REF
C
PREG
= C
= 1µF, C
= 1µF A
= 0dB, A
= +20dB, MCLK = 13MHz, T = +25°C, unless otherwise noted.)
A
REG
MICBIAS
VMICPGA
VPRE
HEADPHONE STARTUP WAVEFORM
HEADPHONE SHUTDOWN WAVEFORM
SDA
(2V/div)
SDA
(2V/div)
MAX9860
SPK+ -SPK-
(1V/div)
SPK+ -SPK-
(1V/div)
TIME (4ms/div)
TIME (2ms/div)
SOFT-START ADC
AUTOMATIC GAIN CONTROL THRESHOLDS
10
SDA
(2V/div)
0
-10
-20
-30
-40
-50
-60
-70
-80
ADC OUTPUT
(500mV/div)
TIME (4ms/div)
-100 -90 -80 -70 -60 -50 -40 -30 -20 -10
INPUT AMPLITUDE (dBV)
0
TOTAL HARMONIC DISTORTION + NOISE
vs. MCLK FREQUENCY, 0dBFS (DAC to HP)
DYNAMIC RANGE
vs. MCLK FREQUENCY, -60dBFS (DAC to HP)
NOISE GATE THRESHOLDS
1
0.1
0
-10
-20
-30
-40
-50
-60
-70
-80
0
LRCLK = 8kHz
LRCLK = 8kHz
-10
-20
-30
-40
-50
-60
-70
0.01
0.001
-80
-90
-100
-110
-120
-90
-100
10
20
30
40
50
60
-80
-60
-40
-20
10
20
30
40
50
60
MCLK FREQUENCY (MHz)
INPUT AMPLITUDE (dBV)
MCLK FREQUENCY (MHz)
12 ______________________________________________________________________________________
16-Bit Mono Audio Voice Codec
MAX9860
Pin Description
PIN
NAME
FUNCTION
Microphone Bias. +1.55V microphone bias for internal and/or external microphone. An external resistor from
2.2kΩ to 470Ω should be used to set the microphone current. Bypass to MICGND with a 1µF capacitor.
1
MICBIAS
2
3
REG
PREG
REF
Internal Bias. PREG/2 voltage reference. Bypass to AGND with a 1µF capacitor (+0.8V).
Positive Internal Regulated Supply. Bypass to AGND with a 1µF capacitor (+1.6V).
Converter Reference (1.23V). Bypass to AGND with a 2.2µF capacitor.
Analog Ground
4
5
AGND
AVDD
OUTP
OUTN
SDA
6
Analog Power Supply. Bypass to AGND with 10µF and 0.1µF capacitors.
Positive Headphone Output
7
8
Negative Headphone Output
2
9
I C Serial-Data Input/Output
2
10
11
12
13
14
15
16
17
18
19
SCL
I C Serial-Data Clock
DVDDIO
DGND
DVDD
MCLK
SDOUT
SDIN
Digital Interface Power Supply. Supply for digital audio interface. Bypass to DGND with a 1µF capacitor.
Digital Ground
Digital Core Power Supply. Bypass to DGND with a 1µF capacitor.
Master Clock Input
Serial Audio Interface ADC Data Output
Serial Audio Interface DAC Data Input
LRCLK
BCLK
IRQ
Serial Audio Interface Left/Right Clock
Serial Audio Interface Bit Clock
Interrupt Request. IRQ is an active-low open drain output. Pull up to DVDDIO with a 10kΩ resistor.
Negative Right Microphone Input. AC-couple to low-side of microphone or connect to negative signal.
AC-couple to ground for single-ended operation.
20
21
22
23
MICRN
MICRP
MICLN
MICLP
Positive Right Microphone Input. AC-couple to high-side of microphone or connect to positive signal.
AC-couple the signal for single-ended operation.
Negative Left Microphone Input. AC-couple to low-side of microphone or connect to negative signal.
AC-couple to ground for single-ended operation.
Positive Left Microphone Input. AC-couple to high-side of microphone or connect to positive signal.
AC-couple the signal for single-ended operation.
24
—
MICGND
EP
MICBIAS Ground. Connect to AGND.
Exposed Pad. Connect to AGND.
______________________________________________________________________________________ 13
16-Bit Mono Audio Voice Codec
Integrated digital filtering provides a range of notch and
Detailed Description
highpass filters for both the playback and record paths
to limit undesirable low-frequency signals and GSM
transmission noise. The digital filtering provides attenu-
ation of out-of-band energy by up to 76dB, eliminating
audible aliasing. A digital sidetone function allows
audio from the record path to be summed into the play-
back path after digital filtering.
The MAX9860 is a low-power, voiceband, mono audio
codec designed to provide a complete audio solution
for wireless voice headsets and other mono audio
devices.
The mono playback path accepts digital audio over a
flexible digital audio interface compatible with I2S, TDM,
and left-justified audio signals. An oversampling sigma-
delta DAC converts an incoming digital data stream to
analog audio and outputs through the mono bridge-tied
load headphone amplifier.
The MAX9860’s flexible clock circuitry utilizes a pro-
grammable clock divider and a digital PLL to allow the
DAC and ADC to operate at maximum dynamic range
for all combinations of master clock (MCLK) and sam-
ple rate (LRCLK). Any master clock between 10MHz to
60MHz is supported as are all sample rates from 8kHz
to 48kHz. Master and slave mode are supported for
maximum flexibility.
MAX9860
The stereo record path has two microphone inputs with
selectable gain. The microphones are powered by an
integrated microphone bias. An oversampling sigma-
delta ADC converts the microphone signals and out-
puts the digital bit stream over the digital audio
interface.
2
I C Registers
The MAX9860 audio codec is completely controlled
through software using an I2C interface. The power-on
default setting is software shutdown, requiring that the
internal registers be programmed to activate the device.
See Table 1 for the device’s complete register map.
The record path includes automatic gain control (AGC)
to optimize the signal level and a noise gate to reduce
idle noise. The automatic gain control monitors the out-
puts of the ADC and makes constant adjustments to the
input gain to reduce the dynamic range of the incoming
microphone signal by up to 20dB. The noise gate cor-
rects for the increase in noise typically associated with
AGC by lowering the gain when there is no audio signal.
I2C Slave Address
The MAX9860 responds to the slave address 0x20 for
all write commands and 0x21 for all read operations.
14 ______________________________________________________________________________________
16-Bit Mono Audio Voice Codec
MAX9860
2
Table 1. I C Register Map
REGISTER
ADDRESS
REGISTER
B7
B6
B5
B4
B3
B2
B1
B0
POR
R/W
STATUS/INTERRUPT
Interrupt Status
CLD
SLD
NG
ULK
0
0
0
0
0
0x00
0x01
0x02
—
—
R
R
Microphone NG/AGC
Readback
AGC
Interrupt Enable
CLOCK CONTROL
System Clock
ICLD
ISLD
IULK
0
0
0
0
0
0
0x00
R/W
0
0
PSCLK
FREQ
16KHZ
0x03
0x04
0x00
0x00
R/W
R/W
Stereo Audio Clock
Control High
PLL
NHI
Stereo Audio Clock
Control Low
NLO
0x05
0x00
R/W
DIGITAL AUDIO INTERFACE
Interface
MAS
0
WCI
0
DBCI
ABCI
DDLY
HIZ
ST
TDM
0
0
0x06
0x07
0x00
0x00
R/W
R/W
Interface
ADLY
BSEL
DIGITAL FILTERING
Voice Filter
AVFLT
DVFLT
0x08
0x00
R/W
DIGITAL LEVEL CONTROL
DAC Attenuation
DVA
0x09
0x0A
0x00
0x00
R/W
R/W
ADC Output Levels
ADCRL
DVG
ADCLL
DVST
DAC Gain and
Sidetone
0
0x0B
0x00
R/W
MICROPHONE LEVEL CONTROL
Microphone Gain
RESERVED
Reserved
0
PAM
0
PGAM
0
0x0C
0x0D
0x00
R/W
0
0
0
0
0
0
0x00
MICROPHONE AUTOMATIC GAIN CONTROL
Microphone AGC
AGCSRC
AGCRLS
AGCATK
AGCHLD
0x0E
0x0F
0x00
0x00
R/W
R/W
Noise Gate,
Microphone AGC
ANTH
AGCTH
POWER MANAGEMENT
System Shutdown SHDN
0
0
0
DACEN
0
ADCLEN ADCREN
0x10
0x00
R/W
______________________________________________________________________________________ 15
16-Bit Mono Audio Voice Codec
Status/Interrupt
Status registers 0x00 and 0x01 are read-only registers
that report the status of various device functions. The
status register bits are cleared upon a read operation of
the status register and are set the next time the event
occurs. Register 0x02 determines whether or not the sta-
tus flags in register 0x00 simultaneously sets IRQ high.
MAX9860
Table 2. Status/Interrupt Registers
REGISTER ADDRESS
B7
B6
SLD
NG
B5
B4
B3
B2
0
B1
B0
0x00
0x01
0x02
CLD
ULK
0
0
0
0
AGC
0
ICLD
ISLD
IULK
0
0
0
0
BITS
FUNCTION
Clip Detect Flag. Indicates that a signal has become clipped in the ADC or DAC digital signal paths. CLD also
indicates that the AGC function, when enabled, has set the microphone PGA to 0dB and no further gain reduction
is possible.
CLD
SLD
ULK
Slew Level Detect Flag. When volume or gain changes are made, the slewing circuitry smoothly steps through all
intermediate settings. When SLD is set high, all slewing has completed and the volume or gain is at its final value.
Digital PLL Unlock Flag. Indicates that the digital audio PLL for the ADC or DAC has become unlocked and digital
signal data is not reliable. When beginning operation in master mode, this flag goes high and can be cleared by
reading the status register.
Noise Gate Attenuation. When the noise gate is enabled these bits indicate the current noise gate attenuation.
Code
000
001
010
011
100
101
110
111
Attenuation
0dB
1dB
2dB
NG
3dB
6dB
8dB
10dB
12dB
AGC Gain. When the AGC is enabled these bits indicate the AGC controlled level to the MIC preamp. The levels
indicated by these bits correspond to the levels defined for the PGAM bits described in register 0x0C.
AGC
16 ______________________________________________________________________________________
16-Bit Mono Audio Voice Codec
MAX9860
prescaled MCLK input (PCLK). This allows high flexibili-
ty in both the MCLK and LRCLK frequencies and can
be used in either master or slave mode.
Clock Control
The MAX9860 can work with a master clock (MCLK)
supplied from any system clock within the range of
10MHz to 60MHz. Internally, the MAX9860 requires a
10MHz to 20MHz clock so a prescaler divides by 1, 2,
or 4 to create the internal clock (PCLK). PCLK is used
to clock all portions of the MAX9860.
Exact Integer Mode: Common MCLK frequencies
(12MHz, 13MHz, and 19.2MHz) can be programmed to
operate in exact integer mode for both 8kHz and 16kHz
sample rates. In these modes, the MCLK and LRCLK
rates are selected by using the FREQ and 16KHZ bits
instead of the NHI, NLO, and PLL control bits.
The MAX9860 is capable of supporting any sample rate
from 8kHz to 48kHz, including all common sample rates
(8kHz, 16kHz, 24kHz, 32kHz, 44.1kHz, 48kHz). To
accommodate a wide range of system architectures,
the MAX9860 supports three main clocking modes:
PLL Mode: When operating in slave mode, a PLL can
be enabled to lock onto externally generated LRCLK
signals that are asynchronously related to PCLK.
Normal Mode: This mode uses a 15-bit clock divider
coefficient to set the sample rate relative to the
Table 3. Clock Control Registers
REGISTER ADDRESS
B7
0
B6
B5
B4
B3
0
B2
B1
B0
0x03
0x04
0x05
0
PSCLK
FREQ
16KHZ
PLL
NHI
NLO
BITS
FUNCTION
MCLK Prescaler
Divides MCLK down to generate a PCLK between 10MHz and 20MHz.
PSCLK[1:0]
00 = Disable clock for low-power shutdown.
01 = Select if MCLK is between 10MHz and 20MHz.
10 = Select if MCLK is between 20MHz and 40MHz.
11 = Select if MCLK is greater than 40MHz.
Integer Clock Mode
Enables exact integer mode for three predefined PCLK frequencies. Exact integer mode is normally
intended for master mode, but can be enabled in slave mode if the externally supplied LRCLK exactly
matches the frequency specified in each mode.
FREQ[1:0]
00 = Normal operation (configure clocking with the PLL, NHI, and NLO bits).
01 = Select when PCLK is 12MHz (LRCLK = PCLK/1500 or PCLK/750).
10 = Select when PCLK is 13MHz (LRCLK = PCLK/1625 or PCLK/812.5).
11 = Select when PCLK is 19.2MHz (LRCLK = PCLK/2400 or PCLK/1200).
When FREQ ≠ 00, the PLL, NHI, and NLO bits are unused.
16kHz Mode
When FREQ ≠ 00:
0 = LRCLK is exactly 8kHz.
1 = LRCLK is exactly 16kHz.
16KHZ
When FREQ = 00, 16KHZ is used to set the AGC clock rate:
0 = Use when LRCLK ≤ 24kHz.
1 = Use when LRCLK > 24kHz.
______________________________________________________________________________________ 17
16-Bit Mono Audio Voice Codec
Table 3. Clock Control Registers (continued)
BITS
FUNCTION
PLL Enable
0 = (Valid for slave and master mode)—The frequency of LRCLK is set by the NHI and NLO divider
bits. Set PLL = 0 in slave mode only if the externally generated LRCLK can be exactly selected
using the LRCLK divider.
1 = (Valid for slave mode only)—Used when the audio master generates an LRCLK not selectable
using the LRCLK divider. A digital PLL locks on to the externally supplied LRCLK signal
regardless of the MCLK frequency.
MAX9860
PLL
Rapid Lock Mode
To enable rapid lock mode set NHI and NLO to the nearest desired ratio and set NLO[0] = 1 (Register
0x05, bit 0) before setting the PLL mode bit.
LRCLK Divider
NHI and NLO control a 15-bit clock divider (N). When the PLL = 0 and FREQ = 00, the frequency of
LRCLK is determined by the clock divider. See Table 4 for common N values.
NHI and NLO
N = (65,536 x 96 x f
)/f
LRCLK PCLK
f
f
= LRCLK frequency
= prescaled MCLK internal clock frequency (PCLK)
LRCLK
PCLK
Table 4. Common N Values
LRCLK (kHz)
MCLK
(MHz)
PSCLK
8
16
32
44.1
48
11.2896
12
01
01
01
01
01
10
10
10
116A
1062
1000
F20
22D4
20C5
2000
1E3F
147B
20C5
1E3F
1D21
45A9
4189
4000
3C7F
28F6
4189
3C7F
3A41
6000 687D
5A51 624E
5833 6000
535F 5ABE
3873 3D71
5A51 624E
535F 5ABE
5048 5762
12.288
13
19.2
24
A3D
1062
F20
26
27
E90
Note: Values in bold italics are exact integers that provide
maximum full-scale performance.
18 ______________________________________________________________________________________
16-Bit Mono Audio Voice Codec
MAX9860
master mode, the MAX9860 outputs LRCLK and BCLK,
while in slave mode, they are inputs. When operating in
master mode, BCLK can be configured in a number of
ways to ensure compatiblity with other audio devices.
Digital Audio Interface
The MAX9860’s digital audio interface supports a wide
range of operating modes to ensure maximum compati-
bility. See Figures 1 through 4 for timing diagrams. In
Table 5. Digital Audio Interface Registers
REGISTER ADDRESS
B7
MAS
0
B6
WCI
0
B5
B4
B3
HIZ
ST
B2
B1
0
B0
0x06
0x07
DBCI
ABCI
DDLY
ADLY
TDM
0
BSEL
BITS
FUNCTION
Master Mode
MAS
0 = The MAX9860 operates in slave mode with LRCLK and BCLK configured as inputs.
1 = The MAX9860 operates in master mode with LRCLK and BCLK configured as outputs.
LRCLK Invert
0 = Left-channel data is input and output while LRCLK is low.
1 = Right-channel data is input and output while LRCLK is low.
WCI
WCI is ignored when TDM = 1.
DAC BCLK Invert (must be set to ABCI)
In master and slave mode:
0 = SDIN is latched into the part on the rising edge of BCLK.
1 = SDIN is latched into the part on the falling edge of BCLK.
DBCI
In master mode:
0 = LRCLK changes state following the rising edge of BCLK.
1 = LRCLK changes state following the falling edge of BCLK.
DAC Delay Mode
0 = SDIN data is latched on the first BCLK edge following an LRCLK edge.
1 = SDIN data is assumed to be delayed one BCLK cycle so that it is latched on the 2nd BCLK edge
DDLY
HIZ
2
following an LRCLK edge (I S-compatible mode).
DDLY is ignored when TDM = 1.
SDOUT High-Impedance Mode
0 = SDOUT is set either high or low after all data bits have been transferred out of the part.
1 = SDOUT goes to a high-impedance state after all data bits have been transferred out of the part,
allowing SDOUT to be shared by other devices.
Use HIZ only when TDM = 1.
TDM Mode Select
0 = LRCLK signal polarity indicates left and right audio.
1 = LRCLK is a framing pulse which transitions polarity to indicate the start of a frame of audio data
consisting of multiple channels.
TDM
When operating in TDM mode the left channel is output immediately following the frame sync pulse. If right-
channel data is being transmitted, the 2nd channel of data immediately follows the 1st channel data.
ADC BCLK Invert (must be set to DBCI)
ABCI
0 = SDOUT is valid on the rising edge of BCLK and transitions immediately after the rising edge.
1 = SDOUT is valid on the falling edge of BCLK and transitions immediately after the falling edge.
______________________________________________________________________________________ 19
16-Bit Mono Audio Voice Codec
Table 5. Digital Audio Interface Registers (continued)
BITS
FUNCTION
ADC Delay Mode
0 = SDOUT data is valid on the first BCLK edge following an LRCLK edge.
1 = SDOUT data is delayed one BCLK cycle so that it is valid on the 2nd BCLK edge following an
ADLY
2
LRCLK edge (I S-compatible mode).
ADLY is ignored when TDM = 1.
MAX9860
Stereo Enable
0 = The interface transmits and receives only one channel of data. If right record path is enabled, no
data from this channel is transmitted.
1 = The interface operates in stereo. The left and right incoming data are summed to mono and then
routed to the DAC. The summed data is divided by 2 to prevent overload. Both the left and right
record signals are transmitted.
ST
BCLK Select
Configures BCLK when operating in master mode. BSEL has no effect in slave mode. Set BSEL = 010,
unless sharing the bus with multiple devices.
000 = Off
001 = 64x LRCLK (192x internal clock divided by 3)
010 = 48x LRCLK (192x internal clock divided by 4)
011 = Reserved for future use.
100 = PCLK/2
BSEL
101 = PCLK/4
110 = PCLK/8
111 = PCLK/16
20 ______________________________________________________________________________________
16-Bit Mono Audio Voice Codec
MAX9860
AUDIO MASTER MODES (ST = 1):
LEFT JUSTIFIED : WCI = 0, _BCI = 0, _DLY = 0
7ns (typ)
7ns (typ)
LEFT
RIGHT
LRCLK
1/f
S
RELATIVE TO PCLK (NOTE 7)
D15
D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
D15
D15
D15
D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
SDOUT
BCLK
SDIN
40ns (max)
0ns (min)
7ns (typ)
7ns (typ)
CONFIGURED BY BSEL
25ns (min)
0ns (min)
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
LEFT JUSTIFIED + LRCLK INVERT: WCI = 1, _BCI = 0, _DLY = 0
7ns (typ)
7ns (typ)
RIGHT
LEFT
LRCLK
SDOUT
BCLK
1/f
1/f
1/f
S
RELATIVE TO PCLK (NOTE 7)
D15
D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
40ns (max)
0ns (min)
7ns (typ)
7ns (typ)
CONFIGURED BY BSEL
25ns (min)
0ns (min)
SDIN
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
LEFT JUSTIFIED + BCLK INVERT: WCI = 0, _BCI = 1, _DLY = 0
7ns (typ)
7ns (typ)
LEFT
RIGHT
LRCLK
S
RELATIVE TO PCLK (NOTE 7)
D15
D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
SDOUT
BCLK
40ns (max)
0ns (min)
7ns (typ)
7ns (typ)
CONFIGURED BY BSEL
25ns (min)
0ns (min)
SDIN
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
2
I S: WCI = 0, _BCI = 0, _DLY = 1
7ns (typ)
7ns (typ)
LEFT
RIGHT
LRCLK
S
RELATIVE TO PCLK (NOTE 7)
D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1
D0
D15
D15
D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
SDOUT
BCLK
40ns (max)
0ns (min)
7ns (typ)
7ns (typ)
CONFIGURED BY BSEL
25ns (min)
0ns (min)
SDIN
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
NOTE 7: THE DELAY FROM A BCLK EDGE AND AN LRCLK EDGE IS DETERMINED BY LENGTH OF TIME THAT PCLK (THE INTERNALLY DIVIDED DOWN VERSION OF MCLK AS DEFINED BY THE PSCLK BITS) IS HIGH DURING
ONE PERIOD OF MCLK PLUS THE INTERNAL DELAY. FOR EXAMPLE: IF PCLK = 12.288MHz, THE DELAY BETWEEN BCLK AND LRCLK IS TYPICALLY 45ns.
Figure 1. Digital Audio Interface Audio Master Mode Examples
______________________________________________________________________________________ 21
16-Bit Mono Audio Voice Codec
VOICE (TDM) MASTER MODES:
_BCI = 0, HIZ = 1, ST = 0
7ns (typ)
7ns (typ)
LRCLK
1/f
S
RELATIVE TO PCLK (NOTE 8)
SDOUT
BCLK
L15 L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0
40ns (max)
0ns (min)
7ns (typ)
7ns (typ)
MAX9860
CONFIGURED BY BSEL
25ns (min)
0ns (min)
SDIN
L15 L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0
_BCI = 1, HIZ = 1, ST = 0
7ns (typ)
7ns (typ)
LRCLK
1/f
S
RELATIVE TO PCLK (NOTE 8)
L15 L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0
SDOUT
BCLK
40ns (max)
0ns (min)
7ns (typ)
7ns (typ)
CONFIGURED BY BSEL
25ns (min)
0ns (min)
SDIN
L15 L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0
_BCI = 0, HIZ = 0, ST = 0
7ns (typ)
7ns (typ)
LRCLK
1/f
S
RELATIVE TO PCLK (NOTE 8)
SDOUT
BCLK
L15 L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0
40ns (max)
0ns (min)
7ns (typ)
7ns (typ)
CONFIGURED BY BSEL
25ns (min)
0ns (min)
SDIN
L15 L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0
_BCI = 0, HIZ = 1, ST = 1
7ns (typ)
7ns (typ)
LRCLK
SDOUT
BCLK
1/f
S
RELATIVE TO PCLK (NOTE 8)
L15 L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0 R15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0
40ns (max)
0ns (min)
7ns (typ)
7ns (typ)
CONFIGURED BY BSEL
25ns (min)
0ns (min)
SDIN
L15 L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0 R15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0
NOTE 8: THE DELAY FROM A BCLK EDGE AND AN LRCLK EDGE IS DETERMINED BY LENGTH OF TIME THAT PCLK (THE INTERNALLY DIVIDED DOWN VERSION OF MCLK AS DEFINED BY THE PSCLK BITS) IS HIGH DURING
ONE PERIOD OF MCLK PLUS THE INTERNAL DELAY. FOR EXAMPLE: IF PCLK = 12.288MHz, THE DELAY BETWEEN BCLK AND LRCLK IS TYPICALLY 45ns.
Figure 2. Digital Audio Interface Voice Master Mode Examples
22 ______________________________________________________________________________________
16-Bit Mono Audio Voice Codec
MAX9860
AUDIO SLAVE MODES (ST = 1):
LEFT JUSTIFIED: WCI = 0, _BCI = 0, _DLY = 0
LEFT
RIGHT
LRCLK
SDOUT
1/f
S
25ns (min)
0ns (min)
D15
D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
40ns (max)
D15
D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
0ns (min)
30ns (min)
BCLK
SDIN
30ns (min)
75ns (min)
0ns (min)
25ns (min)
D13
D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
D12 D11
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
D15 D14
LEFT JUSTIFIED + LRCLK INVERT: WCI = 1, _BCI = 0, _DLY = 0
RIGHT
LEFT
LRCLK
1/f
S
0ns (min)
25ns (min)
SDOUT
BCLK
D15
D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
D15
D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
40ns (max)
0ns (min)
30ns (min)
75ns (min)
0ns (min)
25ns (min)
SDIN
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
D15 D14 D13 D12 D11 D10
LEFT JUSTIFIED + BCLK INVERT: WCI = 0, _BCI = 1, _DLY = 0
LEFT
LRCLK
RIGHT
1/f
S
25ns (min)
0ns (min)
SDOUT
BCLK
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
D15
D14 D13 D12 D11 D10
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
D15
D14 D13 D12 D11 D10
40ns (max)
0ns (min)
30ns (min)
75ns (min)
0ns (min)
25ns (min)
SDIN
D15 D14 D13 D12 D11 D10
D15 D14 D13 D12 D11 D10
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
2
I S: WCI = 0, _BCI = 0, _DLY = 1
LEFT
RIGHT
LRCLK
1/f
S
0ns (min)
25ns (min)
D14 D13 D12 D11 D10
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
D15
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
D15
D14 D13 D12 D11 D10
SDOUT
BCLK
40ns (max)
0ns (min)
30ns (min)
75ns (min)
25ns (min)
0ns (min)
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
SDIN
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Figure 3. Digital Audio Interface Audio Slave Mode Examples
______________________________________________________________________________________ 23
16-Bit Mono Audio Voice Codec
VOICE (TDM) SLAVE MODES: _BCI = 0, HIZ =1, ST = 0
LRCLK
1/f
1/f
1/f
S
S
S
0ns (min)
25ns (min)
0ns (min)
SDOUT
BCLK
L15 L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0
40ns (max)
0ns (min)
30ns (min)
MAX9860
75ns (min)
0ns (min)
25ns (min)
SDIN
L15 L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0
_BCI = 1, HIZ = 1, ST = 0
LRCLK
0ns (min)
25ns (min)
0ns (min)
0ns (min)
0ns (min)
SDOUT
BCLK
L15 L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0
40ns (max)
0ns (min)
30ns (min)
75ns (min)
0ns (min)
25ns (min)
SDIN
L15 L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0
_BCI = 0, HIZ = 0, ST = 0
LRCLK
0ns (min)
25ns (min)
SDOUT
BCLK
L15 L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0
40ns (max)
0ns (min)
30ns (min)
75ns (min)
0ns (min)
25ns (min)
SDIN
L15 L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0
_BCI = 0, HIZ = 1, ST = 1
LRCLK
SDOUT
1/f
S
0ns (min)
25ns (min)
L15 L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0 R15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0
40ns (max)
0ns (min)
30ns (min)
BCLK
75ns (min)
0ns (min)
25ns (min)
SDIN
L15 L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0 R15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0
Figure 4. Digital Audio Interface Voice Slave Mode Examples
24 ______________________________________________________________________________________
16-Bit Mono Audio Voice Codec
MAX9860
Digital Filtering
The MAX9860 incorporates selecable highpass and
notch filters for both the playback and record paths.
Each filter is valid for a specific sample rate.
Table 6. Digital Filter Registers
REGISTER ADDRESS
B7
B6
B5
B4
B3
B2
B1
B0
0x08
AVFLT
DVFLT
BITS
FUNCTION
AVFLT
DVFLT
ADC Voice Filter Frequency Select. See Table 7.
DAC Voice Filter Frequency Select. See Table 7.
Table 7. Digital Filters
CODE
0x0
FILTER TYPE
SAMPLE RATE
DESCRIPTION
—
—
Disabled
0x1
Elliptical
Butterworth
Elliptical
Butterworth
Butterworth
—
16kHz
16kHz
8kHz
8kHz
48kHz
—
Elliptical highpass with 217Hz notch
500Hz Butterworth highpass
Elliptical highpass with 217Hz notch
500Hz Butterworth highpass
200Hz Butterworth highpass
Reserved
0x2
0x3
0x4
0x5
0x6 to 0xF
______________________________________________________________________________________ 25
16-Bit Mono Audio Voice Codec
adjustment is provided for the two record channels.
Sidetone gain adjustment is also provided to set the
sidetone level relative to the playback level.
Digital Level Control
The MAX9860 includes digital gain adjustment for the
playback and record paths. Independent gain
Table 8. Digital Level Control Registers
REGISTER ADDRESS
B7
B6
B5
B4
B3
B2
B1
B0
0x09
0x0A
0x0B
DVA
MAX9860
ADCRL
DVG
ADCLL
0
DVST
BITS
FUNCTION
DAC Level Adjust
Adjusts the digital audio level before being converted by the DAC. The least significant bit of DVA is
always 0.
CODE
0x00
0x02
0x04
0x06
0x08
0x0A
0x0C
0x0E
0x10
0x12
0x14
0x16
0x18
0x1A
0x1C
0x1E
0x20
0x22
0x24
0x26
0x28
0x2A
0x2C
0x2E
0x30
0x32
0x34
0x36
0x38
0x3A
0x3C
0x3E
GAIN
+3
+2
+1
0
-1
-2
-3
-4
-5
-6
-7
-8
CODE
0x40
0x42
0x44
0x46
0x48
0x4A
0x4C
0x4E
0x50
0x52
0x54
0x56
0x58
0x5A
0x5C
0x5E
0x60
0x62
0x64
0x66
0x68
0x6A
0x6C
0x6E
0x70
0x72
0x74
0x76
0x78
0x7A
0x7C
0x7E
GAIN
-29
-30
-31
-32
-33
-34
-35
-36
-37
-38
-39
-40
-41
-42
-43
-44
-45
-46
-47
-48
-49
-50
-51
-52
-53
-54
-55
-56
-57
-58
-59
-60
CODE
0x80
0x82
0x84
0x86
0x88
0x8A
0x8C
0x8E
0x90
0x92
0x94
0x96
0x98
0x9A
0x9C
0x9E
0xA0
0xA2
0xA4
0xA6
0xA8
0xAA
0xAC
0xAE
0xB0
0xB2
0xB4
0xB6
0xB8
0xBA
≥ 0xBC
—
GAIN
-61
-62
-63
-64
-65
-66
-67
-68
-69
-70
-71
-72
-73
-74
-75
-76
-77
-78
-79
-80
-81
-82
-83
-84
-85
-86
-87
-88
-89
-90
MUTE
—
-9
-10
-11
-12
-13
-14
-15
-16
-17
-18
-19
-20
-21
-22
-23
-24
-25
-26
-27
-28
DVA
26 ______________________________________________________________________________________
16-Bit Mono Audio Voice Codec
MAX9860
Table 8. Digital Level Control Registers (continued)
BITS
FUNCTION
Left and Right ADC Output Level
Adjusts the digital audio level output by the ADCs.
CODE
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
0x8
0x9
0xA
0xB
0xC
0xD
0xE
0xF
GAIN
+3
+2
+1
0
-1
-2
-3
-4
-5
-6
-7
-8
ADCRL/ADCLL
-8
-10
-11
-12
DAC Gain
The gain set by DVG adds to the level set by DVA.
CODE
00
GAIN
0
DVG
01
+6
10
11
+12
+18
Sidetone
Sets the level of left ADC output mixed into the DAC.
CODE
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
GAIN
Disabled
0
CODE
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x18
0x19
0x1A
0x1B
0x1C
0x1D
0x1E
0x1F
GAIN
-30
-32
-34
-36
-38
-40
-42
-44
-46
-48
-50
-52
-54
-56
-58
-60
-2
-4
-6
-8
-10
-12
-14
-16
-18
-20
-22
-24
-26
-28
DVST
______________________________________________________________________________________ 27
16-Bit Mono Audio Voice Codec
gain and then routed to the ADCs. The first stage offers
Microphone Inputs
The MAX9860 provides two differential microphone
inputs and a low-noise 1.55V microphone bias for power-
ing the microphones. In typical applications, the left
microphone is used to record a voice signal and the
right microphone is used to record a background noise
signal. In applications that require only one microphone,
use the left microphone input and disable the right ADC.
The microphone signals are amplified by two stages of
selectable 0dB, 20dB, or 30dB settings. The second
stage is a programmable gain amplifier (PGA) adjustable
from 0dB to 20dB in 1dB steps. Zero-crossing detection
is included on the PGA to minimize zipper noise while
making gain changes. See Figure 5 for a detailed dia-
gram of the microphone input structure.
MAX9860
MAX9860
0/20/30dB
1.55V
REG
MICBIAS
V
CM
0dB to +20dB
PGA
MICLP
MICLN
ADC
L
PREAMP
-
MICGND
AGC
0/20/30dB
V
CM
MICRP
MICRN
ADC
R
PREAMP
PGA
0dB to +20dB
Figure 5. Microphone Input Block Diagram
28 ______________________________________________________________________________________
16-Bit Mono Audio Voice Codec
MAX9860
Table 9. Microphone Input Register
REGISTER ADDRESS
B7
B6
B5
B4
B3
B2
B1
B0
0x0C
0
PAM
PGAM
BITS
FUNCTION
Left and Right Microphone Preamp Gain
CODE
00
01
GAIN (dB)
Disabled
0
PAM
10
+20
11
+30
Note: Selecting 00 disables the microphone inputs and microphone bias automatically.
Left and Right Microphone PGA
CODE
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
GAIN (dB)
+20
CODE
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
0x11
0x12
0x13
≥ 0x14
—
GAIN (dB)
+9
+8
+7
+6
+5
+4
+3
+2
+1
0
+19
+18
+17
+16
+15
+14
+13
+12
PGAM
+11
+10
—
Note: When AGC is enabled, the AGC controller overrides these settings.
______________________________________________________________________________________ 29
16-Bit Mono Audio Voice Codec
Since AGC increases the level of all signals below a
Automatic Gain Control (AGC)
and Noise Gate
user-defined threshold, the noise floor effectively is
increased by 20dB. To counteract this, a noise gate is
included to reduce the gain at low levels. Unlike typical
noise gates that completely silence the output below a
threshold, the noise gate in the MAX9860 reduces the
gain for signals below the defined level. As the signal
level becomes further below the threshold, the gain is
further reduced. The Automatic Gain Control
Thresholds and Noise Gate Thresholds graphs in the
Typical Operating Characteristics show the resulting
steady-state transfer curves when AGC and the noise
gate are enabled.
The MAX9860 includes AGC on both microphone
inputs. AGC is enabled by setting the hold time through
AGCHLD. AGC dynamically controls the analog PGA
microphone input gain to hold the level constant over a
20dB input range, enhancing the voice path operation
for various use conditions. When AGC is enabled, it
monitors the signal level at the output of the ADC and
then makes gain adjustments by controlling the analog
microphone PGA. When AGC is enabled, PGAM is not
user programmable.
MAX9860
Table 10. AGC and Noise Gate Registers
REGISTER ADDRESS
B7
B6
B5
B4
B3
B2
B1
B0
0x0E
0x0F
AGCSRC
AGCRLS
AGCATK
AGCHLD
ANTH
AGCTH
BITS
FUNCTION
AGC/Noise Gate Signal Source Select
0 = The left ADC output is used by the AGC and noise gate.
AGCSRC
1 = The sum of the left and right ADC outputs is used by the AGC and noise gate.
AGC Release Time
Time taken by the AGC circuit to increase the gain from minimum to maximum.
CODE
000
001
010
011
100
101
TIME
78ms
156ms
312ms
625ms
1.25s
2.5s
AGCRLS
110
111
5s
10s
AGC Attack Time
The time constant of the AGC gain reduction curve.
CODE
TIME (ms)
AGCATK
AGCHLD
00
01
10
11
3
12
50
200
AGC Hold Time
Time the AGC circuit waits before beginning to increase gain when a signal below the threshold is
detected.
CODE
00
TIME (ms)
AGC disabled
01
50
10
11
100
400
30 ______________________________________________________________________________________
16-Bit Mono Audio Voice Codec
MAX9860
Table 10. AGC and Noise Gate Registers (continued)
BITS
FUNCTION
Noise Gate Threshold
The signal level at which the noise gate begins reducing the gain. When the signal level is above the
threshold the noise gate has no effect. When the signal level is below the threshold, the noise gate
decreases the gain by 1dB for every 2dB the signal is below the threshold.
The noise gate can be enabled independently from AGC. When AGC is enabled, PGAM must be set to
+20dB (indicating a small signal is present) for the noise gate to attenuate.
For microphone signals, use the noise gate and AGC simultaneously with ANTH set between -16dB
and -28dB.
ANTH
ANTH[3:0]
0x0
LEVEL (dBFS)
ANTH[3:0]
0x8
LEVEL (dBFS)
Disabled
-72
-44
-40
-36
-32
-28
-24
-20
-16
0x1
0x9
0x2
-68
0xA
0x3
-64
0xB
0x4
-60
0xC
0x5
-56
0xD
0x6
-52
0xE
0x7
-48
0xF
AGC Signal Threshold
The target output signal level. When the signal level is below the threshold, the AGC increases the
gain. The signal level is measured after ADCRL and ADCLL are applied to the ADC output.
ANTH[3:0]
0x0
LEVEL (dBFS)
ANTH[3:0]
0x8
LEVEL (dBFS)
-3
-4
-11
-12
-13
-14
-15
-16
-17
-18
0x1
0x9
AGCTH
0x2
-5
0xA
0x3
-6
0xB
0x4
-7
0xC
0x5
-8
0xD
0x6
-9
0xE
0x7
-10
0xF
______________________________________________________________________________________ 31
16-Bit Mono Audio Voice Codec
ADCs can be independently enabled so that only the
required circuitry is active.
Power Management
The MAX9860 includes complete power management
control to minimize power usage. The DAC and both
Table 11. Power Management Register
REGISTER ADDRESS
B7
B6
B5
B4
B3
B2
B1
B0
0x10
SHDN
0
0
0
DACEN
0
ADCLEN
ADCREN
MAX9860
BITS
FUNCTION
Active-Low Software Shutdown
0 = MAX9860 is in full shutdown.
1 = MAX9860 is powered on.
SHDN
2
When SHDN = 0. All register settings are preserved and the I C interface remains active.
DAC Enable
DACEN
0 = DAC disabled.
1 = DAC enabled.
ADC Left/Right Enable
0 = Left/right ADC disabled.
1 = Left/right ADC enabled.
ADCLEN/ADCREN
The left ADC must be enabled when using the right ADC.
Revision Code
The MAX9860 includes a revision code to allow easy
identification of the device revision. The current revision
code is 0x40.
Table 12. Revision Code Register
ADDR
B7
B6
B5
B4
B3
B2
B1
B0
0xFF
REV
I2C Serial Interface
transmits data on SDA in sync with the master-generat-
ed SCL pulses. The master acknowledges receipt of
each byte of data. Each read sequence is framed by a
START or REPEATED START condition, a not acknowl-
edge, and a STOP condition. SDA operates as both an
input and an open-drain output. A pullup resistor, typi-
cally greater than 500Ω, is required on SDA. SCL oper-
ates only as an input. A pullup resistor, typically greater
than 500Ω, is required on SCL if there are multiple mas-
ters on the bus, or if the single master has an open-
drain SCL output. Series resistors in line with SDA and
SCL are optional. Series resistors protect the digital
inputs of the MAX9860 from high voltage spikes on the
bus lines, and minimize crosstalk and undershoot of the
bus signals.
The MAX9860 features an I2C/SMBus™-compatible,
2-wire serial interface consisting of a serial-data line
(SDA) and a serial-clock line (SCL). SDA and SCL facili-
tate communication between the MAX9860 and the
master at clock rates up to 400kHz. Figure 6 shows the
2-wire interface timing diagram. The master generates
SCL and initiates data transfer on the bus. The master
device writes data to the MAX9860 by transmitting the
proper slave address followed by the register address
and then the data word. Each transmit sequence is
framed by a START (S) or REPEATED START (Sr) con-
dition and a STOP (P) condition. Each word transmitted
to the MAX9860 is 8 bits long and is followed by an
acknowledge clock pulse. A master reading data from
the MAX9860 transmits the proper slave address fol-
lowed by a series of nine SCL pulses. The MAX9860
SMBus is a trademark of Intel Corp.
32 ______________________________________________________________________________________
16-Bit Mono Audio Voice Codec
MAX9860
SDA
t
BUF
t
SU,STA
t
SU,DAT
t
HD,STA
t
SP
t
LOW
t
SU,STO
t
HD,DAT
t
SCL
t
HIGH
HD,STA
t
t
F
R
START CONDITION
REPEATED START CONDITION
STOP
CONDITION
START
CONDITION
Figure 6. 2-Wire Interface Timing Diagram
Bit Transfer
Acknowledge
One data bit is transferred during each SCL cycle. The
data on SDA must remain stable during the high period
of the SCL pulse. Changes in SDA while SCL is high
are control signals (see the START and STOP
Conditions section).
The acknowledge bit (ACK) is a clocked 9th bit that the
MAX9860 uses to handshake receipt each byte of data
when in write mode (see Figure 7). The MAX9860 pulls
down SDA during the entire master-generated 9th clock
pulse if the previous byte is successfully received.
Monitoring ACK allows for detection of unsuccessful
data transfers. An unsuccessful data transfer occurs if
a receiving device is busy or if a system fault has
occurred. In the event of an unsuccessful data transfer,
the bus master retries communication. The master pulls
down SDA during the 9th clock cycle to acknowledge
receipt of data when the MAX9860 is in read mode. An
acknowledge is sent by the master after each read byte
to allow data transfer to continue. A not acknowledge is
sent when the master reads the final byte of data from
the MAX9860, followed by a STOP condition.
START and STOP Conditions
SDA and SCL idle high when the bus is not in use.
A master initiates communication by issuing a START (S)
condition. A START condition is a high-to-low transition
on SDA with SCL high. A STOP (P) condition is a low-to-
high transition on SDA while SCL is high (Figure 7). A
START condition from the master signals the beginning
of a transmission to the MAX9860. The master terminates
transmission, and frees the bus, by issuing a STOP con-
dition. The bus remains active if a REPEATED START
(Sr) condition is generated instead of a STOP condition.
Write Data Format
A write to the MAX9860 includes transmission of a
START condition, the slave address with the R/W bit set
to 0, one byte of data to configure the internal register
address pointer, one or more bytes of data, and a
STOP condition. Figure 9 illustrates the proper frame
format for writing one byte of data to the MAX9860.
Figure 10 illustrates the frame format for writing n bytes
of data to the MAX9860.
Early STOP Conditions
The MAX9860 recognizes a STOP condition at any
point during data transmission except if the STOP con-
dition occurs in the same high pulse as a START condi-
tion. For proper operation, do not send a STOP
condition during the same SCL high pulse as the
START condition.
Slave Address
The slave address is defined as the seven most signifi-
cant bits (MSBs) followed by the read/write bit. For the
MAX9860, the seven most significant bits are 0010000.
Setting the read/write bit to 1 (slave address = 0x21)
configures the MAX9860 for read mode. Setting the
read/write bit to 0 (slave address = 0x20) configures
the MAX9860 for write mode. The address is the first
byte of information sent to the MAX9860 after the
START condition.
The slave address with the R/W bit set to 0 indicates
that the master intends to write data to the MAX9860.
The MAX9860 acknowledges receipt of the address
byte during the master-generated 9th SCL pulse.
The second byte transmitted from the master config-
ures the MAX9860’s internal register address pointer.
The pointer tells the MAX9860 where to write the next
byte of data. An acknowledge pulse is sent by the
MAX9860 upon receipt of the address pointer data.
______________________________________________________________________________________ 33
16-Bit Mono Audio Voice Codec
S
Sr
P
SCL
SDA
MAX9860
Figure 7. START (S), STOP (P), and REPEATED START (Sr) Conditions
CLOCK PULSE FOR
ACKNOWLEDGMENT
START
CONDITION
SCL
1
28
9
NOT ACKNOWLEDGE
SDA
ACKNOWLEDGE
Figure 8. Acknowledge
ACKNOWLEDGE FROM MAX9860
B7 B6 B5 B4 B3 B2 B1 B0
ACKNOWLEDGE FROM MAX9860
ACKNOWLEDGE FROM MAX9860
REGISTER ADDRESS
A
P
S
SLAVE ADDRESS
0
A
A
DATA BYTE
1 BYTE
R/W
AUTOINCREMENT INTERNAL
REGISTER ADDRESS POINTER
Figure 9. Writing One Byte of Data to the MAX9860
The third byte sent to the MAX9860 contains the data
that is written to the chosen register. An acknowledge
pulse from the MAX9860 signals receipt of the data byte.
The address pointer autoincrements to the next register
address after each received data byte. This autoincre-
ment feature allows a master to write to sequential regis-
ters within one continuous frame. Figure 10 illustrates
how to write to multiple registers with one frame. The
master signals the end of transmission by issuing a
STOP condition. Register addresses greater than 0x10
are reserved. Do not write to these addresses.
Read Data Format
Send the slave address with the R/W bit set to 1 to initi-
ate a read operation. The MAX9860 acknowledges
receipt of its slave address by pulling SDA low during
the 9th SCL clock pulse. A START command followed
by a read command resets the address pointer to reg-
ister 0x00.
The first byte transmitted from the MAX9860 is the con-
tents of register 0x00. Transmitted data is valid on the
rising edge of SCL. The address pointer autoincre-
ments after each read data byte. This autoincrement
34 ______________________________________________________________________________________
16-Bit Mono Audio Voice Codec
MAX9860
ACKNOWLEDGE FROM MAX9860
B7 B6 B5 B4 B3 B2 B1 B0
ACKNOWLEDGE FROM MAX9860
B7 B6 B5 B4 B3 B2 B1 B0
ACKNOWLEDGE FROM MAX9860
SLAVE ADDRESS
ACKNOWLEDGE FROM MAX9860
S
0
A
A
A
REGISTER ADDRESS
DATA BYTE 1
1 BYTE
DATA BYTE n
1 BYTE
A
P
R/W
AUTOINCREMENT INTERNAL
REGISTER ADDRESS POINTER
Figure 10. Writing N Bytes of Data to the MAX9860
NOT ACKNOWLEDGE FROM MASTER
ACKNOWLEDGE FROM MAX9860
REGISTER ADDRESS
REPEATED START
ACKNOWLEDGE FROM MAX9860
ACKNOWLEDGE FROM MAX9860
SLAVE ADDRESS
A
P
S
0
A
A
Sr
SLAVE ADDRESS
1
A
DATA BYTE
1 BYTE
R/W
R/W
AUTOINCREMENT INTERNAL
REGISTER ADDRESS POINTER
Figure 11. Reading One Byte of Data from the MAX9860
ACKNOWLEDGE FROM MAX9860
ACKNOWLEDGE FROM MAX9860
REGISTER ADDRESS
ACKNOWLEDGE FROM MAX9860
SLAVE ADDRESS
A
P
S
0
A
A
Sr
SLAVE ADDRESS
1
A
DATA BYTE
1 BYTE
R/W
REPEATED START
R/W
AUTOINCREMENT INTERNAL
REGISTER ADDRESS POINTER
Figure 12. Reading N Bytes of Data from the MAX9860
feature allows all registers to be read sequentially within
one continuous frame. A STOP (P) condition can be
issued after any number of read data bytes. If a STOP
condition is issued followed by another read operation,
the first data byte to be read is from register 0x00.
The master acknowledges receipt of each read byte
during the acknowledge clock pulse. The master must
acknowledge all correctly received bytes except the
last byte. The final byte must be followed by a not
acknowledge from the master and then a STOP condi-
tion. Figure 11 illustrates the frame format for reading
one byte from the MAX9860. Figure 12 illustrates the
frame format for reading multiple bytes from the
MAX9860.
The address pointer can be preset to a specific register
before a read command is issued. The master presets
the address pointer by first sending the MAX9860’s
slave address with the R/W bit set to 0 followed by the
register address. A REPEATED START (Sr) condition is
then sent followed by the slave address with the R/W bit
set to 1. The MAX9860 then transmits the contents of
the specified register. The address pointer autoincre-
ments after transmitting the first byte.
______________________________________________________________________________________ 35
16-Bit Mono Audio Voice Codec
Route microphone signals from the microphone to the
Pin Configuration
MAX9860 as a differential pair, ensuring that the positive
and negative signals follow the same path as closely as
possible with equal trace length. When using single-
ended microphones or other single-ended audio
sources, AC ground the negative microphone input sig-
nal as near to the audio source as possible and then treat
the positive and negative traces as differential pairs.
TOP VIEW
24
23
22
21
20
19
18
BCLK
MICBIAS
1
2
3
4
5
6
+
The MAX9860 thin QFN package features an exposed
thermal pad on its underside. This pad lowers the pack-
age’s thermal resistance by providing a direct heat
conduction path from the die to the PCB. Connect the
exposed thermal pad to AGND.
17 LRCLK
16 SDIN
REG
PREG
REF
MAX9860
MAX9860
15
14
SDOUT
MCLK
AGND
AVDD
*EP
11
An evaluation kit (EV kit) is available to provide an
example layout for the MAX9860. The EV kit allows
quick setup of the MAX9860 and includes easy-to-use
software allowing all internal registers to be controlled.
13 DVDD
7
8
9
10
12
THIN QFN
4mm x 4mm
*EP = EXPOSED PAD
Applications Information
Proper layout and grounding are essential for optimum
performance. When designing a PCB for the MAX9860,
partition the circuitry so that the analog sections of the
MAX9860 are separated from the digital sections. This
ensures that the analog audio traces do not need to be
routed near digital traces.
Use a large continuous ground plane on a dedicated
layer of the PCB to minimize loop areas. Connect
AGND, DGND, and MICGND directly to the ground
plane using the shortest trace length possible. Proper
grounding improves audio performance, minimizes
crosstalk between channels, and prevents any digital
noise from coupling into the analog audio signal.
Ground the bypass capacitors on REG, PREG, and REF
directly to the ground plane with minimum trace length.
Also be sure to minimize the path length to AGND and
MICGND. Bypass AVDD directly to AGND. Bypass
MICBIAS directly to MICGND.
Connect all digital I/O termination to the ground plane
with minimum path length to DGND. Bypass DVDD and
DVDDIO directly to DGND.
36 ______________________________________________________________________________________
16-Bit Mono Audio Voice Codec
MAX9860
Functional Diagram/Typical Operating Circuit
1.7V TO 3.6V
1.7V TO 1.9V
1.7V TO 1.9V
1μF
1μF
10μF
0.1μF
11
13
6
DVDD
AVDD
DVDDIO
DIGITAL ANALOG
DAC
0, +6dB,
+12dB, +24dB
7
8
OUTP
OUTN
-90dB TO 0
DVA
15
16
17
18
SDOUT
SDIN
INTERPOLATION
FILTER
MONO
P
Σ
DVG
DIGITAL AUDIO
INTERFACE
P
P
P
P
LRCLK
BCLK
0,
20dB,
30dB
DVST
MAX9860
0 TO +20dB
(1dB STEPS)
1μF
-60dB TO 0dB
(2dB STEPS)
MICLP
MICLN
23
22
P
LEFT
ADC
DVDDIO
PGAM
PAM
P
-12dB TO +3dB
1μF
1μF
P
P
P
ADCLL/
ADCRL
DECIMATION
FILTER
10kΩ
0,
20dB,
30dB
P
P
0 TO +20dB
(1dB STEPS)
19
14
IRQ
21 MICRP
TIMING AND
CONTROL LOGIC
P
RIGHT
ADC
P
P
LOW-LEVEL
AUDIO
QUIETING
CONTROL
PGAM
PAM
MCLK
MICRN
20
DVDDIO
1μF
MICBIAS
1
AUTOMATIC
GAIN
CONTROL
P
1.5kΩ
1.5kΩ
MICBIAS
SCL
SDA
10
9
2.2μF
STATUS
2
P
I C SERIAL
PORT
P
USER-
INTERNAL REGULATORS
PROGRAMMABLE
MODE CONTROL
DGND
12
AGND
5
MICGND
24
REG
PREG
REF
4
2
3
1μF
1μF
2.2μF
2
INDICATES USER PROGRAMMABLE I C CONTROL BITS.
P
______________________________________________________________________________________ 37
16-Bit Mono Audio Voice Codec
Package Information
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages.
PACKAGE TYPE
PACKAGE CODE
DOCUMENT NO.
21-0139
24 TQFN-EP
T2444+4
MAX9860
38 ______________________________________________________________________________________
16-Bit Mono Audio Voice Codec
MAX9860
Package Information (continued)
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages.
______________________________________________________________________________________ 39
16-Bit Mono Audio Voice Codec
Revision History
REVISION REVISION
DESCRIPTION
PAGES
CHANGED
NUMBER
DATE
0
1
10/08
9/09
Initial release
—
Corrected error in Table 11
32
MAX9860
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
40 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2009 Maxim Integrated Products
Maxim is a registered trademark of Maxim Integrated Products, Inc.
相关型号：
MAX9867EVKIT
Isolation Header for Direct Communication with the MAX9867 I2C and Digital Audio Interfaces
MAXIM
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