首页 |元器件品牌

MAX9685C/D [MAXIM]

Ultra-Fast ECL-Output Comparator with Latch Enable; 超高速ECL输出比较器，带有锁存使能
MAX9685C/D
型号： MAX9685C/D
厂家： MAXIM INTEGRATED PRODUCTS    MAXIM INTEGRATED PRODUCTS
描述：

Ultra-Fast ECL-Output Comparator with Latch Enable
超高速ECL输出比较器，带有锁存使能

比较器 放大器 放大器电路
文件： 总8页 (文件大小：70K)
中文：  中文翻译
下载：  下载PDF数据表文档文件
 查看货源
19-2398; Rev 1; 7/93  
Ult ra -Fa s t ECL-Ou t p u t Co m p a ra t o r  
w it h La t c h En a b le  
MAX9685  
_______________Ge n e ra l De s c rip t io n  
The MAX9685 is an ultra-fast ECL comparator manufac-  
____________________________Fe a t u re s  
♦ 1.3ns Propagation Delay  
tured with a high-frequency bipolar process (f = 6GHz)  
T
♦ 0.5ns Latch Setup Time  
capable of very short propagation delays. This design  
maintains the excellent DC matching characteristics nor-  
mally found only in slower comparators.  
♦ +5V, -5.2V Power Supplies  
♦ Pin-Compatible with AD9685, Am6685  
The device is pin-compatible with the AD9685 and  
Am6685, but exceeds their AC characteristics.  
♦ Available in Commercial, Extended-Industrial,  
The MAX9685 has differential inputs and complemen-  
tary outputs that are fully compatible with ECL-logic lev-  
els. Output current levels are capable of driving 50Ω  
terminated transmission lines. The ultra-fast operation  
makes signal processing possible at frequencies in  
excess of 600MHz.  
and Military Temperature Ranges  
♦ Available in Narrow SO Package  
A latch-enable (LE) function is provided to allow the  
comparator to be used in a sample-hold mode. When  
LE is ECL high, the comparator functions normally.  
When LE is driven ECL low, the outputs are forced to an  
unambiguous ECL-logic state, dependent on the input  
conditions at the time of the latch input transition. If the  
latch-enable function is not used, the LE pin must be  
connected to ground.  
______________Ord e rin g In fo rm a t io n  
PART  
TEMP. RANGE  
0°C to +70°C  
0°C to +70°C  
0°C to +70°C  
0°C to +70°C  
0°C to +70°C  
-40°C to +85°C  
-40°C to +85°C  
-55°C to +125°C  
-55°C to +125°C  
PIN-PACKAGE*  
16 Plastic DIP  
16 Narrow SO  
16 CERDIP  
MAX9685CPE  
MAX9685CSE  
MAX9685CJE  
MAX9685CTW  
MAX9685C/D  
MAX9685EPE  
MAX9685ESE  
MAX9685MJE  
MAX9685MTW  
10 TO-100  
Dice**  
________________________Ap p lic a t io n s  
High-Speed A/D Converters  
High-Speed Line Receivers  
Peak Detectors  
16 Plastic DIP  
16 Narrow SO  
16 CERDIP  
10 TO-100  
Threshold Detectors  
*
Contact factory for availability of 20-pin PLCC.  
** Contact factory for dice specifications.  
High-Speed Triggers  
__________________________________________________________P in Co n fig u ra t io n s  
TOP VIEW  
GND1  
GND1  
V+  
1
2
3
4
5
6
7
8
16 GND2  
15 N.C.  
V+  
GND2  
10  
MAX9685  
1
4
9
6
IN+  
IN-  
14 N.C.  
IN+  
IN-  
Q OUT  
Q OUT  
2
3
8
7
13 N.C.  
N.C.  
LE  
12 Q OUT  
11 Q OUT  
10 N.C.  
N.C.  
V-  
5
LE  
N.C.  
9
N.C.  
V-  
TO-100  
DIP/SO  
________________________________________________________________ Maxim Integrated Products  
1
Ca ll t o ll fre e 1 -8 0 0 -9 9 8 -8 8 0 0 fo r fre e s a m p le s o r lit e ra t u re .  
Ult ra -Fa s t ECL-Ou t p u t Co m p a ra t o r  
w it h La t c h En a b le  
ABSOLUTE MAXIMUM RATINGS  
Supply Voltages .....................................................................±6V  
Output Short-Circuit Duration .......................................Indefinite  
Input Voltages ........................................................................±5V  
Differential Input Voltages .....................................................7.0V  
Output Current ....................................................................30mA  
CERDIP (derate 10.00mW/°C above +70°C)...............800mW  
TO-100 (derate 6.67mW/°C above +70°C)..................533mW  
Operating Temperature Ranges  
MAX9685C_ _ .....................................................0°C to +70°C  
MAX9685E_ _ ..................................................-40°C to +85°C  
MAX9685M_ _................................................-55°C to +125°C  
Storage Temperature Range .............................-55°C to +150°C  
Lead Temperature (soldering, 10sec) .............................+300°C  
Continuous Power Dissipation (T = +70°C)  
A
Plastic DIP (derate 10.53mW/°C above +70°C) ..........842mW  
Narrow SO (derate 8.70mW/°C above +70°C) ............696mW  
MAX9685  
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional  
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to  
absolute maximum rating conditions for extended periods may affect device reliability.  
ELECTRICAL CHARACTERISTICS  
(V+ = +5V, V- = -5.2V, R = 50Ω, V = -2V, T = +25°C, unless otherwise noted.)  
L
T
A
MAX9685C/E  
MAX9685M  
PARAMETER  
SYMBOL  
CONDITIONS  
UNITS  
MIN  
TYP MAX  
MIN  
TYP MAX  
T
= +25°C  
-5  
-7  
5
-5  
-8  
5
A
Input Offset Voltage  
V
R
=100Ω  
S
mV  
µV/°C  
µA  
OS  
T
A
= T  
to T  
MAX  
7
8
MIN  
Temperature Coefficient ∆V /∆T  
10  
15  
OS  
T
A
= +25°C  
5
5
Input Offset Current  
I
OS  
T
A
= T  
to T  
MAX  
8
12  
MIN  
T
= +25°C  
10  
20  
30  
10  
20  
40  
A
Input Bias Current  
I
µA  
V
B
T
A
= T to T  
MIN MAX  
Input Voltage Range  
V
CM  
(Note 1)  
-2.5  
80  
+2.5  
-2.5  
80  
+2.5  
Common-Mode  
Rejection Ratio  
CMRR  
dB  
Power-Supply  
Rejection Ratio  
PSRR  
60  
3
60  
3
dB  
Input Resistance  
R
C
(Note 1)  
60  
60  
kΩ  
IN  
IN  
Input Capacitance  
pF  
T
= T  
= T  
-1.05  
-0.89  
-0.96  
-1.14  
-0.88  
-0.96  
-1.89  
-1.83  
-1.85  
-1.90  
-1.83  
-1.85  
-0.87  
-0.70  
-0.81  
-0.88  
-0.70  
-0.81  
-1.69  
-1.57  
-1.65  
-1.65  
-1.57  
-1.65  
22  
-1.16  
0.88  
-0.89  
-0.69  
-0.81  
A
MIN  
MAX9685C,  
MAX9685M  
T
A
MAX  
T
A
= +25°C  
-0.96  
Logic Output High  
Voltage  
V
V
V
OH  
T
A
= T  
= T  
MIN  
MAX9685E  
T
A
MAX  
T
A
= +25°C  
T
A
= T  
-1.90  
-1.82  
-1.85  
-1.65  
-1.55  
-1.65  
MIN  
MAX9685C,  
MAX9685M  
T
A
= T  
MAX  
T
A
= +25°C  
Logic Output Low  
Voltage  
V
OL  
T
A
= T  
= T  
MIN  
T
A
MAX9685E  
MAX  
T
A
= +25°C  
T
A
= +25°C  
16  
20  
16  
20  
22  
25  
32  
36  
Positive Supply Current  
I
mA  
mA  
CC  
T
A
= T  
to T  
24  
MIN  
MAX  
T
A
= +25°C  
32  
Negative Supply  
Current  
I
EE  
T
A
= T  
to T  
36  
MIN  
MAX  
2
_______________________________________________________________________________________  
Ult ra -Fa s t ECL-Ou t p u t Co m p a ra t o r  
w it h La t c h En a b le  
MAX9685  
SWITCHING CHARACTERISTICS  
(V+ = 5V, V- = -5.2V, R = 50Ω, V = -2V, T = +25°C, unless otherwise noted.)  
L
T
A
MAX9685C/E  
MIN TYP MAX  
MAX9685M  
MIN TYP MAX  
PARAMETER  
SYMBOL  
CONDITIONS  
UNITS  
T
= +25°C  
1.3  
1.5  
1.8  
2.0  
1.3  
1.8  
A
Input to Output High  
(Notes 1, 2)  
t
T
A
= 0°C to +70°C  
= -55°C to +125°C  
= +25°C  
ns  
pd+  
T
A
1.7  
1.3  
2.4  
1.8  
T
A
1.3  
1.5  
1.8  
2.0  
Input to Output Low  
(Notes 1, 2)  
t
T
A
= 0°C to +70°C  
= -55°C to +125°C  
= +25°C  
ns  
ns  
pd-  
T
A
1.7  
1.2  
2.4  
1.7  
T
A
1.2  
1.4  
1.7  
2.0  
Latch-Enable to Output  
High (Notes 1, 2)  
t
(E)  
(E)  
T
A
= 0°C to +70°C  
= -55°C to +125°C  
= +25°C  
pd+  
T
A
2.0  
1.2  
3.0  
1.7  
T
A
1.2  
1.4  
1.7  
2.0  
Latch-Enable to Output  
High (Notes 1, 2)  
t
T
A
= 0°C to +70°C  
= -55°C to +125°C  
ns  
ns  
pd-  
T
A
2.0  
2.0  
3.0  
Latch-Enable Pulse  
Width (Note 2)  
t
(E)  
3.0  
2.0  
3.0  
pw  
Minimum Setup Time  
Minimum Hold Time  
t
0.5  
0.5  
1.0  
1.0  
0.5  
0.5  
1.0  
1.0  
ns  
ns  
s
t
h
Note 1: Not tested, guaranteed by design.  
Note 2: V = 100mV, V = 10mV  
IN  
OD  
minimum slew-rate requirements. The tendency of the  
part to oscillate is a function of the layout and source  
impedance of the circuit employed. Poor layout and  
larger source impedance will increase the minimum  
slew-rate requirement.  
__________Ap p lic a t io n s In fo rm a t io n  
La yo u t  
Because of the MAX9685’s large gain-bandwidth char-  
acteristic, special precautions need to be taken if its  
high-speed capabilities are to be used. A PC board  
with a ground plane is mandatory. Mount all decou-  
pling capacitors as close to the power-supply pins as  
possible, and process the ECL outputs in microstrip  
fashion, consistent with the load termination of 50Ω to  
120Ω. For low-impedance applications, microstrip lay-  
out at the input may also be helpful. Pay close atten-  
tion to the bandwidth of the decoupling and terminating  
components. Chip components can be used to mini-  
mize lead inductance. An unused LE pin must be con-  
nected to ground.  
Figure 1 shows a high-speed receiver application with  
50Ω input and output termination. With this configura-  
tion, in which a ground plane and microstrip PC board  
were used, the minimum slew rate for clean output  
switching is 1.6V/µs. Sine-wave inputs imply a mini-  
mum s ig na l s ize of 360mV  
a t 500kHz a nd  
RMS  
90mV  
at 4MHz.  
RMS  
Slew Rate  
E
=
RMS  
2
2nf  
In many applications, the addition of regenerative feed-  
b a c k will a s s is t the inp ut s ig na l throug h the line a r  
region, which will lower the minimum slew-rate require-  
ment considerably. For example, with the addition of  
In p u t S le w -Ra t e Re q u ire m e n t s  
As with all high-speed comparators, the high gain-  
bandwidth product of these devices creates oscillation  
problems when the input traverses through the linear  
region. For clean switching without oscillation or steps  
in the output waveform, the input must meet certain  
p os itive fe e d b a c k c omp one nts R = 1kΩ a nd C  
=
f
f
10p F, the minimum s le w-ra te re q uire me nt c a n b e  
reduced by a factor of four.  
_______________________________________________________________________________________  
3
Ult ra -Fa s t ECL-Ou t p u t Co m p a ra t o r  
w it h La t c h En a b le  
INPUT  
OUTPUT  
20mV/div  
2ns/div  
500mV/div  
50Ω  
V
IN  
LE  
INPUT  
-0V  
50Ω  
MAX9685  
-2V  
OUTPUT  
-0.9V  
-1.7V  
R
f
C
f
50Ω  
50Ω  
Figure 1. Regenerative Feedback. High-speed receiver with  
50Ω input and output termination.  
Figure 2. As a high-speed receiver, the MAX9685 is capable  
of processing signals in excess of 600MHz. Figure 2 is a  
100MHz example with an input signal level of 14mV  
.
RMS  
The timing diagram (Figure 3) illustrates the series of  
e ve nts tha t c omp le te the c omp a re func tion, und e r  
worst-case conditions.  
t
t
Input to Output Low Delay—The propagation  
delay measured from the time the input signal  
crosses the input offset voltage to the 50%  
point of an output high-to-low transition.  
pd-  
The top line of the diagram illustrates two latch-enable  
pulses. Each pulse is high for the compare function  
and low for the latch function. The first pulse demon-  
strates the compare function; part of the input action  
takes place during the compare mode. The second  
pulse demonstrates a compare-function interval during  
which there is no change in the input.  
(E) La tc h-Ena b le to Outp ut Hig h De la y—The  
propagation delay measured from the 50%  
point of the latch-enable signal low-to-high  
transition to the 50% point of an output low-to-  
high transition.  
pd+  
t
(E) La tc h-Ena b le to Outp ut Low De la y—The  
propagation delay measured from the 50%  
point of the latch-enable signal low-to-high  
transition to the 50% point of an output high-  
to-low transition.  
pd-  
The leading edge of the input signal (illustrated as a  
large-amplitude, small-overdrive pulse) switches the  
comparator after time interval t  
.
Output Q and Q  
transistors are similar in timing. The input signal must  
occur at time t before the latch falling edge, and it  
pd  
s
must be maintained for time t after the edge to be  
h
t
t
(E) Minimum La tc h-Ena b le Puls e Wid th—The  
minimum time the latch-enable signal must be  
high to acquire and hold an input signal.  
pw  
acquired. After t , the output is no longer affected by  
h
the input status until the latch is again strobed. A mini-  
mum la tc h p ulse width of t (E) is ne e de d for the  
pw  
Minimum Se tup Time —The minimum time  
before the negative transition of the latch-  
enable pulse that an input signal must be pre-  
sent to be acquired and held at the outputs.  
s
strobe operation, and the output transitions occur after  
a time t (E).  
pd  
De fin it io n o f Te rm s  
V
OS  
Input Offset Voltage—The voltage required  
between the input terminals to obtain 0V dif-  
ferential at the output.  
t
Minimum Hold Time—The minimum time after  
the negative transition of the latch-enable signal  
that an input signal must remain unchanged to  
be acquired and held at the output.  
h
V
Input Voltage Pulse Amplitude  
Input Voltage Overdrive  
IN  
V
OD  
t
Input to Output High Delay—The propagation  
delay measured from the time the input signal  
crosses the input offset voltage to the 50%  
point of an output low-to-high transition.  
pd+  
4
_______________________________________________________________________________________  
Ult ra -Fa s t ECL-Ou t p u t Co m p a ra t o r  
w it h La t c h En a b le  
MAX9685  
COMPARE  
LATCH  
50%  
ENABLE  
t (E)  
pw  
t
s
LATCH  
t
h
DIFFERENTIAL  
INPUT  
V
IN  
VOLTAGE  
V
OS  
V
OD  
t
pd  
t (E)  
pd  
50%  
50%  
Q
Q
Figure 3. Timing Diagram  
_______________________________________________________________________________________  
5
Ult ra -Fa s t ECL-Ou t p u t Co m p a ra t o r  
w it h La t c h En a b le  
________________________________________________________P a c k a g e In fo rm a t io n  
INCHES  
MILLIMETERS  
DIM  
E
MIN  
MAX  
0.200  
–
MIN  
–
MAX  
5.08  
–
A
–
E1  
D
A1 0.015  
A2 0.125  
A3 0.055  
0.38  
3.18  
1.40  
0.41  
1.14  
0.20  
0.13  
7.62  
6.10  
2.54  
7.62  
–
0.175  
0.080  
0.022  
0.065  
0.012  
0.080  
0.325  
0.310  
–
4.45  
2.03  
0.56  
1.65  
0.30  
2.03  
8.26  
7.87  
–
A3  
A2  
A1  
A
L
MAX9685  
B
0.016  
B1 0.045  
0.008  
D1 0.005  
0.300  
E1 0.240  
0.100  
eA 0.300  
C
0° - 15°  
E
C
e
e
B1  
eA  
eB  
–
–
B
eB  
L
–
0.400  
0.150  
10.16  
3.81  
0.115  
2.92  
D1  
INCHES  
MILLIMETERS  
PKG. DIM  
PINS  
Plastic DIP  
PLASTIC  
DUAL-IN-LINE  
PACKAGE  
(0.300 in.)  
MIN  
MAX MIN  
MAX  
8
P
P
P
P
P
N
D
D
D
D
D
D
0.348 0.390 8.84  
9.91  
14  
16  
18  
20  
24  
0.735 0.765 18.67 19.43  
0.745 0.765 18.92 19.43  
0.885 0.915 22.48 23.24  
1.015 1.045 25.78 26.54  
1.14 1.265 28.96 32.13  
21-0043A  
INCHES  
MILLIMETERS  
DIM  
MIN  
MAX  
0.069  
0.010  
0.019  
0.010  
0.157  
MIN  
1.35  
0.10  
0.35  
0.19  
3.80  
MAX  
1.75  
0.25  
0.49  
0.25  
4.00  
A
0.053  
D
A1 0.004  
B
C
E
e
0.014  
0.007  
0.150  
0°-8°  
A
0.101mm  
0.004in.  
0.050  
1.27  
e
H
L
0.228  
0.016  
0.244  
0.050  
5.80  
0.40  
6.20  
1.27  
A1  
C
B
L
INCHES  
MILLIMETERS  
DIM PINS  
Narrow SO  
SMALL-OUTLINE  
PACKAGE  
MIN MAX  
MIN  
MAX  
5.00  
8.75  
8
0.189 0.197 4.80  
D
D
D
E
H
14 0.337 0.344 8.55  
16 0.386 0.394 9.80 10.00  
21-0041A  
(0.150 in.)  
6
_______________________________________________________________________________________  
Ult ra -Fa s t ECL-Ou t p u t Co m p a ra t o r  
w it h La t c h En a b le  
MAX9685  
___________________________________________P a c k a g e In fo rm a t io n (c o n t in u e d )  
INCHES  
MIN  
MILLIMETERS  
DIM  
MAX  
0.200  
0.023  
0.065  
0.015  
0.310  
0.320  
MIN  
–
MAX  
5.08  
0.58  
1.65  
0.38  
7.87  
8.13  
E1  
E
A
B
–
0.014  
0.36  
0.97  
0.20  
5.59  
7.37  
D
B1 0.038  
A
C
E
0.008  
0.220  
E1 0.290  
e
L
0.100  
2.54  
0.125  
0.150  
0.015  
–
0.200  
–
3.18  
3.81  
0.38  
–
5.08  
–
0°-15°  
C
Q
L1  
Q
S
L
L1  
0.070  
0.098  
–
1.78  
2.49  
–
e
B1  
S1 0.005  
0.13  
B
S1  
S
INCHES  
MILLIMETERS  
DIM PINS  
MIN  
–
MAX MIN MAX  
CERDIP  
D
D
D
D
D
D
8
0.405  
0.785  
0.840  
0.960  
1.060  
1.280  
–
–
–
–
–
–
10.29  
19.94  
21.34  
24.38  
26.92  
CERAMIC DUAL-IN-LINE  
PACKAGE  
14  
16  
18  
20  
24  
–
–
–
(0.300 in.)  
–
–
32.51  
21-0045A  
INCHES  
MILLIMETERS  
DIM  
φD  
MIN  
MAX  
MIN  
4.19  
0.41  
0.41  
8.51  
7.75  
2.79  
MAX  
4.70  
0.48  
0.53  
9.40  
8.51  
4.06  
A
0.165  
0.016  
0.185  
0.019  
0.021  
0.375  
0.335  
0.160  
φD1  
φb  
φb1 0.016  
φD 0.335  
φD1 0.305  
φD2 0.110  
F
L1  
A
Q
L2  
e
e1  
F
0.230 BSC  
0.115 BSC  
5.84 BSC  
2.92 BSC  
1.02  
L
BASE &  
SEATING  
PLANE  
φb  
0.040  
0.034  
0.045  
0.750  
0.050  
k
0.027  
0.027  
0.500  
0.69  
0.69  
0.86  
1.14  
φb1  
e
k1  
L
12.70  
19.05  
1.27  
e1  
L1  
L2  
Q
α
0.250  
0.010  
6.35  
0.25  
β
0.045  
1.14  
36° BSC  
36° BSC  
36° BSC  
β
36° BSC  
21-0023A  
α
10-PIN  
φD2  
TO-100 METAL CAN  
PACKAGE  
k1  
k
_______________________________________________________________________________________  
7
Ult ra -Fa s t ECL-Ou t p u t Co m p a ra t o r  
w it h La t c h En a b le  
MAX9685  
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are  
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.  
8
___________________Ma x im In t e g ra t e d P ro d u c t s , 1 2 0 S a n Ga b rie l Drive , S u n n yva le , CA 9 4 0 8 6 (4 0 8 ) 7 3 7 -7 6 0 0  
© 19943 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.  

相关型号：

SI9130DB

 5- and 3.3-V Step-Down Synchronous Converters

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY

SI9135LG-T1

 SMBus Multi-Output Power-Supply Controller

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY

SI9135LG-T1-E3

 SMBus Multi-Output Power-Supply Controller

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY

SI9135_11

 SMBus Multi-Output Power-Supply Controller

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY

SI9136_11

 Multi-Output Power-Supply Controller

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY

SI9130CG-T1-E3

 Pin-Programmable Dual Controller - Portable PCs

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY

SI9130LG-T1-E3

 Pin-Programmable Dual Controller - Portable PCs

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY

SI9130_11

 Pin-Programmable Dual Controller - Portable PCs

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY

SI9137

 Multi-Output, Sequence Selectable Power-Supply Controller for Mobile Applications

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY

SI9137DB

 Multi-Output, Sequence Selectable Power-Supply Controller for Mobile Applications

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY

SI9137LG

 Multi-Output, Sequence Selectable Power-Supply Controller for Mobile Applications

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY

SI9122E

 500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification Drivers

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
©2020 ICPDF网 联系我们和版权申明