MAX9383 [MAXIM]
ECL/PECL Phase-Frequency Detectors ; ECL / PECL相位频率检测器\n
| 型号： | MAX9383 |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | ECL/PECL Phase-Frequency Detectors
|
| 文件： | 总10页 (文件大小：215K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-2234; Rev 1; 11/02
ECL/PECL Phase-Frequency Detectors
General Description
Features
The MAX9382/MAX9383 are high-speed PECL/ECL
phase-frequency detectors designed for use in high-
bandwidth phase-locked loop (PLL) applications. The
devices compare a single-ended reference (R) and a
VCO (V) input and produce pulse streams on differen-
tial up (U) and down (D) outputs. When integrated, the
difference of the output pulse streams provides a con-
trol voltage proportional to input phase or frequency dif-
ference. Guaranteed minimum short pulse duration
completely eliminates minimum phase difference
requirements during the lock condition, maximizing
loop jitter performance.
ꢀ Guaranteed Minimum Pulse Width Eliminates
Dead Band
ꢀ 450MHz Typical Bandwidth with up to ±π Phase
Detection
ꢀ 75kΩ Internal Input Pulldown Resistors
ꢀ 44mA Typical Supply Current
ꢀ ±±kꢀ ESD Protection ꢁHuman Body Modelꢂ
ꢀ Pin Compatible with MCK1±140 and MCH1±140
ꢀ Available in 8-Pin µMAX and SO Packages
The MAX9382/MAX9383 feature low propagation and
reset delay, making them ideal for high-frequency clock
synchronization use. The MAX9382 uses 100K logic
levels, has a supply voltage range of V
- V = 4.2V
EE
CC
to 5.5V, and is pin compatible with Motorola’s
MCK12140. The MAX9383 uses 10H logic levels with a
supply voltage range of V
- V = 4.75V to 5.5V and
EE
CC
Ordering Information
is pin compatible with the MCH12140.
The MAX9382/MAX9383 are available in industry-stan-
dard 8-pin SO and space-saving 8-pin µMAX packages.
PART
TEMP RANGE
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
PIN-PACKAGE
8 µMAX
8 SO
MAX938±EUA*
MAX9382ESA
MAX9383EUA*
MAX9383ESA
Applications
8 µMAX
8 SO
Precision Clock Distribution
*Future product—contact factory for availability.
Central Office
DSLAM
DLC
Base Station
ATE
Functional Diagram
Pin Configuration
TOP VIEW
U
U
R
MAX9382
MAX9383
R
U
U
D
D
1
2
3
4
8
7
6
5
V
R
V
V
CC
Q
S
MAX9382
MAX9383
S
Q
R
D
EE
V
D
µMAX/SO
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
ECL/PECL Phase-Frequency Detectors
ABSOLUTE MAXIMUM RATINGS
V
- V ............................................................................+6.0V
Junction-to-Case Thermal Resistance
CC
EE
Inputs (R, V).................................................(V ) to (V - 0.3V)
8-Pin µMAX ...............................................................+39°C/W
8-Pin SO....................................................................+40°C/W
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature......................................................+±50°C
Storage Temperature Range.............................-65°C to +±50°C
ESD Protection
CC
EE
Continuous Output Current.................................................50mA
Surge Output Current........................................................±00mA
Junction-to-Ambient Thermal Resistance in Still Air*
8-Pin µMAX ..............................................................+22±°C/W
8-Pin SO ..................................................................+±70°C/W
Junction-to-Ambient Thermal Resistance with*
Human Body Model (R, V, U, U, D, D)............................±2ꢀV
Soldering Temperature (±0s).......................................... +300°C
500LFPM Airflow
8-Pin µMAX ..............................................................+±55°C/W
8-Pin SO.....................................................................+99°C/W
*Ratings are for single-layer board.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
MAX938± DC ELECTRICAL CHARACTERISTICS
(V
- V = 4.2V to 5.5V. Outputs loaded with 50Ω ±±1 to V
- 2V, unless otherwise noted. Typical values at V - V = 4.5V.)
CC EE
CC
EE
CC
(Notes ±, 2, 3)
-40°C
+85°C
+±5°C
TYP
PARAMETER
INPUTS ꢁR, ꢀꢂ
CONDITIONS
UNITS
SYMBOL
MIN
TYP
MAX
MIN
MAX
MIN
TYP
MAX
Input High
Voltage
V
-
V
-
V
-
V
-
V
-
V
-
CC
CC
CC
CC
CC
CC
V
V
V
IH
±.±65
0.880 ±.±65
0.880 ±.±65
0.880
Input Low
Voltage
V
-
V
-
V
-
V
-
V
-
V
-
CC
CC
CC
CC
CC
CC
V
IL
±.8±0
±.475 ±.8±0
±. 475 ±.8±0
±.475
Input High
Current
I
V
V
= V
= V
±50
±50
±50
µA
µA
IH
IN
IN
IHMAX
ILMIN
Input Low
Current
I
0.5
0.5
0.5
IL
OUTPUTS ꢁU, U, D, Dꢂ
Single-Ended
Output High
Voltage
V
V
= V or
V
-
V
-
V
-
V
-
V
-
V
-
V
-
V
-
V
-
CC
IN
IL
IH
CC
CC
CC
CC
CC
CC
CC
CC
V
V
OH
±.085 0.990 0.880 ±.035 0.960 0.880 ±.035 0.940 0.880
Single-Ended
Output Low
Voltage
V
V
= V or
V
-
V
-
V
-
V
-
V
-
V
-
V
-
V
-
V
-
CC
IN
IL
IH
CC
CC
CC
CC
CC
CC
CC
CC
V
V
OL
±.890 ±.8±0 ±.555 ±.850 ±.770 ±.620 ±.8±0 ±.730 ±.600
Differential
Output Voltage
V
V
-
V
V
= V or
IH
OH
IN
IL
585
820
43
585
8±0
44
585
800
45
mV
mA
OL
POWER SUPPLY
Supply Current
I
(Note 4)
56
56
58
EE
±
_______________________________________________________________________________________
ECL/PECL Phase-Frequency Detectors
MAX9383 DC ELECTRICAL CHARACTERISTICS
(V
- V = 4.75V to 5.5V. Outputs loaded with 50Ω ±±1 to V
- 2V, unless otherwise noted. Typical values at V - V = 5.2V.)
CC EE
CC
EE
CC
(Notes ±, 2, 3)
-40°C
+±5°C
+85°C
PARAMETER SYMBOL CONDITIONS
UNITS
MIN
TYP
MAX
MIN
TYP
MAX
MIN
TYP
MAX
INPUTS ꢁR, ꢀꢂ
Input High
Voltage
V
-
V
-
V
-
V
-
V
-
V
-
CC
CC
CC
CC
CC
CC
V
V
V
IH
±.230
0.890 ±.±30
0.8±0 ±.060
0.720
Input Low
Voltage
V
-
V
-
V
-
V
-
V
-
V
-
CC
CC
CC
CC
CC
CC
V
IL
±.950
±.500 ±.950
±. 480 ±.950
±.480
Input High
Current
I
V
V
= V
= V
±50
±50
±50
µA
µA
IH
IN
IN
IHMAX
ILMIN
Input Low
Current
I
0.5
0.5
0.5
IL
OUTPUTS ꢁU, U, D, Dꢂ
Single-Ended
Output High
Voltage
V
V
= V or
V
-
V
-
V
-
V
-
V
-
V
-
V
-
V
-
V
-
CC
IN
IL
IH
CC
CC
CC
CC
CC
CC
CC
CC
V
V
OH
±.±±5 ±.0±0 0.890 0.980 0.924 0.8±0 0.945 0.900 0.720
Single-Ended
Output Low
Voltage
V
= V or
V
-
V
-
V
-
V
-
V
-
V
-
V
-
V
-
V
-
CC
IN
IH
CC
CC
CC
CC
CC
CC
CC
CC
V
V
OL
V
±.990
±.832 ±.650 ±.950
±.740 ±.630 ±.950
±.700 ±.595
IL
Differential
Output Voltage
V
V
-
V
V
= V or
IH
OH
IN
IL
650
822
37
650
8±7
38
650
803
mV
mA
OL
POWER SUPPLY
Supply Current
I
(Note 4)
52
52
39
52
EE
MAX938±/MAX9383 AC ELECTRICAL CHARACTERISTICS
(Over specified DC input parameters, f = ±00MHz, outputs loaded with 50Ω ±±1 to V
- 2V, unless otherwise noted.) (Note 5)
CC
-40°C
+±5°C
+85°C
PARAMETER SYMBOL CONDITIONS
UNITS
MIN
TYP
MAX
MIN
TYP
MAX
MIN
TYP
MAX
R Input to U
Output Delay
t
Figure ±
Figure ±
Figure ±
Figure ±
Figure ±
575
650
750
590
660
780
635
720
830
ps
ps
ps
ps
ps
PRU
V Input to D
Output Delay
t
t
575
945
945
370
650
750
590
960
960
370
660
780
635
720
830
PVD
R Input to D
Output Delay
±±20
±±20
470
±320
±320
±±±0
±±±0
450
±360
±360
±005
±005
370
±±50
±±50
430
±360
±360
PRD
V Input to U
Output Delay
t
PVU
Minimum Pulse
Duration
t
Pmin
_______________________________________________________________________________________
3
ECL/PECL Phase-Frequency Detectors
MAX938±/MAX9383 AC ELECTRICAL CHARACTERISTICS ꢁcontinuedꢂ
(Over specified DC input parameters, f = ±00MHz, outputs loaded with 50Ω ±±1 to V
- 2V, unless otherwise noted.) (Note 5)
CC
-40°C
+±5°C
+85°C
PARAMETER
SYMBOL CONDITIONS
UNITS
MIN
TYP
MAX
MIN
TYP
MAX
MIN
TYP
MAX
π usable
phase
difference
range
Maximum
Operating
Frequency
f
400
450
400
450
400
450
MAX
MHz
V
= 200MHz,
IN
30
70
28
60
28
60
501 duty
Phase Offset
ps
cycle (Note 6)
V
= 400MHz,
IN
Added Random
Jitter
ps
(RMS)
0.2
±.0
0.2
±.0
0.2
±.0
501 duty
cycle (Note 7)
t
RJ
Output Rise/ Fall
Time
201 to 801,
Figure 2
t , t
R
80
±60
±00
±80
±±0
±90
ps
F
Note 1: Measurements are made with the device in thermal equilibrium.
Note ±: Current into a pin is defined as positive. Current out of a pin is defined as negative.
Note 3: DC parameters are production tested at +85°C. DC limits are guaranteed by design and characterization over the full oper-
ating temperature range.
Note 4: All pins open except V
and V
.
EE
CC
Note 5: Guaranteed by design and characterization. Limits are set to ±6 sigma.
Note 6: Phase offset is defined as the difference in propagation delay timing between the two input paths. It is measured between
the U and D outputs at the differential crosspoint with a rising edge simultaneously applied at the R and V inputs.
Note 7: Device jitter added to the input signal.
4
_______________________________________________________________________________________
ECL/PECL Phase-Frequency Detectors
Typical Operating Characteristics
(V
- V = +4.5V (MAX9382) or V
- V = +5.2V (MAX9383), V = V
- ±.00V, V = V
- ±.60V, f = f = ±00MHz, outputs
CC
EE
CC
EE
IH
CC
IL
CC
R
V
loaded with 50Ω to V
- 2V, T = +25°C, unless otherwise noted.)
CC
A
MAX9382
TRANSITION TIME vs. TEMPERATURE
MAX9383
TRANSITION TIME vs. TEMPERATURE
SUPPLY CURRENT vs. TEMPERATURE
150
125
100
75
200
45.0
42.5
40.0
37.5
35.0
32.5
30.0
MAX9382
RISE TIME
FALL TIME
175
150
125
100
RISE TIME
FALL TIME
MAX9383
50
-40
-15
10
35
60
85
-40
-15
10
35
60
80
85
-40
-15
10
35
60
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
OUTPUT SHORT-PULSE DURATION
vs. TEMPERATURE
PROPAGATION DELAY
vs. TEMPERATURE
550
525
500
475
450
425
750
725
700
675
650
625
600
t
OR t
PVD
PRU
MAX9382
MAX9383
MAX9383
MAX9382
400
-15
85
-40
-15
10
35
60
80
-40
10
35
60
TEMPERATURE (°C)
TEMPERATURE (°C)
OUTPUT PHASE ERROR
vs. INPUT PHASE DIFFERENCE
DIFFERENTIAL OUTPUT VOLTAGE
vs. FREQUENCY
50
40
30
20
10
0
830
820
810
800
790
780
770
MAX9383
MAX9382
-4
-2
0
2
4
0
500
1000
1500
2000
INPUT PHASE DIFFERENCE (ns)
FREQUENCY (MHz)
_______________________________________________________________________________________
5
ECL/PECL Phase-Frequency Detectors
Pin Description
PIN
NAME
FUNCTION
Inverting Up Output. Pulse stream is generated at this pin when f > f or V lags R in phase.
R
V
±
U
Terminate with 50Ω resistor to V
- 2V or equivalent.
CC
Noninverting Up Output. Pulse stream is generated at this pin when f > f or V lags R in phase.
R
V
2
3
4
U
D
D
Terminate with 50Ω resistor to V
- 2V or equivalent.
CC
Inverting Down Output. Pulse stream is generated at this pin when f > f or R lags V in phase.
V
R
Terminate with 50Ω resistor to V
- 2V or equivalent.
CC
Noninverting Down Output. Pulse stream is generated at this pin when f > f or R lags V in phase.
V
R
Terminate with 50Ω resistor to V
- 2V or equivalent.
CC
5
6
7
V
EE
Negative Supply
V
R
Single-Ended VCO Input
Single-Ended Reference Input
Positive Supply. Bypass from V
capacitors as close to the device as possible with the smaller value capacitor closest to the device.
to V with 0.±µF and 0.0±µF ceramic capacitors. Place the
EE
CC
8
V
CC
detect phase differences up to ±2π. The application
Detailed Description
frequency and the characteristics of the device internal
The MAX9382/MAX9383 are high-speed phase or fre-
quency detectors. The MAX9382 is compatible with ±00K
reset circuits determine the usable input phase differ-
ence range.
logic and has a power-supply range of V
- V = 4.2V
EE
CC
to 5.5V. The MAX9383 is compatible with ±0H logic with a
Frequency Detection
Figure 4 is the state diagram for the MAX9382/
MAX9383. With the two inputs at the same frequency,
and input R leading input V, the device toggles
between states 0 and 2. Similarly, if input R lags input
V, the device toggles between states 0 and ±. With the
two inputs at different frequencies, the output becomes
a function of the frequency difference. The normalized
ideal transfer function is given by:
power-supply range of V
- V = 4.75V to 5.5V. Both
EE
CC
devices are specified to function from -40°C to +85°C.
Each device is symmetrical; the R and V input functions
may be swapped, together with the U and D output
functions, and the inputs and outputs relabeled.
Because of this device symmetry, a necessary condi-
tion for correct phase measurement operation is that
the U and D outputs must both be high (state 0 condi-
tion) when the rising edge of the leading input is
received. This condition is automatically generated
when the two inputs are at different frequencies.
fR
2fV
VOUT_AVE =±-
for fV > fR
and
Phase Detection
The MAX9382/MAX9383 are intended for use in high-
bandwidth PLL applications. These devices compare a
single-ended VCO input (V) to a single-ended refer-
ence input (R) to determine the phase or frequency
relationship between V and R. The device differential
outputs U, U and D, D provide pulse trains with duty
cycle proportional to the phase or frequency difference
between R and V. These outputs are the up and down
signals required to control the system VCO. Figure ±
shows typical waveforms when V leads R and V lags R.
Subtracting and integrating these two outputs provide
the necessary VCO control signal. Figure 3 shows the
device transfer function obtained. The detector can
fV
2fR
VOUT_AVE =±-
for fR > fV
Output Pulses
When inputs R and V are at the same phase and fre-
quency, outputs U, U and D, D produce a stream of
minimum duration pulses that occur at the rising edges
of the input waveforms. This is the locꢀ condition. If
either input starts to lead the other in phase, the width
of pulses on the corresponding output (U for R input, D
for V input) increases in proportion to the phase differ-
ence. In a PLL implementation, these outputs direct the
6
_______________________________________________________________________________________
ECL/PECL Phase-Frequency Detectors
R
V
U
U
D
D
t
t
PVU
t
Pmin
PRU
a) INPUT AND OUTPUT WAVEFORMS FOR V LEADING R
R
V
U
U
D
D
t
t
PRD
t
Pmin
PVD
b) INPUT AND OUTPUT WAVEFORMS FOR V LAGGING R
Figure 1. Typical Waveforms when f = f
R
V
system VCO to increase or decrease frequency to
maintain the locꢀ condition.
U - U
OR
80%
20%
80%
20%
The minimum output pulse duration is an important
parameter for the design of the signal processing func-
tions, which follow the phase detector. When controlling
a charge-pump integrator, a detector can produce a
dead-zone characteristic at the locꢀ condition if the
minimum pulse width is too short. MAX9382/MAX9383
eliminate this dead-zone characteristic, and the result-
ing phase offset at locꢀ, by providing a well-defined
minimum output pulse width.
D - D
t
t
R
F
Figure 2. Output Transition Times
PECL systems, connect V
to a positive supply and
CC
V
EE
to ground.
Applications Information
Power-Supply Bypassing
The MAX9382/MAX9383 input and output levels are
defined to be relative to the positive supply voltage. In
ECL systems, the positive supply voltage is convention-
ally chosen to be system ground. This arrangement
produces the best noise immunity, since ground is nor-
mally a system-wide reference voltage. Operate the
Adequate power-supply bypassing is necessary to
maximize the performance and noise immunity of ECL
devices. This is particularly true of a PECL system
where the power-supply voltage is used as a reference.
Bypass V
to V with high-frequency surface-mount
EE
ceramic 0.±µF and 0.0±µF capacitors in parallel and as
close to the device as possible, with the 0.0±µF capaci-
CC
devices with V
connected to ground and V con-
EE
CC
nected to a negative supply for ECL systems. With
_______________________________________________________________________________________
7
ECL/PECL Phase-Frequency Detectors
Circuit Board Traces
Input and output trace characteristics affect the perfor-
mance of ECL/PECL devices. Connect each of the
detector’s inputs and outputs to a 50Ω characteristic
impedance trace. Avoid impedance discontinuities,
maintain the distance between differential traces, avoid
sharp corners, and ꢀeep the electrical length of the dif-
ferential traces matched. This maximizes common-
mode noise rejection and reduces signal sꢀew. Trace
vias cause impedance discontinuities, so ꢀeep the
number of vias in the 50Ω traces to a minimum. Reduce
reflections by maintaining the 50Ω characteristic
impedance through connectors and across cables.
f > f
V
f < f
V
R
R
OR
OR
V LEADS R
V LAGS R
V
OH
AVG
(U)
V
V
OL
OH
AVG
(D)
V
V
OL
- V
OH
OL
AVG
(U - D)
0
Output Termination
V
4π
- V
OL
OH
Terminate outputs through 50Ω to V
- 2V or use an
CC
-4π
-3π
-2π
-π
π
2π
3π
0
equivalent Thevenin termination. When a single-ended
signal is taꢀen from a differential output, terminate both
outputs. For example, if the U output of the MAX9382 or
MAX9383 is connected to a single-ended input, termi-
nate both the U and U outputs.
Figure 3. Average Output Voltage vs. Phase Difference
tor closest to the device pins. Use multiple parallel vias
for ground plane connection to minimize inductance.
Chip Information
TRANSISTOR COUNT: 706
PROCESS: Bipolar
R
V
STATE 2
STATE 0
STATE 1
VCO
U = 0
D = 1
VCO
UP
U = 1
U = 1
D = 1
R
V
DOWN
D = 0
V
R
Figure 4. MAX9382/MAX9383 State Diagram
8
_______________________________________________________________________________________
ECL/PECL Phase-Frequency Detectors
Package Information
(The pacꢀage drawing(s) in this data sheet may not reflect the most current specifications. For the latest pacꢀage outline information,
go to www.maxim-ic.com/packages.)
4X S
8
8
MILLIMETERS
INCHES
DIM MIN
MAX
MAX
MIN
-
-
0.043
0.006
0.037
0.014
0.007
0.120
1.10
0.15
0.95
0.36
0.18
3.05
A
0.002
0.030
0.010
0.005
0.116
0.05
0.75
0.25
0.13
2.95
A1
A2
b
E
H
ÿ 0.50±0.1
c
D
e
0.0256 BSC
0.65 BSC
0.6±0.1
E
H
0.116
0.188
0.016
0∞
0.120
2.95
4.78
0.41
0∞
3.05
5.03
0.66
6∞
0.198
0.026
6∞
L
1
1
α
S
0.6±0.1
0.0207 BSC
0.5250 BSC
BOTTOM VIEW
D
TOP VIEW
A1
A2
A
c
α
e
L
b
SIDE VIEW
FRONT VIEW
PROPRIETARY INFORMATION
TITLE:
PACKAGE OUTLINE, 8L uMAX/uSOP
APPROVAL
DOCUMENT CONTROL NO.
REV.
1
21-0036
J
1
_______________________________________________________________________________________
9
ECL/PECL Phase-Frequency Detectors
Package Information (continued)
(The pacꢀage drawing(s) in this data sheet may not reflect the most current specifications. For the latest pacꢀage outline information,
go to www.maxim-ic.com/packages.)
INCHES
MILLIMETERS
DIM
A
MIN
MAX
0.069
0.010
0.019
0.010
MIN
1.35
0.10
0.35
0.19
MAX
1.75
0.25
0.49
0.25
0.053
0.004
0.014
0.007
N
A1
B
C
e
0.050 BSC
1.27 BSC
E
0.150
0.228
0.016
0.157
0.244
0.050
3.80
5.80
0.40
4.00
6.20
1.27
E
H
H
L
VARIATIONS:
INCHES
1
MILLIMETERS
DIM
D
MIN
MAX
0.197
0.344
0.394
MIN
4.80
8.55
9.80
MAX
5.00
N
8
MS012
AA
TOP VIEW
0.189
0.337
0.386
D
8.75 14
10.00 16
AB
D
AC
D
C
A
B
0∞-8∞
e
A1
L
FRONT VIEW
SIDE VIEW
PROPRIETARY INFORMATION
TITLE:
PACKAGE OUTLINE, .150" SOIC
APPROVAL
DOCUMENT CONTROL NO.
REV.
1
21-0041
B
1
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
10 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2002 Maxim Integrated Products
Printed USA
is a registered trademarꢀ of Maxim Integrated Products.
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