MAX9374-MAX9374A [MAXIM]
Differential LVPECL-to-LVDS Translators; 差分LVPECL至LVDS转换器
| 型号： | MAX9374-MAX9374A |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Differential LVPECL-to-LVDS Translators |
| 文件： | 总9页 (文件大小：168K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-2326; Rev 0; 1/02
Differential LVPECL-to-LVDS Translators
General Description
Features
The MAX9374 and MAX9374A are 2.0GHz differential
LVPECL-to-LVDS translators and are designed for tele-
com applications. They feature 250ps propagation
delay. The differential output conforms to the ANSI
TIA/EIA-644 LVDS standard. The inputs are biased with
internal resistors such that the output is differential low
ꢀ Guaranteed 2.0GHz Operating Frequency
ꢀ 250ps (typ) Propagation Delay
ꢀ 1.0ps RMS Jitter (typ)
ꢀ 2.375V to 2.625V Low-Voltage Supply Range
(MAX9374)
when inputs are open. An on-chip V reference output
BB
is available for single-ended operation.
ꢀ On-Chip V
Reference for Single-Ended Input
BB
The MAX9374 is designed for low-voltage operation
from a 2.375V to 2.625V power supply for use in 2.5V
systems. The MAX9374A is designed for 3.0V to 3.6V
operation in systems with a nominal 3.3V supply. Both
devices are offered in industry-standard 8-pin SOT23
and SO packages.
ꢀ Output Low for Open Inputs
ꢀ Output Conforms to ANSI TIA/EIA-644 LVDS
Standard
ꢀ ESD Protection >2.0kV (Human Body Model)
ꢀ Available in Small 8-Pin SOT23 Package
Ordering Information
Applications
Precision Clock Buffer
Low-Jitter Data Repeater
Central Office Clock Distribution
DSLAM/DLC
TEMP
RANGE
PIN-
PACKAGE
TOP
MARK
PART
MAX9374EKA-T
-40 C to +85 C 8 SOT23-8
-40 C to +85 C 8 SO
AAKU
—
MAX9374ESA
MAX9374AEKA-T -40 C to +85 C 8 SOT23-8
MAX9374AESA -40 C to +85 C 8 SO
AAKV
—
Base Station
Mass Storage
Pin Configurations/Functional Diagrams appear at end of
data sheet.
Typical Application Circuit
LVDS RECEIVER
MAX9374/MAX9374A
Z = 50Ω
0
D
Q
LVPECL
INPUT
100Ω
D
Q
Z = 50Ω
0
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
Differential LVPECL-to-LVDS Translators
ABSOLUTE MAXIMUM RATINGS
CC
V
to GND...........................................................................4.0V
Junction-to-Ambient Thermal Resistance with
V , V to GND..............................................-0.3V to V
+ 0.3V
500 LFPM Airflow
D
D
CC
V
V
to V ................................................................................3.0V
8-Pin SOT23...............................................................+78°C/W
8-Pin SO.....................................................................+99°C/W
Junction-to-Case Thermal Resistance
D
D
Sink/Source Current.......................................................1mA
BB
Short-Circuit Duration (Q, Q to GND).........................Continuous
8-Pin SOT23...............................................................+80°C/W
8-Pin SO.....................................................................+40°C/W
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range.............................-65°C to +150°C
ESD Protection
Short-Circuit Duration (Q to Q)...................................Continuous
Continuous Power Dissipation (T = +70°C)
A
8-Pin SOT23 (derate 8.9mW/°C above +70°C)............714mW
8-Pin SO (derate 5.9mW/°C above +70°C)..................470mW
Junction-to-Ambient Thermal Resistance
8-Pin SOT23.............................................................+112°C/W
8-Pin SO...................................................................+170°C/W
Human Body Model (D, D, Q, Q) .......................................2kV
Soldering Temperature (10s)...........................................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(V
= 2.375V to 2.625V for MAX9374, V
= 3.0V to 3.6V for MAX9374A, 100Ω 1ꢀ across outputs, V = 0.095V to V
or 3V,
CC
CC
ID
CC
whichever is less, V
= 1.2V to V , V
= GND to V
- 0.095V, unless otherwise noted. Typical values are at V
= 2.0V, V
=
ILD
IHD
CC ILD
CC
IHD
1.85V, V
= 3.3V for MAX9374A, V
= 2.5V for MAX9374.) (Notes 1, 2)
CC
CC
-40°C
+25°C
+85°C
PARAMETER
SYMBOL
)
CONDITIONS
UNITS
MIN TYP MAX MIN TYP MAX MIN TYP MAX
DIFFERENTIAL INPUT (D,
High Voltage of
Differential Input
V
Figure 1
Figure 1
1.2
V
1.2
V
1.2
V
CC
V
V
IHD
CC
CC
Low Voltage of
Differential Input
V
-
V
-
V
-
CC
CC
CC
V
GND
GND
GND
ILD
0.095
0.095
0.095
V
connected
BB
Single-Ended Input
High Voltage
to D (V for
V
-
V
-
V
-
CC
IL
CC
CC
V
V
V
V
CC
V
V
IH
CC
CC
1.165
1.165
1.165
V
connected
BB
to D), Figure 1
V
connected
BB
Single-Ended Input
Low Voltage
V
-
V
-
V
-
CC
to D (V for
CC
CC
IH
V
V
V
V
EE
IL
EE
EE
V
connected
1.475
1.475
1.475
BB
to D), Figure 1
V
V
V
< 3.0V
0.1
0.1
V
0.1
0.1
V
0.1
0.1
V
V
V
-
CC
CC
CC
CC
CC
IHD
Differential Input Voltage
Input Current
V
≥ 3.0V
3.0
3.0
3.0
ILD
, V
IHMAX ILMIN
I
-150
150 -150
150 -150
150
µA
IN
(Note 3)
DIFFERENTIAL OUTPUT (Q,
Output High Voltage
)
V
Figure 1
Figure 1
1.6
0.9
1.6
0.9
1.6
V
V
OH
Output Low Voltage
V
0.9
OL
Differential Output
Voltage
V
Figure 1
250
350
450
250
350
450
250
350
450
mV
OD
2
_______________________________________________________________________________________
Differential LVPECL-to-LVDS Translators
DC ELECTRICAL CHARACTERISTICS (continued)
(V
= 2.375V to 2.625V for MAX9374, V
= 3.0V to 3.6V for MAX9374A, 100Ω 1ꢀ across outputs, V = 0.095V to V
or 3V,
CC
CC
ID
CC
whichever is less, V
= 1.2V to V , V
= GND to V
- 0.095V, unless otherwise noted. Typical values are at V
= 2.0V, V
=
ILD
IHD
CC ILD
CC
IHD
1.85V, V
= 3.3V for MAX9374A, V
= 2.5V for MAX9374.) (Notes 1, 2)
CC
CC
-40°C
+25°C
+85°C
PARAMETER
SYMBOL
CONDITIONS
UNITS
MIN TYP MAX MIN TYP MAX MIN TYP MAX
25 25 25
1.125 1.25 1.375 1.125 1.25 1.375 1.125 1.25 1.375
Change in V
Between
OD
Complementary Output
States
∆V
1
1
1
mV
V
OD
Output Offset Voltage
V
OS
Change in V Between
OS
Complementary Output
States
∆V
3
25
30
3
25
30
3
25
30
mV
OS
Output Short-Circuit
Current
Q or Q short to
GND
I
23
23
23
mA
OSC
V
AND SUPPLY
BB
I
=
0.6mA
V
1.38
-
V
- V
-
V
- V
-
V
1.26
-
CC
BB
CC
CC
CC
CC
CC
Reference Voltage
Supply Current
V
V
BB
(Note 4)
1.26 1.38
1.26 1.38
I
(Note 5)
16
30
18
30
20
30
mA
CC
AC ELECTRICAL CHARACTERISTICS
(V
= 2.375V to 2.625V for MAX9374, V
= 3.0V to 3.6V for MAX9374A, 100Ω 1ꢀ across outputs, V
- V
= 0.15V to V
or
CC
CC
IHD
ILD
CC
3V, whichever is less, V
= 1.2V to V , V
= GND to V
- 0.15V, f = 1GHz, input transition time = 125ps, input duty cycle =
IHD
CC ILD
CC IN
50ꢀ, unless otherwise noted. Typical values are at V
unless otherwise noted.) (Notes 1, 6)
= 2.0V, V
= 1.85V, V
= 3.3V for MAX9374A, V
= 2.5V for MAX9374,
IHD
ILD
CC
CC
-40°C
+25°C
+85°C
PARAMETER
SYMBOL
CONDITIONS
UNITS
MIN TYP MAX MIN TYP MAX MIN TYP MAX
Differential Input to
Differential Output Delay
t
t
,
PLHD
PHLD
Figure 1
116
126
240
250
420
128
138
250
250
403
145
155
260
260
440
ps
Single-Ended Input to
Differential Output Delay
t
t
,
PLHS
Figure 1
(Note 7)
430
304
2
415
275
2
450
295
2
ps
ps
PHLS
Part-to-Part Skew
t
SKPP
f
= 1.0GHz,
IN
0.9
0.8
1
1
clock pattern
Added Random Jitter
(Note 8)
t
t
ps
(RMS)
RJ
f
= 2.0GHz,
IN
2
0.9
2
0.9
2
clock pattern
f
= 2.0Gbps,
IN
Added Deterministic
Jitter (Note 8)
223 -1 PRBS
pattern
45
75
46
75
38
75
ps
(P-P)
DJ
Operating Frequency
Output Rise/Fall Time
f
V
≥ 250mV
OD
2.0
2.2
92
2.0
2.2
91
2.0
2.2
90
MHz
ps
MAX
20% to 80%,
Figure 1
t , t
R
200
200
200
F
_______________________________________________________________________________________
3
Differential LVPECL-to-LVDS Translators
AC ELECTRICAL CHARACTERISTICS (continued)
(V
= 2.375V to 2.625V for MAX9374, V
= 3.0V to 3.6V for MAX9374A, 100Ω 1% across outputs, V
- V
= 0.15V to V
or
CC
CC
IHD
ILD
CC
3V, whichever is less, V
= 1.2V to V , V
= GND to V
- 0.15V, f = 1GHz, input transition time = 125ps, input duty cycle =
IHD
CC ILD
CC IN
50%, unless otherwise noted. Typical values are at V
unless otherwise noted.) (Notes 1, 6)
= 2.0V, V
= 1.85V, V
= 3.3V for MAX9374A, V
= 2.5V for MAX9374,
IHD
ILD
CC
CC
Note 1: Measurements are made with the device in thermal equilibrium.
Note 2: DC parameters are production tested at T = +25°C and guaranteed by design over the full operating temperature range.
A
Note 3: Current into a pin is defined as positive. Current out of a pin is defined as negative.
Note 4: Use V as a reference for inputs on the same device only.
BB
Note 5: 100Ω across the outputs, all other pins open except V
and GND.
CC
Note 6: Guaranteed by design and characterization. Limits are set at 6 sigma.
Note 7: Measured between outputs of different parts at the signal crossing points under identical conditions for a same-edge transition.
Note 8: Device jitter added to the input signal.
Typical Operating Characteristics
(MAX9374A, 100Ω 1% across outputs, f = 1GHz, input transition time = 125ps, input duty cycle = 50%, V
= 3.3V, V
= 2.0V,
IHD
IN
CC
V
= 1.85V, T = +25°C, unless otherwise noted.)
ILD
A
DIFFERENTIAL OUTPUT VOLTAGE (V
vs. FREQUENCY
)
OD
RISE/FALL TIME vs. TEMPERATURE
SUPPLY CURRENT vs. TEMPERATURE
MAX9374 toc02
140
120
100
80
400
350
300
250
200
150
100
3
2
1
0
24
22
20
18
16
14
12
10
100Ω LOAD
V
OD
RISE
JITTER
FALL
60
40
-40
-15
10
35
60
85
0.1 0.4 0.7 1.0 1.3 1.6 1.9 2.2
-40
-15
10
35
60
85
TEMPERATURE (°C)
FREQUENCY (GHz)
TEMPERATURE (°C)
PROPAGATION DELAY vs. HIGH VOLTAGE
OF DIFFERENTIAL INPUT (V
PROPAGATION DELAY vs. TEMPERATURE
)
IHD
280
260
240
220
200
180
300
280
260
240
220
200
1.2 1.5 1.8 2.1 2.4 2.7 3.0 3.3
(V)
-40
-15
10
35
60
85
V
TEMPERATURE (°C)
IHD
4
_______________________________________________________________________________________
Differential LVPECL-to-LVDS Translators
Pin Description
PIN
SOT23
NAME
FUNCTION
SO
Reference Output Voltage. Connect to the inverting or noninverting data input to provide a reference
1
4
V
for single-ended operation. When used, bypass with a 0.01µF ceramic capacitor to V ; otherwise,
CC
BB
leave it open.
2
3
4
5
3
2
GND
D
Ground. Provide a low-impedance connection to the ground plane.
Inverted LVPECL Data Input. 36.5kΩ pullup to V
and 75kΩ pulldown to GND.
CC
D
Noninverted LVPECL Data Input. 75kΩ pullup to V
and 75kΩ pulldown to GND.
CC
Positive Supply Voltage. Bypass V
to GND with 0.1µF and 0.01µF ceramic capacitors. Place the
CC
5
8
V
CC
capacitors as close to the device as possible with the smaller value capacitor closest to the device.
Noninverted LVDS Output. Typically terminate with 100Ω to Q.
Inverted LVDS Output. Typically terminate with 100Ω to Q.
6
7
8
7
6
1
Q
Q
N.C.
No Connection. Not internally connected.
D
D
V
V
IHD
ILD
V
- V
ILD
IHD
t
t
PHL_
PLH_
Q
Q
V
V
OH
OL
V
V
OS
OD
80%
80%
0 (DIFFERENTIAL)
0 (DIFFERENTIAL)
20%
20%
(Q) - (Q)
t
t
F
R
Figure 1. MAX9374/MAX9374A Timing Diagram
_______________________________________________________________________________________
5
Differential LVPECL-to-LVDS Translators
Differential LVDS Output
Detailed Description
The differential outputs conform to the ANSI TIA/EIA-644
LVDS standard. Typically, terminate the outputs with 100Ω
across Q and Q, as shown in the Typical Application
Circuit. The outputs are short-circuit protected.
The MAX9374/MAX9374A are 2.0GHz differential
LVPECL-to-LVDS translators. The output is differential
LVDS and conforms to the ANSI TIA/EIA-644 LVDS
standard. The inputs are biased with internal resistors
such that the output is differential low when inputs are
Applications Information
Supply Bypassing
to GND with high-frequency surface-mount
open. An on-chip V
reference output is available for
BB
single-ended input operation. The MAX9374 is
designed for low-voltage operation from 2.375V to
2.625V in systems with a nominal 2.5V supply. The
MAX9374A is designed for 3.0V to 3.6V operation in
systems with a nominal 3.3V supply.
Bypass V
CC
ceramic 0.1µF and 0.01µF capacitors in parallel and as
close to the device as possible, with the 0.01µF capaci-
tor closest to the device. Use multiple parallel vias to
minimize parasitic inductance. When using the V ref-
BB
Differential LVPECL Input
The MAX9374/MAX9374A accept differential LVPECL
inputs and can be configured to accept single-ended
erence output, bypass it with a 0.01µF ceramic capaci-
tor to V
(if the V
reference is not used, it can be
BB
CC
left open).
inputs through the use of the V voltage reference out-
BB
Controlled-Impedance Traces
put. The maximum magnitude of the differential signal
Input and output trace characteristics affect the perfor-
mance of the MAX9374/MAX9374A. Connect high-fre-
quency input and output signals to 50Ω characteristic
impedance traces. Minimize the number of vias to pre-
vent impedance discontinuities. Reduce reflections by
maintaining the 50Ω characteristic impedance through
cables and connectors. Reduce skew within a differen-
tial pair by matching the electrical length of the traces.
applied to the input is 3.0V or V , whichever is less.
CC
This limit also applies to the difference between any ref-
erence voltage input and a single-ended input.
Specifications for the high and low voltages of a differ-
ential input (V
and V ) and the differential input
ILD
- V ) apply simultaneously.
IHD
ILD
voltage (V
IHD
Single-Ended Inputs and V
BB
The differential inputs can be configured to accept a
Output Termination
Terminate the outputs with 100Ω across Q and Q as
shown in the Typical Application Circuit. Both outputs
must be terminated.
single-ended input through the use of the V
refer-
BB
ence voltage. A noninverting, single-ended input is pro-
duced by connecting V to the D input and applying a
BB
single-ended input signal to the D input. Similarly, an
inverting input is produced by connecting V to the D
BB
input and applying the input signal to the D input. With
a differential input configured as single ended (using
V
BB
), the single-ended input can be driven to V
and
CC
GND or with a single-ended LVPECL signal. Note that a
single-ended input must be at least V 95mV or a
differential input of at least 95mV to switch the outputs
to the V and V levels specified in the DC Electrical
BB
OH
OL
Characteristics table.
When using the V
reference output, bypass it with a
BB
0.01µF ceramic capacitor to V . If the V reference is
CC
BB
not used, leave it unconnected. Use V only for inputs
that are on the same device as the V reference.
BB
BB
Input Bias Resistors
Internal biasing resistors ensure a (differential) output-
low condition in the event that the inputs are not connect-
ed. The inverting input (D) is biased with a 36.5kΩ pull-
down to V
and a 75kΩ pullup to GND. The
CC
noninverting input (D) is biased with a 75kΩ pullup to
V
CC
and 75kΩ pulldown to GND.
6
_______________________________________________________________________________________
Differential LVPECL-to-LVDS Translators
Pin Configurations/Functional Diagrams
V
1
2
8
7
1
2
8
7
N.C.
Q
N.C.
D
V
CC
BB
75kΩ
75kΩ
75kΩ
75kΩ
36.5kΩ
GND
Q
3
4
6
5
3
4
6
5
D
D
Q
D
Q
36.5kΩ
75kΩ
75kΩ
V
V
GND
CC
BB
MAX9374/MAX9374A
MAX9374/MAX9374A
SOT23
SO
Chip Information
TRANSISTOR COUNT: 236
PROCESS: Bipolar
_______________________________________________________________________________________
7
Differential LVPECL-to-LVDS Translators
Package Information
8
_______________________________________________________________________________________
Differential LVPECL-to-LVDS Translators
Package Information (continued)
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 _____________________ 9
© 2002 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
相关型号：
MAX9374AEKA+T
PECL to LVDS Translator, 1 Func, Complementary Output, BIPolar, PDSO8, SOT-23, 8 PIN
MAXIM
MAX9374AESA+
PECL to LVDS Translator, 1 Func, Complementary Output, BIPolar, PDSO8, MS-012AA, SOIC-8
MAXIM
MAX9374AESA-T
PECL to LVDS Translator, 1 Func, Complementary Output, BIPolar, PDSO8, MS-012AA, SOIC-8
MAXIM
MAX9374EKA+T
PECL to LVDS Translator, 1 Func, Complementary Output, BIPolar, PDSO8, SOT-23, 8 PIN
MAXIM
MAX9374ESA+
PECL to LVDS Translator, 1 Func, Complementary Output, BIPolar, PDSO8, MS-012AA, SOIC-8
MAXIM
©2020 ICPDF网 联系我们和版权申明