MAX9240AGTM+ [MAXIM]
Line Receiver,;
| 型号： | MAX9240AGTM+ |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Line Receiver, 接口集成电路 |
| 文件： | 总51页 (文件大小：2110K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
EVALUATION KIT AVAILABLE
MAX9240A
6.25MHz to 100MHz, 25-Bit GMSL Deserializer for
Coax or STP Cable With Line Fault Detect
General Description
Benefits and Features
● Ideal for Camera Applications
• Works with Low-Cost 50Ω Coax Cable and FAKRA
Connectors or 100Ω STP
The MAX9240A compact deserializer is designed to
interface with a GMSL serializer over 50Ω coax or 100Ω
shielded twisted-pair (STP) cable. The device pairs with
the MAX9271 or MAX9273 serializers.
• Error Detection/Correction
• 9.6kbps to 1Mbps Control Channel in I C-to-I C
Mode with Clock Stretch Capability
• Best-in-Class Supply Current: 90mA (max)
• Double-Rate Clock for Megapixel Cameras
2
2
The parallel output is programmable for single or double
output. Double output strobes out half of a parallel word
on each pixel clock cycle. Double output can be used with
GMSL serializers that have the double-input feature.
•
Cable Equalization Allows 15m Cable at Full Speed
The device features an embedded control channel that
operates at 9.6kbps to 1Mbps. Using the control chan-
nel, a microcontroller (µC) can program the serializer/
deserializer and peripheral device registers at any time,
independent of video timing. Two programmable GPIO
ports and a continuously sampled GPI input are available.
• 48-Pin (7mm x 7mm) TQFN-EP Package with
0.5mm Lead Pitch
● High-Speed Data Deserialization for Megapixel
Cameras
• Up to 1.5Gbps Serial-Bit Rate with Single or
Double Output: 6.25MHz to 100MHz Clock
For use with longer cables, the device has a program-
mable equalizer. Programmable spread spectrum is avail-
able on the parallel output. The serial input meets ISO
10605 and IEC 61000-4-2 ESD standards. The core sup-
ply range is 1.7V to 1.9V and the I/O supply range is 1.7V
to 3.6V. The device is available in a 48-pin (7mm x 7mm)
TQFN-EP package with 0.5mm lead pitch and operates
over the -40°C to +105°C temperature range.
● Multiple Control-Channel Modes for System Flexibility
• 9.6kbps to 1Mbps Control Channel in UART-to-
2
UART or UART-to-I C Modes
● Reduces EMI and Shielding Requirements
• Input Programmable for 100mV to 500mV Single-
Ended or 50mV to 400mV Differential
• Programmable Spread Spectrum on the Parallel
Output Reduces EMI
Applications
• Tracks Spread Spectrum on Serial Input
● Automotive Camera Systems
● Peripheral Features for Camera Power-Up and
Verification
• Built-In PRBS Checker for BER Testing of the
Serial Link
• Fault Detection of Serial Link Shorted Together,
to Ground, to Battery, or Open
• Two GPIO Ports
• Dedicated “Up/Down” GPI for Camera Frame Sync
Trigger and Other Uses
Ordering Information appears at end of data sheet.
• Remote/Local Wake-Up from Sleep Mode
Typical Application Circuit appears at end of data sheet.
● Meets Rigorous Automotive and Industrial
Requirements
For related parts and recommended products to use with this part, refer
to www.maximintegrated.com/MAX9240A.related.
• -40°C to +105°C Operating Temperature
• ±10kV Contact and ±15kV Air IEC 61000-4-2 ESD
Protection
• ±10kV Contact and ±30kV Air ISO 10605 ESD
Protection
19-7319; Rev 0; 3/14
MAX9240A
6.25MHz to 100MHz, 25-Bit GMSL Deserializer for
Coax or STP Cable With Line Fault Detect
TABLE OF CONTENTS
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Benefits and Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Absolute Maximum Ratings* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Package Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Typical Operating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Functional Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Detailed Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Register Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Bit Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Serial Link Signaling and Data Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Reverse Control Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Data-Rate Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Control Channel and
Register Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
UART Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Interfacing Command-Byte-Only
2
I C Devices with UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
UART Bypass Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
2
I C Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
START and STOP Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Bit Transfer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Slave Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Bus Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Format for Writing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Format for Reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
2
I C Communication with Remote-Side Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
2
I C Address Translation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Control-Channel Broadcast Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
GPO/GPI Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
PRBS Test. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Line Equalizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Spread Spectrum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Maxim Integrated
│ 2
www.maximintegrated.com
MAX9240A
6.25MHz to 100MHz, 25-Bit GMSL Deserializer for
Coax or STP Cable With Line Fault Detect
TABLE OF CONTENTS (continued)
Manual Programming
of the Spread-Spectrum Divider. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Additional Error Detection and Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Cyclic Redundancy Check (CRC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Hamming Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
HS/VS Encoding and/or Tracking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Serial Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Coax-Mode Splitter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Cable Type Configuration Input (CX/TP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Sleep Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Power-Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Configuration Link. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Link Startup Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Applications Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Error Checking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
ERR Output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Autoerror Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Dual µC Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Changing the Clock Frequency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Fast Detection of
Loss-of-Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Providing a Frame Sync
(Camera Applications). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
Software Programming
of the Device Addresses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
Three-Level Configuration Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
Configuration Blocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
Compatibility with other GMSL Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
GPIOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
Staggered Parallel Outputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
Local Control-Channel Enable (LCCEN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Line-Fault Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Internal Input Pulldowns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
2
Choosing I C/UART Pullup Resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
AC-Coupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Selection of AC-Coupling Capacitors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Power-Supply Circuits and Bypassing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Power-Supply Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Maxim Integrated
│ 3
www.maximintegrated.com
MAX9240A
6.25MHz to 100MHz, 25-Bit GMSL Deserializer for
Coax or STP Cable With Line Fault Detect
TABLE OF CONTENTS (continued)
Cables and Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Board Layout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
ESD Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
Typical Application Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Chip Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
LIST OF FIGURES
Figure 1. Reverse Control-Channel Output Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 2. Test Circuit for Differential Input Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 2a. Line Fault . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 3. Worst-Case Pattern Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 4. Parallel Clock Output High and Low Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 5. I2C Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 6. Output Rise-and-Fall Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 7. Deserializer Delay. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 8. GPI-to-GPO Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 9. Lock Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 10. Power-Up Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 11. Single-Output Waveform (Serializer Using Single Input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 12. Single-Output Waveform (Serializer Using Double Input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 13. Double-Output Waveform (Serializer Using Single Input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 14. Double-Output Waveform (Serializer Using Double Input). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 15. Serial-Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 16. GMSL UART Protocol for Base Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 17. GMSL UART Data Format for Base Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 18. SYNC Byte (0x79). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 19. ACK Byte (0xC3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 20. Format Conversion Between GMSL UART and I2C with Register Address (I2CMETHOD = 0) . . . . . . . . 30
Figure 21. Format Conversion Between GMSL UART and I2C with Register Address (I2CMETHOD = 1) . . . . . . . . 30
Figure 22. START and STOP Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 23. Bit Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 24. Acknowledge. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 25. Slave Address. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 26. Format for I2C Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
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MAX9240A
6.25MHz to 100MHz, 25-Bit GMSL Deserializer for
Coax or STP Cable With Line Fault Detect
LIST OF FIGURES (continued)
Figure 27. Format for Write to Multiple Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 28. Format for I2C Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 29. 2:1 Coax-Mode Splitter Connection Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 30. Coax-Mode Connection Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 31. State Diagram, Remote Microcontroller Application. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 32. Human Body Model ESD Test Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 33. IEC 61000-4-2 Contact Discharge ESD Test Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 34. ISO 10605 Contact Discharge ESD Test Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
LIST OF TABLES
Table 1. Power-Up Default Register Map (see Table 16). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 2. Output Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 3. Data-Rate Selection Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
2
Table 4. I C Bit-Rate Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 5. Cable Equalizer Boost Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 6. Parallel Output Spread. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 7. Modulation Coefficients and Maximum SDIV Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 8. Configuration Input Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 9. Startup Procedure for Video-Display Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 10. Startup Procedure for Image-Sensing Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 11. MAX9240A Feature Compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 12. Staggered Output Delay. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
Table 13. Double-Function Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
Table 13a. Line Fault Mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
Table 14. Typical Power-Supply Currents (Using Worst-Case Input Pattern) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 15. Suggested Connectors and Cables for GMSL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 16. Register Table (see Table 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Maxim Integrated
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MAX9240A
6.25MHz to 100MHz, 25-Bit GMSL Deserializer for
Coax or STP Cable With Line Fault Detect
Absolute Maximum Ratings*
AVDD to EP.............................................................-0.5V to +1.9V
DVDD to EP...........................................................-0.5V to +1.9V
IOVDD to EP..........................................................-0.5V to +3.9V
IN+, IN- to EP.........................................................-0.5V to +1.9V
LMN_ TO EP (15mA current limit).........................-0.5V to +3.9V
TQFN (derate 40mW/°C above +70°C).....................3200mW
Junction Temperature......................................................+150°C
Operating Temperature Range......................... -40°C to +105°C
Storage Temperature Range............................. -65°C to +150°C
Lead Temperature (soldering, 10s).................................+300°C
Soldering Temperature (reflow).......................................+260°C
All other pins to EP................................-0.5V to (V
+ 0.5V)
IOVDD
IN+, IN- short circuit to ground or supply .................Continuous
Continuous Power Dissipation (T = +70°C)
*EP is connected to PCB ground.
A
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
(Note 1)
Package Thermal Characteristics
TQFN
Junction-to-Ambient Thermal Resistance (θ )...........25°C/W
Junction-to-Case Thermal Resistance (θ )..................1°C/W
JC
JA
Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer
board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.
DC Electrical Characteristics
(V
= V
= 1.7V to 1.9V, V
= 1.7V to 3.6V, R = 100Ω ±1% (differential), EP connected to PCB ground, T = -40°C to
AVDD
DVDD
IOVDD
L
A
+105°C, unless otherwise noted. Typical values are at V
= V
= V
= 1.8V, T = +25°C.)(Note 2)
AVDD
DVDD
IOVDD A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
SINGLE-ENDED INPUTS (I2CSEL, LCCEN, GPI, PWDN, MS/HVEN)
0.65 x
High-Level Input Voltage
V
V
IH1
V
IOVDD
0.35 x
Low-Level Input Voltage
V
V
IL1
V
IOVDD
Input Current
I
V
= 0V to V
IOVDD
-10
+20
µA
IN1
IN
THREE-LEVEL LOGIC INPUTS (CX/TP)
0.7 x
High-Level Input Voltage
Low-Level Input Voltage
V
V
V
IH
V
IOVDD
0.3 x
V
IL
V
IOVDD
Mid-Level Input Current
Input Current
I
(Note 3)
-10
+10
µA
µA
INM
I
-150
+150
IN
SINGLE-ENDED OUTPUTS (DOUT_, PCLKOUT)
V
V
IOVDD
- 0.3
DCS = 0
DCS = 1
High-Level Output Voltage
Low-Level Output Voltage
V
I
I
= -2mA
= 2mA
V
V
OH1
OUT
OUT
IOVDD
- 0.2
DCS = 0
DCS = 1
0.3
V
OL1
0.2
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MAX9240A
6.25MHz to 100MHz, 25-Bit GMSL Deserializer for
Coax or STP Cable With Line Fault Detect
DC Electrical Characteristics (continued)
(V
= V
= 1.7V to 1.9V, V
= 1.7V to 3.6V, R = 100Ω ±1% (differential), EP connected to PCB ground, T = -40°C to
AVDD
DVDD
IOVDD
L
A
+105°C, unless otherwise noted. Typical values are at V
= V
= V
= 1.8V, T = +25°C.)(Note 2)
AVDD
DVDD
IOVDD A
PARAMETER
SYMBOL
CONDITIONS
MIN
15
3
TYP
25
7
MAX
39
UNITS
V
V
V
V
V
V
V
V
= 3.0V to 3.6V
= 1.7V to 1.9V
= 3.0V to 3.6V
= 1.7V to 1.9V
= 3.0V to 3.6V
= 1.7V to 1.9V
= 3.0V to 3.6V
= 1.7V to 1.9V
V
= 0V,
DCS = 0
IOVDD
IOVDD
IOVDD
IOVDD
IOVDD
IOVDD
IOVDD
IOVDD
O
13
DOUT_
20
5
35
10
33
10
54
16
63
V
= 0V,
DCS = 1
O
21
Output Short-Circuit Current
I
mA
OS
15
5
50
V
= 0V,
DCS = 0
O
17
PCLKOUT
30
9
97
V
= 0V,
DCS = 1
O
32
OPEN-DRAIN INPUTS/OUTPUTS (GPIO0/DBL, GPIO1/BWS, RX/SDA/EDC, TX/SCL/ES, ERR, LOCK, LFLT)
0.7 x
High-Level Input Voltage
V
V
V
IH2
V
IOVDD
0.3 x
IOVDD
+5
Low-Level Input Voltage
V
IL2
V
RX/SDA, TX/SCL
-110
-80
Input Current
I
(Note 4)
LOCK, ERR, GPIO_, LFLT
DBL, BWS, EDC, ES
+5
+20
0.4
0.3
µA
IN2
-10
V
V
= 1.7V to 1.9V
= 3.0V to 3.6V
IOVDD
IOVDD
Low-Level Output Voltage
V
I
= 3mA
OUT
V
OL2
OUTPUT FOR REVERSE CONTROL CHANNEL (IN+, IN-)
Differential High Output Peak
V
No high-speed data transmission (Figure 1)
No high-speed data transmission (Figure 1)
30
60
mV
mV
ROH
Voltage, (V +) - (V -)
IN
IN
Differential Low Output Peak
Voltage, (V +) - (V -)
V
-60
-30
ROL
IN
IN
DIFFERENTIAL INPUTS (IN+, IN-)
Activity detector, medium
60
45
threshold (0x22 D[6:5] = 01)
(Figure 2)
Differential High Input Threshold
V
mV
mV
IDH(P)
(Peak) Voltage, (V +) - (V -)
IN
IN
Activity detector,
low threshold (0x22 D[6:5] = 00)
Activity detector, medium
-60
threshold (0x22 D[6:5] = 01)
(Figure 2)
Differential Low Input Threshold
(Peak) Voltage, (V +) - (V -)
V
IDL(P)
IN
IN
Activity detector, medium
-45
1
threshold (0x22 D[6:5] = 00)
Input Common-Mode Voltage
((V +) + (V -))/2
V
1.3
1.6
V
CMR
IN
IN
Differential Input Resistance
(Internal)
R
80
105
130
Ω
I
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MAX9240A
6.25MHz to 100MHz, 25-Bit GMSL Deserializer for
Coax or STP Cable With Line Fault Detect
DC Electrical Characteristics (continued)
(V
= V
= 1.7V to 1.9V, V
= 1.7V to 3.6V, R = 100Ω ±1% (differential), EP connected to PCB ground, T = -40°C to
AVDD
DVDD
IOVDD
L
A
+105°C, unless otherwise noted. Typical values are at V
= V
= V
= 1.8V, T = +25°C.)(Note 2)
AVDD
DVDD
IOVDD A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
SINGLE-ENDED INPUTS (IN+, IN-)
Activity detector, medium threshold
(0x22 D[6:5] = 01)
43
33
Single-Ended High Input
Threshold (Peak) Voltage,
(V +) - (V -)
V
mV
IDH(P)
Activity detector, low threshold
(0x22 D[6:5] = 00)
IN
IN
Activity detector, medium threshold
(0x22 D[6:5] = 01)
-43
Single-Ended Low Input
Threshold (Peak) Voltage,
(V +) - (V -)
V
mV
Ω
IDL(P)
Activity detector, medium threshold
(0x22 D[6:5] = 00)
-33
IN
IN
Input Resistance (Internal)
R
40
52.5
65
I
LINE FAULT DETECTION INPUT (LMN0, LMN1)
Short-to-GND Threshold
Normal Threshold
V
V
Figure 2A
Figure 2A
0.3
V
V
TG
0.57
1.07
TN
V
0.06
+
IO
Open Threshold
V
Figure 2A
1.45
V
TO
Open Input Voltage
V
Figure 2A
Figure 2A
1.47
1.75
V
V
IO
Short-to-Battery Threshold
POWER SUPPLY
V
2.47
TE
f
f
f
= 25MHz
= 50MHz
= 50MHz
= 100MHz
42
61
42
62
50
15
65
90
BWS = 0, single output,
EQ off
PCLKOUT
PCLKOUT
PCLKOUT
Worst-Case Supply Current
(Figure 3)
I
mA
WCS
70
BWS = 0, double output,
EQ off
f
90
PCLKOUT
Sleep Mode Supply Current
Power-Down Current
ESD PROTECTION
I
100
70
µA
µA
CCS
I
PWDN = EP
CCZ
Human Body Model, R = 1.5kΩ, C = 100pF
±8
D
S
IEC 61000-4-2,
Contact discharge
Air discharge
±10
R
C
= 330Ω,
= 150pF
D
S
±15
±10
IN+, IN- (Note 5)
V
V
kV
kV
ESD
ISO 10605,
Contact discharge
Air discharge
R
C
= 2kΩ,
= 330pF
D
S
±30
All Other Pins (Note 6)
Human Body Model, R = 1.5kΩ , C = 100pF
±4
ESD
D
S
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MAX9240A
6.25MHz to 100MHz, 25-Bit GMSL Deserializer for
Coax or STP Cable With Line Fault Detect
AC Electrical Characteristics
(V
= V
= 1.7V to 1.9V, V
= 1.7V to 3.6V, R = 100Ω ±1% (differential), EP connected to PCB ground, T = -40°C to
AVDD
DVDD
IOVDD
L
A
+105°C, unless otherwise noted. Typical values are at V
= V
= V
= 1.8V, T = +25°C.)(Note 2)
AVDD
DVDD
IOVDD A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
PARALLEL CLOCK OUTPUT (PCLKOUT)
BWS = 0, DRS = 1
8.33
16.66
6.25
12.5
25
16.66
50
BWS = 0, DRS = 0
BWS = 1, DRS = 1
12.5
37.5
75
Clock Frequency
f
MHz
PCLKOUT
BWS = 1, DRS = 0
BWS = 1, DRS = 0, 15-bit double input
BWS = 0, DRS = 0, 11-bit double input
33.33
40
100
60
Clock Duty Cycle
Clock Jitter
DC
t
/t or t
/t (Figure 4, Note 7)
50
%
HIGH T
LOW T
Period jitter, peak to peak, spread off,
t
1.5Gbps, PRBS pattern, UI = 1/f
0.05
UI
J
PCLKOUT
(Note 7)
I2C/UART PORT TIMING
I2C/UART Bit Rate
9.6
20
1000
120
kbps
30% to 70%, C = 10pF to 100pF,
L
Output Rise Time
t
ns
R
1kΩ pullup to V
IOVDD
70% to 30%, C = 10pF to 100pF,
L
Output Fall Time
t
20
120
ns
F
1kΩ pullup to V
IOVDD
Input Setup Time
t
I2C only (Figure 5, Note 7)
I2C only (Figure 5, Note 7)
100
ns
ns
SET
Input Hold Time
t
0
HOLD
SWITCHING CHARACTERISTICS
20% to 80%,
= 1.7V to
1.9V (Note 7)
DCS = 1, C = 10pF
0.4
0.5
0.25
0.3
0.5
0.6
0.3
0.4
2.2
2.8
1.7
2.0
3.1
3.8
2.2
2.4
L
V
IOVDD
DCS = 0, C = 5pF
L
PCLKOUT Rise-and-Fall Time
t , t
ns
R
F
20% to 80%,
DCS = 1, C = 10pF
L
V
= 3.0V to
IOVDD
DCS = 0, C = 5pF
3.6V (Note 7)
L
20% to 80%,
DCS = 1, C = 10pF
L
V
= 1.7V to
IOVDD
DCS = 0, C = 5pF
1.9V (Note 7)
L
Parallel Data Rise-and-Fall Time
(Figure 6)
t , t
ns
R
F
20% to 80%,
DCS = 1, C = 10pF
L
V
= 3.0V to
IOVDD
DCS = 0, C = 5pF
3.6V (Note 7)
L
Spread spectrum
enabled
6960
2160
400
(Figure 7,
Notes 7, 8)
Deserializer Delay
t
Bits
SD
Spread spectrum
disabled
Reverse Control-Channel Output
Rise Time
No forward-channel data transmission
t
180
180
ns
ns
R
(Figure 1, Note 7)
Reverse Control-Channel Output
Fall Time
No forward-channel data transmission
t
400
F
(Figure 1, Note 7)
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MAX9240A
6.25MHz to 100MHz, 25-Bit GMSL Deserializer for
Coax or STP Cable With Line Fault Detect
AC Electrical Characteristics (continued)
(V
= V
= 1.7V to 1.9V, V
= 1.7V to 3.6V, R = 100Ω ±1% (differential), EP connected to PCB ground, T = -40°C to
AVDD
DVDD
IOVDD
L
A
+105°C, unless otherwise noted. Typical values are at V
= V
= V
= 1.8V, T = +25°C.)(Note 2)
AVDD
DVDD
IOVDD A
PARAMETER
GPI-to-GPO Delay
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Deserializer GPI to serializer GPO
(cable delay not included) (Figure 8)
t
350
µs
GPIO
Spread spectrum enabled
Spread spectrum disabled
1.5
1
(Figure 9,
Note 7)
Lock Time
t
ms
ms
LOCK
Power-Up Time
t
(Figure 10)
6
PU
Note 2: Limits are 100% production tested at T = +105°C. Limits over the operating temperature range and relevant supply volt-
A
age range are guaranteed by design and characterization.
Note 3: To provide a midlevel, leave the input open, or, if driven, put driver in high impedance. High-impedance leakage current
must be less than ±10µA.
Note 4: I min due to voltage drop across the internal pullup resistor.
IN
Note 5: Specified pin to ground.
Note 6: Specified pin to all supply/ground.
Note 7: Guaranteed by design and not production tested.
Note 8: Measured in serial link bit times. Bit time = 1/(30 x f
) for BWS = GND. Bit time = 1/(40 x f
) for BWS = 1.
PCLKOUT
PCLKOUT
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MAX9240A
6.25MHz to 100MHz, 25-Bit GMSL Deserializer for
Coax or STP Cable With Line Fault Detect
Typical Operating Characteristics
(V
= V
= V
= 1.8V, DBL = low, T = +25°C, unless otherwise noted.)
AVDD
DVDD
IOVDD A
SUPPLY CURRENT
SUPPLY CURRENT
vs. PCLKOUT FREQUENCY (BWS = 0)
vs. PCLKOUT FREQUENCY (BWS = 1)
75
75
70
65
60
55
50
45
40
35
PRBS ON, SS OFF,
COAX MODE
PRBS ON, SS OFF,
COAX MODE
70
65
60
55
50
45
40
35
EQ ON
EQ ON
EQ OFF
EQ OFF
5
10 15 20 25 30 35 40 45 50
PCLKOUT FREQUENCY (MHz)
5
10
15
20
25
30
35
40
PCLKOUT FREQUENCY (MHz)
SUPPLY CURRENT
SUPPLY CURRENT
vs. PCLKOUT FREQUENCY (BWS = 0)
vs. PCLKOUT FREQUENCY (BWS = 1)
65
60
55
50
45
40
35
60
55
50
45
40
35
PRBS ON, EQ OFF,
COAX MODE
PRBS ON, EQ OFF,
COAX MODE
SS ON
SS ON
SS OFF
SS OFF
5
10 15 20 25 30 35 40 45 50
PCLKOUT FREQUENCY (MHz)
5
10
15
20
25
30
35
40
PCLKOUT FREQUENCY (MHz)
OUTPUT POWER SPECTRUM vs. PCLKOUT
FREQUENCY (VARIOUS SPREAD)
OUTPUT POWER SPECTRUM vs. PCLKOUT
FREQUENCY (VARIOUS SPREAD)
0
-10
-20
-30
-40
-60
-60
-70
-80
-90
0
-10
-20
-30
-40
-60
-60
-70
-80
-90
-100
f
= 20MHz
f
= 50MHz
PCLKOUT
PCLKOUT
0% SPREAD
0% SPREAD
1% SPREAD
4% SPREAD
2% SPREAD
4% SPREAD
2% SPREAD
18.5 19.0 19.5 20.0 20.5 21.0 21.5
PCLKOUT FREQUENCY (MHz)
47
48
49
50
51
52
53
PCLKOUT FREQUENCY (MHz)
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MAX9240A
6.25MHz to 100MHz, 25-Bit GMSL Deserializer for
Coax or STP Cable With Line Fault Detect
Typical Operating Characteristics (continued)
(V
= V
= V
= 1.8V, DBL = low, T = +25°C, unless otherwise noted.)
AVDD
DVDD
IOVDD A
SERIAL LINK SWITCHING PATTERN
WITH 6dB PREEMPHASIS (PARALELL
SERIAL LINK SWITCHING PATTERN
WITH 6dB PREEMPHASIS (PARALELL
BIT RATE = 50MHz, 10m STP CABLE)
BIT RATE = 50MHz, 20m COAX CABLE)
MAX9240A toc07
MAX9240A toc08
50mv/div
200ps/div
1.5Gbps
50mv/div
200ps/div
1.5Gbps
MAXIMUM PCLKOUT FREQUENCY
vs. STP CABLE LENGTH (BER ≤ 10-
MAXIMUM PCLKOUT FREQUENCY
vs. COAX CABLE LENGTH (BER ≤ 10-
10
10
)
)
60
40
20
0
60
40
20
0
OPTIMUM PE/EQ
SETTINGS
6dB PE, EQ OFF
NO PE, 10.7dB EQ
6dB PE, EQ OFF
NO PE, 10.7dB EQ
NO PE, EQ OFF
NO PE, EQ OFF
-12
BER CAN BE AS LOW AS 10 FOR
-12
BER CAN BE AS LOW AS 10 FOR
CABLE LENGTHS LESS THAN 10m
CABLE LENGTHS LESS THAN 10m
0
5
10
15
20
0
5
10
15
20
25
STP CABLE LENGTH (m)
COAX CABLE LENGTH (m)
MAXIMUM PCLKOUT FREQUENCY
vs. ADDITIONAL DIFFERENTIAL C (BER ≤ 10-
10
)
L
60
OPTIMUM PE/EQ
SETTINGS
10m STP CABLE
6dB PE, EQ OFF
50
40
30
20
10
0
NO PE, 10.7dB EQ
NO PE, EQ OFF
-12
BER CAN BE AS LOW AS 10 FOR
C < 4pF FOR OPTIMUM PE/EQ SETTINGS
L
0
2
4
6
8
10
ADDITIONAL DIFFERENTIAL LOAD CAPACITANCE (pF)
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MAX9240A
6.25MHz to 100MHz, 25-Bit GMSL Deserializer for
Coax or STP Cable With Line Fault Detect
Pin Configuration
TOP VIEW
35 34 33 32 31 30 29 28 27
36
26
25
DOUT20
DOUT7
DOUT6
DOUT5
24
23
22
37
38
39
DOUT21/HS0
DOUT22/VS0
21 DOUT23/HS1
20 IOVDD
DOUT4 40
IOVDD 41
DOUT3
DOUT2
42
43
19 DOUT24/VS1
MAX9240A
18
LFLT
17 LMN1
16 LMN0
15 LOCK
DOUT1 44
DOUT0 45
PCLKOUT
46
47
48
EP
+
ERR
MS/HVEN
AVDD
14
13
PWDN
2
3
4
5
6
7
8
9
10
1
11
12
TQFN
(7mm x 7mm X 0.75mm)
CONNECT EP TO GROUND PLANE
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MAX9240A
6.25MHz to 100MHz, 25-Bit GMSL Deserializer for
Coax or STP Cable With Line Fault Detect
Pin Description
PIN
NAME
FUNCTION
GPIO/Bus Width Select Input. Function is determined by the state of LCCEN (Table 13).
GPIO1 (LCCEN = high): Open-drain, general-purpose input/output with internal 60kΩ pullup to IOVDD.
BWS (LCCEN = low): Input with internal pulldown to EP. Set BWS = low for 22-bit input latch. Set
BWS = high for 30-bit input latch.
1
GPIO1/BWS
GPIO/Double-Mode Input. Function is determined by the state of LCCEN (Table 13).
GPIO0 (LCCEN = high): Open-drain, general-purpose input/output with internal 60kΩ pullup to IOVDD.
DBL (LCCEN = low): Input with internal pulldown to EP. Set DBL = high to use double-input mode. Set
DBL = low to use single-input mode.
2
GPIO0/DBL
3
CX/TP
Coax/Twisted-Pair Three-Level Configuration Input (Table 8)
I2C Select. Control-channel interface protocol select input with internal pulldown to EP.
Set I2CSEL = high to select I2C slave interface. Set I2CSEL = low to select UART interface.
4
I2CSEL
Local Control-Channel Enable Input with Internal Pulldown to EP. LCCEN = high enables the control-
channel interface pins. LCCEN = low disables the control-channel interface pins and selects an
alternate function on the indicated pins (Table 13).
5
LCCEN
1.8V Analog Power Supply. Bypass AVDD to EP with 0.1µF and 0.001µF capacitors as close as
possible to the device with the smaller capacitor closest to AVDD.
6, 48
AVDD
7
8
9
IN+
IN-
Noninverting Coax/Twisted-Pair Serial Input
Inverting Coax/Twisted-Pair Serial Input
GPI
General-Purpose Input. The GMSL serializer GPO (or INT) input follows GPI.
Receive/Serial Data/Error Detection Correction. Function is determined by the state of LCCEN (Table 13).
RX/SDA (LCCEN = high): Input/output with internal 30kI pullup to IOVDD. In UART mode, RX/SDA
is the Rx input of the MAX9240’s UART. In the I2C mode, RX/SDA is the SDA input/output of the
MAX9240’s I2C master/slave. RX/SDA has an open-drain driver and requires a pullup resistor.
EDC (LCCEN = low): Input with internal pulldown to EP. Set EDC = high to enable error detection
correction. Set EDC = low to disable error detection correction.
10
RX/SDA/EDC
Transmit/Serial Clock/Edge Select. Function is determined by the state of LCCEN (Table 13).
TX/SCL (LCCEN = high). Input/output with internal 30kI pullup to IOVDD. In UART mode, TX/SCL
is the Tx output of the MAX9240’s UART. In the I2C mode, TX/SCL is the SCL input/output of the
MAX9240’s I2C master/slave. TX/SCL has an open-drain driver and requires a pullup resistor.
ES (LCCEN = low): Input with internal pulldown to EP. When ES is high, PCLKOUT indicates valid
data on the falling edge of PCLKOUT. When ES is low, PCLKOUT indicates valid data on the rising
edge of PCLKOUT. Do not change the ES input while the pixel clock is running.
11
TX/SCL/ES
1.8V Digital Power Supply. Bypass DVDD to EP with 0.1µF and 0.001µF capacitors as close as possible
to the device with the smaller value capacitor closest to DVDD.
12
13
14
DVDD
PWDN
ERR
Active-Low Power-Down Input with Internal Pulldown to EP. Set PWDN low to enter power-down mode
to reduce power consumption.
Error Output. Open-drain data error detection and/or correction indication output with internal 60kΩ
pullup to IOVDD. ERR is output high when PWDN = low.
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MAX9240A
6.25MHz to 100MHz, 25-Bit GMSL Deserializer for
Coax or STP Cable With Line Fault Detect
Pin Description (continued)
PIN
NAME
FUNCTION
Open-Drain Lock Output with Internal 60kΩ Pullup to IOVDD. LOCK = high indicates that PLLs are
locked with correct serial-word-boundary alignment. LOCK = low indicates that PLLs are not locked or
an incorrect serial-word-boundary alignment. LOCK remains low when the configuration link is active or
during PRBS test. LOCK is output high when PWDN = low.
15
LOCK
16
17
LMN0
Line Fault Monitor Input 0 (see Figure 2A)
LMN1
Line Fault Monitor Input 1 (see Figure 2A)
Active-Low Open-Drain Line Fault Output. LFLT has a 60kΩ internal pullup to IOVDD. LFLT = low
indicates a line fault. LFLT is output high when PWDN = low.
18
LFLT
Parallel Data/Vertical Sync 1 Output. Defaults to parallel data output on power-up.
Parallel data output when VS/HS encoding is disabled.
19
DOUT24/VS1
Decoded vertical sync for upper half of single-output when VS/HS encoding is enabled (Table 2).
I/O Supply Voltage. 1.8V to 3.3V logic I/O power supply. Bypass IOVDD to EP with 0.1µF and 0.001µF
capacitors as close as possible to the device with the smallest value capacitor closest to IOVDD.
20, 41
21
IOVDD
Parallel Data/Horizontal Sync 1 Output. Defaults to parallel data output on power-up.
Parallel data output when VS/HS encoding is disabled.
DOUT23/HS1
Decoded horizontal sync for upper half of single-output when VS/HS encoding is enabled (Table 2).
Parallel Data/Vertical Sync 0 Output. Defaults to parallel data output on power-up.
Parallel data output when VS/HS encoding is disabled.
Decoded vertical sync for lower half of single-output when VS/HS encoding is enabled (Table 2).
22
DOUT22/VS0
DOUT21/HS0
Parallel Data/Horizontal Sync 0 Output. Defaults to parallel data input on power-up.
Parallel data output when VS/HS encoding is disabled.
23
Decoded horizontal sync for lower half of single-output when VS/HS encoding is enabled (Table 2).
24–40,
42–45
DOUT20–
DOUT0
Parallel Data Outputs
46
PCLKOUT
Parallel Clock Output. Latches parallel data into the input of another device.
Mode Select/HS and VS Encoding Enable with Internal Pulldown to EP. Function is determined by the
state of LCCEN (Table 13).
47
MS/HVEN
MS (LCCEN = high). Set MS = low to select base mode. Set MS = high to select the bypass mode.
HVEN (LCCEN = low): Set HVEN = high to enable HS/VS encoding on DOUT_/HS_ and DOUT_/VS_.
Set HVEN = low to use DOUT_/HS_ and DOUT_/VS_ as parallel data outputs.
Exposed Pad. EP is internally connected to device ground. MUST connect EP to the PCB ground plane
through an array of vias for proper thermal and electrical performance.
—
EP
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MAX9240A
6.25MHz to 100MHz, 25-Bit GMSL Deserializer for
Coax or STP Cable With Line Fault Detect
Functional Diagram
PCLKOUT
LFLT
SSPLL
CLKDIV
CDRPLL
LMN0
LMN1
LINE
FAULT
DOUT[20:0]
IN+
IN-
SERIAL
TO
PARALLEL
DOUT21/HS0
DOUT22/ VS0
DOUT23/HS1
DOUT24/ VS1
CML Rx
AND EQ
FIFO
SCRAMBLE/
CRC/
HAMMING/
8b/10b
1x[24:0]
OR
2x[10:0]
OR
Tx
DECODE
2x[14:0]
REVERSE
CONTROL
CHANNEL
VS /HS
GPIO
GPIO0/DBL
GPIO1/BWS
GPI
FCC
MAX9240A
2
UART/I C
TX/SCL/ES
RX/SDA/EDC
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MAX9240A
6.25MHz to 100MHz, 25-Bit GMSL Deserializer for
Coax or STP Cable With Line Fault Detect
R /2
L
IN+
IN-
REVERSE
CONTROL-CHANNEL
TRANSMITTER
V
OD
V
CMR
R /2
L
IN+
IN-
IN-
V
CMR
IN+
V
ROH
0.9 x V
ROH
0.1 x V
ROH
(IN+) - (IN-)
0.1 x V
0.9 x V
ROL
t
R
ROL
V
ROL
t
F
Figure 1. Reverse Control-Channel Output Parameters
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MAX9240A
6.25MHz to 100MHz, 25-Bit GMSL Deserializer for
Coax or STP Cable With Line Fault Detect
R /2
L
IN+
IN-
V
ID(P)
R /2
L
_
V
IN+
+
_
C
C
IN
IN
+
_
V
IN-
V
V
| V - V
|
ID(P) = IN+ IN-
(V + V )/2
CMR = IN+
IN-
Figure 2. Test Circuit for Differential Input Measurement
1.8V
45.3kΩ*
4.99kΩ*
45.3kΩ*
4.99kΩ*
GMSL
DESERIALIZER
LMN0
LMN1
LMN0
GMSL
DESERIALIZER
OUTPUT
LOGIC
(IN+)
TWISTED PAIR
IN+
IN-
49.9kΩ*
49.9kΩ*
CONNECTORS
LFLT
REFERENCE
VOLTAGE
1.8V
GENERATOR
45.3kΩ*
4.99kΩ*
LMN1
LMN0
GMSL
DESERIALIZER
OUTPUT
LOGIC
(IN-)
COAX
IN+
IN-
49.9kΩ*
49.9Ω*
CONNECTORS
*±1%
TOLERANCE
Figure 2a. Line Fault
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MAX9240A
6.25MHz to 100MHz, 25-Bit GMSL Deserializer for
Coax or STP Cable With Line Fault Detect
PCLKOUT
DOUT_
NOTE: PCLKOUT PROGRAMMED FOR RISING LATCH EDGE.
Figure 3. Worst-Case Pattern Output
t
T
V
OH MIN
t
HIGH
PCLKOUT
V
OL MAX
t
LOW
Figure 4. Parallel Clock Output High and Low Times
START
CONDITION
(S)
BIT 7
MSB
(A7)
STOP
CONDITION
(P)
BIT 6
(A6)
BIT 0
(R/W)
ACKNOWLEDGE
(A)
PROTOCOL
t
t
t
HIGH
SU;STA
LOW
1/f
SCL
SCL
t
SP
t
BUF
t
t
f
r
SDA
t
t
t
t
t
SU;STO
HD;STA
t
HD;DAT
VD;DAT
VD;ACK
SU;DAT
2
Figure 5. I C Timing Parameters
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MAX9240A
6.25MHz to 100MHz, 25-Bit GMSL Deserializer for
Coax or STP Cable With Line Fault Detect
C
L
SINGLE-ENDED OUTPUT LOAD
0.8 x V
I0VDD
0.2 x V
I0VDD
t
t
R
F
Figure 6. Output Rise-and-Fall Times
SERIAL-WORD LENGTH
SERIAL WORD N
SERIAL WORD N+1
SERIAL WORD N+2
IN+/-
FIRST BIT
LAST BIT
DOUT_
PARALLEL WORD N-1
PARALLEL WORD N
PARALLEL WORD N-2
PCLKOUT
t
SD
NOTE: PCLKOUT PROGRAMMED FOR RISING LATCHING EDGE.
Figure 7. Deserializer Delay
V
IH_MIN
DESERIALIZER
GPI
V
IL_MAX
t
GPIO
t
GPIO
V
OH_MIN
SERIALIZER
GPO
V
OL_MAX
Figure 8. GPI-to-GPO Delay
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MAX9240A
6.25MHz to 100MHz, 25-Bit GMSL Deserializer for
Coax or STP Cable With Line Fault Detect
IN+/-
IN+ - IN-
V
PWDN
IH1
t
LOCK
t
PU
LOCK
V
OH
LOCK
V
OH
PWDN MUST BE HIGH
Figure 9. Lock Time
Figure 10. Power-Up Delay
Register Mapping
Detailed Description
Registers set the operating conditions of the deserializer
and are programmed using the control channel in base
mode. The deserializer holds its device address and the
device address of the serializer it is paired with. Similarly,
the serializer holds its device address and the address of
the deserializer. Whenever a device address is changed,
the new address should be written to both devices. The
default device address of the deserializer is set by the
CX/TP input and the default device address of any GMSL
serializer is 0x80 (see Table 1 and Table 8). Registers
0x00 and 0x01 in both devices hold the device addresses.
The MAX9240A deserializer, when paired with the
MAX9271 or MAX9273 serializer, provides the full set
of operating features, but offers basic functionality when
paired with any GMSL serializer.
The deserializer has a maximum serial-bit rate of 1.5Gbps
for 15m or more of cable and operates up to a maximum
output clock of 50MHz in 25-bit, single-output mode, or
75MHz to 100MHz in 15-bit/11-bit, double-output mode,
respectively. This bit rate and output flexibility support
a wide range of displays, from QVGA (320 x 240) to
WVGA (800 x 480) and higher with 18-bit color, as well as
megapixel image sensors. Input equalization, combined
with GMSL serializer pre/deemphasis, extends the cable
length and enhances link reliability
Bit Map
The parallel output functioning and width depend on set-
tings of the double-/single-output mode (DBL), HS/VS
encoding (HVEN), error correction used (EDC), and bus
width (BWS) pins. Table 2 lists the bit map for the control
pin settings. Unused output bits are pulled low.
The control channel enables a µC to program the serial-
izer and deserializer registers and program registers on
peripherals. The control channel is also used to configure
and access the GPIO. The µC can be located at either
end of the link, or when using two µCs, at both ends. Two
modes of control-channel operation are available. Base
The parallel output has two output modes: single and
double output. In single-output mode, the deserialized
parallel data is clocked out every PCLKOUT cycle. The
device accepts pixel clocks from 6.25MHz to 50MHz
(Figures 11 and 12).
2
mode uses either I C or GMSL UART protocol, while
bypass mode uses a user-defined UART protocol. UART
2
protocol allows full-duplex communication, while I C
In double-output mode, the device splits deserialized
data into two half-sized words that are output at twice the
serial-word rate (Figures 13 and 14). The serializer/dese-
rializer use pixel clock rates from 33.3MHz to 100MHz
for 11-bit, double-output mode and 25MHz to 75MHz for
15-bit, double-output mode.
allows half-duplex communication.
Spread spectrum is available to reduce EMI on the paral-
lel output. The serial input complies with ISO 10605 and
IEC 61000-4-2 ESD protection standards.
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MAX9240A
6.25MHz to 100MHz, 25-Bit GMSL Deserializer for
Coax or STP Cable With Line Fault Detect
PCLKOUT
DOUT[24:0] OR
DOUT[21:0]
FIRST WORD
SECOND WORD
THIRD WORD
FOURTH WORD
VS0, VS1
HS0, HS1
VS (FROM FIRST WORD)
HS (FROM FIRST WORD)
VS (FROM SECOND WORD)
HS (FROM SECOND WORD)
VS (FROM THIRD WORD)
HS (FROM THIRD WORD)
VS (FROM FOURTH WORD)
HS (FROM FOURTH WORD)
NOTE: DIAGRAM SHOWS POSSIBLE LOCATIONS FOR TRANSITIONS ON VS_/HS_. VS_/HS_ HAVE MINIMUM LENGTH REQUIREMENTS.
NOTE: HS_, VS_ ACTIVE ONLY WHEN HVEN = 1.
Figure 11. Single-Output Waveform (Serializer Using Single Input)
PCLKOUT
DOUT[14:0] OR
FIRST WORD (FROM LATCH A)
FIRST WORD (FROM LATCH B)
FIRST WORD (FROM LATCH A)
FIRST WORD (FROM LATCH B)
SECOND WORD (FROM LATCH A)
SECOND WORD (FROM LATCH B)
SECOND WORD (FROM LATCH A)
SECOND WORD (FROM LATCH B)
THIRD WORD (FROM LATCH A)
THIRD WORD (FROM LATCH B)
THIRD WORD (FROM LATCH A)
THIRD WORD (FROM LATCH B)
FOURTH WORD (FROM LATCH A)
FOURTH WORD (FROM LATCH B)
FOURTH WORD (FROM LATCH A)
FOURTH WORD (FROM LATCH B)
DOUT[10:0]
DOUT[24:15] OR
DOUT[21:11]
VS0, HS0
VS1, HS1
NOTE: DIAGRAM SHOWS POSSIBLE LOCATIONS FOR TRANSITIONS ON VS_ /HS_. VS_ /HS_ HAVE MINIMUM LENGTH REQUIREMENTS.
NOTE: HS_, VS_ ACTIVE ONLY WHEN HVEN = 1.
Figure 12. Single-Output Waveform (Serializer Using Double Input)
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MAX9240A
6.25MHz to 100MHz, 25-Bit GMSL Deserializer for
Coax or STP Cable With Line Fault Detect
PCLKOUT
DOUT[14:0] OR
DOUT[10:0]
DOUTA FIRST WORD
DOUTB FIRST WORD
DOUTA SECOND WORD
DOUTB SECOND WORD
VS0, HS0
(SERIALIZER
DBL = 0)
FIRST WORD
SECOND WORD
NOTE: DIAGRAM SHOWS POSSIBLE LOCATIONS FOR TRANSITIONS ON VS0/HS0. VS0/HS0 HAVE MINIMUM LENGTH REQUIREMENTS.
NOTE: HS0, VS0 ACTIVE ONLY WHEN HVEN = 1.
Figure 13. Double-Output Waveform (Serializer Using Single Input)
PCLKOUT
DOUT[14:0] OR
DOUTA FIRST WORD
DOUTA FIRST WORD
DOUTB FIRST WORD
DOUTB FIRST WORD
DOUTA SECOND WORD
DOUTA SECOND WORD
DOUTB SECOND WORD
DOUTB SECOND WORD
DOUT[10:0]
VS0, HS0
(SERIALIZER
DBL = 1)
NOTE: DIAGRAM SHOWS POSSIBLE LOCATIONS FOR TRANSITIONS ON VS0/HS0. VS0/HS0 HAVE MINIMUM LENGTH REQUIREMENTS.
NOTE: HS0, VS0 ACTIVE ONLY WHEN HVEN = 1.
Figure 14. Double-Output Waveform (Serializer Using Double Input)
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MAX9240A
6.25MHz to 100MHz, 25-Bit GMSL Deserializer for
Coax or STP Cable With Line Fault Detect
Table 1. Power-Up Default Register Map (see Table 16)
REGISTER POWER-UP
POWER-UP DEFAULT SETTINGS
(MSB FIRST)
ADDRESS
DEFAULT
(hex)
(hex)
SERID = 1000000, serializer device address
RESERVED = 0
0x00
0x01
0x80
DESID = 1001000 (CX/TP = high or low), DESID = 1001001 (CX/TP = midlevel), deserializer device
0x90 or 0x92 address is determined by the state of the CX/TP input at power-up
CFGBLOCK = 0, registers 0x00 to 0x1F are read/write
SS = 00, spread spectrum disabled
RESERVED = 01
PRNG = 11, automatically detect the pixel clock range
SRNG = 11, automatically detect serial-data rate
0x02
0x03
0x1F
AUTOFM = 00, calibrate spread-modulation rate only once after locking
RESERVED = 0
SDIV = 00000, autocalibrate sawtooth divider
0x00
0x07
LOCKED = 0, LOCK output is low (read only)
OUTENB = 0, output enabled
PRBSEN = 0, PRBS test disabled
SLEEP = 0, sleep mode deactivated (see the Link Startup Procedure section)
INTTYPE = 01, base mode uses UART
0x04
REVCCEN = 1, reverse control channel active (sending)
FWDCCEN = 1, forward control channel active (receiving)
I2CMETHOD = 0, I2C master sends the register address
DCS = 0, normal parallel output driver current
HVTRMODE = 1, full periodic HS/VS tracking
ENEQ = 0, equalizer disabled
0x05
0x06
0x24
EQTUNE = 1001, 10.7dB equalization
0x02 or 0x22 RESERVED = 00X00010
DBL = 0 or 1, single-/double-input mode setting determined by the state of LCCEN and
GPIO0/DBL at startup
DRS = 0, high data-rate mode
BWS = 0 or 1, bit width setting determined by the state of LCCEN and GPIO1/BWS at startup
ES = 0 or 1, edge-select input setting determined by the state of LCCEN and TX/SCL/ES at startup
HVTRACK = 0 or 1, HS/VS tracking setting determined by the state of LCCEN and MS/HVEN at
startup
0x07
0xXX
HVEN = 0 or 1, HS/VS tracking encoding setting determined by the state of LCCEN and MS/HVEN
at startup
EDC = 00 or 10, error-detection/correction setting determined by the state of LCCEN and
RX/SDA/EDC at startup
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MAX9240A
6.25MHz to 100MHz, 25-Bit GMSL Deserializer for
Coax or STP Cable With Line Fault Detect
Table 1. Power-Up Default Register Map (see Table 16) (continued)
REGISTER POWER-UP
POWER-UP DEFAULT SETTINGS
ADDRESS
DEFAULT
(hex)
(MSB FIRST)
(hex)
INVVS = 0, deserializer does not invert VSYNC
INVHS = 0, deserializer does not invert HSYNC
RESERVED = 0
0x08
0x00
UNEQDBL = 0, serializer DBL is not the same as deserializer
DISSTAG = 0, outputs are staggered
AUTORST = 0, error registers/output autoreset disabled
ERRSEL = 00, detected errors trigger ERR
I2CSCRA = 0000000, I2C address translator source A is 0x00
RESERVED = 0
0x09
0x0A
0x0B
0x0C
0x00
0x00
0x00
0x00
I2CDSTA = 0000000, I2C address translator destination A is 0x00
RESERVED = 0
I2CSCRB = 0000000, I2C address translator source B is 0x00
RESERVED = 0
I2CDSTB = 0000000, I2C address translator destination B is 0x00
RESERVED = 0
I2CLOCACK = 1, acknowledge not generated when forward channel is not available
I2CSLVSH = 01, 469ns/234ns I2C setup/hold time
I2CMSTBT = 101, 339kbps (typ) I2C-to-I2C master bit-rate setting
I2CSLVTO = 10, 1024µs (typ) I2C-to-I2C slave remote timeout
0x0D
0x0E
0xB6
RESERVED = 01
GPIEN = 1, enable GPI-to-GPO signal transmission to serializer
GPIIN = 0, GPI input is low (read only)
GPIO1OUT = 1, set GPIO1 to high
GPIO1IN = 0, GPIO1 input is low (read only)
GPIO0OUT = 1, set GPIO0 to high
0x6A
0x00
GPIO0IN = 0, GPIO0 input is low (read only)
0x0F
0x10
DETTHR = 00000000, error threshold set to zero for detected errors
0x00
(read only)
DETERR = 00000000, zero errors detected
0x11
0x12
0x00
0x00
(read only)
0x00
CORRTHR = 00000000, error threshold set to zero for corrected errors
CORRERR = 00000000, zero errors corrected
0x13
PRBSERR = 00000000, zero PRBS errors detected
(read only)
PRBSOK = 0, PRBS test not completed
RESERVED = 000
LFNEG = 10, no faults detected
LFPOS = 10, no faults detected
0x0A
(read only)
0x14
0x15
0x16
0x17
0x18
0x19
0x2X
0x30
0x54
0x30
0xC8
RESERVED = 00100XXX
RESERVED = 00110000
RESERVED = 01010100
RESERVED = 00110000
RESERVED = 11001000
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MAX9240A
6.25MHz to 100MHz, 25-Bit GMSL Deserializer for
Coax or STP Cable With Line Fault Detect
Table 1. Power-Up Default Register Map (see Table 16) (continued)
REGISTER POWER-UP
POWER-UP DEFAULT SETTINGS
ADDRESS
DEFAULT
(hex)
(MSB FIRST)
(hex)
0xXX
(read only)
0x1A
0x1B
0x1C
RESERVED = XXXXXXXX
RESERVED = XXXXXXXX
RESERVED = XXXXXXXX
0xXX
(read only)
0xXX
(read only)
CXTP = 0, twisted-pair input
CXSEL = 0, noninverting input
I2CSEL = 0, UART input
LCCEN = 0, local control channel disabled
RESERVED = XXXX
0x0X
(read only)
0x1D
0x0A
(read only)
0x1E
0x1F
ID = 00001100, device ID is 0x0C
RESERVED = 000
CAPS = 0, not HDCP capable
REVISION = XXXX
0x0X
(read only)
X = Indeterminate.
Table 2. Output Map
OUTPUT* (PAIRED WITH
OUTPUT* (PAIRED WITH
PCLK RANGE**
EDC
BWS
DBL
HVEN
MAX9271)
MAX9273)
(MHz)
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
DOUT0:15
DOUT0:13, HS, VS
DOUT0:10
DOUT0:21
DOUT0:20, HS, VS
DOUT0:10
16.66 to 50
16.66 to 50
33.33 to 100
33.33 to 100
12.5 to 37.5
12.5 to 37.5
25 to 75
DOUT0:10, HS, VS
DOUT0:15
DOUT0:10, HS, VS
DOUT0:21
DOUT0:13, HS, VS
DOUT0:14
DOUT0:20, HS, VS
DOUT0:14
DOUT0:13, HS, VS
DOUT0:15
DOUT0:14, HS, VS
DOUT0:15
25 to 75
16.66 to 50
16.66 to 50
33.33 to 100
33.33 to 100
12.5 to 37.5
12.5 to 37.5
25 to 75
DOUT0:13, HS, VS
DOUT0:7
DOUT0:15, HS, VS
DOUT0:7
DOUT0:7, HS, VS
DOUT0:15
DOUT0:7, HS, VS
DOUT0:21
DOUT0:13, HS, VS
DOUT0:14
DOUT0:20, HS, VS
DOUT0:14
DOUT0:13, HS, VS
DOUT0:14, HS, VS
25 to 75
*The number of available outputs depends on the serializer attached to the MAX9240A.
**Device is in high-speed mode (DRS = LOW). See Table 3 for PCLK ranges in low-speed mode (DRS = high).
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MAX9240A
6.25MHz to 100MHz, 25-Bit GMSL Deserializer for
Coax or STP Cable With Line Fault Detect
the opposite direction of the video stream. The reverse
control channel and forward video data coexist on the
Serial Link Signaling and Data Format
The serializer uses differential CMLsignaling to drive twist-
ed-pair cable and single-ended CML to drive coax cable
with programmable pre/deemphasis and AC-coupling.
The deserializer uses AC-coupling and programmable
channel equalization.
same serial cable, forming a bidirectional link. The
reverse control channel operates independently from the
forward control channel. The reverse control channel is
available 2ms after power-up. The serializer temporarily
disables the reverse control channel for 350Fs after start-
ing/stopping the forward serial link.
Input data is scrambled and then 8b/10b coded. The
deserializer recovers the embedded serial clock, then
samples, decodes, and descrambles the data. In 24-bit
or 32-bit mode, 22 or 30 bits contain the video data
and/or error-correction bits, if used. The 23rd or 31st bit
carries the forward control-channel data. The last bit is the
parity bit of the previous 23 or 31 bits (Table 15).
Data-Rate Selection
The serializer/deserializer use DRS, DBL, and BWS to set
the PCLKOUT frequency range (Table 3). Set DRS = 1
for a PCLKOUT frequency range of 6.25MHz to 12.5MHz
(32-bit, single-output mode) or 8.33MHz to 16.66MHz (24-
bit, single-output mode). Set DRS = 0 for normal opera-
tion. It is not recommended to use double-output mode
when DRS = 1.
Reverse Control Channel
The serializer uses the reverse control channel to receive
2
I C/UART and GPO signals from the deserializer in
Table 3. Data-Rate Selection Table
DRS SETTING
DBL SETTING
BWS SETTING
PCLKOUT RANGE (MHz)
16.66 to 50
0
0
0
0
1
1
1
1
0 (single input)
0 (24-bit mode)
0
1 (32-bit mode)
12.5 to 35
1 (double input)
0
1
0
1
0
1
33.3 to 100
1
0
0
1
1
25 to 75
8.33 to 16.66
6.25 to 12.5
Do Not Use
Do Not Use
24 BITS
32 BITS
D0
D1
D21
FCC
PCB
D0
D1
D29
FCC
PCB
FORWARD
CONTROL-
CHANNEL BIT
FORWARD
CONTROL-
CHANNEL BIT
VIDEO AND ERROR
CORRECTION DATA
VIDEO AND ERROR
CORRECTION DATA
PACKET
PARITY
PACKET
PARITY
CHECK BIT
CHECK BIT
NOTE: SERIAL DATA SHOWN BEFORE SCRAMBLING AND 8b/10b ENCODING
Figure 15. Serial-Data Format
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MAX9240A
6.25MHz to 100MHz, 25-Bit GMSL Deserializer for
Coax or STP Cable With Line Fault Detect
The deserializer uses differential line coding to send
signals over the reverse channel to the serializer. The bit
rate of the control channel is 9.6kbps to 1Mbps in both
directions. The serializer/deserializer automatically detect
the control-channel bit rate in base mode. Packet bit-rate
changes can be made in steps of up to 3.5 times higher
or lower than the previous bit rate. See the Changing the
Clock Frequency section for more information.
Control Channel and
Register Programming
The control channel is available for the µC to send and
receive control data over the serial link simultaneously
with the high-speed data. The µC controls the link from
either the serializer or the deserializer side to support
video-display or image-sensing applications. The control
channel between the µC and serializer or deserializer
runs in base mode or bypass mode, according to the
mode selection (MS/HVEN) input of the device connected
to the µC. Base mode is a half-duplex control channel and
bypass mode is a full-duplex control channel.
Figure 16 shows the UART protocol for writing and read-
ing in base mode between the µC and the serializer/
deserializer.
Figure17showstheUARTdataformat. Evenparityisused.
Figure 18 and Figure 19 detail the formats of the SYNC
byte (0x79) and theACK byte (0xC3). The µC and the con-
nected slave chip generate the SYNC byte and ACK byte,
respectively. Events such as device wake-up and GPI
generate transitions on the control channel that can be
ignored by the µC. Data written to the serializer/deserial-
izer registers do not take effect until after the ACK byte is
sent. This allows the µC to verify that write commands are
received without error, even if the result of the write com-
mand directly affects the serial link. The slave uses the
SYNC byte to synchronize with the host UART’s data rate.
If the GPI or MS/HVEN inputs of the deserializer toggle
while there is control-channel communication, or if a line
fault occurs, the control-channel communication is cor-
rupted. In the event of a missed or delayed acknowledge
(~1ms due to control-channel timeout), the µC should
assume there was an error in the packet transmission or
response. In base mode, the µC must keep the UART Tx/
Rx lines high no more than 4 bit times between bytes in a
packet. Keep the UART Tx/Rx lines high for at least 16 bit
times before starting to send a new packet.
UART Interface
In base mode, the µC is the host and can access the
registers of both the serializer and deserializer from
either side of the link using the GMSL UART protocol.
The µC can also program the peripherals on the remote
side by sending the UART packets to the serializer or
2
deserializer, with the UART packets converted to I C
by the device on the remote side of the link. The µC
communicates with a UART peripheral in base mode
(through INTTYPE register settings), using the half-
duplex default GMSL UART protocol of the serializer/
deserializer. The device addresses of the serializer/
deserializer in base mode are programmable. The default
value is 0x80 for the serializer and is determined by the
CX/TP input for the deserializer (Table 8).
2
When the peripheral interface is I C, the serializer/
deserializer convert UART packets to I C that have
device addresses different from those of the serializer or
deserializer. The converted I C bit rate is the same as the
2
2
original UART bit rate.
WRITE DATA FORMAT
DEV ADDR + R/W REG ADDR NUMBER OF BYTES BYTE 1
SYNC
BYTE N
ACK
MASTER READS FROM SLAVE
MASTER WRITES TO SLAVE
READ DATA FORMAT
SYNC
DEV ADDR + R/W REG ADDR NUMBER OF BYTES
MASTER WRITES TO SLAVE
ACK
BYTE 1
BYTE N
MASTER READS FROM SLAVE
Figure 16. GMSL UART Protocol for Base Mode
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MAX9240A
6.25MHz to 100MHz, 25-Bit GMSL Deserializer for
Coax or STP Cable With Line Fault Detect
1 UART FRAME
START
D0
D1
D2
D3
D4
D5
D6
D7
PARITY
STOP
FRAME 1
FRAME 2
FRAME 3
STOP
START
STOP
START
*BASE MODE USES EVEN PARITY
Figure 17. GMSL UART Data Format for Base Mode
D0
1
D1
0
D2
0
D3
1
D4
1
D5
1
D6
1
D7
0
D0
1
D1
1
D2
0
D3
0
D4
0
D5
0
D6
1
D7
1
START
PARITYSTOP
START
PARITY STOP
Figure 18. SYNC Byte (0x79)
Figure 19. ACK Byte (0xC3)
As shown in Figure 20, the remote-side device converts
connected to the deserializer, there is a 1ms wait time
between setting MS/HVEN high and the bypass con-
trol channel being active. There is no delay time when
switching to bypass mode when the µC is connected to
the serializer. Do not send a logic-low value longer than
100µs to ensure proper GPO functionality. Bypass mode
accepts bit rates down to 10kbps in either direction. See
the GPO/GPI Control section for GPI functionality limita-
tions. The control-channel data pattern should not be held
low longer than 100µs if GPI control is used.
packets going to or coming from the peripherals from
2
UART format to I C format and vice versa. The remote
device removes the byte number count and adds or
2
2
receives the ACK between the data bytes of I C. The I C
bit rate is the same as the UART bit rate.
Interfacing Command-Byte-Only
2
I C Devices with UART
2
The serializer/deserializer UART-to-I C conversion
can interface with devices that do not require register
2
addresses, such as the MAX7324 GPIO expander. In
I C Interface
2
this mode, the I C master ignores the register address
2
2
In I C-to-I C mode, the deserializer’s control-channel
byte and directly reads/writes the subsequent data bytes
2
interface sends and receives data through an I C-
(Figure 21). Change the communication method of the
compatible 2-wire interface. The interface uses a serial-
data line (SDA) and a serial-clock line (SCL) to achieve
bidirectional communication between master and slave(s).
A µC master initiates all data transfers to and from the
device and generates the SCL clock that synchronizes
2
I C master using the I2CMETHOD bit. I2CMETHOD = 1
sets command-byte-only mode, while I2CMETHOD = 0
sets normal mode where the first byte in the data stream
is the register address.
2
the data transfer. When an I C transaction starts on the
UART Bypass Mode
local-side device’s control-channel port, the remote-side
In bypass mode, the serializer/deserializer ignore UART
commands from the µC and the µC communicates with
the peripherals directly using its own defined UART pro-
tocol. The µC cannot access the serializer/deserializer
registers in this mode. Peripherals accessed through the
forward control channel using the UART interface need
to handle at least one PCLKOUT period ± 10ns of jitter
due to the asynchronous sampling of the UART signal
by PCLKOUT. Set MS/HVEN = high to put the control
channel into bypass mode. For applications with the µC
2
device’s control-channel port becomes an I C master
2
2
that interfaces with remote-side I C perhipherals. The I C
master must accept clock stretching, which is imposed by
the deserializer (holding SCL low). The SDA and SCL lines
operate as both an input and an open-drain output. Pullup
resistors are required on SDA and SCL. Each transmis-
sion consists of a START condition (Figure 5) sent by a
master, followed by the device’s 7-bit slave address plus a
R/W bit, a register address byte, one or more data bytes,
and finally a STOP condition.
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MAX9240A
6.25MHz to 100MHz, 25-Bit GMSL Deserializer for
Coax or STP Cable With Line Fault Detect
2
UART-TO-I C CONVERSION OF WRITE PACKET (I2CMETHOD = 0)
SERIALIZER/DESERIALIZER
11
µC
11
11
11
11
11
11
SYNC FRAME
DEVICE ID + WR
REGISTER ADDRESS NUMBER OF BYTES
DATA 0
DATA N
ACK FRAME
SERIALIZER/DESERIALIZER
PERIPHERAL
1
7
1
1
8
1
8
1
8
1
1
S
DEV ID W A REG ADDR
A
DATA 0
A
DATA N
A
P
2
UART-TO-I C CONVERSION OF READ PACKET (I2CMETHOD = 0)
SERIALIZER/DESERIALIZER
11
µC
11
11
11
11
ACK FRAME
11
DATA 0
11
DATA N
SYNC FRAME
DEVICE ID + RD
REGISTER ADDRESS NUMBER OF BYTES
SERIALIZER/DESERIALIZER
PERIPHERAL
1
7
1
1
8
1
1
7
1
1
8
1
8
1
1
S
DEV ID W A REG ADDR
A
S
DEV ID
R
A
DATA 0
A
DATA N
A
P
S: START
P: STOP
A: ACKNOWLEDGE
: MASTER TO SLAVE
: SLAVE TO MASTER
2
2
Figure 20. Format Conversion Between GMSL UART and I C with Register Address (I CMETHOD = 0)
2
UART-TO-I C CONVERSION OF WRITE PACKET (I2CMETHOD = 1)
µC
SERIALIZER/DESERIALIZER
11
SYNC FRAME
11
11
11
11
DATA 0
11
DATA N
11
ACK FRAME
DEVICE ID + WR
REGISTER ADDRESS NUMBER OF BYTES
SERIALIZER/DESERIALIZER
PERIPHERAL
1
7
1
1
8
1
8
1
1
S
DEV ID
W
A
DATA 0
A
DATA N
A
P
2
UART-TO-I C CONVERSION OF READ PACKET (I2CMETHOD = 1)
µC
SERIALIZER/DESERIALIZER
11
11
11
11
11
11
DATA 0
11
DATA N
SYNC FRAME
DEVICE ID + RD
REGISTER ADDRESS NUMBER OF BYTES
ACK FRAME
SERIALIZER/DESERIALIZER
PERIPHERAL
1
7
1
1
8
1
8
1
1
S
DEV ID
R
A
DATA 0
A
DATA N
A
P
: MASTER TO SLAVE
: SLAVE TO MASTER S: START
P: STOP A: ACKNOWLEDGE
2
2
Figure 21. Format Conversion Between GMSL UART and I C with Register Address (I CMETHOD = 1)
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MAX9240A
6.25MHz to 100MHz, 25-Bit GMSL Deserializer for
Coax or STP Cable With Line Fault Detect
START and STOP Conditions
Acknowledge
Both SCL and SDA remain high when the interface is not
busy. A master signals the beginning of a transmission
with a START (S) condition by transitioning SDA from high
to low while SCL is high (Figure 22). When the master has
finished communicating with the slave, it issues a STOP
(P) condition by transitioning SDA from low to high while
SCL is high. The bus is then free for another transmission.
The acknowledge bit is a clocked 9th bit that the recipi-
ent uses to handshake receipt of each byte of data
(Figure 24). Thus, each byte transferred effectively requires
9 bits. The master generates the 9th clock pulse, and the
recipient pulls down SDA during the acknowledge clock
pulse. The SDA line is stable low during the high period
of the clock pulse. When the master is transmitting to the
slave device, the slave device generates the acknowl-
edge bit because the slave device is the recipient. When
the slave device is transmitting to the master, the master
generates the acknowledge bit because the master is the
recipient. The device generates an acknowledge even
when the forward control channel is not active (not locked).
To prevent acknowledge generation when the forward
control channel is not active, set the I2CLOCACK bit low.
Bit Transfer
One data bit is transferred during each clock pulse
(Figure 23). The data on SDA must remain stable while
SCL is high.
SDA
SCL
P
S
STOP
CONDITION
START
CONDITION
Figure 22. START and STOP Conditions
SDA
SCL
DATA LINE STABLE;
DATA VALID
CHANGE OF DATA
ALLOWED
Figure 23. Bit Transfer
START
CONDITION
CLOCK PULSE FOR
ACKNOWLEDGE
1
2
8
9
SCL
SDA
BY
TRANSMITTER
SDA
BY
RECEIVER
S
Figure 24. Acknowledge
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MAX9240A
6.25MHz to 100MHz, 25-Bit GMSL Deserializer for
Coax or STP Cable With Line Fault Detect
beyond storing the register address (Figure 26). Any
Slave Address
bytes received after the register address are data bytes.
The first data byte goes into the register selected by the
register address, and subsequent data bytes go into
subsequent registers (Figure 27). If multiple data bytes
are transmitted before a STOP condition, these bytes
are stored in subsequent registers because the register
addresses autoincrement.
The serializer/deserializer have a 7-bit-long slave address.
The bit following a 7-bit slave address is the R/W bit, which
is low for a write command and high for a read command.
The slave address is 100100X1 for read commands and
100100X0 for write commands. See Figure 25.
Bus Reset
2
The device resets the bus with the I C START condition
Format for Reading
for reads. When the R/W bit is set to 1, the serializer/
deserializer transmit data to the master, thus the master
is reading from the device.
The serializer/deserializer are read using the internally
stored register address as an address pointer, the same
way the stored register address is used as an address
pointer for a write. The pointer autoincrements after each
data byte is read using the same rules as for a write. Thus,
a read is initiated by first configuring the register address
by performing a write (Figure 28). The master can now
read consecutive bytes from the device, with the first
data byte being read from the register address pointed by
the previously written register address. Once the master
sends a NACK, the device stops sending valid data.
Format for Writing
A write to the serializer/deserializer comprises the trans-
mission of the slave address with the R/W bit set to zero,
followed by at least one byte of information. The first
byte of information is the register address or command
byte. The register address determines which register of
the device is to be written by the next byte, if received.
If a STOP (P) condition is detected after the register
address is received, the device takes no further action
0
0
1
0
1/0
0
R/W
SDA
SCL
1
ACK
MSB
LSB
Figure 25. Slave Address
0 = WRITE
ADDRESS = 0x80
REGISTER ADDRESS = 0x00
REGISTER 0x00 WRITE DATA
S
1
0
0
0
0
0
0
0
A
0
0
0
0
0
0
0
0
A
D7 D6 D5 D4 D3 D2 D1 D0
A
P
S = START BIT
P = STOP BIT
A = ACK
D_ = DATA BIT
2
Figure 26. Format for I C Write
0 = WRITE
ADDRESS = 0x80
REGISTER ADDRESS = 0x0000
S
1
0
0
0
0
0
0
0
A
0
0
0
0
0
0
0
0
A
N
S = START BIT
P = STOP BIT
A = ACK
N = NACK
D_ = DATA BIT
REGISTER 0x00 WRITE DATA
REGISTER 0x02 WRITE DATA
D7 D6 D5 D4 D3 D2 D1 D0
A
D7 D6 D5 D4 D3 D2 D1 D0
P
Figure 27. Format for Write to Multiple Registers
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MAX9240A
6.25MHz to 100MHz, 25-Bit GMSL Deserializer for
Coax or STP Cable With Line Fault Detect
0 = WRITE
ADDRESS = 0x80
REGISTER ADDRESS = 0x00
S
1
0
0
0
0
0
0
0
0
A
A
0
0
0
0
0
0
0
0
A
N
1 = READ
ADDRESS = 0x81
REGISTER 0x00 READ DATA
REPEATED START
S
1
0
0
0
0
0
0
D7 D6 D5 D4 D3 D2 D1 D0
P
S = START BIT
P = STOP BIT
A = ACK
N = NACK
D_ = DATA BIT
2
Figure 28. Format for I C Read
2
Table 4. I C Bit-Rate Ranges
LOCAL BIT RATE
f > 50kbps
REMOTE BIT-RATE RANGE
Up to 1Mbps
I2CMSTBT SETTING
Any
Up to 110
000
20kbps < f < 50kbps
f < 20kbps
Up to 400kbps
Up to 10kbps
2
I C Communication with Remote-Side Devices
Control-Channel Broadcast Mode
2
The deserializer supports I C communication with a
The deserializer supports broadcast commands to con-
trol multiple peripheral devices. Select an unused device
address to use as a broadcast device address. Program
the remote-side GMSL device to translate the broadcast
device address (source address stored in registers 0x09,
0x0B) to the peripheral device address (destination
address stored in registers 0x0A, 0x0C). Any commands
sent to the broadcast address are sent to all designated
peripherals, while commands sent to a peripheral’s unique
device address are sent to that particular device only.
peripheral on the remote side of the communication link
using SCL clock stretching. While multiple masters can
reside on either side of the communication link, arbitra-
tion is not provided. The connected masters need to sup-
port SCL clock stretching. The remote-side I C bit-rate
range must be set according to the local-side I C bit rate.
Supported remote-side bit rates can be found in Table 4.
Set the I2CMSTBT (register 0x0D) to set the remote I C
bit rate. If using a bit rate different than 400kbps, local- and
remote-side I C setup and hold times should be adjusted
2
2
2
2
GPO/GPI Control
by setting the SLV_SH register settings on both sides.
GPO on the serializer follows GPI transitions on the
deserializer. This GPO/GPI function can be used to
transmit signals such as frame sync in a surround-view
camera system. The GPI-to-GPO delay is 0.35ms (max).
Keep the time between GPI transitions to a minimun
0.35ms. This includes transitions from the other dese-
rializer in coax-splitter mode. Bit D4 of register 0x0E in
the deserializer stores the GPI input state. GPO is low
after power-up. The FC can set GPO by writing to the
serializer SET_GPO register bit. Do not send a logic-low
value on the deserializer RX/SDA input (UART mode)
longer than 100µs in either base or bypass mode to
ensure proper GPO/GPI functionality.
2
I C Address Translation
2
The deserializer supports I C address translation for up to
two device addresses. Use address translation to assign
unique device addresses to peripherals with limited
2
I C addresses. Source addresses (address to translate
from) are stored in registers 0x09 and 0x0B. Destination
addresses (address to translate to) are stored in registers
0x0A and 0x0C.
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MAX9240A
6.25MHz to 100MHz, 25-Bit GMSL Deserializer for
Coax or STP Cable With Line Fault Detect
spectrum modulation frequency within 20kHz to 40kHz.
Additionally, manual configuration of the sawtooth divider
(SDIV: 0x03, D[5:0]) allows the user to set a modulation
frequency according to the PCLKOUT frequency. When
ranges are manually selected, program the SDIV value
for a fixed modulation frequency around 20kHz.
PRBS Test
The serializer includes a PRBS pattern generator that
works with bit-error verification in the deserializer. To run
the PRBS test, set PRBSEN = 1 (0x04, D5) in the deseri-
alizer and then in the serializer. To exit the PRBS test, set
PRBSEN = 0 (0x04, D5) in the serializer.
Manual Programming
Line Equalizer
of the Spread-Spectrum Divider
The deserializer includes an adjustable line equalizer to
further compensate cable attenuation at high frequencies.
The cable equalizer has 11 selectable levels of compen-
sation from 2.1dB to 13dB (Table 5). The device powers
up with the equalizer disabled. To select other equaliza-
tion levels, set the corresponding register bits in the dese-
rializer (0x05 D[3:0]). Use equalization in the deserializer,
together with preemphasis in the serializer, to create the
most reliable link for a given cable.
The modulation rate for the deserializer relates to the
PCLKOUT frequency as follows:
f
PCLKOUT
f
= 1+ DRS
(
)
M
MOD× SDIV
where:
= Modulation frequency
f
M
DRS = DRS value (0 or 1)
= PCLKOUT frequency
f
Spread Spectrum
PCLKOUT
To reduce the EMI generated by transitions, the dese-
rializer output is programmable for spread spectrum. If
the serializer driving the deserializer has programmable
spread spectrum, do not enable spread for both at the
same time or their interaction will cancel benefits. The
programmable spread-spectrum amplitudes are ±2% and
±4% (Table 6).
MOD = Modulation coefficient given in Table 7
SDIV = 5-bit SDIV setting, manually programmed by
the µC
To program the SDIV setting, first look up the modulation
coefficient according to the desired bus-width and spread-
spectrum settings. Solve the above equation for SDIV using
the desired pixel clock and modulation frequencies. If the
calculated SDIV value is larger than the maximum allowed
SDIV value in Table 7, set SDIV to the maximum value.
The deserializer includes
a sawtooth divider to
control the spread-modulation rate. Autodetection of
the PCLKOUT operation range guarantees a spread-
Table 5. Cable Equalizer Boost Levels
Table 6. Parallel Output Spread
SS
00
01
10
11
SPREAD (%)
No spread spectrum. Power-up default.
±2% spread spectrum.
BOOST SETTING
(0x05 D[3:0])
TYPICAL BOOST GAIN
(dB)
0000
0001
0010
0011
0100
0101
0110
0111
1000
2.1
2.8
3.4
4.2
5.2
6.2
7
No spread spectrum.
±4% spread spectrum.
Table 7. Modulation Coefficients and
Maximum SDIV Settings
8.2
9.4
SPREAD-
SPECTRUM
SETTING (%)
MODULATION
COEFFICIENT
(dec)
SDIV UPPER
LIMIT (dec)
10.7
Default*
1001
4
2
208
208
15
30
1010
1011
11.7
13
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MAX9240A
6.25MHz to 100MHz, 25-Bit GMSL Deserializer for
Coax or STP Cable With Line Fault Detect
Additional Error Detection and Correction
HS/VS Encoding and/or Tracking
In default mode (additional error detection and correc-
tion disabled), data encoding/decoding is the same as in
previous GMSL serializers/deserializers (parity only). At
the serializer, the parallel input word is scrambled and a
parity bit is added. The scrambled word is divided into 3 or
4 bytes (depending on the BWS setting), 8b/10b encoded,
and then transmitted serially. At the deserializer, the same
operations are performed in reverse order. The parity bit
is used by the deserializer to find the word boundary and
for error detection. Errors are counted in an error counter
register and an error pin indicates errors.
HS/VS encoding by a GMSL serializer allows horizontal
and vertical synchronization signals to be transmitted
while conserving pixel data bandwidth. With HS/VS
encoding enabled, 10-bit pixel data with a clock up to
100MHz can be transmitted using one video pixel of data
per HS/VS transition versus 8-bit data with a clock up to
100MHz without HS/VS encoding. The deserializer per-
forms HS/VS decoding, tracks the period of the HS/VS
signals, and uses voting to filter HS/VS bit errors. When
using HS/VS encoding, use a minimum HS/VS low-pulse
duration of two PCLKOUT cycles when DBL = 0 on the
deserializer. When DBL = 1, use a minimum HS/VS low-
pulse duration of five PCLKOUT cycles and a minimum
high-pulse duration of two PCLKOUT cycles. When using
hamming code with HS/VS encoding, do not send more
than two transitions every 16 PCLKOUT cycles.
The deserializer can use one of two additional error-detec-
tion/correction methods (selectable by register setting):
1) 6-bit cyclic redundancy check
2) 6-bit hamming code with 16-word interleaving
When the serializer uses double-input mode (DBL = 1),
the active duration, plus the blanking duration of HS or
VS signals, should be an even number of PCLKOUT
cycles. When DBL = 1 in the serializer and DBL = 0 in the
deserializer, two pixel clock cycles of HS/VS at the serial-
izer input are output at the HS0/VS0 and HS1/VS1 output
of the deserializer in one cycle. The first cycle of HS/VS
goes out of HS0/VS0 and the second cycle goes out of
HS1/VS1. HS1 and VS1 are not used when HVEN = 0.
Cyclic Redundancy Check (CRC)
When CRC is enabled, the serializer adds 6 bits of CRC
to the input data. This reduces the available bits in the
input data word by 6, compared to the non-CRC case
(see Table 2 for details). For example, 16 bits are avail-
able for input data instead of 22 bits when BWS = 0, and
24 bits instead of 30 bits when BWS = 1.
6
The CRC generator polynomial is x + x + 1 (as used in
the ITU-T G704 telecommunication standard).
If HS/VS tracking is used without HS/VS encoding, use
DOUT0 for HSYNC and DOUT1 for VSYNC. In this case,
if DBL values on the serializer/deserializer are different,
set the UNEQDBL register bit in the deserializer to 1.
If the serializer and deserializer have unequal DBL set-
tings and HVEN = 0, then HS/VS inversion should only
be used on the side that has DBL = 1. HS/VS encoding
sends packets when HSYNC or VSYNC is low; use HS/
VS inversion register bits if input HSYNC and VSYNC
signals use an active-low convention in order to send data
packets during the inactive pixel clock periods.
The parity bit is still added when CRC is enabled, because
it is used for word-boundary detection. When CRC is
enabled, each data word is scrambled and then the
6-bit CRC and 1-bit parity are added before the 8b/10b
encoding.
At the deserializer, the CRC code is recalculated. If the
recalculated CRC code does not match the received CRC
code, an error is flagged. This CRC error is reported to the
error counter.
Hamming Code
Serial Input
Hamming code is a simple and effective error-correction
code to detect and/or correct errors. The MAX9240A
deserializer (when used with the MAX9271/MAX9273
GMSL serializers) uses a single-error correction/double-
error detection per pixel hamming-code scheme.
The device can receive serial data from two kinds of
cables: 100Ω twisted pair and 50Ω coax (contact the
factory for devices compatible with 75Ω cables).
Coax-Mode Splitter
The deserializer uses data interleaving for burst error tol-
erance. Burst errors up to 11 consecutive bits on the serial
link are corrected and burst errors up to 31 consecutive
bits are detected.
In coax mode, OUT+ and OUT- of the serializer are active.
This enables use as a 1:2 splitter (Figure 29). In coax
mode, connect OUT+ to IN+ of the deserializer. Connect
OUT- to IN- of the second deserializer. Control-channel
data is broadcast from the serializer to both deserializers
and their attached peripherals. Assign a unique address
Hamming code adds overhead similar to CRC. See Table 2
for details regarding the available input word size.
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MAX9240A
6.25MHz to 100MHz, 25-Bit GMSL Deserializer for
Coax or STP Cable With Line Fault Detect
GMSL
SERIALIZER
MAX9240A
GMSL
SERIALIZER
MAX9240A
OUT+
IN+
IN-
OUT-
OUT+
OUT-
IN+
OPTIONAL
COMPONENTS
FOR INCREASED
POWER-SUPPLY
REJECTION
IN-
AVDD
MAX9240A
OPTIONAL COMPONENTS
FOR INCREASED POWER-SUPPLY
REJECTION
50Ω
IN+
IN-
Figure 29. 2:1 Coax-Mode Splitter Connection Diagram
Figure 30. Coax-Mode Connection Diagram
to send control data to one deserializer. Leave all unused
IN_ pins unconnected, or connect them to ground through
50Ω and a capacitor for increased power-supply rejection.
If OUT- is not used, connect OUT- to AVDD through a 50Ω
resistor (Figure 30). When there are µCs at the serializer,
and at each deserializer, only one µC can communicate at
a time. Disable one splitter control-channel link to prevent
contention. Use the DIS_REV_P or DIS_REV_N register
bits to disable a control-channel link.
Table 8. Configuration Input Map
CX/TP
High
Mid
FUNCTION
Coax+ input. Device address 0x90.
Coax- input. Device address 0x92.
Twisted-pair input. Device address 0x90.
Low
the activity on the serial link and then when it locks, it
automatically sets its SLEEP register bit to 0.
Cable Type Configuration Input (CX/TP)
Power-Down Mode
CX/TP determines the power-up state of the serial input.
In coax mode, CX/TP also determines which coax input
is active, along with the default device address (Table 8).
These functions can be changed after power-up by writing
to the appropriate register bits.
The deserializer has a power-down mode that further
reduces power consumption compared to sleep mode.
Set PWDN low to enter power-down mode. In power-
down mode, the outputs of the device remain in high
impedance. Entering power-down resets the device’s
registers. Upon exiting power-down, the state of external
pins GPIO1/BWS, GPIO0/DBL, CX/TP, I2CSEL, LCCEN,
RX/SDA/EDC, TX/SCL/ES, and MS/HVEN are latched.
Sleep Mode
The deserializer includes a sleep mode to reduce power
consumption. The device enters or exits sleep mode by a
command from a local µC or a remote µC using the con-
trol channel. Set the SLEEP bit to 1 to initiate sleep mode.
The serializer sleeps immediately after setting its SLEEP
= 1. The deserializer sleeps after serial link inactivity or
8ms (whichever arrives first) after setting its SLEEP = 1.
To wake up from the local side, send an arbitrary control-
channel command to the deserializer, wait 5ms for the
chip to power up, and then write 0 to the SLEEP register
bit to make the wake-up permanent. To wake up from the
remote side, enable serialization. To deserializer detects
Configuration Link
The control channel can operate in a low-speed mode
called configuration link in the absence of a clock input.
This allows a microprocessor to program configuration
registers before starting the video link. An internal oscil-
lator provides the clock for the configuration link. Set
CLINKEN = 1 on the serializer to enable the configuration
link. The configuration link is active until the video link is
enabled. The video link overrides the configuration link
and attempts to lock when SEREN = 1.
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MAX9240A
6.25MHz to 100MHz, 25-Bit GMSL Deserializer for
Coax or STP Cable With Line Fault Detect
sensing applications. The control channel is available after
the video link or the configuration link is established. If
the deserializer powers up after the serializer, the control
channel becomes unavailable until 2ms after power-up.
Link Startup Procedure
Table 9 lists the startup procedure for video-display appli-
cations. Table 10 lists the startup procedure for image-
Table 9. Startup Procedure for Video-Display Applications
NO.
—
1
µC
µC connected to serializer.
Powers up.
SERIALIZER
DESERIALIZER
Sets all configuration inputs. If any
configuration inputs are available on
one end of the link but not on the other,
always connects that configuration input
low.
Sets all configuration inputs. If any
configuration inputs are available on
one end of the link but not on the other,
always connects that configuration input
low.
Powers up and loads default settings.
Powers up and loads default settings.
Enables configuration link by
setting CLINKEN = 1 (if not
enabled automatically) and gets
an acknowledge. Waits for link to
be established (~3ms).
2
Establishes configuration link.
Locks to configuration link signal.
Writes one link configuration
bit (DRS, BWS, or EDC) in
the deserializer and gets an
acknowledge.
Configuration changed from default
settings (loss-of-lock can occur when
BWS or EDC changes).
3
4
5
6
7
—
Writes corresponding serializer
link configuration bit and gets an
acknowledge.
Configuration changed from default
settings.
Relocks to configuration link signal.
Waits for link to be established
(~3ms) and then repeats steps 3
and 4 until all serial link bits are
configured.
—
—
Writes remaining configuration bits
in the serializer/deserializer and
gets an acknowledge.
Configuration changed from default
settings.
Configuration changed from default
settings.
Enables video link by setting
SEREN = 1 and gets an
acknowledge. Waits for link to be
established (~3ms).
Locks to serial link signal and begins
deserializing data.
Begins serializing data.
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MAX9240A
6.25MHz to 100MHz, 25-Bit GMSL Deserializer for
Coax or STP Cable With Line Fault Detect
Table 10. Startup Procedure for Image-Sensing Applications
NO.
µC
SERIALIZER
DESERIALIZER
Sets all configuration inputs. If any
configuration inputs are available on
one end of the link but not on the other,
always connects that configuration input
low.
Sets all configuration inputs. If any
configuration inputs are available on one
end of the link but not on the other, always
connects that configuration input low.
—
µC connected to deserializer.
Powers up and loads default settings.
Establishes serial link.
Powers up and loads default settings.
Locks to serial link signal.
1
3
Powers up.
Writes deserializer configuration
bits and gets an acknowledge.
Configuration changed from default settings
(loss-of-lock can occur).
—
Writes serializer configuration
bits. Cannot get an acknowledge
(or gets a dummy acknowledge)
if loss-of-lock occurred.
Configuration changed from default
settings.
4
5
Relocks the serial link signal.
Enables video link by setting
SEREN = 1 (if not enabled
automatically). Cannot get an
acknowledge (or gets a dummy
acknowledge) if loss-of-lock
occurred. Waits for link to be
established (~3ms).
Locks to serial link signal and begins
deserializing data.
Begins serializing data.
SLEEP = 1, VIDEO LINK OR CONFIG
LINK NOT LOCKED AFTER 8ms
CONFIG LINK
CONFIG LINK
OPERATING
UNLOCKED
WAKE-UP
SIGNAL
SIGNAL
POWER-ON
IDLE
SERIAL PORT
LOCKING
SLEEP
DETECTED
PROGRAM
REGISTERS
CONFIG LINK
LOCKED
0
SLEEP
VIDEO LINK
LOCKED
VIDEO LINK
UNLOCKED
SERIAL LINK ACTIVITY STOPS OR 8ms ELAPSES AFTER
µC SETS SLEEP = 1
PWDN = HIGH,
POWER-ON
GPI CHANGES FROM
LOW TO HIGH OR
PRBSEN = 0
PRBSEN = 1
SEND GPI TO
POWER-DOWN
VIDEO LINK
OPERATING
VIDEO LINK
PRBS TEST
PWDN = LOW OR
HIGH TO LOW
ALL STATES
OR
POWER-OFF
POWER-OFF
GMSL
SERIALIZER
0
SLEEP
Figure 31. State Diagram, Remote Microcontroller Application
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MAX9240A
6.25MHz to 100MHz, 25-Bit GMSL Deserializer for
Coax or STP Cable With Line Fault Detect
In addition, the control channel does not provide arbitra-
tion between I C masters on both sides of the link. An
acknowledge frame is not generated when communica-
Applications Information
2
Error Checking
The deserializer checks the serial link for errors and
stores the number of detected and corrected errors in
the 8-bit registers, DETERR (0x10) and CORRERR
(0x12). If a large number of 8b/10b errors are detected
within a short duration (error rate R 1/4), the deserializer
loses lock and stops the error counter. The deserializer
then attempts to relock to the serial data. DETERR and
CORRERR reset upon successful video link lock, suc-
cessful readout of their respective registers (through µC),
or whenever autoerror reset is enabled. The deserializer
uses a separate PRBS register during the internal PRBS
test, and DETERR and CORRERR are reset to 0x00.
tion fails due to contention. If communication across the
serial link is not required, the µCs can disable the forward
and reverse control channel using the FWDCCEN and
REVCCEN bits (0x04, D[1:0]) in the serializer/deserial-
izer. Communication across the serial link is stopped and
contention between µCs cannot occur.
As an example of dual µC use in an image-sensing appli-
cation, the serializer can be in sleep mode and waiting for
wake-up by the µC on the deserializer side. After wake-
up, the serializer-side µC assumes master control of the
serializer’s registers.
Changing the Clock Frequency
It is recommended that the serial link be enabled after
ERR Output
The deserializer has an open-drain ERR output. This
output asserts low whenever the number of detected/
corrected errors exceeds their respective error thresholds
during normal operation, or when at least one PRBS error
is detected during PRBS test. ERR reasserts high when-
ever DETERR and CORRERR reset, due to DETERR/
CORRERR readout, video link lock, or autoerror reset.
the video clock (f
) and the control-channel
PCLKOUT
clock (f
/f ) are stable. When changing the clock
UART I2C
frequency, stop the video clock for 5µs, apply the clock
at the new frequency, then restart the serial link or toggle
SEREN. On-the-fly changes in clock frequency are possi-
ble if the new frequency is immediately stable and without
glitches. The reverse control channel remains unavailable
for 350µs after serial link start or stop. When using the
Autoerror Reset
UART interface, limit on-the-fly changes in f
to fac-
UART
The default method to reset errors is to read the respec-
tive error registers in the deserializer (0x10, 0x12, and
0x13). Autoerror reset clears the error counters DETERR/
CORRERR and the ERR output ~1Fs after ERR goes low.
Autoerror reset is disabled on power-up. Enable autoerror
reset through AUTORST (0x08, D2). Autoerror reset does
not run when the device is in PRBS test mode.
tors of less than 3.5 at a time to ensure that the device
recognizes the UART sync pattern. For example, when
lowering the UART frequency from 1Mbps to 100kbps,
first send data at 333kbps then at 100kbps for reduction
ratios of 3 and 3.333, respectively.
Fast Detection of
Loss-of-Synchronization
Dual µC Control
A measure of link quality is the recovery time from loss-of-
synchronization. The host can be quickly notified of loss-
of-lock by connecting the deserializer’s LOCK output to
the GPI input. If other sources use the GPI input, such as
a touch-screen controller, the µC can implement a routine
to distinguish between interrupts from loss-of-sync and
normal interrupts. Reverse control-channel communica-
tion does not require an active forward link to operate and
accurately tracks the LOCK status of the GMSL link. LOCK
asserts for video link only and not for the configuration link.
Usually systems have one µC to run the control channel,
located on the serializer side for video-display applica-
tions or on the deserializer side for image-sensing appli-
cations. However, a µC can reside on each side simulta-
neously and trade off running the control channel. In this
case, each µC can communicate with the serializer and
deserializer and any peripheral devices.
Contention occurs if both µCs attempt to use the control
channel at the same time. It is up to the user to prevent
this contention by implementing a higher-level protocol.
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MAX9240A
6.25MHz to 100MHz, 25-Bit GMSL Deserializer for
Coax or STP Cable With Line Fault Detect
CX/TP through a pullup resistor to IOVDD to set a high
level, a pulldown resistor to GND to set a low level, or
IOVDD/2 or open to set a midlevel. For digital control, use
Providing a Frame Sync
(Camera Applications)
The GPI/GPO provides a simple solution for camera
applications that require a frame sync signal from the
ECU (e.g., surround-view systems). Connect the ECU
frame sync signal to the GPI input, and connect the GPO
output to the camera frame sync input. GPI/GPO have
a typical delay of 275µs. Skew between multiple GPI/
GPO channels is 115µs (max). If a lower skew signal is
required, connect the camera’s frame sync input to one of
three-state logic to drive the three-level logic input.
Configuration Blocking
The deserializer can block changes to registers. Set
CFGBLOCK to make all registers read only. Once set, the
registers remain blocked until the supplies are removed or
until PWDN is low.
2
the GMSL deserializer’s GPIOs and use an I C broadcast
write command to change the GPIO output state. This has
a maximum skew of 1.5µs.
Compatibility with other GMSL Devices
The MAX9240A deserializer is designed to pair with the
MAX9271/MAX9273 serializers, but interoperate with any
GMSL serializers. See the Table 11 for operating limitations.
Software Programming
of the Device Addresses
GPIOs
Both the serializer and the deserializer have program-
mable device addresses. This allows multiple GMSL
The deserializer has two open-drain GPIOs available
when not used as configuration inputs. GPIO1OUT and
GPIO0OUT (0x0E, D3 and D1) set the output state of the
GPIOs. Setting the GPIO output bits to 0 pulls the output
low, while setting the bits to 1 leaves the output undriven
and pulled high through internal/external pullup resistors.
The GPIO input buffers are always enabled. The input
states are stored in GPIO1 and GPIO0 (0x0E, D2 and
D0). Set GPIO1OUT/GPIO0OUT to 1 when using GPIO1/
GPIO0 as an input.
2
devices, along with I C peripherals, to coexist on the
same control channel. The serializer device address is in
register 0x00 of each device, while the deserializer device
address is in register 0x01 of each device. To change a
device address, first write to the device whose address
changes (register 0x00 of the serializer for serializer
device address change, or register 0x01 of the deserial-
izer for deserializer device address change). Then write
the same address into the corresponding register on the
other device (register 0x00 of the deserializer for serial-
izer device address change, or register 0x01 of the serial-
izer for deserializer device address change).
Staggered Parallel Outputs
The deserializer staggers the parallel data outputs to
reduce EMI and noise. Staggering outputs also reduces
the power-supply transient requirements. By default, the
deserializer staggers outputs according to Table 12. Disable
output staggering through the DISSTAG bit (0x08, D3).
Three-Level Configuration Inputs
CX/TP is a three-level input that controls the serial-
interface configuration and power-up defaults. Connect
Table 11. MAX9240A Feature Compatibility
MAX9240A FEATURE
GMSL DESERIALIZER
HSYNC/VSYNC encoding
Hamming-code error correction
I2C-to-I2C
If feature not supported in the serializer, must be turned off in the deserializer.
If feature not supported in the serializer, must be turned off in the deserializer.
If feature not supported in the serializer, must use UART-to-I2C or UART-to-UART.
CRC error detection
If feature not supported in the serializer, must be turned off in the deserializer.
If feature not supported in the serializer, the data is inputted as a single word at 1/2 the output
frequency.
Double output
If feature not supported in the deserializer, must connect unused serial output through 200nF
and 50Ω in series to AVDD and set the reverse control-channel amplitude to 100mV.
Coax
I2S encoding
If feature is supported in the serializer, must disable I2S in the serializer.
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MAX9240A
6.25MHz to 100MHz, 25-Bit GMSL Deserializer for
Coax or STP Cable With Line Fault Detect
Table 12. Staggered Output Delay
OUTPUT DELAY RELATIVE TO DOUT0 (ns)
OUTPUT
DISSTAG = 0
DISSTAG = 1
DOUT0–DOUT5, DOUT21, DOUT22
DOUT6–DOUT10, DOUT23, DOUT24
DOUT11–DOUT15
0
0.5
1
0
0
0
0
0
DOUT16–DOUT20
1.5
0.75
PCLKOUT
Table 13. Double-Function Configuration
GPIO0/DBL
FUNCTION
GPIO1/BWS
FUNCTION
MS/HVEN
FUNCTION
LCCEN
RX/SDA/EDC FUNCTION
TX/SCL/ES FUNCTION
MS input
(low = base mode,
high = bypass mode)
Functions as
GPIO
Functions as
GPIO
High
UART/I2C input/output
UART/I2C input/output
DBL input
(low = single
input,
high = double
input)
BWS input
(low = 24-bit
mode,
high = 32-bit
mode)
HVEN input
(low = HS/VS
encoding disabled,
high = HS/VS
EDC input
ES input
(low = error detection/
correction disabled,
high = error detection/
correction enabled)
(low = valid DOUT_ on
rising edge of PCLKOUT,
high = valid DOUT_ on
falling edge of PCLKOUT)
Low
encoding enabled)
Table 13a. Line Fault Mapping
REGISTER ADDRESS
BITS
NAME
VALUE
00
LINE FAULT TYPE
Negative cable wire shorted to supply voltage
Negative cable wire shorted to ground
Normal operation
01
D[3:2]
LFNEG
10
11
Negative cable wire disconnected
Positive cable wire shorted to supply voltage
Positive cable wire shorted to ground
Normal operation
0x14
00
01
D[1:0]
LFPOS
10
11
Positive cable wire disconnected
required external resistor connections. LFLT goes low
when a line fault is detected and LFLT goes high when
the line returns to normal. The line-fault failure type is
stored in 0x14 D[3:0] of the deserializer. Filter LFLT with
the µC to reduce the detector’s susceptibility to temporary
ground shifts. The fault detector threshold voltages are
referenced to the deserializer ground. Additional passive
components set the DC level of the cable (Figure 2a). If
the serializer and GMSL deserializer grounds are differ-
ent, the link DC voltage during normal operation can vary
and cross one of the fault detection thresholds.
Local Control-Channel Enable (LCCEN)
The deserializer provides inputs for limited configura-
tion of the device when a µC is not connected. Connect
LCCEN = low upon power-up to disable the local control
channel and enable the double-function configuration
inputs (Table 13). All input configuration states are latched
at power-up.
Line-Fault Detection
The line-fault detector in the deserializer monitors for line
failures such as short to ground, short to battery, and
open link for system fault diagnosis. Figure 2a shows the
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MAX9240A
6.25MHz to 100MHz, 25-Bit GMSL Deserializer for
Coax or STP Cable With Line Fault Detect
For the fault detection circuit, select the resistor’s power
rating to handle a short to the battery. In coax mode,
leave the unused line-fault inputs unconnected. To detect
the short-together case, refer to Application Note 4709:
GMSL Line-Fault Detection. Table 13a lists the mapping
for line-fault types.
transmission line impedance (usually 100Ω differential and
50Ω single-ended). This leaves the capacitor selection to
change the system time constant. Use 0.22µF or larger
high-frequency surface-mount ceramic capacitors, with
sufficient voltage rating to withstand a short to battery, to
pass the lower speed reverse control-channel signal. Use
capacitors with a case size less than 3.2mm x 1.6mm to
have lower parasitic effects to the high-speed signal.
Internal Input Pulldowns
The control and configuration inputs, except three-level
inputs, include a pulldown resistor to GND. External pull-
down resistors are not needed.
Power-Supply Circuits and Bypassing
The deserializer uses an AVDD and DVDD of 1.7V to
1.9V. All inputs and outputs, except for the serial input,
derive power from an IOVDD of 1.7V to 3.6V that scales
with IOVDD. Proper voltage-supply bypassing is essential
for high-frequency circuit stability. The GPI-to-GPO delay
is 0.35ms (max). Keep the time between GPI transmis-
sions to a minimum 0.35ms.
2
Choosing I C/UART Pullup Resistors
2
The I C and UART open-drain lines require a pullup
resistor to provide a logic-high level. There are tradeoffs
between power dissipation and speed, and a compromise
may be required when choosing pullup resistor values.
Every device connected to the bus introduces some
Power-Supply Table
2
capacitance even when the device is not in operation. I C
specifies 300ns rise times (30% to 70%) for fast mode,
which is defined for data rates up to 400kbps (see the I C
specifications in the AC Electrical Characteristics table
for details). To meet the fast-mode rise-time requirement,
Power-supply currents shown in the Electrical
Characteristics table are the sum of the currents from
AVDD, DVDD, and IOVDD. Typical currents from the indi-
vidual power supplies are shown in Table 14.
2
choose the pullup resistors so that rise time t = 0.85 x
R
Cables and Connectors
R
x C
< 300ns. The waveforms are not recog-
PULLUP
nized if the transition time becomes too slow. The deserial-
BUS
Interconnect for CML typically has a differential imped-
ance of 100Ω. Use cables and connectors that have
matched differential impedance to minimize impedance
discontinuities. Coax cables typically have a characteristic
impedance of 50Ω (contact the factory for 75Ω operation).
Table 15 lists the suggested cables and connectors used
in the GMSL link.
2
2
izer supports I C/UART rates up to 1Mbps (UART-to-I C
mode) and 400kbps (I C-to-I C mode).
2
2
AC-Coupling
AC-coupling isolates the receiver from DC voltages up
to the voltage rating of the capacitor. Capacitors at the
serializer output and at the deserializer input are needed
for proper link operation and to provide protection if either
end of the cable is shorted to a battery. AC-coupling
blocks low-frequency ground shifts and low-frequency
common-mode noise.
Table 14. Typical Power-Supply Currents
(Using Worst-Case Input Pattern)
PCLK (MHz)
AVDD (mA)
25.1
DVDD (mA)
9.2
IOVDD (mA)
10.3
25
50
Selection of AC-Coupling Capacitors
33.3
13.7
13.3
Voltage droop and the digital sum variation (DSV) of trans-
mitted symbols cause signal transitions to start from dif-
ferent voltage levels. Because the transition time is fixed,
starting the signal transition from different voltage levels
causes timing jitter. The time constant for an AC-coupled
link needs to be chosen to reduce droop and jitter to an
acceptable level. The RC network for an AC-coupled link
consists of the CML/coax receiver termination resistor
Table 15. Suggested Connectors and
Cables for GMSL
SUPPLIER
CONNECTOR
CABLE
RG174
TYPE
Coax
STP
Rosenberger 59S2AX-400A5-Y
JAE
MX38-FF
GT11L-2S
A-BW-Lxxxxx
(R ), the CML/coax driver termination resistor (R ),
TR TD
F-2WME
AWG28
and the series AC-coupling capacitors (C). The RC time
constant, for four equal-value series capacitors, is (C x
Nissei
STP
STP
Rosenberger D4S10A-40ML5-Z
Dacar 538
(R
+ R ))/4. R
and R
are required to match the
TD
TR TD
TR
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MAX9240A
6.25MHz to 100MHz, 25-Bit GMSL Deserializer for
Coax or STP Cable With Line Fault Detect
Board Layout
R
D
Separate the LVCMOS logic signals and CML/coax high-
speed signals to prevent crosstalk. Use a four-layer PCB
with separate layers for power, ground, CML/coax, and
LVCMOS logic signals. Layout PCB traces close to each
other for a 100Ω differential characteristic impedance.
The trace dimensions depend on the type of trace used
(microstrip or stripline). Note that two 50Ω PCB traces do
not have 100Ω differential impedance when brought close
together—the impedance goes down when the traces
are brought closer. Use a 50Ω trace for the single-ended
output when driving coax.
1MΩ
1.5kΩ
CHARGE-CURRENT- DISCHARGE
LIMIT RESISTOR
RESISTANCE
HIGH-
VOLTAGE
DC
DEVICE
UNDER
TEST
C
100pF
S
STORAGE
CAPACITOR
SOURCE
Figure 32. Human Body Model ESD Test Circuit
Route the PCB traces for differential CML channel in par-
allel to maintain the differential characteristic impedance.
Avoid vias. Keep PCB traces that make up a differential
pair equal length to avoid skew within the differential pair.
R
330Ω
D
CHARGE-CURRENT- DISCHARGE
ESD Protection
LIMIT RESISTOR
RESISTANCE
HIGH-
VOLTAGE
DC
DEVICE
UNDER
TEST
ESD tolerance is rated for Human Body Model, IEC
61000-4-2, and ISO 10605. The ISO 10605 and IEC
61000-4-2 standards specify ESD tolerance for electronic
systems. The serial link inputs are rated for ISO 10605
ESD protection and IEC 61000-4-2 ESD protection. All
pins are tested for the Human Body Model. The Human
C
150pF
S
STORAGE
CAPACITOR
SOURCE
Figure 33. IEC 61000-4-2 Contact Discharge ESD Test Circuit
Body Model discharge components are C = 100pF and
S
R
= 1.5kΩ (Figure 32). The IEC 61000-4-2 discharge
D
components are C = 150pF and R = 330Ω (Figure 33).
S
D
R
2kΩ
D
The ISO 10605 discharge components are C = 330pF
S
and R = 2kΩ (Figure 34).
D
CHARGE-CURRENT- DISCHARGE
LIMIT RESISTOR
RESISTANCE
HIGH-
VOLTAGE
DC
DEVICE
UNDER
TEST
C
S
STORAGE
CAPACITOR
330pF
SOURCE
Figure 34. ISO 10605 Contact Discharge ESD Test Circuit
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MAX9240A
6.25MHz to 100MHz, 25-Bit GMSL Deserializer for
Coax or STP Cable With Line Fault Detect
Table 16. Register Table (see Table 1)
REGISTER
ADDRESS
DEFAULT
VALUE
BITS
NAME
VALUE
FUNCTION
Serializer device address.
D[7:1]
SERID
XXXXXXX
0
1000000
0x00
D0
—
Reserved.
0
Deserializer device address. Default address is
determined by the state of the CX/TP input (Table 8).
1001000,
1001001
D[7:1]
DESID
XXXXXXX
0x01
0
Normal operation.
D0
CFGBLOCK
0
1
Registers 0x00 to 0x1F are read only.
No spread spectrum.
00
01
10
11
01
00
01
10
11
00
01
10
11
00
±2% spread spectrum.
D[7:6]
D[5:4]
D[3:2]
SS
—
00
01
11
No spread spectrum.
±4% spread spectrum.
Reserved.
12.5MHz to 25MHz pixel clock.
25MHz to 50MHz pixel clock.
Do not use.
0x02
PRNG
Automatically detect the pixel clock range.
0.5Gbps to 1Gbps serial-data rate.
1Gbps to 1.5Gbps serial-data rate.
Automatically detect serial-data rate.
Automatically detect serial-data rate.
Calibrate spread-modulation rate only once after locking.
D[1:0]
D[7:6]
SRNG
11
Calibrate spread-modulation rate every 2ms after
locking.
01
10
11
AUTOFM
00
Calibrate spread-modulation rate every 16ms after
locking.
0x03
Calibrate spread-modulation rate every 256ms after
locking.
D5
—
0
Reserved.
0
00000
Autocalibrate sawtooth divider.
D[4:0]
SDIV
00000
Manual SDIV setting. See the Manual Programming of
the Spread-Spectrum Divider section.
XXXXX
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MAX9240A
6.25MHz to 100MHz, 25-Bit GMSL Deserializer for
Coax or STP Cable With Line Fault Detect
Table 16. Register Table (see Table 1) (continued)
REGISTER
ADDRESS
DEFAULT
VALUE
BITS
D7
NAME
LOCKED
OUTENB
PRBSEN
SLEEP
VALUE
FUNCTION
0
LOCK output is low.
LOCK output is high.
Enable outputs.
0
(read only)
1
0
D6
0
0
0
1
Disable outputs.
0
Disable PRBS test.
Enable PRBS test.
Normal mode.
D5
1
0
D4
1
Activate sleep mode.
0x04
00
01
10, 11
0
Local control channel uses I2C when I2CSEL = 0.
Local control channel uses UART when I2CSEL = 0.
Local control channel disabled.
D[3:2]
D1
INTTYPE
01
1
Disable reverse control channel to serializer (sending).
Enable reverse control channel to serializer (sending).
REVCCEN
1
Disable forward control channel from serializer
(receiving).
0
1
0
1
D0
D7
FWDCCEN
1
Enable forward control channel from serializer
(receiving).
I2C conversion sends the register address when
converting UART to I2C.
I2CMETHOD
0
Disable sending of I2C register address when
converting UART to I2C (command-byte-only mode).
0
Normal parallel output driver current.
Boosted parallel output driver current.
Partial periodic HS/VS tracking.
Full periodic HS/VS tracking.
Equalizer disabled. Power-up default.
Equalizer enabled.
D6
D5
D4
DCS
HVTRMODE
ENEQ
0
1
0
1
0
1
0
1
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
11XX
2.1dB equalizer-boost gain.
2.8dB equalizer-boost gain.
3.4dB equalizer-boost gain.
4.2dB equalizer-boost gain.
5.2dB equalizer-boost gain.
6.2dB equalizer-boost gain.
7dB equalizer-boost gain.
0x05
D[3:0]
EQTUNE
1001
8.2dB equalizer-boost gain.
9.4dB equalizer-boost gain.
10.7dB equalizer-boost gain. Power-up default.
11.7dB equalizer-boost gain.
13dB equalizer-boost gain.
Do not use.
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6.25MHz to 100MHz, 25-Bit GMSL Deserializer for
Coax or STP Cable With Line Fault Detect
Table 16. Register Table (see Table 1) (continued)
REGISTER
ADDRESS
DEFAULT
VALUE
BITS
NAME
VALUE
00000010
0
FUNCTION
0x06
D[7:0]
—
Reserved.
00000010
Single-input mode. Power-up default when LCCEN =
high or GPIO0/DBL = low.
D7
D6
D5
DBL
DRS
BWS
0, 1
Double-input mode. Power-up default when LCCEN =
low and GPIO0/DBL = high.
1
0
High data-rate mode.
Low data-rate mode.
0
1
24-bit mode. Power-up default when LCCEN = high
or GPIO1/BWS = low.
0
0, 1
32-bit mode. Power-up default when LCCEN = low and
GPIO1/BWS = high.
1
Output data valid on rising edge of PCLKOUT.
Power-up default when LCCEN = high or TX/SCL/ES
= low. Do not change this value while the pixel clock is
running.
0
D4
ES
0, 1
Output data valid on falling edge of PCLKOUT.
Power-up default when LCCEN = low and TX/SCL/
ES = high. Do not change this value while the pixel
clock is running.
1
0x07
HS/VS tracking disabled. Power-up default when
LCCEN = high or MS/HVEN = low.
0
1
0
1
D3
HVTRACK
HVEN
0, 1
0, 1
HS/VS tracking enabled. Power-up default when
LCCEN = low and MS/HVEN = high.
HS/VS encoding disabled. Power-up default when
LCCEN = high or MS/HVEN = low.
D2
HS/VS encoding enabled. Power-up default when
LCCEN = low and MS/HVEN = high.
1-bit parity error detection (GMSL compatible).
Power-up default when LCCEN = high or RX/SDA/
EDC = low.
00
01
10
11
6-bit CRC error detection.
D[1:0]
EDC
00, 10
6-bit hamming code (single-bit error correct, double-
bit error detect) and 16-word interleaving. Power-up
default when LCCEN = low and RX/SDA/EDC = high.
Do not use.
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MAX9240A
6.25MHz to 100MHz, 25-Bit GMSL Deserializer for
Coax or STP Cable With Line Fault Detect
Table 16. Register Table (see Table 1) (continued)
REGISTER
ADDRESS
DEFAULT
VALUE
BITS
NAME
VALUE
FUNCTION
No VS or DOUT0 inversion.
0
Invert VS when HVEN = 1. Invert DOUT0 when
HVEN = 0.
Do not use if DBL = 0 in the deserializer and DBL = 1 in
the serializer.
D7
INVVS
0
1
0
No HS or DOUT1 inversion.
Invert HS when HVEN = 1. Invert DOUT1 when
HVEN = 0. Do not use if DBL = 0 in the deserializer and
DBL = 1 in the serializer.
D6
INVHS
0
1
D5
D4
—
0
0
Reserved.
0
0
Serializer DBL is not the same as deserializer.
0x08
UNEQDBL
Serializer DBL same as deserializer (set to 1 only when
HVEN = 0 and HVTRACK = 1).
1
0
1
0
Enable staggered outputs.
D3
DISSTAG
0
0
Disable staggered outputs.
Do not automatically reset error registers and outputs.
D2
AUTORST
Automatically reset DETERR and CORRERR registers
1Fs after ERR asserts.
1
00
01
ERR asserts when DETERR is larger than DETTHR.
ERR asserts when CORRERR is larger than
CORRTHR.
D[1:0]
ERRSEL
00
ERR asserts when DETERR is larger than DETTHR or
CORRERR is larger than CORRTHR.
10, 11
D[7:1]
D0
I2CSRCA
—
XXXXXXX
I2C address translator source A.
0000000
0x09
0x0A
0x0B
0x0C
0
Reserved.
0
D[7:1]
D0
I2CDSTA
—
XXXXXXX
I2C address translator destination A.
Reserved.
I2C address translator source B.
0000000
0
0
D[7:1]
D0
I2CSRCB
—
XXXXXXX
0000000
0
XXXXXXX
0
Reserved.
0
0000000
0
D[7:1]
D0
I2CDSTB
—
I2C address translator destination B.
Reserved.
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MAX9240A
6.25MHz to 100MHz, 25-Bit GMSL Deserializer for
Coax or STP Cable With Line Fault Detect
Table 16. Register Table (see Table 1) (continued)
REGISTER
ADDRESS
DEFAULT
VALUE
BITS
NAME
VALUE
FUNCTION
Acknowledge not generated when forward channel is
not available.
0
D7
I2CLOCACK
1
I2C-to-I2C slave generates local acknowledge when
forward channel is not available.
1
00
352ns/117ns I2C setup/hold time.
469ns/234ns I2C setup/hold time.
938ns/352ns I2C setup/hold time.
1046ns/469ns I2C setup/hold time.
8.47kbps (typ) I2C-to-I2C master bit-rate setting.
28.3kbps (typ) I2C-to-I2C master bit-rate setting.
84.7kbps (typ) I2C-to-I2C master bit-rate setting.
105kbps (typ) I2C-to-I2C master bit-rate setting.
173kbps (typ) I2C-to-I2C master bit-rate setting.
339kbps (typ) I2C-to-I2C master bit-rate setting.
533kbps (typ) I2C-to-I2C master bit-rate setting.
837kbps (typ) I2C-to-I2C master bit-rate setting.
64µs (typ) I2C-to-I2C slave remote timeout.
256µs (typ) I2C-to-I2C slave remote timeout.
1024µs (typ) I2C-to-I2C slave remote timeout.
No I2C-to-I2C slave remote timeout.
Reserved.
01
D[6:5]
D[4:2]
D[1:0]
I2CSLVSH
I2CMSTBT
I2CSLVTO
01
10
11
000
001
0x0D
010
011
101
100
101
110
111
00
01
10
10
11
D[7:6]
—
01
01
1
0
Disable GPI-to-GPO signal transmission to serializer.
Enable GPI-to-GPO signal transmission to serializer.
GPI input is low.
D5
GPIEN
1
0
0
D4
D3
D2
D1
GPIIN
(read only)
1
GPI input is high.
0
Set GPIO1 to low.
GPIO1OUT
GPIO1IN
1
0x0E
1
Set GPIO1 to high.
0
GPIO1 input is low.
0
(read only)
1
GPIO1 input is high.
0
Set GPIO0 to low.
GPIO0OUT
1
1
Set GPIO0 to high.
0
GPIO0 input is low.
0
D0
GPIO0IN
DETTHR
(read only)
1
GPIO0 input is high.
0x0F
0x10
0x11
0x12
D[7:0]
D[7:0]
D[7:0]
D[7:0]
XXXXXXXX
Error threshold for detected errors.
00000000
00000000
(read only)
DETERR
XXXXXXXX
XXXXXXXX
XXXXXXXX
Detected error counter.
CORRTHR
CORRERR
Error threshold for corrected errors.
Corrected error counter.
00000000
00000000
(read only)
00000000
(read only)
0x13
D[7:0]
PRBSERR
XXXXXXXX
PRBS error counter.
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MAX9240A
6.25MHz to 100MHz, 25-Bit GMSL Deserializer for
Coax or STP Cable With Line Fault Detect
Table 16. Register Table (see Table 1) (continued)
REGISTER
ADDRESS
DEFAULT
VALUE
BITS
D7
NAME
PRBSOK
—
VALUE
FUNCTION
0
PRBS test not completed.
0
(read only)
1
PRBS test completed with success.
Reserved.
000
(read only)
D[6:4]
000
00
01
Negative cable wire shorted to supply voltage
Negative cable wire shorted to ground
Normal operation
10
0x14
D[3:2]
D[1:0]
LFNEG
(read only)
10
11
Negative cable wire disconnected
Positive cable wire shorted to supply voltage
Positive cable wire shorted to ground
Normal operation
00
01
10
LFPOS
(read only)
10
11
Positive cable wire disconnected
Reserved.
0x15
0x16
0x17
0x18
0x19
D[7:0]
D[7:0]
D[7:0]
D[7:0]
D[7:0]
—
—
—
—
—
00100XXX
00110000
01010100
00110000
11001000
00100XXX
00110000
01010100
00110000
11001000
Reserved.
Reserved.
Reserved.
Reserved.
00000000
(read only)
0x1A
0x1B
0x1C
D[7:0]
D[7:0]
D[7:0]
D7
—
—
XXXXXXXX
XXXXXXXX
XXXXXXXX
Reserved.
Reserved.
Reserved.
00000000
(read only)
00000000
(read only)
—
0
1
0
1
0
1
0
1
CX/TP input is low.
CX/TP input is high.
CXSEL is 0.
0
CXTP
CXSEL
I2CSEL
LCCEN
—
(read only)
0
D6
(read only)
CXSEL is 1.
Input is low.
0
0x1D
D5
(read only)
Input is high.
Input is low.
0
D4
(read only)
Input is high.
0000
(read only)
D[3:0]
D[7:0]
D[7:5]
XXXX
00001100
000
Reserved.
00001100
(read only)
0x1E
0x1F
ID
Device identifier (MAX9240A = 0x0C).
Reserved.
000
(read only)
—
0
1
Not HDCP capable.
HDCP capable.
Device revision.
0
D4
CAPS
(read only)
D[3:0]
REVISION
XXXX
(read only)
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MAX9240A
6.25MHz to 100MHz, 25-Bit GMSL Deserializer for
Coax or STP Cable With Line Fault Detect
Typical Application Circuit
CAMERA APPLICATION
PCLK
DATA
FS
PCLKIN
DIN0–DIN9
GPO
PCLKOUT
PCLK
DATA
DOUT0–DOUT9
CONF1
CONF0
CAMERA
GPU
MAX9240A
45kΩ
5kΩ
45kΩ
5kΩ
MAX9271
LMN0
LMN1
RX/SDA/EDC
TX/SCL/ES
TX
RX
UART
TO PERIPHERALS
LFLT
GPI
LFLT
FS
RX/SDA/EDC
TX/SCL/DBL
LCCEN
OUT+
OUT-
IN+
IN-
LOCK
CX/TP
50kΩ
50kΩ
ECU
NOTE: NOT ALL PULLUP/PULLDOWN RESISTORS ARE SHOWN. SEE PIN DESCRIPTION FOR DETAILS.
Package Information
Ordering Information
For the latest package outline information and land patterns
(footprints), go to www.maximintegrated.com/packages. Note
that a “+”, “#”, or “-” in the package code indicates RoHS status
only. Package drawings may show a different suffix character, but
the drawing pertains to the package regardless of RoHS status.
PART
TEMP RANGE
PIN-PACKAGE
48 TQFN-EP*
48 TQFN-EP*
MAX9240AGTM+
MAX9240AGTM/V+**
-40°C to +105°C
-40°C to +105°C
+Denotes a lead(Pb)-free/RoHS-compliant package.
/V denotes an automotive qualified part.
*EP = Exposed pad.
PACKAGE
TYPE
PACKAGE
CODE
OUTLINE
NO.
LAND
PATTERN NO.
**Future product—contact factory for availability.
48 TQFN-EP
T4877+4
21-0144
90-0130
Chip Information
PROCESS: BiCMOS
Maxim Integrated
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www.maximintegrated.com
MAX9240A
6.25MHz to 100MHz, 25-Bit GMSL Deserializer for
Coax or STP Cable With Line Fault Detect
Revision History
REVISION REVISION
PAGES
DESCRIPTION
CHANGED
NUMBER
DATE
0
3/14
Initial release
—
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim Integrated’s website at www.maximintegrated.com.
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses
are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits)
shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
©
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.
2014 Maxim Integrated Products, Inc.
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