MAX9210_V01 [MAXIM]
Programmable DC-Balance 21-Bit Deserializers;
| 型号： | MAX9210_V01 |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Programmable DC-Balance 21-Bit Deserializers |
| 文件： | 总17页 (文件大小：1294K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MAX9210/MAX9214/
MAX9220/MAX9222
Programmable DC-Balance
21-Bit Deserializers
General Description
Features
The MAX9210/MAX9214/MAX9220/MAX9222 deserial-
ize three LVDS serial data inputs into 21 single-ended
LVCMOS/ LVTTL outputs. A parallel rate LVDS clock
received with the LVDS data streams provides timing
for deserialization. The outputs have a separate supply,
allowing 1.8V to 5V output logic levels.
● Programmable DC Balance or Non-DC Balance
● DC Balance Allows AC-Coupling for Wider Input
Common-Mode Voltage Range
● As Low as 8MHz Operation (MAX9210/MAX9220)
● Falling-Edge Output Strobe (MAX9220/MAX9222)
● Slower Output Transitions for Reduced EMI
The MAX9210/MAX9214/MAX9220/MAX9222 fea-
ture programmable DC balance, which allows isolation
between a serializer and deserializer using AC-coupling.
Each deserializer decodes data transmitted by one of
MAX9209/MAX9213 serializers.
(MAX9210/MAX9220)
● High-Impedance Outputs when PWRDWN is Low
Allow Output Busing
● Pin Compatible with DS90CR216A/DS90CR218A
The MAX9210/MAX9214 have rising-edge output strobes,
and when DC balance is not programmed, are compat-
ible with non-DC-balanced 21-bit deserializers such as
the DS90CR216A and DS90CR218A. The MAX9220/
MAX9222 have falling-edge output strobes.
(MAX9210/MAX9214)
● Fail-Safe Inputs in Non-DC-Balanced Mode
● 5V Tolerant PWRDWN Input
● PLL Requires No External Components
● Up to 1.785Gbps Throughput
Two frequency versions and two DC-balance default
conditions are available for maximum replacement flex-
ibility and compatibility with popular non-DC-balanced
deserializers. The transition time of the single-ended
outputs is increased on the low-frequency version parts
(MAX9210/MAX9220) for reduced EMI. The LVDS inputs
meet IEC 61000-4-2 Level 4 ESD specification, ±15kV for
Air Discharge and ±8kV Contact Discharge.
● Separate Output Supply Pins Allow Interface to 1.8V,
2.5V, 3.3V, and 5V Logic
● LVDS Inputs Meet IEC 61000-4-2 Level and ISO
10605 ESD Requirements
● LVDS Inputs Conform to ANSI TIA/EIA-644 LVDS
Standard
The MAX9210/MAX9214/MAX9220/MAX9222 are avail-
able in a TSSOP package, and operate over the -40°C to
+85°C temperature range.
● Low-Profile 48-Lead TSSOP Package
● +3.3V Main Power Supply
● -40°C to +85°C Operating Temperature Range
Applications
● Digital Copiers
● Laser Printers
Ordering Information
PART
TEMP RANGE
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
PIN-PACKAGE
48 TSSOP
48 TSSOP
48 TSSOP
48 TSSOP
MAX9210EUM
MAX9214EUM
MAX9220EUM
MAX9222EUM
Functional Diagram and Pin Configuration appear at end of
data sheet.
19-2864; Rev 6; 5/14
MAX9210/MAX9214/
MAX9220/MAX9222
Programmable DC-Balance
21-Bit Deserializers
Absolute Maximum Ratings
V
to GND .........................................................-0.5V to +4.0V
ESD Protection
Human Body Model (R = 1.5kΩ, C = 100pF)
CC
V
to GND.......................................................-0.5V to +6.0V
CCO
D
S
RxIN_, RxCLK IN_ to GND..................................-0.5V to +4.0V
All Pins to GND ...........................................................±5kV
PWRDWN to GND ...............................................-0.5V to +6.0V
IEC 61000-4-2 (R = 330Ω, C = 150pF)
Contact Discharge (RxIN_, RxCLK IN_) to GND............±8kV
Air Discharge (RxIN_, RxCLK IN_) to GND..................±15kV
D
S
DCB/NC to GND....................................... -0.5V to (V
+ 0.5V)
+ 0.5V)
CC
RxOUT_, RxCLK OUT to GND ..............-0.5V to (V
CCO
Continuous Power Dissipation (T = +70°C)
ISO 10605 (R = 2kΩ, C = 330pF)
D S
A
TSSOP (derate 16mW/°C above +70°C) ..................1282mW
Storage Temperature Range............................ -65°C to +150°C
Junction Temperature......................................................+150°C
Contact Discharge (RxIN_, RxCLK IN_) to GND............±8kV
Air Discharge (RxIN_, RxCLK IN_) to GND..................±25kV
Lead Temperature (soldering, 10s) .................................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
DC Electrical Characteristics
(V
= +3.0V to +3.6V, V
= +3.0V to +5.5V, PWRDWN = high, DCB/NC = high or low, differential input voltage |V | = 0.05V to
CC
CCO ID
1.2V, input common-mode voltage V
= |V
| to 2.4V - |V
|, T = -40°C to +85°C, unless otherwise noted. Typical values are at
CM
ID/2
ID/2 A
V
= V
= +3.3V, |V | = 0.2V, V
= 1.25V, T = +25°C.) (Notes 1, 2)
CC
CCO
ID
CM A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
SINGLE-ENDED INPUTS (PWRDWN, DCB/NC)
PWRDWN
2.0
2.0
-0.3
-20
5.5
+ 0.3
+0.8
+20
High-Level Input Voltage
V
V
IH
DCB/NC
V
CC
Low-Level Input Voltage
Input Current
V
I
V
µA
V
IL
V
= high or low, PWRDWN = high or low
IN
IN
Input Clamp Voltage
V
I
= -18mA
-1.5
CL
CL
SINGLE-ENDED OUTPUTS (RxOUT_, RxCLK OUT)
I
= -100µA
V
V
V
V
- 0.1
OH
CCO
CCO
CCO
CCO
RxCLK OUT
MAX9210/
- 0.25
- 0.40
- 0.25
High-Level Output Voltage
V
V
OH
MAX9220
I
I
I
= -2mA
= 100µA
= 2mA
RxOUT_
OH
OL
OL
MAX9214/MAX9222
0.1
0.2
RxCLK OUT
RxOUT_
MAX9210/
MAX9220
Low-Level Output Voltage
V
V
OL
0.26
0.2
MAX9214/MAX9222
PWRDWN = low,
_ = -0.3V to V
High-Impedance Output Current
I
-20
20
µA
OZ
V
+ 0.3V
CCO
OUT
Maxim Integrated
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MAX9210/MAX9214/
MAX9220/MAX9222
Programmable DC-Balance
21-Bit Deserializers
DC Electrical Characteristics (continued)
(V
= +3.0V to +3.6V, V
= +3.0V to +5.5V, PWRDWN = high, DCB/NC = high or low, differential input voltage |V | = 0.05V to
CC
CCO ID
1.2V, input common-mode voltage V
= |V
| to 2.4V - |V
|, T = -40°C to +85°C, unless otherwise noted. Typical values are at
CM
ID/2
ID/2 A
V
= V
= +3.3V, |V | = 0.2V, V
= 1.25V, T = +25°C.) (Notes 1, 2)
A
CC
CCO
ID
CM
PARAMETER
SYMBOL
CONDITIONS
MIN
-10
-5
TYP
MAX
-40
-20
-40
-75
-37
-75
UNITS
RxCLK OUT
RxOUT_
MAX9210/
MAX9220
V
= 3.0V
CCO
to 3.6V,
mA
V
= 0
Output Short-Circuit Current
(Note: Short one output at a
time.)
OUT
MAX9214/MAX9222
-10
-28
-14
-28
I
OS
RxCLK OUT
RxOUT_
MAX9210/
MAX9220
V
= 4.5V
CCO
to 5.5V,
= 0
V
OUT
MAX9214/MAX9222
LVDS INPUTS
Differential Input High Threshold
Differential Input Low Threshold
Input Current
V
50
mV
mV
µA
TH
V
-50
-25
TL
I
,
IN+
PWRDWN = high or low
+25
+25
I
IN-
I
,
V
= V = 0 or open,
CCO
INO+
CC
Power-Off Input Current
Input Resistor 1
-25
42
µA
I
DCB/NC, PWRDWN = 0 or open
INO-
PWRDWN = high or low, Figure 1
R
78
kΩ
IN1
IN2
V
= V
= 0 or open, Figure 1
CC
CCO
PWRDWN = high or low, Figure 1
Input Resistor 2
R
246
410
kΩ
V
= V
CCO
= 0 or open, Figure 1
MAX9210/
CC
POWER SUPPLY
8MHz
32
46
42
57
16MHz
34MHz
16MHz
34MHz
66MHz
10MHz
20MHz
33MHz
40MHz
20MHz
33MHz
40MHz
66MHz
85MHz
C = 8pF, worst-
L
case pattern,
MAX9220
81
98
DC-balanced mode;
52
63
V
= V
= 3.0V
CC
CCO
MAX9214/
MAX9222
to 3.6V, Figure 2
86
106
177
42
152
33
Worst-Case Supply Current
I
46
58
mA
CCW
MAX9210/
MAX9220
67
80
C = 8pF, worst
L
case pattern,
non-DC-balanced
78
94
53
64
mode; V
= V
CC
CCO
72
85
= 3.0V to 3.6V,
Figure 2
MAX9214/
MAX9222
81
99
127
159
149
186
50
Power-Down Supply Current
I
PWRDWN = low
µA
CCZ
Maxim Integrated
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MAX9210/MAX9214/
MAX9220/MAX9222
Programmable DC-Balance
21-Bit Deserializers
AC Electrical Characteristics
(V
= V
= +3.0V to +3.6V, 100mV
at 200kHz supply noise, C = 8pF, PWRDWN = high, DCB/NC = high or low, differential
CC
CCO
P-P
L
input voltage |V | = 0.1V to 1.2V, input common mode voltage V
= |V
| to 2.4V - |V
|, T = -40°C to +85°C, unless otherwise
ID
CM
ID/2
ID/2 A
noted. Typical values are at V
= V
= +3.3V, |V | = 0.2V, V
= 1.25V, T = 25°C.) (Notes 3, 4, 5)
CC
CCO
ID
CM A
PARAMETER
SYMBOL
CONDITIONS
MIN
3.52
2.2
TYP
5.04
3.15
3.15
3.18
2.12
2.12
7044
3137
1327
685
MAX
6.24
3.9
UNITS
RxOUT_
MAX9210/
MAX9220
0.1V
0.9V
Figure 3
to
to
CCO
CCO
Output Rise Time
Output Fall Time
CLHT
CHLT
,
,
RxCLK OUT
ns
MAX9214/MAX9222
2.2
3.9
RxOUT_
RxCLK OUT
1.95
1.3
4.35
2.9
MAX9210/
MAX9220
0.9V
0.1V
Figure 3
CCO
CCO
ns
MAX9214/MAX9222
8MHz
1.3
2.9
6600
2560
900
330
6600
2500
960
330
16MHz
34MHz
66MHz
10MHz
20MHz
40MHz
85MHz
DC-balanced mode,
Figure 4 (Note 6)
RxIN Skew Margin
RSKM
ps
7044
3300
1448
685
Non-DC-balanced mode,
Figure 4 (Note 6)
RxCLK OUT High Time
RxCLK OUT Low Time
RCOH
RCOL
RSRC
RHRC
RCCD
Figures 5a, 5b
Figures 5a, 5b
Figures 5a, 5b
Figures 5a, 5b
Figures 6a, 6b
0.35 x RCOP
0.35 x RCOP
0.30 x RCOP
0.45 x RCOP
ns
ns
ns
ns
ns
RxOUT Setup to RxCLK OUT
RxOUT Hold from RxCLK OUT
RxCLK IN to RxCLK OUT Delay
4.9
6.17
8.1
32800 x RCIP
100
Deserializer Phase-Locked Loop
Set
RPLLS
RPDD
Figure 7
Figure 8
ns
ns
Deserializer Power-Down Delay
Note 1: Current into a pin is defined as positive. Current out of a pin is defined as negative. All voltages are referenced to ground
except V and V
.
TL
TH
Note 2: Maximum and minimum limits over temperature are guaranteed by design and characterization. Devices are production
tested at T = +25°C.
A
Note 3: AC parameters are guaranteed by design and characterization, and are not production tested. Limits are set at ±6 sigma.
Note 4: C includes probe and test jig capacitance.
L
Note 5: RCIP is the period of RxCLK IN. RCOP is the period of RxCLK OUT. RCIP = RCOP.
Note 6: RSKM measured with ≤ 150ps cycle-to-cycle jitter on RxCLK IN.
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MAX9210/MAX9214/
MAX9220/MAX9222
Programmable DC-Balance
21-Bit Deserializers
Typical Operating Characteristics
(V
= V
= +3.3V, C = 8pF, PWRDWN = high, differential input voltage │V │ = 0.2V, input common-mode voltage V
= 1.2V,
CM
CC
CCO
L
ID
T
= +25°C, unless otherwise noted.)
A
WORST-CASE PATTERN AND PRBS
SUPPLY CURRENT vs. FREQUENCY
WORST-CASE PATTERN AND PRBS
SUPPLY CURRENT vs. FREQUENCY
100
90
80
70
60
100
90
80
70
60
MAX9220
DC-BALANCED MODE
MAX9220
NON-DC-BALANCED MODE
WORST-CASE PATTERN
WORST-CASE PATTERN
50
40
50
40
7
2 - 1 PRBS
7
2 - 1 PRBS
30
20
30
20
5
10
15
20
30
35
40
5
10
15
20
30
35
40
25
25
FREQUENCY (MHz)
FREQUENCY (MHz)
WORST-CASE PATTERN SUPPLY CURRENT
vs. FREQUENCY
WORST-CASE PATTERN SUPPLY CURRENT
vs. FREQUENCY
160
160
MAX9214
MAX9214
DC-BALANCED MODE
NON-DC-BALANCED MODE
140
120
100
80
140
120
100
80
60
60
40
40
30
5
20
35
50
65
80
15
45
60
75
90
FREQUENCY (MHz)
FREQUENCY (MHz)
OUTPUT TRANSITION TIME
OUTPUT TRANSITION TIME
vs. OUTPUT SUPPLY VOLTAGE (V
)
vs. OUTPUT SUPPLY VOLTAGE (V
)
CCO
CCO
5
7
6
5
4
3
2
1
MAX9220
MAX9214
4
3
2
1
t
R
t
R
t
F
t
F
2.5
3.0
3.5
4.0
4.5
5.0
2.5
3.0
3.5
4.0
4.5
5.0
OUTPUT SUPPLY VOLTAGE (V)
OUTPUT SUPPLY VOLTAGE (V)
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MAX9210/MAX9214/
MAX9220/MAX9222
Programmable DC-Balance
21-Bit Deserializers
Pin Description
PIN
NAME
FUNCTION
1, 2, 4, 5,
45, 46, 47
RxOUT14–
RxOUT20
Channel 2 Single-Ended Outputs
Ground
3, 25, 32, 38, 44
GND
LVTTL/LVCMOS DC-Balance Programming Input:
MAX9210: pulled up to V
MAX9214: pulled up to V
MAX9220: pulled up to V
MAX9222: pulled up to V
See Table 1.
CC
CC
CC
CC
6
DCB/NC
7, 13, 18
LVDS GND
RxIN0-
LVDS Ground
8
9
Inverting Channel 0 LVDS Serial Data Input
Noninverting Channel 0 LVDS Serial Data Input
Inverting Channel 1 LVDS Serial Data Input
Noninverting Channel 1 LVDS Serial Data Input
LVDS Supply Voltage
RxIN0+
RxIN1-
10
11
RxIN1+
12
LVDS V
CC
14
RxIN2-
RxIN2+
Inverting Channel 2 LVDS Serial Data Input
Noninverting Channel 2 LVDS Serial Data Input
Inverting LVDS Parallel Rate Clock Input
Noninverting LVDS Parallel Rate Clock Input
PLL Ground
15
16
RxCLK IN-
RxCLK IN+
PLL GND
17
19, 21
20
PLL V
PLL Supply Voltage
CC
5V Tolerant LVTTL/LVCMOS Power-Down Input. Internally pulled down to GND. Outputs
are high impedance when PWRDWN = low or open.
22
23
PWRDWN
Parallel Rate Clock Single-Ended Output. MAX9210/MAX9214, rising edge strobe.
MAX9220/MAX9222, falling edge strobe.
RxCLK OUT
24, 26, 27, 29,
30, 31, 33
RxOUT0–
RxOUT6
Channel 0 Single-Ended Outputs
Output Supply Voltage
28, 36, 48
V
CCO
34, 35, 37, 39,
40, 41, 43
RxOUT7–
RxOUT13
Channel 1 Single-Ended Outputs
Digital Supply Voltage
42
V
CC
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MAX9210/MAX9214/
MAX9220/MAX9222
Programmable DC-Balance
21-Bit Deserializers
Table 1. DC-Balance Programming
OUTPUT STROBE
EDGE
OPERATING
FREQUENCY (MHz)
DEVICE
DCB/NC
OPERATING MODE
High or open
Low
DC balanced
Non-DC balanced
DC balanced
8 to 34
MAX9210
Rising
Rising
Falling
Falling
10 to 40
High or open
Low
16 to 66
MAX9214
MAX9220
MAX9222
Non-DC balanced
DC balanced
20 to 85
High or open
Low
8 to 34
Non-DC balanced
DC balanced
10 to 40
High or open
Low
16 to 66
Non-DC balanced
20 to 85
Detailed Description
V
CC
The MAX9210/MAX9220 operate at a parallel clock
frequency of 8MHz to 34MHz in DC-balanced mode
and 10MHz to 40MHz in non-DC-balanced mode. The
MAX9214/MAX9222 operate at a parallel clock frequency
of 16MHz to 66MHz in DC-balanced mode and 20MHz to
85MHz in non-DC-balanced mode. The transition times of
the single-ended outputs are increased on the MAX9210/
MAX9220 for reduced EMI.
RIN2
RxIN_ + OR
RxCLK IN+
RxIN_ + OR
RxCLK IN+
V
CC
- 0.3V
RIN1
RIN1
RIN1
RIN1
DC-balanced or non-DC-balanced operation is controlled
by the DCB/NC pin (see Table 1 for DCB/NC default set-
tings and operating modes). In non-DC-balanced mode,
each channel deserializes 7 bits every cycle of the parallel
clock. In DC-balanced mode, 9 bits are deserialized every
clock cycle (7 data bits + 2 DCbalance bits). The highest
data rate in DC-balanced mode for the MAX9214 and
MAX9222 is 66MHz x 9 = 594Mbps. In non-DC-balanced
mode, the maximum data rate is 85MHz x 7 = 595Mbps.
1.2V
RxIN_ - OR
RxCLK IN-
RxIN_ - OR
RxCLK IN-
NON-DC-BALANCED MODE
DC-BALANCED MODE
DC Balance
Figure 1. LVDS Input Circuits
Data coding by the MAX9209/MAX9213 serializers (which
are companion devices to the MAX9210/MAX9214/
MAX9220/MAX9222 deserializers) limits the imbalance
of ones and zeros transmitted on each channel. If +1 is
assigned to each binary 1 transmitted and -1 is assigned
to each binary 0 transmitted, the variation in the running
sum of assigned values is called the digital sum variation
(DSV). The maximum DSV for the data channels is 10.
At most, 10 more zeros than ones, or 10 more ones than
zeros, are transmitted. The maximum DSV for the clock
channel is five. Limiting the DSV and choosing the correct
coupling capacitors maintains differential signal amplitude
and reduces jitter due to droop on AC-coupled links.
RCIP
RxCLK OUT
ODD RxOUT
EVEN RxOUT
RISING EDGE STROBE SHOWN.
Figure 2. Worst-Case Test Pattern
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MAX9210/MAX9214/
MAX9220/MAX9222
Programmable DC-Balance
21-Bit Deserializers
90%
90%
RxOUT_ OR
RxCLK OUT
10%
10%
RxOUT_ OR
RxCLK OUT
8pF
CLHT
CHLT
Figure 3. Output Load and Transition Times
IDEAL SERIAL BIT TIME
1.3V
1.1V
RxCLK IN
V
= 0
ID
RCCD
1.5V
RxCLK OUT
RSKM
RSKM
IDEAL
IDEAL
Figure 6a. Rising-Edge Clock-IN to Clock-OUT Delay
MIN
MAX
INTERNAL STROBE
+
Figure 4. LVDS Receiver Input Skew Margin
RxCLK IN
V
ID
= 0
-
RCCD
RCIP
1.5V
RxCLK OUT
RxCLK OUT
2.0V
2.0V
2.0V
0.8V
0.8V
RCOL
RCOH
RHRC
2.0V
Figure 6b. Falling-Edge Clock-IN to Clock-OUT Delay
RSRC
2.0V
0.8V
RxOUT_
0.8V
2V
Figure 5a. Rising-Edge Output Setup/Hold and High/Low Times
PWRDWN
3V
RCIP
V
CC
RPLLS
2.0V
0.8V
2.0V
RxCLK OUT
0.8V
0.8V
RxCLK IN
RCOH
RSRC
RCOL
RHRC
2.0V
0.8V
2.0V
0.8V
RxCLK OUT
RxOUT_
HIGH-Z
Figure 5b. Falling-Edge Output Setup/Hold and High/Low Times
Figure 7. Phase-Locked Loop Set Time
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MAX9210/MAX9214/
MAX9220/MAX9222
Programmable DC-Balance
21-Bit Deserializers
To obtain DC balance on the data channels, the serial-
izer parallel data is inverted or not inverted, depending
on the sign of the digital sum at the word boundary. Two
complementary bits are appended to each group of 7 par-
allel input data bits to indicate to the MAX9210/MAX9214/
MAX9220/MAX9222 deserializers whether the data bits
are inverted (see Figures 9 and 10). The deserializer
restores the original state of the parallel data. The LVDS
clock signal alternates duty cycles of 4/9 and 5/9, which
maintain DC balance.
PWRDWN
0.8V
RxCLK IN
RPDD
RxOUT_
RxCLK OUT
AC-Coupling Benefits
Bit errors experienced with DC-coupling can be elimi-
nated by increasing the receiver common-mode voltage
range by AC-coupling. AC-coupling increases the com-
mon-mode voltage range of an LVDS receiver to nearly
HIGH-Z
Figure 8. Power-Down Delay
+
-
RxCLK IN
CYCLE N - 1
CYCLE N
CYCLE N + 1
TxIN15 TxIN14 TxIN20 TxIN19 TxIN18 TxIN17 TxIN16 TxIN15 TxIN14 TxIN20 TxIN19 TxIN18 TxIN17 TxIN16 TxIN15 TxIN14
RxIN2
TxIN8
RxIN1
TxIN7
TxIN0
TxIN13 TxIN12 TxIN11 TxIN10 TxIN9
TxIN8
TxIN1
TxIN7
TxIN0
TxIN13 TxIN12 TxIN11 TxIN10 TxIN9
TxIN8
TxIN1
TxIN7
TxIN0
TxIN1
RxIN0
TxIN6
TxIN5
TxIN4
TxIN3
TxIN2
TxIN6
TxIN5
TxIN4
TxIN3
TxIN2
TxIN_ IS DATA FROM THE SERIALIZER.
Figure 9. Deserializer Serial Input in Non-DC-Balanced Mode
+
-
RxCLK IN
CYCLE N - 1
CYCLE N
CYCLE N + 1
DCB2 TxIN20 TxIN19 TxIN18 TxIN17 TxIN16 TxIN15 TxIN14
DCA2
RxIN2
DCB2
TxIN20 TxIN19 TxIN18 TxIN17 TxIN16 TxIN15 TxIN14
DCA2
DCA1
DCA0
DCA1
RxIN1
DCB1
DCB0
TxIN13 TxIN12 TxIN11 TxIN10 TxIN9
TxIN8
TxIN1
TxIN7
TxIN0
DCB1 TxIN13 TxIN12 TxIN11 TxIN10
TxIN9
TxIN2
TxIN8
TxIN1
TxIN7
TxIN0
DCA0
RxIN0
TxIN6
TxIN5
TxIN4
TxIN3
TxIN2
DCB0
TxIN6
TxIN5
TxIN4
TxIN3
TxIN_, DCA_, AND DCB_ ARE DATA FROM THE SERIALIZER.
Figure 10. Deserializer Serial Input in DC-Balanced Mode
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MAX9210/MAX9214/
MAX9220/MAX9222
Programmable DC-Balance
21-Bit Deserializers
the voltage rating of the capacitor. The typical LVDS
driver output is 350mV centered on an offset voltage of
1.25V, making single-ended output voltages of 1.425V
and 1.075V. An LVDS receiver accepts signals from 0 to
2.4V, allowing approximately ±1V common-mode differ-
ence between the driver and receiver on a DC-coupled
link (2.4V - 1.425V = 0.975V and 1.075V - 0V = 1.075V).
Common-mode voltage differences may be due to ground
potential variation or common-mode noise. If there is
more than ±1V of difference, the receiver is not guaran-
teed to read the input signal correctly and may cause bit
errors. AC-coupling filters low-frequency ground shifts and
common-mode noise and passes high-frequency data. A
common-mode voltage difference up to the voltage rating
of the coupling capacitor (minus half the differential swing)
is tolerated. DC-balanced coding of the data is required to
maintain the differential signal amplitude and limit jitter on
an AC-coupled link. A capacitor in series with each output
of the LVDS driver is sufficient for AC-coupling. However,
two capacitors—one at the serializer output and one at
the deserializer input—provide protection in case either
end of the cable is shorted to a high voltage.
Applications Information
Selection of AC-Coupling Capacitors
Voltage droop and the DSV of transmitted symbols cause
signal transitions to start from different voltage levels.
Because the transition time is finite, starting the signal
transition from different voltage levels causes timing jit-
ter. The time constant for an AC-coupled link needs to be
chosen to reduce droop and jitter to an acceptable level.
The RC network for an AC-coupled link consists of the
LVDS receiver termination resistor (R ), the LVDS driver
T
output resistor (R ), and the series AC-coupling capaci-
O
tors (C). The RC time constant for two equal-value series
MAX9210
MAX9214
MAX9220
MAX9222
MAX9209
MAX9213
TRANSMISSION LINE
TxOUT
RxIN
7
7
7
7
100Ω
100Ω
100Ω
100Ω
7 : 1
7 : 1
7 : 1
PLL
1 : 7
1 : 7
1 : 7
PLL
7
7
TxIN
RxOUT
PWRDWN
TxCLK IN
PWRDWN
RxCLK OUT
TxCLK OUT
RxCLK IN
21:3 SERIALIZER
3:21 DESERIALIZER
Figure 11. DC-Coupled Link, Non-DC-Balanced Mode
Maxim Integrated
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MAX9210/MAX9214/
MAX9220/MAX9222
Programmable DC-Balance
21-Bit Deserializers
MAX9210
MAX9214
MAX9220
MAX9222
HIGH-FREQUENCY, CERAMIC
SURFACE-MOUNT CAPACITORS
CAN ALSO BE PLACED AT THE
MAX9209
MAX9213
SERIALIZER INSTEAD OF THE DESERIALIZER.
TxOUT
RxIN
7
7
7
7
100Ω
100Ω
100Ω
100Ω
(7 + 2):1
(7 + 2):1
(7 + 2):1
PLL
1:(9 - 2)
7
TxIN
1:(9 - 2)
1:(9 - 2)
PLL
RxOUT
7
PWRDWN
TxCLK IN
PWRDWN
RxCLK OUT
TxCLK OUT
RxCLK IN
21:3 SERIALIZER
3:21 DESERIALIZER
Figure 12. Two Capacitors per Link, AC-Coupled, DC-Balanced Mode
capacitors is (C x (R + R ))/2 (Figure 12). The RC time
Equation 1 is for two series capacitors (Figure 12). The
T
O
constant for four equal-value series capacitors is (C x (R
bit time (t ) is the period of the parallel clock divided by 9.
T
B
+ R ))/4 (Figure 13).
The DSV is 10. See equation 3 for four series capacitors
(Figure 13).
O
R is required to match the transmission line impedance
T
(usually 100Ω) and R is determined by the LVDS driver
The capacitor for 2% maximum droop at 8MHz parallel
rate clock is:
O
design (the minimum differential output resistance of 78Ω
for the MAX9209/MAX9213 serializers is used in the fol-
lowing example). This leaves the capacitor selection to
change the system time constant.
C = - (2 x t x DSV)/(ln (1 - D) x (R + R ))
B
T
O
C = - (2 x 13.9ns x 10)/(ln (1 - 0.02) x (100Ω + 78Ω))
C = 0.0773μF
In the following example, the capacitor value for a droop
of 2% is calculated. Jitter due to this droop is then calcu-
lated assuming a 1ns transition time:
Jitter due to droop is proportional to the droop and transi-
tion time:
t = t x D (Eq 2)
C = - (2 x t x DSV)/(ln (1 - D) x (R + R )) (Eq 1)
J
T
B
T
O
where:
where:
t = jitter (s).
J
C = AC-coupling capacitor (F).
t = transition time (s) (0 to 100%).
T
t = bit time (s).
B
D = droop (% of signal amplitude).
Jitter due to 2% droop and assumed 1ns transition time is:
DSV = digital sum variation (integer).
ln = natural log.
D = droop (% of signal amplitude).
t = 1ns x 0.02
J
R = termination resistor (Ω).
T
t = 20ps
J
R
= output resistance (Ω).
O
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MAX9210/MAX9214/
MAX9220/MAX9222
Programmable DC-Balance
21-Bit Deserializers
MAX9209
MAX9213
MAX9210
MAX9214
MAX9220
MAX9222
HIGH-FREQUENCY CERAMIC
SURFACE-MOUNT CAPACITORS
TxOUT
RxIN
7
7
7
7
100Ω
(7 + 2):1
(7 + 2):1
(7 + 2):1
PLL
1:(9 - 2)
7
100Ω
100Ω
100Ω
TxIN
1:(9 - 2)
1:(9 - 2)
PLL
RxOUT
7
PWRDWN
TxCLK IN
PWRDWN
RxCLK OUT
TxCLK OUT
RxCLK IN
21:3 SERIALIZER
3:21 DESERIALIZER
Figure 13. Four Capacitors per Link, AC-Coupled, DC-Balanced Mode
The transition time in a real system depends on the fre-
quency response of the cable driven by the serializer. The
capacitor value decreases for a higher frequency parallel
clock and for higher levels of droop and jitter. Use high-
frequency, surface-mount ceramic capacitors.
quency. In this case, all outputs are driven low. To prevent
switching due to noise when the clock input is not driven,
bias the clock input to differential +15mV by connecting a
10kΩ ±1% pullup resistor between the noninverting input
and V , and a 10kΩ ±1% pulldown resistor between the
CC
inverting input and ground. These bias resistors, along
with the 100Ω ±1% tolerance termination resistor, provide
+15mV of differential input. However, the +15mV bias
causes degradation of RSKM proportional to the slew
rate of the clock input. For example, if the clock transi-
tions 250mV in 500ps, the slew rate of 0.5mV/ps reduces
RSKM by 30ps.
Equation 1 altered for four series capacitors (Figure 13) is:
C = - (4 x t x DSV)/(ln (1 - D) x (R + R )) (Eq 3)
B
T
O
Fail-Safe
The MAX9210/MAX9214/MAX9220/MAX9222 have fail-
safe LVDS inputs in non-DC-balanced mode (Figure 1).
Fail-safe drives the outputs low when the corresponding
LVDS input is open, undriven and shorted, or undriven
and parallel terminated. The fail-safe on the LVDS clock
input drives all outputs low. Fail-safe does not operate in
DC-balanced mode.
Unused LVDS Data Inputs
In non-DC-balanced mode, leave unused LVDS data
inputs open. In non-DC balanced mode, the input failsafe
circuit drives the corresponding outputs low and no pullup
or pulldown resistors are needed. In DC-balanced mode,
at each unused LVDS data input, pull the inverting input
Input Bias and Frequency Detection
In DC-balanced mode, the inverting and noninverting
LVDS inputs are internally connected to +1.2V through
42kΩ (min) to provide biasing for AC-coupling (Figure 1).
A frequency-detection circuit on the clock input detects
when the input is not switching, or is switching at low fre-
up to V
using a 10kΩ resistor, and pull the noninvert-
CC
ing input down to ground using a 10kΩ resistor. Do not
connect a termination resistor. The pullup and pulldown
resistors drive the corresponding outputs low and prevent
switching due to noise.
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MAX9210/MAX9214/
MAX9220/MAX9222
Programmable DC-Balance
21-Bit Deserializers
inputs are rated for ±8kV Contact Discharge and ±15kV
Air Discharge. The Human Body Model discharge com-
PWRDWN
Driving PWRDWN low puts the outputs in high impedance,
stops the PLL, and reduces supply current to 50μA or less.
Driving PWRDWN high drives the outputs low until the
PLL locks. The outputs of two deserializers ca be bused to
form a 2:1 mux with the outputs controlled by PWRDWN.
Wait 100ns between disabling one deserializer (driving
PWRDWN low) and enabling the second one (driving
PWRDWN high) to avoid contention of the bused outputs.
ponents are C = 100pF and R = 1.5kΩ (Figure 15).
S
D
For the Human Body Model, all pins are rated for ±5kV
Contact Discharge. The ISO 10605 discharge compo-
nents are C = 330pF and R = 2kΩ (Figure 16). For
S
D
ISO 10605, the LVDS inputs are rated for ±8kV Contact
Discharge and ±25kV Air Discharge.
5V Tolerant Input
PWRDWN is 5V tolerant and is internally pulled down to
Input Clock and PLL Lock Time
GND. DCB/NC is not 5V tolerant. The input voltage range
There is no required timing sequence for the application
or reapplication of the parallel rate clock (RxCLK IN) rela-
tive to PWRDWN, or to a power-supply ramp for proper
PLL lock. The PLL lock time is set by an internal counter.
The maximum time to lock is 32,800 clock periods. Power
and clock should be stable to meet the lock time specifica-
tion. When the PLL is locking, the outputs are low.
for DCB/NC is nominally ground to V . Normally, DCB/
CC
NC is connected to V
or ground.
CC
R
D
50Ω TO 100Ω
330Ω
CHARGE-CURRENT- DISCHARGE
Power-Supply Bypassing
There are separate on-chip power domains for digital cir-
cuits, outputs, PLL, and LVDS inputs. Bypass each V
LIMIT RESISTOR
RESISTANCE
HIGH-
VOLTAGE
DC
DEVICE
UNDER
TEST
C
150pF
S
STORAGE
CAPACITOR
,
CC
V
CCO
, PLL V , and LVDS V
pin with high-frequency,
CC
CC
SOURCE
surface-mount ceramic 0.1μF and 0.001μF capacitors in
parallel as close to the device as possible, with the small-
est value capacitor closest to the supply pin.
Figure 14. IEC 61000-4-2 Contact Discharge ESD Test Circuit
Cables and Connectors
Interconnect for LVDS typically has a differential imped-
ance of 100Ω. Use cables and connectors that have
matched differential impedance to minimize impedance
discontinuities.
R
1.5kΩ
D
1MΩ
CHARGE-CURRENT- DISCHARGE
LIMIT RESISTOR
RESISTANCE
Twisted-pair and shielded twisted-pair cables offer supe-
rior signal quality compared to ribbon cable and tend to
generate less EMI due to magnetic field canceling effects.
Balanced cables pick up noise as common mode, which
is rejected by the LVDS receiver.
HIGH-
VOLTAGE
DC
DEVICE
UNDER
TEST
C
S
STORAGE
CAPACITOR
100pF
SOURCE
Board Layout
Figure 15. Human Body ESD Test Circuit
Keep the LVTTL/LVCMOS outputs and LVDS input sig-
nals separated to prevent crosstalk. A four-layer print-
edcircuit board (PCB) with separate layers for power,
ground, LVDS inputs, and digital signals is recommended.
R
2kΩ
D
50Ω TO 100Ω
CHARGE-CURRENT- DISCHARGE
ESD Protection
LIMIT RESISTOR
RESISTANCE
HIGH-
VOLTAGE
DC
The MAX9210/MAX9214/MAX9220/MAX9222 ESD toler-
ance is rated for IEC 61000-4-2, Human Body Model and
ISO 10605 standards. IEC 61000-4-2 and ISO 10605
specify ESD tolerance for electronic systems. The IEC
61000-4-2 discharge components are CS = 150pF and
DEVICE
UNDER
TEST
C
330pF
S
STORAGE
CAPACITOR
SOURCE
R
= 330Ω (Figure 14). For IEC 61000-4-2, the LVDS
D
Figure 16. ISO 10605 Contact Discharge ESD Test Circuit
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MAX9210/MAX9214/
MAX9220/MAX9222
Programmable DC-Balance
21-Bit Deserializers
The maximum supply current in DC-balanced mode for
Skew Margin (RSKM)
V
= V = 3.6V at f = 34MHz is 106mA (from the
CCO C
CC
Skew margin (RSKM) is the time allowed for degrada-
tion of the serial data sampling setup and hold times by
sources other than the deserializer. The deserializer sam-
pling uncertainty is accounted for and does not need to be
subtracted from RSKM. The main outside contributors of
jitter and skew that subtract from RSKM are interconnect
intersymbol interference, serializer pulse position uncer-
tainty, and pair-to-pair path skew.
DC Electrical Characteristics table). Add 10.4mA to get
the total approximate maximum supply current at V
=
CCO
5.5V and V
= 3.6V.
CC
If the output supply voltage is less than V
= 3.6V, the
CCO
reduced supply current can be calculated using the same
formula and method.
At high switching frequency, high supply voltage, and
high capacitive loading, power dissipation can exceed
the package power dissipation rating. Do not exceed
the maximum package power dissipation rating. See the
Absolute Maximum Ratings for maximum package power
dissipation capacity and temperature derating.
V
Output Supply and Power Dissipation
CCO
The outputs have a separate supply (V
) for inter-
CCO
facing to systems with 1.8V to 5V nominal input logic
levels. The DC Electrical Characteristics table gives the
maximum supply current for V
= 3.6V with 8pF load
CCO
at several switching frequencies with all outputs switch-
ing in the worst-case switching pattern. The approximate
Rising- or Falling-Edge Output Strobe
The MAX9210/MAX9214 have a rising-edge output strobe,
which latches the parallel output data into the next chip on
the rising edge of RxCLK OUT. The MAX9220/MAX9222
have a falling-edge output strobe, which latches the par-
allel output data into the next chip on the falling edge of
RxCLK OUT. The deserializer output strobe polarity does
not need to match the serializer input strobe polarity. A
deserializer with rising or falling edge output strobe can
be driven by a serializer with a rising edge input strobe.
incremental supply current for V
other than 3.6V
CCO
with the same 8pF load and worst-case pattern can be
calculated using:
I = C V 0.5f x 21 (data outputs)
I
T I
C
+ CTV f x 1 (clock output)
I C
where:
I = incremental supply current.
I
C = total internal (C ) and external (C ) load capaci-
T
INT
L
tance.
V = incremental supply voltage.
I
f
C
= output clock switching frequency.
The incremental current is added to (for V
> 3.6V)
CCO
or subtracted from (for V
< 3.6V) the DC Electrical
CCO
Characteristics table maximum supply current. The inter-
nal output buffer capacitance is C = 6pF. The worst-
INT
case pattern switching frequency of the data outputs is
half the switching frequency of the output clock.
In the following example, the incremental supply current is
calculated for V
= 5.5V, f = 34MHz, and C = 8pF:
CCO
C L
V = 5.5V - 3.6V = 1.9V
I
C = C
+ C = 6pF + 8pF = 14pF
L
T
INT
where:
I = C V 0.5F x 21 (data outputs) + C V f x 1 (clock
I
T I
C
T I C
output).
I = (14pF x 1.9V x 0.5 x 34MHz x 21) + (14pF x 1.9V x
I
34MHz).
I = 9.5mA + 0.9mA = 10.4mA.
I
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MAX9210/MAX9214/
MAX9220/MAX9222
Programmable DC-Balance
21-Bit Deserializers
Functional Diagram
Pin Configuration
DATA
CHANNEL 0
LVDS DATA
RECEIVER 0
TOP VIEW
RxOUT0–6
RxOUT7–13
RxOUT14–20
RxCLK OUT
RxIN0+
SERIAL-TO-
PARALLEL
CONVERTER
STROBE
RxOUT17
RxOUT18
GND
1
2
3
4
5
6
7
8
9
48 V
CCO
RxIN0-
47 RxOUT16
46 RxOUT15
45 RxOUT14
44 GND
DATA
CHANNEL 1
LVDS DATA
RECEIVER 1
RxOUT19
RxOUT20
DCB/NC
RxIN1+
SERIAL-TO-
PARALLEL
CONVERTER
STROBE
RxIN1-
43 RxOUT13
DATA
CHANNEL 2
LVDS DATA
RECEIVER 2
LVDS GND
RxIN0-
42 V
CC
RxIN2+
SERIAL-TO-
PARALLEL
CONVERTER
41 RxOUT12
40 RxOUT11
39 RxOUT10
38 GND
STROBE
RxIN2-
RxIN0+
MAX9210
MAX9214
MAX9220
MAX9222
RxIN1- 10
RxIN1+ 11
LVDS CLOCK
RECEIVER
RxCLK IN+
REFERENCE
CLOCK
GENERATOR
LVDS V
12
37 RxOUT9
7x/9x
PLL
CC
RxCLK IN-
LVDS GND 13
RxIN2- 14
36 V
CCO
35 RxOUT8
34 RxOUT7
33 RxOUT6
32 GND
DCB/NC
RxIN2+ 15
PWRDWN
RxCLK IN- 16
RxCLK IN+ 17
LVDS GND 18
PLL GND 19
31 RxOUT5
30 RxOUT4
29 RxOUT3
Chip Information
PROCESS: CMOS
PLL V
20
CC
PLL GND 21
PWRDWN 22
RxCLK OUT 23
RxOUT0 24
28
V
CCO
27 RxOUT2
26 RxOUT1
25 GND
TSSOP
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MAX9210/MAX9214/
MAX9220/MAX9222
Programmable DC-Balance
21-Bit Deserializers
Package Information
For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”,
“#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing
pertains to the package regardless of RoHS status.
PACKAGE TYPE
PACKAGE CODE
OUTLINE NO.
21-0155
LAND PATTERN NO.
90-0124
48 TSSOP
U48-1
Maxim Integrated
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MAX9210/MAX9214/
MAX9220/MAX9222
Programmable DC-Balance
21-Bit Deserializers
Revision History
REVISION REVISION
PAGES
CHANGED
DESCRIPTION
NUMBER
DATE
4
3/05
Various changes
—
Removed all references to MAX9212/MAX9216 and thin QFN-EP package; various
style edits; and updated package outline for TSSOP
5
6
11/07
5/14
1–17
1
Removed automotive references from the Applications section
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim Integrated’s website at www.maximintegrated.com.
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses
are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits)
shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
©
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.
2014 Maxim Integrated Products, Inc.
│ 17
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