MAX9122EUE+ [MAXIM]
Line Receiver, 4 Func, 4 Rcvr, CMOS, PDSO16, 4.40 MM, TSSOP-16;
| 型号： | MAX9122EUE+ |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Line Receiver, 4 Func, 4 Rcvr, CMOS, PDSO16, 4.40 MM, TSSOP-16 |
| 文件： | 总12页 (文件大小：232K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-1909; Rev 0; 6/01
Quad LVDS Line Receivers with
Integrated Termination and Flow-Through Pinout
General Description
____________________________Features
The MAX9121/MAX9122 quad low-voltage differential sig-
naling (LVDS) differential line receivers are ideal for appli-
cations requiring high data rates, low power, and low
noise. The MAX9121/MAX9122 are guaranteed to receive
data at speeds up to 500Mbps (250MHz) over controlled-
impedance media of approximately 100Ω. The transmis-
sion media may be printed circuit (PC) board traces or
cables.
ꢀ Integrated Termination Eliminates Four External
Resistors (MAX9122)
ꢀ Flow-Through Pinout
Simplifies PC Board Layout
Reduces Crosstalk
ꢀ Pin Compatible with DS90LV048A
ꢀ Guaranteed 500Mbps Data Rate
ꢀ 300ps Pulse Skew (max)
The MAX9121/MAX9122 accept four LVDS differential
inputs and translate them to LVCMOS outputs. The
MAX9122 features integrated parallel termination resis-
tors (nominally 107Ω), which eliminate the requirement
for four discrete termination resistors and reduce stub
lengths. The MAX9121 inputs are high impedance and
require an external termination resistor when used in a
point-to-point connection.
ꢀ Conform to ANSI TIA/EIA-644 LVDS Standard
ꢀ Single +3.3V Supply
ꢀ Fail-Safe Circuit
Ordering Information
The devices support a wide common-mode input range of
0.05V to 2.35V, allowing for ground potential differences
and common-mode noise between the driver and the
receiver. A fail-safe feature sets the output high when the
inputs are open, or when the inputs are undriven and
shorted or parallel terminated. The EN and EN inputs con-
trol the high-impedance output. The enables are common
to all four receivers. Inputs conform to the ANSI TIA/EIA-
644 LVDS standard. Flow-through pinout simplifies PC
board layout and reduces crosstalk by separating the
LVDS inputs and LVCMOS outputs. The MAX9121/
MAX9122 operate from a single +3.3V supply, and are
specified for operation from -40°C to +85°C. These
devices are available in 16-pin TSSOP and SO packages.
Refer to the MAX9123 data sheet for a quad LVDS line dri-
ver with flow-through pinout.
PART
TEMP. RANGE
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
PIN-PACKAGE
16 TSSOP
16 SO
16 TSSOP
16 SO
MAX9121EUE
MAX9121ESE
MAX9122EUE
MAX9122ESE
Pin Configuration appears at end of data sheet.
Typical Application Circuit
LVDS SIGNALS
T
T
T
T
107Ω
107Ω
107Ω
107Ω
R
R
R
R
X
X
X
X
X
X
X
X
Applications
Digital Copiers
Laser Printers
Cellular Phone Base Stations
Add/Drop Muxes
LVTTL/LVCMOS
DATA INPUT
LVTTL/LVCMOS
DATA OUTPUT
Digital Cross-Connects
DSLAMs
Network Switches/Routers
Backplane Interconnect
Clock Distribution
MAX9122
100Ω SHIELDED TWISTED CABLE OR MICROSTRIP PC BOARD TRACES
MAX9123
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
Quad LVDS Line Receivers with
Integrated Termination and Flow-Through Pinout
ABSOLUTE MAXIMUM RATINGS
CC
IN_+, IN_- to GND .................................................-0.3V to +4.0V
EN, EN to GND...........................................-0.3V to (V
V
to GND...........................................................-0.3V to +4.0V
Storage Temperature Range.............................-65°C to +150°C
Maximum Junction Temperature .....................................+150°C
Operating Temperature Range ...........................-40°C to +85°C
Lead Temperature (soldering, 10s) .................................+300°C
ESD Protection
+ 0.3V)
+ 0.3V)
CC
CC
OUT_ to GND .............................................-0.3V to (V
Continuous Power Dissipation (T = +70°C)
A
(Human Body Model, IN_+, IN_-) .................................... 8ꢀV
16-Pin TSSOP (derate 9.4mW/°C above +70°C) .........755mW
16-Pin SO (derate 8.7mW/°C above +70°C)................696mW
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(V
= +3.0V to +3.6V, differential input voltage |V | = 0.1V to 1.0V, common-mode voltage V
= |V /2| to 2.4V - |V /2|,
CC
ID
CM
ID
ID
T
A
= -40°C to +85°C. Typical values are at V = +3.3V, T = +25°C, unless otherwise noted.) (Note 1)
CC A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
LVDS INPUTS (IN_+, IN_-)
Differential Input High Threshold
Differential Input Low Threshold
V
100
mV
mV
µA
µA
µA
µA
ꢀΩ
ꢀΩ
TH
V
-100
-20
-25
-20
-25
35
TL
0.1V ≤V ≤ 0.6V
20
25
20
25
ID
Input Current (MAX9121)
I _+, I _-
IN IN
0.6V <V ≤ 1.0V
ID
0.1V ≤V ≤ 0.6V, V
= 0
= 0
ID
CC
Power-Off Input Current
(MAX9121)
I
INOFF
0.6V <V ≤ 1.0V, V
ID
CC
Input Resistor 1
Input Resistor 2
R
R
V
V
= 3.6V or 0, Figure 1
= 3.6V or 0, Figure 1
IN1
CC
CC
132
IN2
Differential Input Resistance
(MAX9122)
R
V
= 3.6V or 0, Figure 1
90
107
3.2
132
Ω
DIFF
CC
LVCMOS/LVTTL OUTPUTS (OUT_)
Open, undriven short, or
undriven 100Ω parallel
termination
2.7
I
= -4.0mA
OH
(MAX9121)
Output High Voltage (Table 1)
V
V
OH
V
= +100mV
2.7
2.7
2.7
3.2
3.2
3.2
0.1
ID
Open or undriven short
= +100mV
I
= -4.0mA
OH
(MAX9122)
V
ID
Output Low Voltage
V
I
= +4.0mA, V = -100mV
0.25
-120
+10
V
OL
OS
OZ
OL
ID
Output Short-Circuit Current
Output High-Impedance Current
I
I
Enabled, V = 0.1V, V
_ = 0 (Note 2)
OUT
-15
-10
mA
µA
ID
Disabled, V
= 0 or V
CC
OUT
2
_______________________________________________________________________________________
Quad LVDS Line Receivers with
Integrated Termination and Flow-Through Pinout
DC ELECTRICAL CHARACTERISTICS (continued)
(V
= +3.0V to +3.6V, differential input voltage |V | = 0.1V to 1.0V, common-mode voltage V
= |V /2| to 2.4V - |V /2|,
CC
ID
CM
ID
ID
T
A
= -40°C to +85°C. Typical values are at V = +3.3V, T = +25°C, unless otherwise noted.) (Note 1)
CC A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
LOGIC INPUTS (EN, EN)
Input High Voltage
Input Low Voltage
Input Current
V
2.0
0
V
V
V
IH
CC
V
0.8
15
IL
I
V
= V or 0
CC
-15
µA
IN
IN_
SUPPLY
Supply Current
I
Enabled, inputs open
Disabled, inputs open
9
15
mA
mA
CC
Disabled Supply Current
I
0.07
0.5
CCZ
AC ELECTRICAL CHARACTERISTICS
(V
= +3.0V to +3.6V, C = 15pF, differential input voltage |V | = 0.2V to 1.0V, common-mode voltage V
= |V /2| to 2.4V -
CM ID
CC
L
ID
|V /2|, input rise and fall time = 1ns (20% to 80%), input frequency = 100MHz, T = -40°C to +85°C. Typical values are at V
=
ID
A
CC
+3.3V, V
= 1.2V, |V | = 0.2V, T = +25°C, unless otherwise noted.) (Notes 3, 4)
CM
ID A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Differential Propagation Delay
High to Low
t
Figures 2 and 3
Figures 2 and 3
Figures 2 and 3
Figures 2 and 3
Figures 2 and 3
Figures 2 and 3
1.2
1.93
2.7
ns
PHLD
Differential Propagation Delay
Low to High
t
1.2
1.79
140
2.7
300
400
0.8
1.5
ns
ps
ps
ns
ns
PLHD
Differential Pulse Sꢀew [t
-
PHLD
t
t
t
t
SKD1
SKD2
SKD3
SKD4
t
] (Note 5)
PLHD
Differential Channel-to-Channel
Sꢀew (Note 6)
Differential Part-to-Part Sꢀew
(Note 7)
Differential Part-to-Part Sꢀew
(Note 8)
Rise-Time
t
t
Figures 2 and 3
Figures 2 and 3
0.55
0.54
1.0
1.0
14
14
70
70
ns
ns
ns
ns
ns
ns
TLH
THL
PHZ
Fall-Time
Disable Time High to Z
Disable Time Low to Z
Enable Time Z to High
Enable Time Z to Low
t
R = 2ꢀΩ, Figures 4 and 5
L
t
R = 2ꢀΩ, Figures 4 and 5
L
PLZ
PZH
t
R = 2ꢀΩ, Figures 4 and 5
L
t
R = 2ꢀΩ, Figures 4 and 5
L
PZL
Maximum Operating Frequency
(Note 9)
f
All channels switching
250
300
MHz
MAX
_______________________________________________________________________________________
3
Quad LVDS Line Receivers with
Integrated Termination and Flow-Through Pinout
AC ELECTRICAL CHARACTERISTICS (continued)
(V
= +3.0V to +3.6V, C = 15pF, differential input voltage |V | = 0.2V to 1.0V, common-mode voltage V
= |V /2| to 2.4V -
CM ID
CC
L
ID
|V /2|, input rise and fall time = 1ns (20% to 80%), input frequency = 100MHz, T = -40°C to +85°C. Typical values are at V
=
ID
A
CC
+3.3V, V
= 1.2V, |V | = 0.2V, T = +25°C, unless otherwise noted.) (Notes 3, 4)
CM
ID A
Note 1: Current into a pin is defined as positive. Current out of a pin is defined as negative. All voltages are referenced to ground
except V , V , and V
.
ID
TH TL
Note 2: Short only one output at a time. Do not exceed the absolute maximum junction temperature specification.
Note 3: AC parameters are guaranteed by design and characterization.
Note 4: C includes scope probe and test jig capacitance.
L
Note 5: t
Note 6: t
Note 7: t
is the magnitude difference of differential propagation delays in a channel. t
= |t
- t
|.
SKD1
SKD2
SKD3
SKD1
PHLD PLHD
is the magnitude difference of the t
or t
of one channel and the t
or t
of any other channel on the same part.
PLHD
PHLD
PLHD
PHLD
is the magnitude difference of any differential propagation delays between parts operating over rated conditions at
and within 5°C of each other.
the same V
CC
Note 8: t
Note 9: f
is the magnitude difference of any differential propagation delays between parts operating over rated conditions.
SKD4
MAX
generator output conditions: rise-time = fall-time = 1ns (0% to 100%), 50% duty cycle, V
= +1.3V, V = +1.1V,
OH
OL
MAX9121/MAX9122 output criteria: 60% to 40% duty cycle, V = 0.4V (max), V
= 2.7V (min), load = 15pF.
OL
OH
Typical Operating Characteristics
(V
= +3.3V, V
= +1.2V, |V | = 0.2V, C = 15pF, T = +25°C, unless otherwise noted.) (Figures 2 and 3)
CM ID L A
CC
SUPPLY CURRENT
vs. FREQUENCY
SUPPLY CURRENT vs.
TEMPERATURE
DIFFERENTIAL THRESHOLD VOLTAGE
vs. SUPPLY VOLTAGE
40
30
11.00
10.50
10.00
9.50
9.00
8.50
8.00
7.50
7.00
50
40
30
20
10
0
ALL
CHANNELS
SWITCHING
20
10
ONE
SWITCHING
0
0.01
0.1
1
10
100
1000
-40
-15
10
35
60
85
3.0
3.3
3.6
FREQUENCY (MHz)
TEMPERATURE (°C)
SUPPLY VOLTAGE (V)
OUTPUT HIGH-IMPEDANCE CURRENT
vs. SUPPLY VOLTAGE
OUTPUT SHORT-CIRCUIT CURRENT
vs. SUPPLY VOLTAGE
OUTPUT HIGH VOLTAGE vs.
SUPPLY VOLTAGE
-95
-90
-85
-80
-75
-70
-65
1.30
1.25
1.20
1.15
1.10
3.7
3.5
3.3
3.1
2.9
2.7
3.0
3.3
3.6
3.0
3.3
3.6
3.0
3.3
3.6
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
4
_______________________________________________________________________________________
Quad LVDS Line Receivers with
Integrated Termination and Flow-Through Pinout
Typical Operating Characteristics (continued)
(V
= +3.3V, V
= +1.2V, |V | = 0.2V, C = 15pF, T = +25°C, unless otherwise noted.) (Figures 2 and 3)
CC
CM
ID
L
A
OUTPUT LOW VOLTAGE
vs. SUPPLY VOLTAGE
DIFFERENTIAL PROPAGATION DELAY
vs. SUPPLY VOLTAGE
DIFFERENTIAL PROPAGATION DELAY
vs. TEMPERATURE
100
2.20
2.10
2.00
1.90
1.80
1.70
1.60
99
98
97
96
95
94
93
92
2.10
1.90
1.70
1.50
t
PHLD
t
PHLD
t
PLHD
t
PLHD
3.0
3.3
3.6
3.0
3.3
SUPPLY VOLTAGE (V)
3.6
-40
-15
10
35
60
85
SUPPLY VOLTAGE (V)
TEMPERATURE (°C)
DIFFERENTIAL PROPAGATION DELAY
vs. DIFFERENTIAL INPUT VOLTAGE
DIFFERENTIAL PULSE SKEW vs.
SUPPLY VOLTAGE
DIFFERENTIAL PROPAGATION DELAY
vs. COMMON-MODE VOLTAGE
2.2
2.1
2.0
1.9
1.8
1.7
1.6
1.5
200
175
150
125
100
2.50
2.25
2.00
1.75
1.50
1.25
t
PHLD
t
PHLD
t
PLHD
t
PLHD
100
900
1700
2500
3.0
3.3
3.6
-0.5
0
0.5
1.0
1.5
2.0
2.5
DIFFERENTIAL INPUT VOLTAGE (mV)
SUPPLY VOLTAGE (V)
COMMON-MODE VOLTAGE (V)
TRANSITION TIME vs.
SUPPLY VOLTAGE
TRANSITION TIME vs.
TEMPERATURE
650
600
575
550
525
500
625
600
575
550
525
500
475
450
t
TLH
t
TLH
t
t
THL
THL
3.0
3.3
SUPPLY VOLTAGE (V)
3.6
-40
-15
10
35
60
85
TEMPERATURE (°C)
_______________________________________________________________________________________
5
Quad LVDS Line Receivers with
Integrated Termination and Flow-Through Pinout
Pin Description
PIN
NAME
IN_-
FUNCTION
1, 4, 5, 8
2, 3, 6, 7
Inverting Differential Receiver Inputs
IN_+
Noninverting Differential Receiver Inputs
Receiver Enable Inputs. When EN = high and EN = low or open, the outputs are active. For
other combinations of EN and EN, the outputs are disabled and in high impedance.
9, 16
EN, EN
10, 11, 14, 15
OUT_
GND
LVCMOS/LVTTL Receiver Outputs
Ground
12
13
V
Power-Supply Input. Bypass V
to GND with 0.1µF and 0.001µF ceramic capacitors.
CC
CC
Table 1. Input/Output Function Table
ENABLES
INPUTS
(IN_+) - (IN_-)
OUTPUT
EN
EN
OUT_
V
≥ +100mV
≤ -100mV
H
L
ID
V
ID
H
L or open
Open, undriven short, or undriven
100Ω parallel termination
MAX9121
MAX9122
H
Z
Open or undriven short
All other combinations of ENABLE pins
Don’t care
ences of the transmitter and the receiver, the common-
mode effects of coupled noise, or both. The LVDS stan-
dards specify an input voltage range of 0 to +2.4V
referenced to receiver ground.
Detailed Description
The LVDS interface standard is a signaling method
intended for point-to-point communication over a con-
trolled-impedance medium as defined by the ANSI
TIA/EIA-644 and IEEE 1596.3 standards. The LVDS stan-
dard uses a lower voltage swing than other common
communication standards, achieving higher data rates
with reduced power consumption while reducing EMI
emissions and system susceptibility to noise.
The MAX9122 has an integrated termination resistor
that is internally connected across each receiver input.
The internal termination saves board space, eases lay-
out, and reduces stub length compared to an external
termination resistor. In other words, the transmission
line is terminated on the IC.
The MAX9121/MAX9122 are 500Mbps, four-channel
LVDS receivers intended for high-speed, point-to-point,
low-power applications. Each channel accepts an
LVDS input and translates it to an LVTTL/LVCMOS out-
put. The receiver is capable of detecting differential
signals as low as 100mV and as high as 1V within an
input voltage range of 0 to 2.4V. The 250mV to 400mV
differential output of an LVDS driver is nominally cen-
tered around a +1.2V offset. This offset, coupled with
the receiver’s 0 to 2.4V input voltage range, allows an
approximate 1V shift in the signal (as seen by the
receiver). This allows for a difference in ground refer-
Fail-Safe
The fail-safe feature of the MAX9121/MAX9122 sets an
output high when:
• Inputs are open.
• Inputs are undriven and shorted.
• Inputs are undriven and terminated.
A fail-safe circuit is important because under these
conditions, noise at the inputs may switch the receiver
and it may appear to the system that data is being
6
_______________________________________________________________________________________
Quad LVDS Line Receivers with
Integrated Termination and Flow-Through Pinout
V
CC
V
CC
R
IN2
R
IN2
V
CC
- 0.3V
V
CC
- 0.3V
IN_+
IN_-
IN_+
R
R
R
R
IN1
IN1
OUT_
OUT_
R
DIFF
IN1
IN1
IN_-
MAX9121
MAX9122
Figure 1. Input with Fail-Safe Network
received. Open or undriven terminated input conditions
can occur when a cable is disconnected or cut, or
when the LVDS driver outputs are high impedance. A
short condition can occur because of a cable failure.
close to the device as possible, with the smaller valued
capacitor closest to V
.
CC
Differential Traces
Input trace characteristics affect the performance of the
MAX9121/MAX9122. Use controlled-impedance PC
board traces to match the cable characteristic imped-
ance. The termination resistor is also matched to this
characteristic impedance.
The fail-safe input networꢀ (Figure 1) samples the input
common-mode voltage and compares it to V
- 0.3V
CC
(nominal). When the input is driven to levels specified in
the LVDS standards, the input to the common-mode
voltage is less than V
- 0.3V and the fail-safe circuit
CC
Eliminate reflections and ensure that noise couples as
common mode by running the differential traces close
together. Reduce sꢀew by matching the electrical
length of the traces. Excessive sꢀew can result in a
degradation of magnetic field cancellation.
is not activated. If the inputs are open or if the inputs
are undriven and shorted or undriven and parallel ter-
minated, there is no input current. In this case, a pullup
resistor in the fail-safe circuit pulls both inputs above
V
- 0.3V, activating the fail-safe circuit and forcing
CC
the output high.
Each channel’s differential signals should be routed
close to each other to cancel their external magnetic
field. Maintain a constant distance between the differ-
ential traces to avoid discontinuities in differential
impedance. Avoid 90° turns and minimize the number
of vias to further prevent impedance discontinuities.
Applications Information
Power-Supply Bypassing
Bypass the V
pin with high-frequency surface-mount
CC
ceramic 0.1µF and 0.001µF capacitors in parallel as
_______________________________________________________________________________________
7
Quad LVDS Line Receivers with
Integrated Termination and Flow-Through Pinout
IN_+
PULSE
GENERATOR**
OUT_
C
L
IN_-
50Ω*
50Ω*
RECEIVER ENABLED
1/4 MAX9121/MAX9122
*50Ω REQUIRED FOR PULSE GENERATOR.
**WHEN TESTING THE MAX9122, ADJUST THE
PULSE GENERATOR OUTPUT TO ACCOUNT
FOR INTERNAL TERMINATION RESISTOR.
Figure 2. Propagation Delay and Transition Time Test Circuit
IN_-
IN_+
V
ID
= 0
V
ID
V
ID
= 0
t
t
PLHD
PHLD
V
V
OH
80%
50%
80%
V
= (V ) - (V
)
ID
IN_+
IN_-
NOTE: V = (V + V )
IN+
CM
IN-
2
50%
20%
20%
OUT_
OL
t
t
THL
TLH
Figure 3. Propagation Delay and Transition Time Waveforms
value of the integrated resistor is specified in the DC
characteristics.
Cables and Connectors
Transmission media typically have a controlled differen-
tial impedance of 100Ω. Use cables and connectors
that have matched differential impedance to minimize
impedance discontinuities.
The MAX9121 requires an external termination resistor.
The termination resistor should match the differential
impedance of the transmission line. Termination resis-
tance values may range between 90Ω to 132Ω,
depending on the characteristic impedance of the
transmission medium.
Avoid the use of unbalanced cables such as ribbon or
simple coaxial cable. Balanced cables such as twisted
pair offer superior signal quality and tend to generate
less EMI due to magnetic field canceling effects.
Balanced cables picꢀ up noise as common mode,
which is rejected by the LVDS receiver.
When using the MAX9121, minimize the distance
between the input termination resistors and the
MAX9121 receiver inputs. Use 1% surface-mount resis-
tors.
Termination
The MAX9122 has an integrated termination resistor
connected across the inputs of each receiver. The
8
_______________________________________________________________________________________
Quad LVDS Line Receivers with
Integrated Termination and Flow-Through Pinout
V
CC
S
1
R
L
IN_+
IN_-
DEVICE
UNDER
TEST
OUT_
GENERATOR
EN
EN
C
L
50Ω
1/4 MAX9121/MAX9122
C INCLUDES LOAD AND TEST JIG CAPACITANCE.
L
S = V FOR t AND t MEASUREMENTS.
1
CC
PZL
PLZ
S = GND FOR t AND t MEASUREMENTS.
1
PZH
PHZ
Figure 4. High-Impedance Delay Test Circuit
EN WHEN EN = GND OR OPEN
3V
0
1.5V
1.5V
1.5V
3V
0
1.5V
EN WHEN EN = V
CC
t
PZL
V
CC
t
t
PLZ
50%
OUTPUT WHEN
= -100mV
0.5V
V
V
OL
V
ID
t
PZH
PHZ
OUTPUT WHEN
= +100mV
OH
0.5V
V
ID
50%
GND
Figure 5. High-Impedance Delay Waveforms
Board Layout
Because the MAX9121/MAX9122 feature a flow-through
pinout, no special layout precautions are required.
Keep the LVDS and any other digital signals separated
from each other to reduce crosstalꢀ.
Chip Information
TRANSISTOR COUNT: 1354
PROCESS: CMOS
For LVDS applications, a four-layer PC board that pro-
vides separate power, ground, LVDS signals, and input
signals is recommended. Isolate the input LVDS signals
from each other to prevent coupling. Isolate the output
LVCMOS/LVTTL signals from each other to prevent
coupling. Separate the input LVDS signals from the out-
put signals planes with the power and ground planes
for best results.
_______________________________________________________________________________________
9
Quad LVDS Line Receivers with
Integrated Termination and Flow-Through Pinout
Functional Diagram
V
CC
V
CC
IN1+
IN1+
OUT1
OUT2
OUT3
OUT4
OUT1
OUT2
OUT3
OUT4
107Ω
107Ω
107Ω
107Ω
IN1-
IN2+
IN1-
IN2+
IN2-
IN3+
IN2-
IN3+
IN3-
IN4+
IN3-
IN4+
IN4-
IN4-
EN
EN
EN
EN
MAX9121
MAX9122
GND
GND
Pin Configuration
TOP VIEW
IN1-
IN1+
IN2+
IN2-
IN3-
IN3+
IN4+
IN4-
1
2
3
4
5
6
7
8
16 EN
15 OUT1
14 OUT2
MAX9121
MAX9122
13 V
CC
12 GND
11 OUT3
10 OUT4
9
EN
TSSOP/SO
10 ______________________________________________________________________________________
Quad LVDS Line Receivers with
Integrated Termination and Flow-Through Pinout
Package Information
______________________________________________________________________________________ 11
Quad LVDS Line Receivers with
Integrated Termination and Flow-Through Pinout
Package Information (continued)
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
12 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2001 Maxim Integrated Products
Printed USA
is a registered trademarꢀ of Maxim Integrated Products.
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