MAX8819 [MAXIM]
PMIC with Integrated Chargers and Smart Power Selector in a 4mm x 4mm TQFN;
| 型号： | MAX8819 |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | PMIC with Integrated Chargers and Smart Power Selector in a 4mm x 4mm TQFN 集成电源管理电路 |
| 文件： | 总29页 (文件大小：485K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-4166; Rev 1; 4/09
PMIC with Integrated Chargers and Smart
Power Selector in a 4mm x 4mm TQFN
B/MAX819C
General Description
Features
♦ Smart Power Selector
The MAX8819_ is a complete power solution for MP3
players and other handheld applications. The IC
includes a battery charger, step-down converters, and
WLED power. It features an input current-limit switch to
power the IC from an AC-to-DC adapter or USB port, a
1-cell lithium ion (Li+) or lithium polymer (Li-Poly) charg-
er, three step-down converters, and a step-up converter
with serial step dimming for powering two to six white
LEDs. All power switches for charging and switching the
system load between battery and external power are
included on-chip. No external MOSFETs are required.
The MAX8819C offers a sequenced power-up/power-
down of OUT1, OUT2, and then OUT3.
♦ Operates with No Battery Present
♦ USB/AC Adapter One-Cell Li+ Charger
♦ Three 2MHz Step-Down Converters
95% Peak Efficiency
100% Duty Cycle
±±% Output Accuracy over Load/Line/
Temperature
♦ 2 to 6 Series WLED Driver with Dimming Control
♦ Active-Low REG1 Reset Output
♦ Short-Circuit/Thermal-Overload/Input
Undervoltage/Overvoltage Protection
Maxim’s Smart Power Selector™ makes the best use of
AC-to-DC adapter power or limited USB power. Battery
charge current and input current limit are independent-
ly set. Input power not used by the system charges the
battery. Charge current is resistor programmable and
the input current limit can be selected as 100mA,
500mA, or 1A. Automatic input selection switches the
system load from battery to external power. In addition,
on-chip thermal limiting reduces the battery charge rate
to prevent charger overheating.
♦ Power-Up/Down Sequencing (MAX8819C)
♦ Total Solution Size: Less Than 90mm2
Typical Operating Circuit
USB/AC-TO-DC
ADAPTER
SYS
BAT
DC
Applications
DLIM1
DLIM2
MP3 Players
Portable GPS Devices
Low-Power Handheld Products
Cellular Telephones
Digital Cameras
+
Li+/Li-Poly
BATTERY
ENABLE SYSTEM
ENABLE CHARGER
ENABLE BACKLIGHT
EN123
CEN
OUT1
I/O
LX1
EN4
LX4
Handheld Instrumentation
PDAs
MAX8819_
SYS
OVP4
OUT2
MEMORY
LX2
LX3
Ordering Information
SYS
VOLTAGE
(V)
OUT3
CORE
PIN-
PACKAGE
PART
TEMP RANGE
CISET
CHG
MAX8819AETI+ -40°C to +85°C 28 TQFN-EP*
MAX8819BETI+ -40°C to +85°C 28 TQFN-EP*
MAX8819CETI+ -40°C to +85°C 28 TQFN-EP*
4.35
5.3
CHG
FB4
4.35
RST1
RST1
+Denotes a lead(Pb)-free/RoHS-compliant package.
*EP = Exposed pad.
Smart Power Selector is a trademark of Maxim Integrated
Products, Inc.
Pin Configuration appears at end of data sheet.
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
PMIC with Integrated Chargers and Smart
Power Selector in a 4mm x 4mm TQFN
ABSOLUTE MAXIMUM RATINGS
DC, SYS, BAT, CISET, DLIM1, DLIM2, EN123
Continuous Power Dissipation (T = +70°C)
A
CEN, EN4, CHG, RST1, FB1, FB2, FB3 to GND....-0.3V to +6V
28-Pin Thin QFN Single-Layer Board (derate 20.8mW/°C
above +70°C)...........................................................1666.7mW
28-Pin Thin QFN Multilayer Board (derate 28.6mW/°C
above +70°C)...........................................................2285.7mW
PV2 to GND...............................................-0.3V to (V
+ 0.3V)
SYS
PV13 to SYS...........................................................-0.3V to +0.3V
PG1, PG2, PG3, PG4 to GND................................-0.3V to +0.3V
COMP4, FB4 to GND ................................-0.3V to (V
+ 0.3V)
Junction-to-Case Thermal Resistance (θ ) (Note 2)
SYS
JC
LX4 to PG4 .............................................................-0.3V to +33V
OVP4 to GND .........................................................-0.3V to +33V
LX1, LX2, LX3 Continuous Current (Note 1) .........................1.5A
LX4 Current ................................................................750mA
Output Short-Circuit Duration.....................................Continuous
28-Lead Thin QFN...........................................................3°C/W
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature........................................-40°C to +125°C
Storage Temperature.........................................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
RMS
Note 1: LX1, LX2, LX3 have clamp diodes to their respective PG_ and PV_. Applications that forward bias these diodes must take
care not to exceed the package power dissipation limits.
Note 2: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer
board. For detailed information on package thermal considerations, refer to http://www.maxim-ic.com/thermal-tutorial.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(DC, LX_ unconnected; V = V
= 0V, V
= 4V, DLIM[1:2] = 00, EN123 = EN4 = low, V
= V
= V
= 1.1V, V = 0.6V,
FB4
EP
GND
BAT
FB1
FB2
FB3
PV13 = PV2 = SYS, T = -40°C to +85°C, capacitors as shown in Figure 1, R
= 3kΩ, unless otherwise noted.) (Note 3)
A
CISET
PARAMETER
DC POWER INPUT
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DC Voltage Range
V
4.1
4.3
5.5
4.4
V
V
DC
MAX8819A/MAX8819C
MAX8819B
4.35
5.3
SYS Regulation Voltage
V
V
= 5.75V
SYS_REG
DC
DC
5.1
5.5
DC Undervoltage Threshold
DC Overvoltage Threshold
V
V
V
V
V
rising, 500mV typical hysteresis
rising, 300mV typical hysteresis
3.95
5.811
90
4.00
5.9
4.05
6.000
100
V
V
UVLO_DC
OVLO_DC
DC
DC
B/MAX819C
= 5.75V, V
= 5V
SYS
DLIM[1:2] = 10
DLIM[1:2] = 01
DLIM[1:2] = 00
95
DC Current Limit
(Note 4)
for MAX8819B or V
4V for MAX8819A/
MAX8819C
=
SYS
I
450
900
475
1000
0.02
500
mA
DCLIM
1100
0.035
DLIM[1:2] = 11 (suspend)
DLIM[1:2] ≠ 11, I = 0mA, I
= 0mA,
BAT
SYS
EN123 = low, EN4 = low, CEN = high,
= 5.5V
1.33
DC Quiescent Current
I
DCIQ
mA
V
DC
DLIM[1:2] ≠ 11, I
EN4 = low, CEN = low, V = 5.5V
= 0mA, EN123 = low,
SYS
0.95
DC
DC-to-SYS Dropout Resistance
DC-to-SYS Soft-Start Time
R
V
= 4V, I = 400mA, DLIM[1:2] = 01
SYS
0.330
1.5
0.700
Ω
DS
DC
t
ms
SS-D-S
Die temperature where current limit is
reduced
DC Thermal-Limit Temperature
DC Thermal-Limit Gain
100
5
°C
Amount of input current reduction above
thermal-limit temperature
%/°C
SYSTEM
System Operating Voltage Range
V
2.6
5.5
V
SYS
2
_______________________________________________________________________________________
PMIC with Integrated Chargers and Smart
Power Selector in a 4mm x 4mm TQFN
B/MAX819C
ELECTRICAL CHARACTERISTICS (continued)
(DC, LX_ unconnected; V = V
= 0V, V
= 4V, DLIM[1:2] = 00, EN123 = EN4 = low, V
= V
= V
= 1.1V, V = 0.6V,
FB4
EP
GND
BAT
FB1
FB2
FB3
PV13 = PV2 = SYS, T = -40°C to +85°C, capacitors as shown in Figure 1, R
= 3kΩ, unless otherwise noted.) (Note 3)
A
CISET
PARAMETER
SYMBOL
CONDITIONS
falling, 100mV hysteresis
SYS
MIN
TYP
MAX
UNITS
System Undervoltage Lockout
Threshold
V
V
2.45
2.5
2.55
V
UVLO_SYS
DC and BAT are delivering current to SYS;
= 95mA; V = 4.3V,
MAX8819A/MAX8819C (only)
BAT-to-SYS Reverse Regulation
Voltage
V
I
50
66
90
mV
BSREG
BAT
DC
V
V
= 0V, EN123 = low, EN4 = low,
DC
10
0
20
10
= 4V
BAT
V
= 5V, DLIM[1:2] ≠ 11, EN123 = low,
DC
EN4 = low, V
= 4V
BAT
I
+
+
PV2
SYS
V
V
= 0V, EN123 = high, EN4 = low,
DC
Quiescent Current
μA
I
PV13
= 4V (step-down converters are not in
128
362
290
730
BAT
I
dropout)
V
V
= 0V, EN123 = high, EN4 = high,
DC
= 4V (step-down converters are not in
BAT
dropout)
BATTERY CHARGER (V
= 5.0V)
DC
BAT-to-SYS On-Resistance
R
V
= 0V, V
= 4.2V, I = 0.9A
SYS
0.073
4.200
4.200
-100
3.0
0.165
4.221
4.242
-65
Ω
BS
DC
BAT
T
T
= +25°C
4.174
4.158
-135
2.9
A
A
BAT Regulation Voltage
(Figure 2)
V
V
V
BATREG
= -40°C to +85°C
BAT Recharge Threshold
(Note 4)
rising, 180mV hysteresis, Figure 2
mV
V
BAT Prequalification Threshold
V
3.1
BATPRQ
BAT
Guaranteed by BAT fast-charge current
limit
R
Resistance Range
3
15
kΩ
CISET
CISET Voltage
V
R
= 7.5kΩ, I = 267mA
BAT
0.9
87
1.0
92
1.1
100
500
230
425
860
105
105
V
CISET
CISET
DLIM[1:2] = 10, R
DLIM[1:2] = 01, R
DLIM[1:2] = 00, R
DLIM[1:2] = 00, R
DLIM[1:2] = 00, R
= 3kΩ
CISET
CISET
CISET
CISET
CISET
= 3kΩ
450
170
375
740
60
472
200
400
802
82
BAT Fast-Charge Current Limit
I
= 15kΩ
= 7.5kΩ
= 3.74kΩ
mA
CHGMAX
BAT Prequalification Current
Top-Off Threshold (Note 5)
I
V
= 2.5V, R
= 3.74kΩ
mA
mA
PREQUAL
BAT
CISET
CISET
I
T
= +25°C, R
A
= 3.74kΩ
60
82
TOPOFF
V
= 0V, EN123 = low, EN4 = low,
DC
10
0
20
CEN = low, V
= 4V
BAT
BAT Leakage Current
μA
V
= 5V, DLIM[1:2] = 11, EN123 = low,
DC
EN4 = low, V
= 4V
BAT
_______________________________________________________________________________________
±
PMIC with Integrated Chargers and Smart
Power Selector in a 4mm x 4mm TQFN
ELECTRICAL CHARACTERISTICS (continued)
(DC, LX_ unconnected; V = V
= 0V, V
= 4V, DLIM[1:2] = 00, EN123 = EN4 = low, V
= V
= V
= 1.1V, V = 0.6V,
FB4
EP
GND
BAT
FB1
FB2
FB3
PV13 = PV2 = SYS, T = -40°C to +85°C, capacitors as shown in Figure 1, R
= 3kΩ, unless otherwise noted.) (Note 3)
A
CISET
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
333
1.5
MAX
UNITS
Slew rate
mA/ms
Time from 0 to 500mA
Time from 0 to 100mA
Charger Soft-Start Time
t
SS_CHG
0.3
ms
Time from 100mA to 500mA
1.2
Timer Accuracy
+15
350
%
CISET voltage when the fast-charge timer
suspends; 300mV translates to 20% of the
maximum fast-charge current limit
Timer Suspend Threshold
250
700
300
750
mV
CISET voltage when the fast-charge timer
extends; 750mV translates to 50% of the
maximum fast-charge current limit
Timer Extend Threshold
800
mV
Prequalification Time
Fast-Charge Time
Top-Off Time
t
33
660
33
min
min
min
PREQUAL
t
FSTCHG
t
TOPOFF
POWER SEQUENCING (Figures 6 and 7)
REG1, REG2, REG3 Soft-Start
Time
t
, t
SS3
,
SS1 SS2
2.6
5
ms
ms
t
t
REG4 Soft-Start Time
C
= 0.022μF to GND
COMP4
SS4
REGULATOR THERMAL SHUTDOWN
Thermal Shutdown Temperature
Thermal Shutdown Hysteresis
T rising
J
+165
15
°C
°C
REG1–SYNCHRONOUS STEP-DOWN CONVERTER
Input Voltage
PV13 supplied from SYS
V
V
SYS
B/MAX819C
L = 4.7μH,
= 0.13Ω
(Note 6)
MAX8819A/MAX8819B
MAX8819C
400
550
Maximum Output Current
mA
R
LSR
Short-Circuit Current
L = 4.7μH, R
= 0.13Ω
600
230
mA
mV
Hz
V
LSR
Short-Circuit Detection Threshold
Short-Circuit Foldback Frequency
FB1 Voltage
f
/3
OSC
(Note 7)
0.997
1
1.01
1.028
Output Voltage Range
V
V
SYS
T
= +25°C
-50
-5
-10
1
+50
A
A
FB1 Leakage Current
V
= 1.01V
nA
FB1
T
= +85°C
Load Regulation
I
= 100mA to 300mA
%
OUT1
Line Regulation
(Note 9)
1
%/D
mΩ
mΩ
p-Channel On-Resistance
n-Channel On-Resistance
V
V
= 4.0V, I
= 4.0V, I
= 180mA
= 180mA
190
250
PV13
PV13
LX1
LX1
MAX8819A/MAX8819B
MAX8819C
0.565
0.615
0.600
0.650
0.640
0.750
p-Channel Current-Limit
Threshold
A
4
_______________________________________________________________________________________
PMIC with Integrated Chargers and Smart
Power Selector in a 4mm x 4mm TQFN
B/MAX819C
ELECTRICAL CHARACTERISTICS (continued)
(DC, LX_ unconnected; V = V
= 0V, V
= 4V, DLIM[1:2] = 00, EN123 = EN4 = low, V
= V
= V
= 1.1V, V = 0.6V,
FB4
EP
GND
BAT
FB1
FB2
FB3
PV13 = PV2 = SYS, T = -40°C to +85°C, capacitors as shown in Figure 1, R
= 3kΩ, unless otherwise noted.) (Note 3)
A
CISET
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Skip-Mode Transition Current
(Note 8)
80
mA
n-Channel Zero-Crossing
Threshold
10
mA
Maximum Duty Cycle
Minimum Duty Cycle
PWM Frequency
100
1.8
%
%
12.5
2.0
f
2.2
MHz
OSC
Internal Discharge Resistance in
Shutdown
EN123 = low, resistance from LX1 to PG1
1.0
kΩ
REG2–SYNCHRONOUS STEP-DOWN CONVERTER
Input Voltage
PV2 supplied from SYS
L = 4.7μH,
= 0.13Ω
V
V
SYS
MAX8819A/MAX8819B
MAX8819C
300
500
R
Maximum Output Current
mA
LSR
(Note 6)
Short-Circuit Current
L = 4.7μH, R
= 0.13Ω
600
230
mA
mV
Hz
V
LSR
Short-Circuit Detection Threshold
Short-Circuit Foldback Frequency
FB2 Voltage
f
/3
OSC
(Note 7)
0.997
1
1.012
1.028
Output Voltage Range
V
V
SYS
T
= +25°C
-50
-5
-50
1
+50
A
A
FB2 Leakage Current
V
= 1.01V
nA
FB2
T
= +85°C
Load Regulation
I
= 100mA to 300mA
%
OUT2
Line Regulation
(Note 9)
1
%/D
mΩ
mΩ
p-Channel On-Resistance
n-Channel On-Resistance
V
V
= 4.0V, I
= 4.0V, I
= 180mA
= 180mA
290
200
0.550
0.600
80
PV2
PV2
LX2
LX2
MAX8819A/MAX8819B
MAX8819C
0.512
0.565
0.595
0.700
p-Channel Current-Limit
Threshold
A
Skip-Mode Transition Current
(Note 8)
mA
mA
n-Channel Zero-Crossing
Threshold
10
Maximum Duty Cycle
Minimum Duty Cycle
PWM Frequency
100
1.8
%
%
12.5
2.0
f
2.2
MHz
OSC
Internal Discharge Resistance in
Shutdown
EN123 = low, resistance from LX2 to PG2
1.0
-25
kΩ
REG2 Disable
ΔI
V
= 0V, REG2 disabled (Note 10)
PV2
μA
SYS
REG±–SYNCHRONOUS STEP-DOWN CONVERTER
Input Voltage PV13 supplied from SYS
V
V
SYS
_______________________________________________________________________________________
5
PMIC with Integrated Chargers and Smart
Power Selector in a 4mm x 4mm TQFN
ELECTRICAL CHARACTERISTICS (continued)
(DC, LX_ unconnected; V = V
= 0V, V
= 4V, DLIM[1:2] = 00, EN123 = EN4 = low, V
= V
= V
= 1.1V, V
= 0.6V,
UNITS
mA
EP
GND
BAT
FB1
FB2
FB3
FB4
PV13 = PV2 = SYS, T = -40°C to +85°C, capacitors as shown in Figure 1, R
= 3kΩ, unless otherwise noted.) (Note 3)
A
CISET
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
L = 4.7μH,
= 0.13Ω
(Note 6)
MAX8819A/MAX8819B
MAX8819C
300
R
Maximum Output Current
LSR
500
Short-Circuit Current
L = 4.7μH, R
= 0.13Ω
600
230
mA
mV
Hz
V
LSR
Short-Circuit Detection Threshold
Short-Circuit Foldback Frequency
FB3 Voltage
f
/3
OSC
(Note 7)
0.997
1
1.01
1.028
Output Voltage Range
V
V
SYS
T
= +25°C
-50
-5
-50
1.3
1
+50
A
A
FB3 Leakage Current
V
= 1.01V
nA
FB3
T
= +85°C
Load Regulation
Line Regulation
I
= 100mA to 300mA
%
OUT3
(Note 9)
%/D
MAX8819A/MAX8819B
MAX8819C
0.512
0.565
0.550
0.600
80
0.595
0.700
p-Channel Current-Limit
Threshold
A
Skip-Mode Transition Current
(Note 8)
mA
mA
n-Channel Zero-Crossing
Threshold
10
p-Channel On-Resistance
n-Channel On-Resistance
Maximum Duty Cycle
Minimum Duty Cycle
PWM Frequency
V
V
= 4.0V, I
= 4.0V, I
= 180mA
= 180mA
290
120
mΩ
mΩ
%
PV13
PV13
LX3
LX3
100
1.8
12.5
2.0
%
f
2.2
MHz
OSC
Internal Discharge Resistance in
Shutdown
B/MAX819C
EN123 = low, resistance from LX3 to PG3
Power supplied from SYS (see Figure 1)
1.0
kΩ
REG4–STEP-UP CONVERTER
Input Voltage
2.4
5.5
24
V
V
Output Voltage Range
FB4 Regulation Voltage
FB4 Leakage
V
V
SYS
OUT4
V
No dimming
475
500
525
mV
μA
MHz
%
FB4
REG4 disabled (EN4 = low)
-0.050 +0.005 +0.050
Switching Frequency
Minimum Duty Cycle
Maximum Duty Cycle
OVP4 Overvoltage Detection
0.9
1
5
1.1
90
24
94
25
4
%
V
26
+1
V
OVP
OVP4 Input Current
OVP4 = SYS, EN4 = high
μA
REG4 disabled (EN4 = low),
OVP4 = SYS
OVP4 Leakage Current
-1
+0.001
μA
n-Channel On-Resistance
n-Channel Off-Leakage Current
n-Channel Current Limit
V
V
= 4.0V, I
= 200mA
LX4
395
+0.001
695
mΩ
μA
SYS
LX4
= 28V
-1
+1
555
950
mA
6
_______________________________________________________________________________________
PMIC with Integrated Chargers and Smart
Power Selector in a 4mm x 4mm TQFN
B/MAX819C
ELECTRICAL CHARACTERISTICS (continued)
(DC, LX_ unconnected; V = V
= 0V, V
= 4V, DLIM[1:2] = 00, EN123 = EN4 = low, V
= V
= V
= 1.1V, V = 0.6V,
FB4
EP
GND
BAT
FB1
FB2
FB3
PV13 = PV2 = SYS, T = -40°C to +85°C, capacitors as shown in Figure 1, R
= 3kΩ, unless otherwise noted.) (Note 3)
A
CISET
PARAMETER
LED DIMMING CONTROL (EN4)
EN4 Low Shutdown Delay
EN4 High Enable Delay (Figure 8)
EN4 Low Time
SYMBOL
CONDITIONS
MIN
TYP
MAX
3.2
UNITS
t
2
ms
μs
μs
μs
SHDN
t
100
0.5
0.5
HI_INIT
t
500
LO
EN4 High Time
t
HI
RESET (RST1)
Voltage from FB1 to GND, V
50mV hysteresis
falling,
FB1
Reset Trip Threshold
V
0.765
180
0.858
0.945
220
V
THRST
Reset Deassert Delay Time
Reset Glitch Filter
t
200
50
ms
μs
DRST
t
GLRST
LOGIC (DLIM1, DLIM2, EN123, EN4, CHG, RST1)
Logic Input-Voltage Low
Logic Input-Voltage High
Logic Input Pulldown Resistance
Logic Leakage Current
V
V
= 4.1V to 5.5V, V
= 4.1V to 5.5V, V
= 2.6V to 5.5V
= 2.6V to 5.5V
0.4
V
V
DC
DC
SYS
SYS
1.2
400
-1.0
V
= 0.4V to 5.5V, CEN, EN123, EN4
= 0 to 5.5V, DLIM1, DLIM2
760
+0.001
7
1200
+1.0
15
kꢀ
μA
mV
LOGIC
V
LOGIC
Logic Output Voltage Low
I
= 1mA
SINK
Logic Output-High Leakage
Current
V
= 5.5V
-1.0
+0.001
+1.0
μA
LOGIC
Note ±: Limits are 100% production tested at T = +25°C. Limits over the operating temperature range are guaranteed through cor-
A
relation using statistical quality control (SQC) methods.
Note 4: The charger transitions from done to fast-charge mode at this BAT recharge threshold.
Note 5: The charger transitions from fast-charge to top-off mode at this top-off threshold (Figure 2).
Note 6: The maximum output current is guaranteed by correlation to the p-channel current-limit threshold, p-channel on-resistance,
n-channel on-resistance, oscillator frequency, input voltage range, and output voltage range. The parameter is stated for
a 4.7μH inductor with 0.13Ω series resistance. See the Step-Down Converter Maximum Output Current section for more
information.
Note 7: The step-down output voltages are 1% high with no load due to the load-line architecture.
Note 8: The skip-mode current threshold is the transition point between fixed-frequency PWM operation and skip-mode operation.
The specification is given in terms of output load current for inductor values shown in the typical application circuit (Figure 1).
Note 9: Line regulation for the step-down converters is measured as ΔV
/ΔD, where D is the duty cycle (approximately
OUT
V
/V ).
OUT IN
Note 10:REG2 is disabled by connecting PV2 to ground, decreasing the quiescent current.
_______________________________________________________________________________________
7
PMIC with Integrated Chargers and Smart
Power Selector in a 4mm x 4mm TQFN
Typical Operating Characteristics
(Circuit of Figure 1, T = +25°C, unless otherwise noted.)
A
BATTERY LEAKAGE CURRENT
vs. BATTERY VOLTAGE
DC QUIESCENT CURRENT vs.
DC VOLTAGE (CHARGER ENABLED)
DC QUIESCENT CURRENT
vs. DC VOLTAGE (CHARGER DISABLED)
1000
900
800
700
600
500
400
300
200
100
0
1.2
1.0
0.8
0.6
0.4
0.2
0
1.2
1.0
0.8
0.6
0.4
0.2
0
V
DC
= 5V
EN123 = 1
RISING
FALLING
FALLING
RISING
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
BATTERY VOLTAGE (V)
0
1
2
3
4
5
6
0
1
2
3
4
5
6
DC VOLTAGE, V (V)
DC
DC VOLTAGE (V)
BATTERY REGULATION VOLTAGE
vs. TEMPERATURE
BATTERY LEAKAGE CURRENT
vs. BATTERY VOLTAGE
CHARGE CURRENT
vs. BATTERY VOLTAGE
4.25
1000
900
800
700
600
500
400
300
200
100
0
500
450
400
350
300
250
200
150
100
50
V
= 0V
EN123 = 0
DC
4.24
4.23
4.22
4.21
4.20
4.19
4.18
4.17
4.16
4.15
R
= 6.8kΩ
CISET
R
= 15kΩ
CISET
B/MAX819C
0
-40
-15
10
35
60
85
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
BATTERY VOLTAGE (V)
0
1
2
3
4
5
TEMPERATURE (°C)
BATTERY VOLTAGE (V)
SYSTEM VOLTAGE
vs. SYSTEM CURRENT
4.02
SYSTEM VOLTAGE
vs. SYSTEM CURRENT
4.5
4.4
4.3
4.2
4.1
4.0
3.9
3.8
V
V
= 5.1V
DC
= 4V
BATT
4.00
3.98
3.96
3.94
3.92
DLIM[1:2] = 10
DC UNCONNECTED
3.90
V
BATT
= 4V
3.88
0
100 200 300 400 500 600 700 800 900 1000
OUTPUT CURRENT (mA)
0
100 200 300 400 500 600 700 800 900 1000
OUTPUT CURRENT (mA)
8
_______________________________________________________________________________________
PMIC with Integrated Chargers and Smart
Power Selector in a 4mm x 4mm TQFN
B/MAX819C
Typical Operating Characteristics (continued)
(Circuit of Figure 1, T = +25°C, unless otherwise noted.)
A
SYSTEM VOLTAGE
vs. SYSTEM CURRENT
AC-TO-DC ADAPTER CONNECT
MAX8819A toc10
4.5
4.4
4.3
4.2
4.1
4.0
3.9
3.8
V
5V/div
2V/div
DC
4.3V
3.84V
CHARGING
4V
V
SYS
C
DC
C
CHARGING
SYS
1A
I
DC
1A/div
1A/div
NEGATIVE BATTERY
CURRENT FLOWS
INTO THE
V
V
= 5.1V
DC
BATTERY
I
BAT
= 4V
BATT
BATTERY CHARGER
SOFT-START
-1A
DLIM[1:2] = 01
0
100 200 300 400 500 600 700 800 900 1000
OUTPUT CURRENT (mA)
400μs/div
POWER-UP SEQUENCING
(MAX8819C)
POWER-UP SEQUENCING
(MAX8819A/MAX8819B)
MAX8819A toc12
MAX8819A toc11
V
EN123
2V/div
2V/div
0V
V
V3
0V
2V/div
0V
V
V1
2V/div
0V
V
V
V2
V1
2V/div
0V
V
V
V2
V3
2V/div
0V
2V/div
0V
1ms/div
2ms/div
REG1 EFFICIENCY
POWER-DOWN SEQUENCING
(MAX8819C)
vs. LOAD CURRENT (V
= 3.01V)
REG1
MAX8819A toc13
100
90
80
70
60
50
40
30
20
10
0
I
I
I
= 200mA
= 180mA
= 220mA 2V/div
V3
V2
V1
V
V3
0V
V
V
V2
V1
2V/div
0V
2V/div
V
RST1
0V
2V/div
0V
0.1
1
10
100
1000
100μs/div
LOAD CURRENT (mA)
_______________________________________________________________________________________
9
PMIC with Integrated Chargers and Smart
Power Selector in a 4mm x 4mm TQFN
Typical Operating Characteristics (continued)
(Circuit of Figure 1, T = +25°C, unless otherwise noted.)
A
REG1 DROPOUT VOLTAGE
vs. LOAD CURRENT
REG1 LOAD REGULATION
3.09
250
200
150
100
50
V
OUT1
= 3V
3.08
3.07
3.06
3.05
3.04
3.03
3.02
3.01
3.00
2.99
SYS IS 100mV BELOW THE
REG1 NOMINAL
REGULATION
VOLTAGE
V
= 3.3V
OUT1
0
0
50 100 150 200 250 300 350 400
REG1 LOAD CURRENT (mA)
0
50 100 150 200 250 300 350 400 450
OUTPUT CURRENT (mA)
REG1 HEAVY-LOAD SWITCHING
REG1 LIGHT-LOAD SWITCHING
WAVEFORMS
WAVEFORMS
MAX8819A toc18
MAX8819A toc17
20mV/div
AC-COUPLED
20mV/div
AC-COUPLED
V
V
OUT1
OUT1
V
2V/div
0V
LX1
2V/div
0V
V
I
LX1
LX1
I
LX1
200mA/div
0mA
100mA/div
0mA
B/MAX819C
200mA LOAD
400ns/div
20mA LOAD
2μs/div
LINE TRANSIENT
REG1 LOAD TRANSIENT (V
= 3V)
OUT
MAX8819A toc19
MAX8819A toc20
300mA
5V
100mA/div
4V
4V
V
2V/div
SYS
30mA
30mA
I
OUT1
OUT1
V
100mV/div
3V DC OFFSET
50mV/div
AC-COUPLED
V
OUT1
V
I
= 3V
= 30mA
OUT1
OUT1
100μs/div
200μs/div
10 ______________________________________________________________________________________
PMIC with Integrated Chargers and Smart
Power Selector in a 4mm x 4mm TQFN
B/MAX819C
Typical Operating Characteristics (continued)
(Circuit of Figure 1, T = +25°C, unless otherwise noted.)
A
REG3 EFFICIENCY
vs. LOAD CURRENT (V
REG2 EFFICIENCY
= 1.21V)
vs. LOAD CURRENT (V
= 1.82V)
REG2 LOAD REGULATION
REG3
REG2
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
1.86
1.85
1.84
1.83
1.82
1.81
1.80
0.1
1
10
100
1000
0.1
1
10
100
1000
0
50 100 150 200 250 300 350 400
REG2 LOAD CURRENT (mA)
LOAD CURRENT (mA)
LOAD CURRENT (mA)
REG3 LIGHT-LOAD SWITCHING
WAVEFORMS
REG3 LOAD REGULATION
MAX8819A toc25
1.225
1.220
1.215
1.210
1.205
1.200
1.195
1.190
1.185
20mV/div
AC-COUPLED
V
OUT3
V
I
LX3
LX3
2V/div
0V
100mA/div
0mA
20mA LOAD
0
50 100 150 200 250 300 350 400
REG3 LOAD CURRENT (mA)
2μs/div
REG3 HEAVY-LOAD SWITCHING
REG3 LOAD TRANSIENT
WAVEFORMS
MAX8819A toc27
MAX8819A toc26
320mA
20mV/div
AC-COUPLED
V
OUT3
100mA/div
30mA
30mA
I
OUT3
OUT3
V
I
LX3
LX3
2V/div
0V
V
100mV/div
1.2V DC OFFSET
200mA/div
0mA
200mA LOAD
400ns/div
200μs/div
______________________________________________________________________________________ 11
PMIC with Integrated Chargers and Smart
Power Selector in a 4mm x 4mm TQFN
Typical Operating Characteristics (continued)
(Circuit of Figure 1, T = +25°C, unless otherwise noted.)
A
LED EFFICIENCY
vs. LED CURRENT (6 LEDS)
LED EFFICIENCY vs. SYS VOLTAGE
100
90
80
70
60
50
40
30
20
10
0
100
95
6 LEDS
90
85
80
75
70
65
60
55
50
4 LEDS
I
= 25mA
LED
INDUCTOR: TOKO 1096AS-100M
DIODE: NXP PMEG3005EB
V
= 3.6V
20
SYS
0
5
10
15
25
2.5
3.0
3.5
4.0
4.5
5.0
5.5
LED CURRENT (mA)
SYS VOLTAGE (V)
REG4 INPUT CURRENT
vs. SYS VOLTAGE
LED EFFICIENCY
vs. LED CURRENT (4 LEDS)
LED AND BOOST EFFICIENCY
vs. SYS VOLTAGE
300
250
200
150
100
50
100
90
80
70
60
50
40
30
20
10
0
100
95
90
85
80
75
70
65
60
55
50
BOOST
LED
I
= 25mA
6 LEDS
INDUCTOR: TOKO 1096AS-100M
DIODE: NXP PMEG3005EB
LED
B/MAX819C
V
SYS
= 3.6V
6 LEDS, I = 25mA
LED
0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
0
5
10
15
20
25
2.5
3.0
3.5
4.0
4.5
5.0
5.5
SYS VOLTAGE (V)
LED CURRENT (mA)
SYS VOLTAGE (V)
REG4 STARTUP AND SHUTDOWN
RESPONSE
FB4 VOLTAGE vs. LED CURRENT
MAX8819A toc33
500
2V/div
V
EN4
450
400
350
300
250
200
150
100
50
V
OVP4
10V/div
0V
I
10mA/div
0mA
LED
0
0
5
10
15
20
25
2ms/div
LED CURRENT (mA)
12 ______________________________________________________________________________________
PMIC with Integrated Chargers and Smart
Power Selector in a 4mm x 4mm TQFN
B/MAX819C
Typical Operating Characteristics (continued)
(Circuit of Figure 1, T = +25°C, unless otherwise noted.)
A
MAXIMUM LED CURRENT
vs. TEMPERATURE
MINIMUM LED CURRENT
vs. TEMPERATURE
25.5
25.4
25.3
25.2
25.1
25.0
24.9
24.8
24.7
24.6
24.5
0.750
0.745
0.740
0.735
0.730
-40
-15
10
35
60
85
-40
-15
10
35
60
85
TEMPERATURE (°C)
TEMPERATURE (°C)
Pin Description
PIN
1
NAME
FUNCTION
COMP4
FB4
External Compensation Capacitor for REG4
REG4 Feedback Input
2
3
OVP4
PG4
Overvoltage Protection Node for REG4
REG4 Power Ground
4
5
LX4
Inductor Switching Node for REG4
Analog Ground
6
GND
EN4
7
REG4 Enable Input and Dimming Control Digital Input
Active-Low, Open-Drain Reset Output. RST1 pulls low to indicate that FB1 is below its regulation
threshold. RST1 goes high 200ms after FB1 reaches its regulation threshold. RST1 is high-impedance
when EN123 is low, and DC is unconnected.
8
9
RST1
Positive Battery Terminal Connection. Connect BAT to the positive terminal of a single-cell Li+/Li-Poly
battery. Bypass BAT to GND with a 4.7μF ceramic capacitor.
BAT
System Supply Output. Bypass SYS to GND with a 10μF ceramic capacitor. When a valid voltage is
present at DC and DLIM[1:2] ≠ 11, V
is limited to 4.35V (MAX8819A/MAX8819C) or 5.3V
SYS
(MAX8819B). When the system load (I
) exceeds the input current limit, V
drops 75mV
SYS
SYS
10
SYS
(V ) below V , allowing both the external power source and the battery to service SYS. SYS is
BSREG BAT
connected to BAT through an internal 70mΩ system load switch when a valid source is not present at
DC.
DC Power Input. DC is capable of delivering 1A to SYS. DC supports both AC adapters and USB
inputs. As shown in Table 1, the DC current limit is controlled by DLIM1 and DLIM2.
11
12
13
DC
CEN
FB1
Battery Charger Enable Input
Feedback Input for REG1. Connect FB1 to the center of a resistor voltage-divider from the REG1
output capacitors to GND to set the output voltage from 1V to V
.
SYS
______________________________________________________________________________________ 1±
PMIC with Integrated Chargers and Smart
Power Selector in a 4mm x 4mm TQFN
Pin Description (continued)
PIN
NAME
FUNCTION
Charge Rate Select Input. Connect a resistor from CISET to GND (R
current limit, prequalification-charge current limit, and top-off threshold.
) to set the fast-charge
CISET
14
CISET
Active-Low, Open-Drain Charge Status Output. CHG pulls low to indicate that the battery is charging.
See Figure 3 for more information.
15
16
17
CHG
PG1
LX1
REG1 Power Ground
Inductor Switching Node for REG1. When enabled, LX1 switches between PV13 and PG1 to regulate
the FB1 voltage to 1.0V. When disabled, LX1 is pulled to PG1 by 1kΩ in shutdown.
Power Input for the REG1 and REG3 Converters. Connect PV13 to SYS. Bypass PV13 to PG1 with a
4.7μF ceramic capacitor.
18
PV13
Inductor Switching Node for REG3. When enabled, LX3 switches between PV13 and PG3 to regulate
the FB3 voltage to 1.0V. When disabled, LX3 is pulled to PG3 by a 1kΩ internal resistor.
19
20
21
LX3
PG3
REG3 Power Ground
Input Current-Limit Selection Digital Input 1. Drive high or low according to Table 1 to set the DC input
current limit.
DLIM1
Feedback Input for REG2. Connect FB2 to the center of a resistor voltage-divider from the REG2
22
FB2
output capacitors to GND to set the output voltage from 1V to V
REG2 is disabled by grounding PV2.
. FB2 must be connected to GND if
SYS
Feedback Input for REG3. Connect FB3 to the center of a resistor voltage-divider from the REG3
output capacitors to GND to set the output voltage from 1V to V
23
24
FB3
.
SYS
REG1, REG2, and REG3 Enable Input. Drive EN123 high to enable REG1, REG2, and REG3. Drive EN123
low to disable REG1, REG2, and REG3. The enable/disable sequencing is shown in Figures 6 and 7.
EN123
Power Input for REG2. Connect PV2 to SYS for normal operation. Bypass PV2 to PG2 with a 2.2μF
ceramic capacitor. For systems that do not require REG2, connect PV2, FB2, and PG2 to GND (LX2
may be unconnected or connected to GND).
25
PV2
B/MAX819C
Inductor Switching Node for REG2. When enabled, LX2 switches between PV2 and PG2 to regulate
the FB2 voltage to 1.0V. When disabled, LX2 is pulled to PG2 by a 1kΩ internal resistor.
26
27
28
—
LX2
PG2
DLIM2
EP
REG2 Power Ground
Input Current-Limit Selection Digital Input 2. Drive high or low according to Table 1 to set the DC input
current limit.
Exposed Pad
14 ______________________________________________________________________________________
PMIC with Integrated Chargers and Smart
Power Selector in a 4mm x 4mm TQFN
B/MAX819C
DC
FAST-
CHARGE
CURRENT
(mA)
210
280
420
560
632
SYS
AC-TO-DC
ADAPTER
BATTERY
CAPACITY
(mAh)
DESIRED
CHARGE R7 (kΩ)
RATE (C)
SYS
C1
4.7μF
C5
10μF
Li+/Li-Poly
BATTERY
CHARGER AND
SYSTEM LOAD
SWITCH
300
400
600
800
900
14.3
10.7
7.15
5.36
4.75
0.7
0.7
0.7
SMART
POWER
SELECTOR
BAT
DLIM1
DC I (mA)
LIM
DLIM2
+
DLIM1
DLIM2
C6
4.7μF
1000
475
95
0
0
1
1
0
1
0
1
Li+/LiPo
BATTERY
0.7
0.7
GLITCH FILTER
SUSPEND
ON
CEN
OFF
R2
OUT1
CISET
R6
470kΩ
CHG
PV13
LX1
CHG
BIAS
MAX8819A
MAX8819B
MAX8819C
PV13
SYS
C7
4.7μF
3.0V
400mA
L1
PG1
4.7μH
EN
ON
EN123
REG1
STEP-DOWN
DC-DC
OFF
OUT1
R8
200kΩ
C8*
10μF
FB1
PG1
PWM
PG1
L4
10μH
OUT1
RST1
R9
100kΩ
LX4
PG1
SYS
R10
470kΩ
C2
0.1μF
D7
REG1/RESET
OVP4
PG4
RST1
PV2
LX2
PG4
87% FALLING
50us BLANKING
92% RISING
OUT4
C3
D1
D2
80ms DELAY
0.1μF
50V
PG4
PG4
COMP4
X7R
SYS
C4
0.022μF
C9
2.2μF
UP TO 6
WLED
D3
D4
D5
D6
PG2
1.8V
200mA
L2
4.7μH
EN
REG4
STEP-UP
DC-DC
REG2
STEP-DOWN
DC-DC
OUT2
R12
80.6kΩ
C10*
10μF
FB2
PG2
PG2
PWM
EN
R13
100kΩ
FB4
EN4
PG2
PV13
R1
20
1.2V
300mA
L3
4.7μH
(25mA)
LX3
REG3
STEP-DOWN
DC-DC
OUT3
R14
20.0kΩ
C11*
10μF
FB3
PG3
ON
PULSE
DIMMING
OFF
PG3
PWM
R15
100kΩ
PG3
GND
EP
*22μF FOR MAX8819C IS RECOMMENDED.
Figure 1. Functional Diagram/Typical Applications Circuit
white LEDs. All three step-down converters feature
adjustable output voltages set with external resistors.
Detailed Description
The MAX8819_ is a complete power solution that
includes a battery charger, step-down converters, and
WLED power. As shown in Figure 1, the IC integrates a
DC power input, Li+/Li-Poly battery charger, three step-
down converters, and one step-up converter for powering
The MAX8819_ has one external power input that con-
nects to either an AC-to-DC adapter or USB port. Logic
inputs DLIM1 and DLIM2 select the desired input cur-
rent limit.
______________________________________________________________________________________ 15
PMIC with Integrated Chargers and Smart
Power Selector in a 4mm x 4mm TQFN
In addition to charging the battery, the IC supplies
power to the system through the SYS output. The
charging current is provided from SYS so that the set
input current limit controls the total SYS current, this is
the sum of the system load current and the battery-
charging current.
A thermal-limiting circuit reduces the battery charge
rate and external power source current to prevent the
MAX8819_ from overheating.
System Load Switch
An internal 70mΩ MOSFET connects SYS to BAT when
no voltage source is available at DC. When an external
source is detected at DC, this switch opens and SYS is
powered from the valid input source through the Smart
Power Selector.
In some instances, there may not be enough DC input
current to supply peak system loads. The Smart Power
Selector circuitry offers flexible power distribution from
an AC-to-DC adapter or USB source to the battery and
system load. The battery is charged with any available
power not used by the system load. If a system load
peak exceeds the input current limit, supplemental cur-
rent is taken from the battery. Thermal limiting prevents
overheating by reducing power drawn from the input
source. In the past, it might have been necessary to
reduce system functionality to limit current drain when a
USB source is connected. However, with the
MAX8819_, this is no longer the case. When the DC or
USB source hits its limit, the battery supplies supple-
mental current to maintain the load.
When the system load requirements exceed the input
current limit, the battery supplies supplemental current
to the load through the internal system load switch. If
the system load continuously exceeds the input current
limit, the battery does not charge, even though external
power is connected. This is not expected to occur in
most cases because high loads usually occur only in
short peaks. During these peaks, battery energy is
used, but at all other times the battery charges.
DC Power Input (DC, DLIM1, DLIM2)
DC is a current-limited power input that supplies the
system (SYS) up to 1A. The DC to SYS switch is a linear
regulator designed to operate in dropout. This linear
regulator prevents the SYS voltage from exceeding
5.3V for the MAX8819B or 4.35V for the MAX8819A/
MAX8819C. As shown in Table 1, DC supports four dif-
ferent current limits that are set with the DLIM1 and
DLIM2 digital inputs. These current limits are ideally suit-
ed for use with AC-to-DC wall adapters and USB power.
The operating voltage range for DC is 4.1V to 5.5V, but it
can tolerate up to 6V without damage. When the DC
input voltage is below the undervoltage threshold (4V), it
is considered invalid. When the DC voltage is below the
battery voltage it is considered invalid. The DC power
input is disconnected when the DC voltage is invalid.
Bypass DC to ground with at least a 4.7μF capacitor.
The IC features overvoltage protection. Part of this protec-
tion is a 4.35V (MAX8819A/MAX8819C) or 5.3V
(MAX8819B) voltage limiter at SYS. If DC exceeds the
overvoltage threshold of 5.88V (V ), the input lim-
OVLO_DC
iter disconnects SYS from DC, but battery-powered oper-
ation of all regulators is still allowed.
Input Limiter
The Smart Power Selector seamlessly distributes power
between the current-limited external input (DC), the bat-
tery (BAT), and the system load (SYS). The basic func-
tions performed are:
B/MAX819C
With both an external power supply (DC) and battery
(BAT) connected:
• When the system load requirements are less than
the input current limit, the battery is charged with
residual power from the input.
Four current settings are provided based upon the set-
tings of DLIM1 and DLIM2, see Table 1. DLIM1 and
DLIM2 are deglitched. This deglitching prevents the
problem of major carry transitions momentarily entering
the suspend state.
• When the system load requirements exceed the
input current limit, the battery supplies supplemental
current to the load through the internal system load
switch.
• When the battery is connected and there is no exter-
nal power input, the system (SYS) is powered from
the battery.
Table 1. DC Current-Limit Settings
DLIM1
DLIM2
DC I
(mA)
LIM
• When an external power input is connected and
there is no battery, the system (SYS) is powered
from the external power input.
0
0
1
1
0
1
0
1
1000
475
95
Suspend
16 ______________________________________________________________________________________
PMIC with Integrated Chargers and Smart
Power Selector in a 4mm x 4mm TQFN
B/MAX819C
TOP-OFF
FAST-CHARGE
FAST-CHARGE
PREQUALIFICATION
DONE
(CONSTANT VOLTAGE)
(CONSTANT CURRENT)
V
BATREG
V
BATPRQ
I
CHGMAX
I
PREQUAL
I
TOPOFF
0
HIGH
IMPEDANCE
LOW
Figure 2. Li+/Li-Poly Charge Profile
voltage is less than the prequalification threshold
(3.0V), the charger enters prequalification mode and
charges the battery at 10% of the maximum fast-charge
current while deeply discharged. Once the battery volt-
age rises to 3.0V, the charger transitions to fast-charge
mode and applies the maximum charge current. As
charging continues, the battery voltage rises until it
approaches the battery regulation voltage (4.2V typ)
Battery Charger
Figure 2 shows the typical Li+/Li-Poly charge profile for
the MAX8819_, and Figure 3 shows the battery charger
state diagram.
With a valid DC input that is not suspended, the battery
charger initiates a charge cycle once CEN is driven
high. It first detects the battery voltage. If the battery
______________________________________________________________________________________ 17
PMIC with Integrated Chargers and Smart
Power Selector in a 4mm x 4mm TQFN
1.5V
I
= 2000 x
CHGMAX
DC = INVALID
NO INPUT POWER
= 0mA
R
CISET
I
CHG
CHG = 1
DC = VALID
ANY STATE
DLIM[1:2] = 11
INPUT SUSPENDED
DLIM[1:2] = 11
CHARGER DISABLED
I
= 0mA
CHG = 1
CHG
I
= 0mA
CHG = 1
CEN = 0
CHG
DLIM[1:2] ≠ 11
CEN = 1
IC SETS TIMER = 0
TIMER FAULT
= 0mA
t > t
PREQUAL
I
CHG
CHG = 2Hz SQUAREWAVE
PREQUALIFICATION
I
≤ I
/10
CHG CHGMAX
CHG = 0
t > t
FSTCHG
V
BAT
> 3V,
V
BAT
< 2.82V
IC SETS TIMER = 0
IC SETS TIMER = 0
I
< I
x 53%
CHG CHGMAX
OR V = V
IC RESUMES TIMER
BAT
BATREG
I
< I
x 50%
BATREG
CHG CHGMAX
AND V < V
BAT
IC EXTENDS TIMER BY 2x
FAST-CHARGE
TIMER EXTEND
x 20%) < I < (I x 50%)
CHGMAX
I
≤ I
CHG CHGMAX
CHG = 0
(I
CHGMAX
CHG
CHG = 0
I
< I x 23%
CHG SET
OR V = V
I
< I
x 20%
I
< I
x 10% AND V
BAT
BATREG
CHG CHGMAX
CHG CHGMAX BAT
IC RESUMES TIMER
x 20%
CHG CHGMAX
IC SETS TIMER = 0
IC SETS TIMER = 0
B/MAX819C
I
< I
AND V <V
IC SUSPENDS
BAT BATREG
TOP-OFF
CHG = 1
TIMER
V
I
= V
BATREG
BAT
V
< (V
BATREG
100mV)
BAT
≤ I
/10
CHG CHGMAX
TIMER SUSPEND
< (I x 20%)
IC SETS TIMER = 0
I
t
>
33min
CHG
CHGMAX
TOPOFF
CHG = 0
DONE
(V
BATREG
-100mV) ≤ V ≤ V
BAT BATREG
I
= 0mA
CHG
CHG = 1
Figure 3. Li+/Li-Poly Charger State Diagram
where charge current starts tapering down. When
charge current decreases to 10% of the maximum fast-
charge current, the charger enters a 33min top-off state
and then charging stops. If the battery voltage subse-
quently drops 100mV below the battery regulation volt-
age, charging restarts and the timers reset.
• Battery voltage
• DC input current limit
• The charge-setting resistor, R
CISET
• The system load (I
)
SYS
• The die temperature
The battery charge rate is set by several factors:
18 ______________________________________________________________________________________
PMIC with Integrated Chargers and Smart
Power Selector in a 4mm x 4mm TQFN
B/MAX819C
• The battery charger is enabled by the processor dri-
FAST-CHARGE, PREQUALIFICATION, AND TOP-OFF
CURRENT vs. CHARGE-SETTING RESISTOR
10,000
ving the CEN input high. A valid input must be avail-
able at DC. The battery charger is disabled without
a valid input at DC or by driving CEN low.
• The system current has priority over the battery
charger; the battery charger automatically reduces
its charge current to maintain the input current limit
I
CHGMAX
1000
100
10
while still providing the system current (I
).
SYS
• The input current limit is tapered down from full cur-
rent to zero current when the die temperature transi-
I
I
PREQUAL, TOPOFF
tions from +100°C to +120°C. Since I
has priority
SYS
over the battery charge current, the battery charge
current tapers down before I . The overall result is
SYS
self-regulation of die temperature (see the Thermal
Limiting and Overload Protection section for more
information).
1
0
5
10
(kΩ)
15
20
R
CISET
• The battery charger stops charging in done mode
as shown in Figures 2 and 3.
Figure 4. Calculated Charge Currents vs. R
CISET
Table 2. Calculated Charge Currents vs.
Charge Status Output (CHG)
CHG is an open-drain, active-low output that indicates
charger status. As shown in Figures 2 and 3, CHG is
low when the charger is in its prequalification or fast-
charge states. When a timer count is exceeded in
either state, CHG indicates the fault by blinking at a
2Hz rate and remains in that state until the charger is
reset by CEN going low, removal of DC or setting
DLIM[1:2] = 11.
R
CISET
I
I
I
CHGMAX
(mA)
PREQUAL
(mA)
TOPOFF
(mA)
R
(kΩ)
CISET
3.01
1000
746
601
497
430
372
330
300
273
248
231
214
200
100
75
60
50
43
37
33
30
27
25
23
21
20
100
75
60
50
43
37
33
30
27
25
23
21
20
4.02
4.99
6.04
6.98
8.06
9.09
10
When the MAX8819_ is used with a microprocessor
(μP), connect a pullup resistor between CHG and the
system logic voltage to indicate charge status to the
μP. Alternatively, CHG sinks up to 20mA for an LED
charge indicator.
If the charge status output feature is not required, con-
nect CHG to ground or leave unconnected.
11
12.1
13
Charge Timer
As shown in Figure 3, a fault timer prevents the battery
from charging indefinitely. In prequalification mode, the
charge time is internally fixed to 33min.
14
15
t
= 33min
PREQUAL
nuisance charge timer faults. When the battery charge
current is between 100% and 50% of its programmed
fast-charge level, the fast-charge timer runs at full
speed. When the battery charge current is between
50% and 20% programmed fast-charge level, the fast-
charge timer is slowed by 2x. Similarly, when the bat-
tery charge current is below 20% of the programmed
fast-charge level, the fast-charge timer is paused. The
fast-charge timer is not slowed or paused when the
charger is in the constant voltage portion of its fast-
charge mode (Figure 2) where the charge current
reduces normally.
In fast-charge mode, the charge timer is internally fixed
to 660min.
t
= 660min
FSTCHG
When the charger exits fast-charge mode, a fixed
33min top-off mode is entered:
t
= 33min
TOPOFF
While in the constant-current fast-charge mode (Figure
2), if the MAX8819_ reduces the battery charge current
due to its internal die temperature or large system loads,
it slows down the charge timer. This feature eliminates
______________________________________________________________________________________ 19
PMIC with Integrated Chargers and Smart
Power Selector in a 4mm x 4mm TQFN
Charge Current (CISET)
The IC uses external resistor-dividers to set the step-
down output voltages between 1V and V . Use at
least 10μA of bias current in these dividers to ensure no
change in the stability of the closed-loop system. To set
the output voltage, select a value for the resistor con-
As shown in Table 2 and Figure 4, a resistor from CISET
SYS
to ground (R
) sets the maximum fast-charge cur-
), the charge current in prequalification
CISET
CHGMAX
PREQUAL
rent (I
mode (I
), and the top-off threshold (I
).
TOPOFF
The MAX8819_ supports values of I
from 200mA
nected between FB_ and GND (R
). The recom-
FBL
CHGMAX
as follows:
to 1000mA. Select the R
mended value is 100kΩ. Next, calculate the value of the
CISET
resistor connected from FB_ to the output (R ):
FBH
1.5V
R
= 2000×
CISET
V
1.0V
⎛
⎞
⎠
OUT
I
CHGMAX
R
=R
×
−1
⎟
⎜
⎝
FBH
FBL
Determine I
by considering the characteristics
CHGMAX
of the battery. It is not necessary to limit the charge cur-
rent based on the capabilities of the expected AC-to-
DC adapter or USB/DC input current limit, the system
load, or thermal limitations of the PCB. The IC automati-
cally lowers the charging current as necessary to
accommodate for these factors.
REG1, REG2, and REG3 are optimized for high, medi-
um, and low output voltages, respectively. The highest
overall efficiency occurs with V1 set to the highest out-
put voltage and V3 set to the lowest output voltage.
Step-Down Control Scheme
At light load, the step-down converter switches only as
needed to supply the load. This improves light-load effi-
ciency. At higher load currents (~80mA), the step-down
converter transitions to fixed 2MHz switching.
For the selected value of R
, calculate I
,
CHGMAX
CISET
as follows:
I , and I
PREQUAL
TOPOFF
1.5V
I
= 2000 x
CHGMAX
R
CISET
Step-Down Dropout and Minimum Duty Cycle
All of the step-down regulators are capable of operat-
ing in 100% duty-cycle dropout, however, REG1 has
been optimized for this mode of operation. During
100% duty-cycle operation, the high-side p-channel
MOSFET turns on constantly, connecting the input to
the output through the inductor. The dropout voltage
I
= I
= 10% x I
PREQUAL
TOPOFF
CHGMAX
Step-Down Converters
(REG1, REG2, REG3)
REG1, REG2, and REG3 are high-efficiency, 2MHz cur-
rent-mode step-down converters with adjustable outputs.
REG1 is designed to deliver 400mA for the MAX8819A/
MAX8819B and 550mA for the MAX8819C. REG2 and
REG3 are designed to deliver 300mA for the MAX8819A/
MAX8819B and 500mA for the MAX8819C.
(V ) is calculated as follows:
DO
B/MAX819C
V
= I
R + R
(
)
DO
LOAD P LSR
The PV13 step-down regulator power input must be
connected to SYS. PV2 must also be connected to SYS
for normal operation of REG2, but REG2 can be dis-
abled by connecting PV2, FB2, and PG2 to GND. When
REG2 is disabled, LX2 can be unconencted or con-
nected to GND. The step-down regulators operate with
where:
R = p-channel power switch R
P
R
DS(ON)
= external inductor ESR
LSR
The minimum duty cycle for all step-down regulators is
12.5% (typ), allowing a regulation voltage as low as 1V
over the full SYS operating range. REG3 is optimized
for low duty-cycle operation.
V
from 2.6V to 5.5V. Undervoltage lockout ensures
SYS
that the step-down regulators do not operate with SYS
below 2.55V (max).
Step-Down Input Capacitor
The input capacitor in a step-down converter reduces
current peaks drawn from the power source and
reduces switching noise in the controller. The imped-
ance of the input capacitor at the switching frequency
must be less than that of the source impedance of the
supply so that high-frequency switching currents do not
pass through the input source.
See the Step-Down Converter Enable/Disable (EN123)
and Sequencing section for how to enable and disable
the step-down converters. When enabled, the
MAX8819_ gradually ramps each output up during a
2.6ms soft-start time. When enabled, the MAX8819C
sequentially ramps up each output. Soft-start eliminates
input current surges when regulators are enabled.
See the Step-Down Control Scheme section for informa-
tion about the step-down converters control scheme.
20 ______________________________________________________________________________________
PMIC with Integrated Chargers and Smart
Power Selector in a 4mm x 4mm TQFN
B/MAX819C
The step-down regulator power inputs are critical dis-
Step-Down Output Capacitors
The output capacitance keeps output ripple small and
ensures control-loop stability. The output capacitor must
have low impedance at the switching frequency.
Ceramic, polymer, and tantalum capacitors are suitable
with ceramic exhibiting the lowest ESR and lowest high-
frequency impedance. The MAX8819A/MAX8819B
require at least 10μF of output capacitance. The
MAX8819C requires ar least 22μF of output capacitance.
continuous current paths that require careful bypass-
ing. In the PCB layout, place the step-down converter
input bypass capacitors as close as possible to each
pair of switching converter power input pins (PV_ to
PG_) to minimize parasitic inductance. If making con-
nections to these capacitors through vias, be sure to
use multiple vias to ensure that the layout does not
insert excess inductance or resistance between the
bypass capacitor and the power pins.
As the case sizes of ceramic surface-mount capacitors
decreases, their capacitance vs. DC bias voltage char-
acteristic becomes poor. Due to this characteristic, it is
possible for 0805 capacitors to perform well while 0603
capacitors of the same value may not. The MAX8819A/
MAX8819B require a nominal output capacitance of
10μF, however, after their DC bias voltage derating, the
output capacitance must be at least 7.5μF.
The input capacitor must meet the input ripple current
requirement imposed by the step-down converter.
Ceramic capacitors are preferred due to their low ESR
and resilience to power-up surge currents. Choose the
input capacitor so that its temperature rise due to input
ripple-current does not exceed approximately +10°C.
For a step-down DC-DC converter, the maximum input
ripple current is half of the output current. This maxi-
mum input ripple current occurs when the step-down
Step-Down Inductor
Choose the step-down converter inductance to be
4.7μH. The minimum recommended saturation current
requirement is 700mA. In PWM mode, the peak induc-
tor currents are equal to the load current plus one half
of the inductor ripple current. See Table 3 for suggested
inductors.
converter operates at 50% duty factor (V = 2 x V
).
IN
OUT
Bypass PV13 to PG1 and PG3 with a 4.7μF ceramic
capacitor. If REG2 is required, bypass PV2 to PG2 with
a 2.2μF capacitor. Use capacitors that maintain their
capacitance over temperature and DC bias. Ceramic
capacitors with an X7R or X5R temperature characteris-
tic generally perform well. The capacitor voltage rating
should be 6.3V or greater.
Table ±. Suggested Inductors
INDUCTANCE
ESR
(mΩ)
CURRENT RATING
(mA)
DIMENSIONS
(mm)
MANUFACTURER
Sumida
SERIES
(µH)
CDRH2D11HP
CDH2D09
NR3012
4.7
4.7
4.7
4.7
4.7
4.7
4.7
4.7
4.7
190
218
130
190
160
240
130
110
160
750
700
770
750
740
700
880
1100
900
3.0 x 3.0 x 1.2 = (10.8mm)3
3.0 x 3.0 x 1.0= (9.0mm)3
3.0 x 3.0 x 1.2 = (10.8mm)3
3.0 x 3.0 x 1.0 = (9.0mm)3
2.8 x 2.6 x 1.2 = (8.7mm)3
2.8 x 2.6 x 1.0 = (7.3mm)3
3.0 x 2.8 x 1.2 = (10.8mm)3
2.5 x 2.0 x 1.0 = (5mm)3
2.0 x 1.6 x 1.0 = (3.2mm)3
Taiyo Yuden
NR3010
VLF3012
TDK
VLF3010
TOKO
FDK
DE2812C
MIPF2520
MIPF2016
______________________________________________________________________________________ 21
PMIC with Integrated Chargers and Smart
Power Selector in a 4mm x 4mm TQFN
SYS
+
SYSOK
-
2.5V RISING
100mV HYST.
READY
MAX8819A
MAX8819B
+
-
DIE TEMP
DT165
+165°C
DC
+
-
DCOVLO
6.0V RISING
400mV HYST.
DCPOK
-
DCUVLO
+
4.0V RISING
500mV HYST.
SOFT-START
REG1
EN
EN
REG1OK
REG2OK
OK
OK
2MHz
OSC
EN123
SOFT-START
REG2
BIAS
AND
REF
SOFT-START
REG3
READY
REGON
REGON
EN
EN
64 CYCLE
DELAY
(32µs)
REG3OK
REG4OK
OK
OK
B/MAX819C
SOFT-START
REG4
EN4
Figure 5a. MAX8819A/MAX8819B Enable/Disable Logic
The peak-to-peak inductor ripple current during PWM
operation is calculated as follows:
Step-Down Converter Maximum Output Current
The maximum regulated output current from a step-down
converter is ultimately determined by the p-channel peak
current limit (I ). The calculation follows:
PK
V
(V
− V
)
OUT SYS
OUT
I
=
P−P
V
× f ×L
I = I – (I /2)
OUT_MAX PK P-P
SYS
S
For example, if V
= 5.3V, V
= 3V, f = 2MHz,
OUT S
SYS
where f is the 2MHz switching frequency.
S
L = 4.7μH, and I = 0.6A:
PK
The peak inductor current during PWM operation is cal-
culated as follows:
I
= 3V x (5.3V - 3V)/(5.3V x 2MHz x 4.7μH) = 0.138A
P-P
then I
= 0.6A - (0.138A/2) = 0.531A.
OUT_MAX
I
P−P
I
= I
+
L _PEAK
LOAD
2
22 ______________________________________________________________________________________
PMIC with Integrated Chargers and Smart
Power Selector in a 4mm x 4mm TQFN
B/MAX819C
SYS
+
SYSOK
-
2.5V RISING
100mV HYST.
READY
MAX8819C
+
-
DIE TEMP
DT165
+165°C
DC
+
-
DCOVLO
6.0V RISING
400mV HYST.
DCPOK
-
DCUVLO
+
SOFT-START
REG1
4.0V RISING
500mV HYST.
EN
EN
REG1OK
REG2OK
OK
OK
2MHz
OSC
EN123
SOFT-START
REG2
BIAS
AND
REF
SOFT-START
REG3
READY
REGON
REGON
EN
EN
64 CYCLE
DELAY
(32μs)
REG3OK
REG4OK
OK
OK
SOFT-START
REG4
EN4
Figure 5b. MAX8819C Enable Logic
As the load current is increased beyond this point, the
output voltage sags and the converter goes out of regu-
lation because the inductor current cannot increase
above the p-channel peak current limit.
ground. When the short is removed, the inductor current
raises the voltage on the output capacitor and the step-
down converter resumes normal operation.
REG1 Reset (RST1)
RST1 is an active-low, open-drain output that pulls low
to indicate that FB1 is below its regulation threshold.
RST1 goes high 200ms after FB1 reaches its regulation
threshold. RST1 is high-impedance when EN123 is
high. See Figures 6 and 7.
Step-Down Converter Short-Circuit Protection
The step-down converter implements short-circuit protec-
tion by monitoring the feedback voltage, V . After soft-
FB_
start, if V
drops below 0.23V, the converter reduces its
switching frequency to f /3. The inductor current still
FB_
S
reaches the p-channel peak current limit, however, at
one-third the frequency. Therefore, the output and input
currents are reduced to approximately one-third of the
maximum value in response to an output short circuit to
A 50μs blanking delay is provided when FB1 is falling,
so that RST1 does not glitch if the REG1 output voltage
is dynamically adjusted by altering the resistors in its
feedback network.
______________________________________________________________________________________ 2±
PMIC with Integrated Chargers and Smart
Power Selector in a 4mm x 4mm TQFN
1
2
3
4
5
6
7
8
NOTES
V
DC
V
BAT
< V < V
SYS DC
V
SYS
V
BAT
V
BAT
t
SS-D-S
V
EN123
V
OUT1
V
OUT2
V
OUT3
t
SS1
t
SS2
t
SS3
HIGH
IMPEDANCE
V
RST1
t
DRST1
V
EN4
V
SYS
- V
D
V
OUT4
t
V
- V
SYS D
SS4
V
CEN
B/MAX819C
V
t
SS_CHG
CHG
Figure 6. MAX8819A/MAX8819B Enable/Disable Waveforms Example
Step-Down Converter
Active Discharge in Shutdown
enable/disable logic. Figure 6 shows an example of
enable and disable waveforms for the MAX8819A/
MAX8819B.
Each MAX8819_ step-down converter (REG1, REG2,
REG3) has an internal 1kΩ resistor that discharges the
output capacitor when the converter is off. The dis-
charge resistors ensure that the load circuitry powers
down completely. The internal discharge resistors are
connected when a converter is disabled and when the
device is in UVLO with an input voltage greater than
1.0V. With an input voltage less than 1.0V the internal
discharge resistors are not activated.
Figure 6 notes:
1) The device is off with no external power applied to
DC. The system voltage (V
) is equal to the bat-
SYS
tery voltage (V
).
BAT
2) An external supply is applied to DC that causes the
step-down converter to power up after the DC-to-
SYS soft-start time (t
). When the DC input is
SYS
SS-D-S
valid and DLIM[1:2] ≠ 11, V
increases.
Step-Down Converter Enable/
Disable (EN12±) and Sequencing
Figure 5a shows the MAX8819A/MAX8819B enable and
disable logic. Figure 5b shows the MAX8819C
3) When V1 reaches the reset trip threshold (V
),
THRST
the reset deassert delay timer starts. When the reset
deassert delay timer expires (t ), RST1 goes
DRST1
high-impedance. If RST1 is connected to the RESET
24 ______________________________________________________________________________________
PMIC with Integrated Chargers and Smart
Power Selector in a 4mm x 4mm TQFN
B/MAX819C
1
2
3
4
5
6
7
NOTES
V
DC
V
< V < V
SYS
BAT
DC
V
SYS
V
BAT
V
BAT
t
SS-D-S
V
EN123
V
V
V
t
OUT3
OUT2
OUT1
SS3
t
SS2
t
SS1
HIGH IMPEDANCE
V
RST1
t
DRST1
V
EN4
V
- V
D
V
t
V - V
SYS D
SYS
OUT4
SS4
V
CEN
V
CHG
t
SS_CHG
Figure 7. MAX8819C Enable/Disable Waveforms Example
input of the system μP, the processor can begin its
boot-up sequence up at this time.
Figure 7 notes:
1) The MAX8819C is off with no external power applied
to DC. The system voltage (V ) is equal to the bat-
SYS
4) During the μP’s boot-up sequence, it asserts EN123
to keep the step-down converters enabled, even if
DC is removed.
tery voltage (V
).
BAT
2) An external supply is applied to DC that causes the
step-down regulator to power up after the DC-to-
5) After the μP has booted, it asserts EN4 to turn on the
display’s backlight.
SYS soft-start time (t
). When the DC input is
SS-D-S
valid and DC is not suspended, V
rises.
SYS
6) CEN is asserted by the μP to start a charge cycle.
3) EN123 is pulled high to start the OUT3, OUT2, and
OUT1 power-up sequence. When OUT1 reaches the
7) The external supply is removed from DC and V
SYS
falls. The converters remain enabled because the μP
has asserted EN123 and EN4, but the battery charg-
ing current drops to zero even though CEN is still
asserted. CHG goes high impedance.
reset trip threshold (V
), the reset deassert
THRST
delay timer starts. When the reset deassert delay
timer expires (t 200ms typ.), RST1 goes high-
DRST1
impedance. If RST1 is connected to the RESET input
of the system μP, the processor can begin its boot-
up sequence at this time.
8) System is turned off by deasserting EN123, EN4, and
CEN; RST1 goes low to reset the μP.
______________________________________________________________________________________ 25
PMIC with Integrated Chargers and Smart
Power Selector in a 4mm x 4mm TQFN
4) EN4 to turn on the display’s backlight.
1MHz switching frequency allows for tiny external com-
ponents. The step-up converter control scheme opti-
mizes the efficiency while achieving low EMI and low
input ripple.
5) CEN is asserted by the μP to start a charge cycle.
6) The external supply is removed from DC and V
SYS
falls. The regulators remain enabled because EN123
and EN4 are asserted, but the battery charging cur-
rent drops to zero even though CEN is still asserted.
CHG goes high-impedance.
If the step-up converter (REG4) is not needed, disable
REG4 by grounding EN4, LX4, PG4, and OVP4. COMP4
can be unconnected.
7) System is turned off by deasserting EN123, EN4,
and CEN. OUT1, OUT2, and OUT3 power down in
the opposite order of power-up. RST1 goes low to
reset the μP.
REG4 WLED Driver Configuration
Figure 1 shows that REG4 is configured as a white light
emitting diodes (WLED) driver, typically used to drive
up to six devices with an output voltage up to 24V. The
full-scale current is set by resistor R1, according to the
following relationship:
Step-Up Converter (REG4)
The step-up converter (REG4) operates by regulating
the voltage at FB4 to 0.5V. REG4 operates from the
V
FB4
I
=
, where V
= 0.5V nominally
FS
FB4
R1
< 0.5V/16Ω = 30.9mA
system voltage (V
); this voltage can vary from 2.6V to
SYS
4.35V (MAX8819A/MAX8819C) or 5.3V (MAX8819B). The
I
FS
0
STEP
EN4
1
2
3
4
5
28
t
29
30
31
32
33
t
HI_INIT
> 100μs
t
SHDN
HI
2ms (typ)
t
LO
t
SOFT-START
FULL
FULL
500ns TO 500μs
> 500ns
31/32
31/32
30/32
29/32
28/32
27/32
I
LED
6/32
5/32
4/32
3/32
2/32
1/32
SHUTDOWN
SHUTDOWN
B/MAX819C
Figure 8. Dimming Control Timing Diagram
Table 4. REG4 Recommended Inductors
INDUCTANCE
CURRENT
RATING (mA)
MANUFACTURER
SERIES
ESR (mΩ)
DIMENSIONS (mm)
(µH)
DE2812C
DB3018C
MIP3226
10
10
10
290
240
160
580
630
900
3.0 x 2.8 x 1.2 = (10.8mm)3
3.2 x 3.2 x 1.8 = (18.4mm)3
3.2 x 2.6 x 1 = (8.32mm)3
TOKO
FDK
Table 5. REG4 Recommended Diodes
CONTINUOUS
CURRENT
(mA)
BREAKDOWN
VOLTAGE
(V)
FORWARD VOLTAGE
(mV)
MANUFACTURER
PART NUMBER
PACKAGE
CMDSH05-4
CMHSH5-4
500
500
500
500
470
510
500
430
40
40
30
30
SOD-323
SOD-123
SOD-523
SOD-123
Central Semiconductor
NXP
PMEG3005EB
MBR0530L
ON Semiconductor
26 ______________________________________________________________________________________
PMIC with Integrated Chargers and Smart
Power Selector in a 4mm x 4mm TQFN
B/MAX819C
EN4 enables REG4, disables REG4, and adjusts the volt-
Soft-Start/Inrush Current
The MAX8819_ implements soft-start on many levels to
control inrush current to avoid collapsing supply volt-
ages, and to fully comply with the USB 2.0 specifica-
tions. All DC and charging functions implement soft-start.
The DC node only requires 4.7μF of input capacitance.
Furthermore, all regulators implement soft-start to avoid
transient overload of power inputs.
age on FB4 in 32 linear steps. If current adjustment is not
required, EN4 acts as a simple enable/disable controller.
Driving EN4 high for at least 100μs powers up REG4 and
sets V
to 0.5V. Pulling EN4 low for at least 2ms dis-
FB4
ables REG4. To adjust V
, apply pulses as shown in
FB4
Figure 8. Dim the WLEDs by pulsing EN4 low (500ns to
500μs pulse width). Each pulse reduces the LED current
by 1/32. Note: When REG4 is disabled, OUT4 is equal to
Undervoltage and Overvoltage Conditions
V
SYS
minus the drop from the catch diode.
DC UVLO
DC undervoltage lockout (UVLO) prevents an input sup-
ply from being used when its voltage is below the oper-
In the event that the load (typically WLEDs) opens,
rises quickly until it reaches the overvoltage pro-
tection threshold (typically 25V). When this occurs,
REG4 stops switching and latches off until EN4 is reset
low for at least 2ms.
V
OUT4
ating range. When the voltage from DC to GND (V ) is
DC
less than the DC UVLO threshold (4.0V, typ), the DC
input is disconnected from SYS, the battery charger is
disabled and CHG is high impedance. BAT is connected
to SYS through the internal system load switch in DC
UVLO mode, allowing the battery to power the SYS
node. REG1–REG4 and the LED current sinks are
allowed to operate from the battery in DC UVLO mode.
Step-Up Converter Inductor Selection
The WLED boost converter switches at 1MHz, allowing
the use of a small inductor. A 10μH inductance value is
recommended for most applications. Smaller induc-
tances require less PCB space.
Use inductors with a ferrite core or equivalent.
Powdered iron cores are not recommended for use at
high-switching frequencies. The inductor’s saturation
current rating should preferably exceed the REG4
n-channel current limit of 700mA. Choose an inductor
with a DC resistance less than 300mΩ to maintain high
efficiency. Table 4 lists recommended inductors.
DC OVLO
DC overvoltage lockout (OVLO) is a fail-safe mecha-
nism and prevents an input supply from being used
when its voltage exceeds the operating range. The
absolute maximum ratings state that DC withstands
voltages up to 6V. Systems must be designed so that
DC never exceeds 6V (transient and steady-state). If
the voltage from DC to GND (V ) should exceed the
DC
Step-Up Converter Diode Selection
The REG4 diode must be fast enough to support the
switching frequency (1MHz). Schottky diodes, such as
Central Semiconductor’s CMHSH5-4 or ON Semicon-
ductor’s MBR0530L, are recommended. Make sure that
the diode’s peak-current rating matches or exceeds the
700mA REG4 n-channel current limit. The diode’s aver-
age current rating should match or exceed the output
current. The diode’s reverse breakdown voltage must
exceed the voltage from the converter’s output to
ground. Schottky diodes are preferred due to their low
forward voltage, however, ultra high-speed silicon recti-
fiers are also acceptable.
DC OVLO threshold (5.9V typ) during a fault, the DC
input is disconnected from SYS, the battery charger is
disabled, and CHG is high impedance. BAT is connect-
ed to SYS through the internal system load switch in DC
OVLO mode, allowing the battery to power SYS through
the internal system load switch in DC OVLO mode.
REG1–REG4 are allowed to operate from the battery in
DC OVLO mode. Normal operation resumes when V
falls within its normal operating range.
DC
SYS UVLO
SYS undervoltage lockout (UVLO) prevents the regula-
tors from being used when the input voltage is below
the operating range. When the voltage from SYS to
Step-Up Converter Output Capacitor Selection
For most applications, a 0.1μF ceramic output filter
capacitor is suitable. Choose a voltage rating double
the maximum output voltage to minimize the effect of
the voltage coefficient on decreasing the effective
capacitance. To ensure stability over a wide tempera-
ture range, ceramic capacitors with an X5R or X7R
dielectric are recommended. Place these capacitors as
close as possible to the IC.
GND (V
) is less than the SYS UVLO threshold (2.5V,
SYS
typ), REG1–REG4, the LED current sinks, and the bat-
tery charger are disabled. Additionally, CHG, is high
impedance and RST1 is asserted.
Thermal Limiting and Overload Protection
Smart Power Selector Thermal-Overload Protection
The IC reduces the DC current limit by 5%/°C when the
die temperature exceeds +100°C. The system load
(I
) has priority over the charger current, so input
SYS
______________________________________________________________________________________ 27
PMIC with Integrated Chargers and Smart
Power Selector in a 4mm x 4mm TQFN
OUT_
GATE DRIVE
TO SWITCH
5V/div
0V
R
T
3.35V
3.3V
FB_
500mV/div
3V
3V
V1
RST1
R
B
4.2V
2V/div
R
D
100μs/div
Figure 9. Dynamic Output Voltage Control
Figure 10. Dynamic Voltage Adjustment with Example Values
current is first reduced by lowering charge current. If
the junction temperature still reaches +120°C in spite of
charge current reduction, no input current is drawn
from DC; the battery supplies the entire load and SYS is
regulated 70mV below BAT.
R
is calculated using the higher set voltage and the
D
following equations assuming the switch resistance is
negligible:
R
T
R
=
PAR
V
OUTH
−1
Regulator Thermal-Overload Shutdown
The IC disables all regulator outputs and the battery
charger when the junction temperature rises above
+165°C, allowing the device to cool. When the junction
temperature cools by approximately 15°C the regula-
tors and charger resume the state indicated by the
enable input (EN123, EN4, and CEN) by repeating their
soft-start sequence. Please note that this thermal-over-
load shutdown is a fail-safe mechanism; proper thermal
design should ensure that the junction temperature of
the MAX8819_ never exceeds the absolute maximum
rating of +150°C.
V
FB
1
R
=
D
1
1
R
B
−
R
PAR
where R
is the parallel resistance of R and R ,
B D
PAR
V
is the higher set voltage, and V is the feed-
OUTH
FB
back regulation voltage, 1V (typ).
For example, if V
100kΩ, then:
= 3V, V
= 3.3V, R
=
B
OUTL
OUTH
B/MAX819C
R = 100kΩ x ((3V/1V) - 1) = 200kΩ
T
R
= 200kΩ/((3.3V/1V) - 1) = 86.96kΩ
Applications Information
Dynamic Output Voltage Adjustment
for Step-Down Converters
PAR
R = 1/((1/86.96kΩ) - (1/100kΩ)) = 666.7kΩ
D
Choose R = 665kΩ as the closest standard 1% value.
D
Dynamic output voltage adjustment can be implement-
ed for the step-down converter by adding a resistor
and a switch from FB_ to GND. See Figure 9.
CH1 = gate drive to switch
CH2 = V1, 1V offset; 3V to 3.3V to 3V, 10Ω load
CH3 = RST1
To calculate the resistor-divider, start with the lower
voltage desired and calculate the resistor-divider using
The scope plot (Figure 10) shows V1 switching from 3V
to 3.3V to 3V with the resistor values of the example.
When the switch is turned on, V1 slews from 3V to 3.3V
in about 20μs, which is less than the 50μs RST1 de-
glitch filter, and therefore, RST1 does not trip. When the
switch is turned off, V1 soars to about 3.35V due to the
energy in the inductor. Since V1 is above the regulation
voltage, REG1 skips until V1 decays to the regulation
voltage. The decay rate is determined by the output
capacitance and the load. In this example, the output
capacitance is 10μF and the load is 10Ω, so the time
R and R only. Setting R = 100kΩ is acceptable. Use
T
B
B
the following equation to calculate R :
T
⎛
⎞
V
OUTL
R =R ×
−1
⎟
T
B
⎜
V
⎝
⎠
FB
where V
FB
is the desired lower output voltage and
OUTL
V
is the feedback regulation voltage, 1V (typ).
28 ______________________________________________________________________________________
PMIC with Integrated Chargers and Smart
Power Selector in a 4mm x 4mm TQFN
B/MAX819C
constant is R x C = 100μs, and the output voltage
decays to within 1% of final value in about 500μs.
PCB Layout and Routing
Good printed circuit board (PCB) layout is necessary to
achieve optimal performance. Refer to the MAX8819A
Evaluation Kit for Maxim’s recommended layout.
8819_ETI
TIyww
+ aaaa
Use the following guidelines for the best results:
• The LX_ rapidly switches between PV_ and PG_.
Minimize stray capacitance on LX_ to maintain high
efficiency.
• Keep the FB_ node away from noise sources such
as the inductor.
Figure 11. Package Marking Example
• The exposed pad (EP) is the main path for heat to
exit the IC. Connect EP to the ground plane with
thermal vias to allow heat to dissipate from the
device.
Pin Configuration
TOP VIEW
• Use short and wide traces for high-current and dis-
continuous current paths.
21 20 19 18 17 16 15
• The step-down converter power inputs are critical
discontinuous current paths that require careful
bypassing. Place the step-down converter input
bypass capacitor as close as possible to the PV_
and PG_ pins.
• Minimize the area of the loops formed by the step-
down converters’ dynamic switching currents.
14
13
FB2 22
FB3 23
CISET
FB1
12 CEN
24
25
26
27
28
EN123
MAX8819A
MAX8819B
MAX8819C
DC
11
10
9
PV2
LX2
SYS
BAT
RST1
PG2
Package Marking
The top of the MAX8819_ package is laser etched as
shown in Figure 11:
8
DLIM2
EXPOSED PAD (EP)
+
1
2
3
4
5
6
7
“8819_ETI” is the product identification code. The full
part number is MAX8819_ETI; however, in this case, the
“MAX” prefix is omitted due to space limitations. The “_”
corresponds to the “A” or “B” version.
“yww” is a date code. “y” is the last number in the
Gregorian calendar year. “ww” is the week number in
the Gregorian calendar. For example:
Chip Information
PROCESS: S45T
• “801” is the first week of 2008; the week of
January 1st, 2008.
Package Information
• “052” is the fifty-second week of 2010; the week of
December 27th, 2010.
For the latest package outline information and land patterns, go
to www.maxim-ic.com/packages.
• “aaaa” is an assembly code and lot code.
PACKAGE TYPE PACKAGE CODE DOCUMENT NO.
• “+” denotes lead-free packaging and marks the
pin 1 location.
28 TQFN-EP
T2844+1
21-01±9
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 29
© 2009 Maxim Integrated Products
Maxim is a registered trademark of Maxim Integrated Products, Inc.
相关型号：
MAX8819DETI+
Power Supply Management Circuit, Adjustable, 3 Channel, 4 X 4 MM, ROHS COMPLIANT, TQFN-28
MAXIM
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