MAX8791GTA+ [MAXIM]
Single-Phase, Synchronous MOSFET Drivers; 单相同步MOSFET驱动器
| 型号： | MAX8791GTA+ |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Single-Phase, Synchronous MOSFET Drivers |
| 文件： | 总12页 (文件大小：219K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-0628; Rev 2; 1/10
Single-Phase, Synchronous MOSFET Drivers
/MAX8791B
General Description
Features
The MAX8791/MAX8791B are single-phase, synchro-
nous, noninverting MOSFET drivers. The MAX8791/
MAX8791B are intended to work with controller ICs like
the MAX8736 or MAX8786, in multiphase notebook
CPU core regulators.
o
o
o
o
o
o
o
o
o
Single-Phase, Synchronous MOSFET Drivers
0.5Ω Low-Side On-Resistance
0.7Ω High-Side On-Resistance
8ns Propagation Delay
The regulators can either step down directly from the
battery voltage to create the core voltage, or step down
from the main system supply. The single-stage conver-
sion method allows the highest possible efficiency, while
the 2-stage conversion at higher switching frequency
provides the minimum possible physical size.
15ns Minimum Guaranteed Dead Time
Integrated Boost “Diode”
2V to 24V Input Voltage Range
Selectable Pulse-Skipping Mode
Low-Profile TQFN Package
The low-side drivers are optimized to drive 3nF capaci-
tive loads with 4ns/8ns typical fall/rise times, and the
high-side driver with 8ns/10ns typical fall/rise times.
Adaptive dead-time control prevents shoot-through cur-
rents and maximizes converter efficiency.
The MAX8791/MAX8791B are available in a small, lead-
free, 8-pin, 3mm x 3mm TQFN package.
Ordering Information
Applications
Notebooks/Desktops/Servers
CPU Core Power Supplies
PART
TEMP RANGE
PIN-PACKAGE
MAX8791GTA+
MAX8791BGTA+
-40oC to +105oC
-40oC to +105oC
8 TQFN-EP*
8 TQFN-EP*
Multiphase Step-Down Converters
+Denotes a lead(Pb)-free/RoHS-compliant package.
*EP = Exposed pad.
Typical Operating Circuit
Pin Configuration
INPUT (V )*
IN
5V TO 24V
TOP VIEW
PWM
DH
6
5
MAX8791
MAX8791B
LX
7
8
4
3
DL
BST
LX
SKIP
V
(1.45V
AT 20A)
MAX8791
MAX8791B
PWM
SKIP
OUT
DH
GND
+5V BIAS
SUPPLY
+
V
DD
1
2
DL
GND
TQFN
3mm × 3mm
PAD
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
Single-Phase, Synchronous MOSFET Drivers
ABSOLUTE MAXIMUM RATINGS
DD
V
to GND...............…………………….………….. -0.3V to +6V
Continuous Power Dissipation (T = +70°C)
A
SKIP to GND..................………………………………-0.3V to +6V
PWM to GND................……………………………….-0.3V to +6V
8-Pin 3mm x 3mm TQFN
(derate 23.8mW/°C above +70°C).............................1904mW
Operating Temperature Range .........................-40°C to +105°C
Junction Temperature......................................................+150°C
Storage Temperature Range.............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Soldering Temperature (reflow) .......................................+260°C
DL to GND..................................................-0.3V to (V
+ 0.3V)
DD
BST to GND............................................................-0.3V to +36V
DH to LX....................................................-0.3V to (V + 0.3V)
BST
BST to V .............................................................-0.3V to +30V
DD
BST to LX................…………………………………...-0.3V to +6V
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(Circuit of Figure 1, V
= V
= 5V, T = -40°C to +105°C, unless otherwise noted. Typical values are at T = +25°C.) (Note 1)
SKIP A A
DD
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX UNITS
Input Voltage Range
V
4.20
5.50
V
DD
Rising edge, PWM disabled below this level
Falling edge, PWM disabled below this level
PWM = open; after the shutdown hold time has expired
3.7
3.5
V
Undervoltage
DD
V
V
UVLO(VDD)
Lockout Threshold
3.0
4.0
0.2
/MAX8791B
0.08
Quiescent Supply
SKIP = GND, PWM = GND,
LX = GND (after zero crossing)
0.25
0.6
0.5
1.5
I
mA
ns
DD
Current (V
)
DD
SKIP = GND or V , PWM = V , V
= 5V
DD
DD BST
DRIVERS
t
Minimum on-time
Minimum off-time
50
300
10
ON(MIN)
PWM Pulse Width
t
OFF(MIN)
DL Propagation Delay
DH Propagation Delay
t
PWM high to DL low
PWM low to DH low
ns
ns
PWM-DL
t
14
PWM-DH
T
T
T
T
= 0°C to +85°C
15
15
15
15
30
A
A
A
A
DL-to-DH Dead Time
DH-to-DL Dead Time
DL Transition Time
DH Transition Time
t
t
DL falling to DH rising
DH falling to DL rising
ns
ns
ns
ns
Ω
DL-DH
DH-DL
= -40°C to +105°C
= 0°C to +85°C
30
= -40°C to +105°C
t
Falling, 3.0nF load
Rising, 3.0nF load
Falling, 3.0nF load
Rising, 3.0nF load
12
14
8
F_DL
R_DL
F_DH
R_DH
t
t
t
10
0.9
0.7
0.7
0.5
2.2
2.7
2.7
8
DH, high state (pullup)
DH, low state (pulldown)
2.5
2.3
1.8
1.2
DH Driver On-Resistance
DL Driver On-Resistance
R
BST-LX forced to 5V
ON(DH)
DL, high state (pullup)
DL, low state (pulldown)
R
Ω
ON(DL)
DH Driver Source Current
DH Driver Sink Current
DL Driver Source Current
DL Driver Sink Current
Zero-Crossing Threshold
Boost On-Resistance
I
I
DH forced to 2.5V, BST - LX forced to 5V
DH forced to 2.5V, BST - LX forced to 5V
DL forced to 2.5V
A
A
DH_SOURCE
I
DH_SINK
A
DL_SOURCE
I
DL forced to 2.5V
A
DL_SINK
V
GND - LX, SKIP = GND
3
mV
Ω
ZX
ON(BST)
R
V
DD
= 5V, DH = LX = GND (pulldown state), I
= 10mA
5
12
BST
2
_______________________________________________________________________________________
Single-Phase, Synchronous MOSFET Drivers
/MAX8791B
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, V
= V
= 5V, T = -40°C to +105°C, unless otherwise noted. Typical values are at T = +25°C.) (Note 1)
SKIP A A
DD
PARAMETER
SYMBOL
CONDITIONS
High (DH = high; DL = low)
MIN
TYP
MAX UNITS
V
-
DD
0.4
PWM Input Levels
V
V
- 0.4
/2
V
+ 0.4
/2
DD
DD
Midlevel
Low (DH = low; DL = high)
0.4
-80
400
Sink; PWM forced to V
-400
80
-200
DD
PWM Input Current
I
µA
ns
PWM
Source; PWM forced to GND
+200
Midlevel Shutdown Hold
Time
t
120
300
600
2.4
MID
Rising edge
Falling edge
1.7
1.5
-2
SKIP Input Threshold
SKIP Input Current
V
0.8
-4
I
Sink; SKIP forced to 0.8V to V , T = +25°C
-0.5
µA
°C
SKIP
DD
A
Thermal-Shutdown
Threshold
T
Hysteresis = 20°C
+160
SHDN
Note 1: Limits are 100% production tested at T = +25°C. Maximum and minimum limits over temperature are guaranteed through
A
correlation using statistical-quality-control (SQC) methods.
Typical Operating Characteristics
(Circuit of Figure 1, V
= 5V, C = 3nF, C = 3nF, T = +25°C, unless otherwise noted.)
DD
DH
DL
A
PACKAGE-POWER DISSIPATION
vs. CAPACITIVE LOAD ON DH AND DL
PACKAGE-POWER DISSIPATION
vs. PWM FREQUENCY
DL RISE AND FALL TIMES
vs. CAPACITIVE LOAD
500
450
400
350
300
250
200
150
100
50
300
250
200
150
100
50
30
25
20
15
10
5
C
B
A
RISE TIME
B
A
FALL TIME
A: 300kHz
B: 600kHz
C: 1MHz
A: C = 3.3nF; C = 3.3nF
B: C = 1.5nF; C = 6.8nF
DH
DH
DL
DL
C
= C
DH
DL
0
0
0
1000 2500 4000 5500 7000 8500 10,000
CAPACITANCE (pF)
0
200
400
600
800 1000 1200
1000 2500 4000 5500 7000 8500 10,000
CAPACITANCE (pF)
PWM FREQUENCY (kHz)
_______________________________________________________________________________________
3
Single-Phase, Synchronous MOSFET Drivers
Typical Operating Characteristics (continued)
(Circuit of Figure 1, V
= 5V, C = 3nF, C = 3nF, T = +25°C, unless otherwise noted.)
DD
DH
DL
A
DH AND DL RISE AND FALL TIMES
vs. TEMPERATURE
PACKAGE-POWER DISSIPATION
vs. PWM FREQUENCY
DH RISE AND FALL TIMES
vs. CAPACITIVE LOAD
40
35
30
25
20
15
10
40
35
30
25
20
15
10
5
60
50
40
30
20
10
0
B
A
DL RISE
RISE TIME
DH RISE
DH FALL
FALL TIME
DL FALL
DL IS DRIVING 2 SI7336ADP
DH IS DRIVING 1 SI7892ADP
A: C = 3.3nF; C = 3.3nF
B: C = 1.5nF; C = 6.8nF
DH
DH
DL
DL
C
= C
DH
DL
0
-40
-15
10
35
60
85
110
1000 2500 4000 5500 7000 8500 10,000
CAPACITANCE (pF)
0
200
400
600
800 1000 1200
TEMPERATURE (°C)
PWM FREQUENCY (kHz)
/MAX8791B
PROPAGATION DELAY TIME
vs. TEMPERATURE
TYPICAL APPLICATION CIRCUIT
SWITCHING WAVEFORMS
MAX8791 toc08
16
15
14
13
12
11
10
9
PWM FALL TO DH FALL
5V/div
V
PWM
10V/div
V
LX
PWM RISE TO DL FALL
5V/div
V
V
DL
20V/div
DH
8
-40
-15
10
35
60
85
110
100ns/div
TEMPERATURE (°C)
DH RISE AND DL FALL WAVEFORMS
DH FALL AND DL RISE WAVEFORMS
MAX8791 toc10
MAX8791 toc09
5V/div
V
5V/div
PWM
V
PWM
10V/div
10V/div
V
LX
V
LX
V
5V/div
DL
V
5V/div
DL
10V/div
10V/div
V
DH
V
DH
20ns/div
20ns/div
4
_______________________________________________________________________________________
Single-Phase, Synchronous MOSFET Drivers
/MAX8791B
Typical Operating Characteristics (continued)
= 5V, C = 3nF, C = 3nF, T = +25°C, unless otherwise noted.)
DH DL A
(Circuit of Figure 1, V
DD
SWITCHING WAVEFORMS
SWITCHING WAVEFORMS
(PWM = MID TO LOW TO MID)
(PWM = HIGH TO MID TO HIGH)
MAX8791 toc11
MAX8791 toc12
5V
5V/div
0
5V
5V/div
V
PWM
V
PWM
0
V
DL
0
5V
5V/div
V
DL
5V/div
0
10V
10V/div
0
V
LX
0
V
LX
10V/div
15V
V
DH
10V/div
0
0
V
DH
10V/div
Pin Description
PIN
NAME
FUNCTION
Boost Flying-Capacitor Connection. Gate-drive power supply for DH high-side gate driver. Connect a 0.1µF or
0.22µF capacitor between BST and LX.
1
BST
PWM Input Pin. Noninverting DH control input from the controller IC:
Logic high: DH = high (BST), DL = low (PGND).
Midlevel: After the midlevel hold time expires, the controller enters standby mode. DH and DL pulled low.
2
PWM
Logic low: DH = low (LX), DL = high (V ) when SKIP = high.
DD
Internal pullup and pulldown resistors create the midlevel and prevent the controller from triggering an on-time if
this input is left unconnected (not soldered properly) or driven by a high impedance.
3
4
GND
DL
Power Ground for the DL Gate Drivers and Analog Ground. Connect exposed pad to GND.
PWM Low-Side Gate-Driver Output. Swings between GND and V . DL forced high in shutdown.
DD
Supply Voltage Input for the DL Gate Drivers. Connect to 4.2V to 5.5V supply and bypass to GND with a 1µF
ceramic capacitor.
5
6
7
V
DD
Pulse-Skipping Mode Pin. Enable pulse-skipping mode (zero-crossing comparator enabled) when the driver is
operating in SKIP mode:
SKIP = V
PWM mode
DD
SKIP
SKIP = GND SKIP mode
An internal pulldown current pulls the controller into the low-power pulse-skipping state if this input is left
unconnected (not soldered properly) or driven by a high impedance.
Switching Node and Inductor Connection. Low-power supply for the DH high-side gate driver. LX connects to
the skip-mode zero-crossing comparator.
LX
8
DH
EP
External High-Side nMOSFET Gate-Driver Output. Swings between LX and BST.
—
Exposed Pad. Connect to ground through multiple vias to reduce the thermal impedance.
_______________________________________________________________________________________
5
Single-Phase, Synchronous MOSFET Drivers
PWM
SKIP
DH
C
3nF
DH
BST
C
0.1µF
BST
MAX8791
MAX8791B
LX
DL
PWM SKIP
C
DL
3nF
+5V BIAS
SUPPLY
V
DD
GND
C1
1.0µF
PAD
Figure 1. Test Circuit
/MAX8791B
t
t
PWM-DH
t
PWM-DL
MID
t
t
PWM-DL
MID
PWM
t
t
t
t
R_DL
F_DL
R_DL
F_DL
DL
t
t
DH-DL
DL-DH
DH
t
R_DH
t
t
t
R_DH
R_DH
R_DH
t
PWM-DH
Figure 2. Timing Diagram
_______________________________________________________________________________________
6
Single-Phase, Synchronous MOSFET Drivers
/MAX8791B
INPUT (V )
IN
C
IN
2x 10µF
PWM
SKIP
DH
N
H
L1
0.36µH
BST
LX
C
BST
PWM SKIP
0.22µF
MAX8791
OUTPUT (V
)
OUT
+5V BIAS
SUPPLY
V
DD
MAX8791B
C
OUT
CV
1.0µF
2x 330µF
DD
DL
N
L
D
L
6mΩ
GND
PAD
Figure 3. Typical MOSFET-Driver Application Circuit
Table 1. Typical Components
DESIGNATION
QTY
COMPONENT SUPPLIERS
N
N
1 per phase
1–2 per phase
1 per phase
Optional
Siliconix Si4860DY
H
L
Siliconix Si4336DY
BST Capacitor (C
Schottky Diode
Inductor (L1)
)
0.1µF or 0.22µF ceramic capacitor
3A, 40V Schottky diode
BST
1 per phase
1–2 per phase
1–2 per phase
0.36µH, 26A, 0.9mΩ power inductor
330µF, 6mΩ per phase
Output Capacitors (C
)
OUT
Input Capacitors (C
)
10µF, 25V X5R ceramic capacitors
IN
PWM Input
Detail Description
The drivers for the MAX8791/MAX8791B are disabled—
DH and DL pulled low—if the PWM input remains in the
midlevel window for at least 300ns (typ). Once the
PWM signal is driven high or low, the MAX8791/
MAX8791B immediately exit the low-current shutdown
state and resume active operation. Outside the shut-
down state, the drivers are enabled based on the rising
and falling thresholds specified in the Electrical
Characteristics.
The MAX8791/MAX8791B single-phase gate drivers,
along with the MAX8736 or MAX8786 multiphase con-
trollers, provide flexible multiphase CPU core-voltage
supplies. The low driver resistance allows up to 7A out-
put peak current. Each MOSFET driver in the
MAX8791/MAX8791B is capable of driving 3nF capaci-
tive loads with only 9ns propagation delay and 4ns/8ns
(typ) fall/rise times, allowing operation up to 3MHz per
phase. Larger capacitive loads are allowable but result
in longer propagation and transition times. Adaptive
dead-time control prevents shoot-through currents and
maximizes converter efficiency while allowing operation
with a variety of MOSFETs and PWM controllers. An
input undervoltage lockout (UVLO) circuit allows proper
power-on sequencing.
MOSFET Gate Drivers (DH, DL)
The high-side driver (DH) has a 0.9Ω sourcing resis-
tance and 0.7Ω sinking resistance, resulting in 2.2A
peak sourcing current and 2.7A peak sinking current
with a 5V supply voltage. The low-side driver (DL) has a
typical 0.7Ω sourcing resistance and 0.3Ω sinking
resistance, yielding 2.7A peak sourcing current and 8A
peak sinking current. This reduces switching losses,
making the MAX8791/MAX8791B ideal for both high-
frequency and high output-current applications.
_______________________________________________________________________________________
7
Single-Phase, Synchronous MOSFET Drivers
V
DD
BST
DH
LX
PWM
DRV
DRIVER LOGIC
AND
DEAD-TIME
CONTROL
THERMAL SHUTDOWN
UVLO
DRV#
V
DD
SKIP
DL
LX
GND
/MAX8791B
ZX DETECTION
PAD
Figure 4. Overview Block Diagram
Adaptive Shoot-Through Protection
The DH and DL drivers are optimized for driving mod-
erately sized high-side and larger low-side power
MOSFETs. This is consistent with the low duty factor
seen in the notebook CPU environment, where a large
MOSFET gates as off while charge actually remains.
Use very short, wide traces (50 mils to 100 mils wide if
the MOSFET is 1in from the driver).
Internal Boost Switch
The MAX8791/MAX8791B use a bootstrap circuit to
generate the necessary drive voltage to fully enhance
the high-side n-channel MOSFET. The internal p-chan-
nel MOSFET creates an ideal diode, providing a low
V
- V
differential exists. Two adaptive dead-time
OUT
IN
circuits monitor the DH and DL outputs and prevent the
opposite-side FET from turning on until the other is fully
off. The MAX8791/MAX8791B constantly monitor the
low-side driver output (DL) voltage, and only allow the
high-side driver to turn on when DL drops below the
adaptive threshold. Similarly, the controller monitors the
high-side driver output (DH), and prevents the low side
from turning on until DH falls below the adaptive thresh-
old before allowing DL to turn on.
voltage drop between V
and BST.
DD
The selected high-side MOSFET determines appropriate
boost capacitance values (C
to the following equation:
in Figure 1), according
BST
C
= Q
∆V
BST
GATE
BST
The adaptive driver dead time allows operation without
shoot-through with a wide range of MOSFETs, minimiz-
ing delays and maintaining efficiency. There must be a
low-resistance, low-inductance path from the DL and
DH drivers to the MOSFET gates for the adaptive dead-
time circuits to work properly; otherwise, the sense cir-
cuitry in the MAX8791/MAX8791B interprets the
where Q
is the total gate charge of the high-side
GATE
MOSFET and ∆V
is the voltage variation allowed on
BST
the high-side MOSFET driver. Choose ∆V
0.2V when determining C
should be a low equivalent-series resistance (ESR)
ceramic capacitor.
= 0.1V to
BST
. The boost flying capacitor
BST
8
_______________________________________________________________________________________
Single-Phase, Synchronous MOSFET Drivers
/MAX8791B
losses at V
, consider reducing the size of N
H
5V Bias Supply (V
)
IN(MIN)
(increasing R
DD
but reducing C
). If V does
V
provides the supply voltage for the internal logic cir-
DS(ON)
GATE IN
DD
not vary over a wide range, the minimum power dissi-
pation occurs where the resistive losses equal the
switching losses. Choose a low-side MOSFET that has
cuits. Bypass V
with a 1µF or larger ceramic capaci-
tor to GND to limit noise to the internal circuitry. Connect
these bypass capacitors as close as possible to the IC.
DD
the lowest possible on-resistance (R
), comes in
DS(ON)
Input Undervoltage Lockout
a moderate-sized package (i.e., one or two 8-pin SOs,
DPAK, or D2PAK), and is reasonably priced. Ensure
that the DL gate driver can supply sufficient current to
support the gate charge and the current injected into
the parasitic gate-to-drain capacitor caused by the
high-side MOSFET turning on; otherwise, cross-con-
duction problems can occur.
When V
are held low. Once V
is below the UVLO threshold, DH and DL
DD
is above the UVLO threshold
DD
and while PWM is low, DL is driven high and DH is
driven low. This prevents the output of the converter
from rising before a valid PWM signal is applied.
Low-Power Pulse Skipping
The MAX8791/MAX8791B enter into low-power pulse-
skipping mode when SKIP is pulled low. In skip mode,
an inherent automatic switchover to pulse-frequency
modulation (PFM) takes place at light loads. A zero-
crossing comparator truncates the low-side switch on-
time at the inductor current’s zero crossing. The
comparator senses the voltage across LX and GND.
MOSFET Power Dissipation
Worst-case conduction losses occur at the duty factor
extremes. For the high-side MOSFET (N ), the worst-
H
case power dissipation due to resistance occurs at the
minimum input voltage:
2
⎛
⎞ ⎛
⎞
V
V
I
LOAD
η
TOTAL
OUT
PD (N RESISTIVE)=
R
DS(ON)
H
⎜
⎟ ⎜
⎟
Once V - V
drops below the zero-crossing com-
GND
LX
⎝
⎠ ⎝
⎠
IN
parator threshold (see the Electrical Characteristics),
the comparator forces DL low. This mechanism causes
the threshold between pulse-skipping PFM and non-
skipping PWM operation to coincide with the boundary
between continuous and discontinuous inductor-cur-
rent operation. The PFM/PWM crossover occurs when
the load current of each phase is equal to 1/2 the peak-
to-peak ripple current, which is a function of the induc-
tor value. For a battery input range of 7V to 20V, this
threshold is relatively constant, with only a minor
dependence on the input voltage due to the typically
low duty cycles. The switching waveforms may appear
noisy and asynchronous when light loading activates
the pulse-skipping operation, but this is a normal oper-
ating condition that results in high light-load efficiency.
where η
is the total number of phases. Generally,
TOTAL
a small high-side MOSFET is desired to reduce switch-
ing losses at high input voltages. However, the R
DS(ON)
required to stay within package-power dissipation often
limits how small the MOSFETs can be. Again, the opti-
mum occurs when the switching losses equal the con-
duction (R
) losses. High-side switching losses
DS(ON)
do not usually become an issue until the input is
greater than approximately 15V.
Calculating the power dissipation in high-side
MOSFETs (N ) due to switching losses is difficult since
H
it must allow for difficult quantifying factors that influ-
ence the turn-on and turn-off times. These factors
include the internal gate resistance, gate charge,
threshold voltage, source inductance, and PCB layout
characteristics.
Applications Information
Power-MOSFET Selection
Most of the following MOSFET guidelines focus on the
challenge of obtaining high load-current capability
when using high-voltage (> 20V) AC adapters. Low-
current applications usually require less attention. The
The following switching-loss calculation provides only a
very rough estimate and is no substitute for prototype
evaluation, preferably including verification using a
thermocouple mounted on N :
H
high-side MOSFET (N ) must be able to dissipate the
H
V
I
f
Q
⎛
⎞ ⎛
⎟ ⎜
⎞
IN(MAX)LOAD SW
G(SW)
PD (N SWITCHING) =
+
H
⎜
⎝
⎟
⎠
resistive losses plus the switching losses at both
n
⎠ ⎝ I
TOTAL
2
GATE
V
and V
. Calculate both these sums.
IN(MAX)
IN(MIN)
Ideally, the losses at V
C
V
f
should be roughly equal
OSS IN SW
2
IN(MIN)
to losses at V
the losses at V
losses at V
(reducing R
if the losses at V
, with lower losses in between. If
are significantly higher than the
IN(MAX)
IN(MIN)
IN(MAX)
DS(ON)
where C
G(SW)
MOSFET, and I
current (5A typ).
is the N MOSFET’s output capacitance,
H
OSS
, consider increasing the size of N
H
Q
is the charge needed to turn on the high-side
but increasing C
). Conversely,
GATE
is the peak gate-drive source/sink
GATE
are significantly higher than the
IN(MAX)
_______________________________________________________________________________________
9
Single-Phase, Synchronous MOSFET Drivers
Switching losses in the high-side MOSFET can become
an insidious heat problem when maximum AC adapter
voltages are applied due to the squared term in the
switching-loss equation above. If the high-side MOSFET
where PD(IC) is the power dissipated by the device,
and Θ is the package’s thermal resistance. The typi-
JA
cal thermal resistance is 42°C/W for the 3mm x 3mm
TQFN package.
chosen for adequate R
at low battery voltages
DS(ON)
Avoiding dV/dt Turning on the
Low-Side MOSFET
At high input voltages, fast turn-on of the high-side
MOSFET can momentarily turn on the low-side MOSFET
due to the high dV/dt appearing at the drain of the low-
side MOSFET. The high dV/dt causes a current flow
becomes extraordinarily hot when biased from V
,
IN(MAX)
consider choosing another MOSFET with lower parasitic
capacitance.
For the low-side MOSFET (N ), the worst-case power
L
dissipation always occurs at the maximum input voltage:
2
through the Miller capacitance (C
) and the input
RSS
⎡
⎤
⎥
⎛
⎞
⎟
⎛
⎞
V
I
LOAD
η
TOTAL
OUT
capacitance (C ) of the low-side MOSFET. Improper
ISS
PD (N RESISTIVE) = 1−
R
DS(ON)
⎢
L
⎜
⎝
⎟
⎠
⎜
V
⎝
IN(MAX) ⎠
⎢
⎣
⎥
⎦
selection of the low-side MOSFET that results in a high
ratio of C
/C
makes the problem more severe. To
RSS ISS
The worst case for MOSFET power dissipation occurs
under heavy load conditions that are greater than
avoid this problem, minimize the ratio of C
/C
RSS ISS
when selecting the low-side MOSFET. Adding a 1Ω to
4.7Ω resistor between BST and C can slow the
I
, but are not quite high enough to exceed the
LOAD(MAX)
BST
current limit and cause the fault latch to trip. The
MOSFETs must have a good-sized heatsink to handle the
overload power dissipation. The heat sink can be a large
copper field on the PCB or an externally mounted device.
high-side MOSFET turn-on. Similarly, adding a small
capacitor from the gate to the source of the high-side
MOSFET has the same effect. However, both methods
work at the expense of increased switching losses.
/MAX8791B
An optional Schottky diode only conducts during the
dead time when both the high-side and low-side
MOSFETs are off. Choose a Schottky diode with a
forward voltage low enough to prevent the low-side
MOSFET body diode from turning on during the dead
time, and a peak current rating higher than the peak
inductor current. The Schottky diode must be rated to
handle the average power dissipation per switching
cycle. This diode is optional and can be removed if effi-
ciency is not critical.
Layout Guidelines
The MAX8791/MAX8791B MOSFET driver sources and
sinks large currents to drive MOSFETs at high switch-
ing speeds. The high di/dt can cause unacceptable
ringing if the trace lengths and impedances are not well
controlled. The following PCB layout guidelines are rec-
ommended when designing with the MAX8791/
MAX8791B:
1) Place all decoupling capacitors as close as possi-
ble to their respective IC pins.
IC Power Dissipation and
Thermal Considerations
Power dissipation in the IC package comes mainly from
driving the MOSFETs. Therefore, it is a function of both
switching frequency and the total gate charge of the
selected MOSFETs. The total power dissipation when
both drivers are switching is given by:
2) Minimize the length of the high-current loop from
the input capacitor, the upper switching MOSFET,
and the low-side MOSFET back to the input-capacitor
negative terminal.
3) Provide enough copper area at and around the
switching MOSFETs and inductors to aid in thermal
dissipation.
4) Connect GND of the MAX8791/MAX8791B as close
as possible to the source of the low-side MOSFETs.
PD(IC) = I
× 5V
BIAS
where I
is the bias current of the 5V supply calcu-
lated in the 5V Bias Supply (V ) section. The rise in
BIAS
A sample layout is available in the MAX8786 evaluation kit.
DD
die temperature due to self-heating is given by the
following formula:
∆T = Θ × PD(IC)
J
JA
10 ______________________________________________________________________________________
Single-Phase, Synchronous MOSFET Drivers
/MAX8791B
Package Information
Chip Information
For the latest package outline information and land patterns, go
to www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in
the package code indicates RoHS status only. Package draw-
ings may show a different suffix character, but the drawing per-
tains to the package regardless of RoHS status.
PROCESS: BiCMOS
PACKAGE TYPE PACKAGE CODE DOCUMENT NO.
8 TDFN-EP
TQ833+1
21-0136
______________________________________________________________________________________ 11
Single-Phase, Synchronous MOSFET Drivers
Revision History
REVISION
NUMBER
REVISION
DATE
PAGES
CHANGED
DESCRIPTION
0
1
2
8/06
11/06
1/10
Initial release
—
Updated Electrical Characteristics and PWM Input section.
3, 7
1–12
Added the MAX8791B to entire data sheet.
/MAX8791B
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
12 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2010 Maxim Integrated Products
Maxim is a registered trademark of Maxim Integrated Products, Inc.
相关型号：
MAX8792ETD+T
Switching Controller, Current-mode, 3A, BICMOS, PDSO14, 3 X 3 MM, ROHS COMPLIANT, TDFN-14
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