MAX793CPE [MAXIM]
3.0V/3.3V Adjustable Microprocessor Supervisory Circuits; 3.0V / 3.3V可调微处理器监控电路
| 型号： | MAX793CPE |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | 3.0V/3.3V Adjustable Microprocessor Supervisory Circuits |
| 文件： | 总20页 (文件大小：151K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-0366; Rev 1; 1/96
3 .0 V/3 .3 V Ad ju s t a b le Mic ro p ro c e s s o r
S u p e rvis o ry Circ u it s
34/MAX795
_______________Ge n e ra l De s c rip t io n
____________________________Fe a t u re s
MAX793/MAX794/MAX795
The MAX793/MAX794/MAX795 microprocessor (µP)
supervisory circuits monitor and control the activities of
+3.0V/+3.3V µPs by providing backup-battery switchover,
among other features such as low-line indication, µP
reset, write protection for CMOS RAM, and a watchdog
(see the Selector Guide below). The backup-battery volt-
♦ Precision Supply-Voltage Monitor:
Fixed Reset Trip Voltage (MAX793/MAX795)
Adjustable Reset Trip Voltage (MAX794)
♦ Guaranteed Reset Assertion to V
= 1V
CC
♦ Backup-Battery Power Switching—Battery
Voltage Can Exceed V
age can exceed V , permitting the use of 3.6V lithium
CC
CC
batteries in systems using 3.0V to 3.3V for V
.
CC
♦ On-Board Gating of Chip-Enable Signals—7ns
The MAX793/MAX795 offer a choice of reset threshold
voltage range (denoted by suffix letter): 3.00V to 3.15V
(T), 2.85V to 3.00V (S), and 2.55V to 2.70V (R). The
MAX794’s reset threshold is set externally with a resistor
divider. The MAX793/MAX794 are available in 16-pin
DIP and narrow SO packages, and the MAX795 comes
in 8-pin DIP and SO packages. For similar devices
d e s ig ne d for 5V s ys te ms , s e e the µP Sup e rvis ory
Circuits table at the back of this data sheet.
Max Propagation Delay
MAX793/MAX794 Only
♦ Battery Freshness Seal
♦ Battery OK Output (MAX793)
♦ Uncommitted Voltage Monitor for Power-Fail or
Low-Battery Warning
♦ Independent Watchdog Timer (1.6sec timeout)
♦ Manual Reset Input
_____________________S e le c t o r Gu id e
______________Ord e rin g In fo rm a t io n
FEATURE
Active-Low Reset
Active-High Reset
MAX793
MAX794 MAX795
PART*
TEMP. RANGE
0°C to +70°C
PIN-PACKAGE
16 Plastic DIP
16 Narrow SO
16 Plastic DIP
16 Narrow SO
✔
✔
✔
✔
MAX793_CPE
MAX793_CSE
MAX793_EPE
MAX793_ESE
✔
0°C to +70°C
Programmable Reset
Threshold
-40°C to +85°C
-40°C to +85°C
✔
✔
✔
Low-Line Early Warning
Output
Ordering Information continued on last page.
✔
✔
* The MAX793/MAX795 offer a choice of reset threshold voltage.
Select the letter corresponding to the desired reset threshold
voltage range (T = 3.00V to 3.15V, S = 2.85V to 3.00V, R = 2.55V
to 2.70V) and insert it into the blank to complete the part number.
The MAX794’s reset threshold is adjustable.
Backup-Battery
Switchover
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
External Switch Driver
Power-Fail Comparator
Battery OK Output
Watchdog Input
__________Typ ic a l Op e ra t in g Circ u it
✔
✔
✔
✔
(OPTIONAL)
Si9433DY
SILICONIX
Battery Freshness Seal
Manual Reset Input
Chip-Enable Gating
Pins-Package
3.0V OR 3.3V
✔
0.1µF
0.1µF
PMOS
16-DIP/SO 16-DIP/SO 8-DIP/SO
V
BATT ON OUT
CC
CMOS
RAM
BATT
CE OUT
________________________Ap p lic a t io n s
Battery-Powered Computers and Controllers
Embedded Controllers
0.1µF
3.6V
V
CC
MAX793
ADDRESS
DECODER
A0-A15
CE IN
WDO
MR
I/O
NMI
WDI
+5V SUPPLY
FAILURE
Intelligent Controllers
LOWLINE
PFO
+5V
V
CC
µP
Critical µP Power Monitoring
Portable Equipment
PFI
RESET
RESET
BATT OK
GND
Pin Configurations appear at end of data sheet.
________________________________________________________________ Maxim Integrated Products
1
For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800
3 .0 V/3 .3 V Ad ju s t a b le Mic ro p ro c e s s o r
S u p e rvis o ry Circ u it s
ABSOLUTE MAXIMUM RATINGS
Terminal Voltage (with respect to GND)
Continuous Power Dissipation (T = +70°C)
A
V
........................................................................-0.3V to 6.0V
.....................................................................-0.3V to 6.0V
8-Pin Plastic DIP (derate 9.09mW/°C above +70°C) .....727mW
8-Pin SO (derate 5.88mW/°C above +70°C)..................471mW
16-Pin Plastic DIP (derate 10.53mW/°C above +70°C) .842mW
16-Pin Narrow SO (derate 9.52mW/°C above +70°C) ...696mW
Operating Temperature Ranges
CC
V
BATT
All Other Inputs ..................-0.3V to the higher of V or V
CC
BATT
Continuous Input Current
.................................................................................200mA
V
CC
V
................................................................................50mA
MAX793_C_ _/MAX794C_ _/MAX795_C_ _ ......... 0°C to +70°C
MAX793_E_ _/MAX794E_ _/MAX795_E_ _ ........-40°C to +85°C
Storage Temperature Range .............................-65°C to +160°C
Lead Temperature (soldering, 10sec) .............................+300°C
BATT
GND ..................................................................................20mA
Output Current
V
OUT
................................................................................200mA
All Other Outputs ..............................................................20mA
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
CC
(V
= 3.17V to 5.5V for the MAX793T/MAX795T, V
= 3.02V to 5.5V for the MAX793S/MAX795S, V
= 2.72V to 5.5V for the
CC
CC
MAX793R/MAX794/MAX795R, V
= 3.6V, T = T
to T , unless otherwise noted. Typical values are at T = +25°C.)
MAX A
BATT
A
MIN
PARAMETER
SYMBOL
CONDITIONS
MIN
1.0
TYP
MAX
5.5
5.5
60
UNITS
MAX79_C
MAX79_E
Operating Voltage Range,
V
V
, V
CC BATT
(Note 1)
1.1
V
< 3.6V
< 5.5V
< 3.6V
< 5.5V
46
62
35
49
CC
MAX793/MAX794,
MR = V
CC
V
CC
80
V
CC
Supply Current
I
µA
SUPPLY
7
(excluding I
, I
)
OUT CE OUT
V
CC
50
MAX795
V
CC
70
V
Supply Current in
CC
MAX793/MAX794
MAX795
32
24
45
35
V
V
BATT
= 2.1V,
= 2.3V
CC
Battery-Backup Mode
(excluding I
I
µA
SUPPLY
)
OUT
BATT Supply Current
(excluding I ) (Note 2)
1
1
µA
µA
µA
OUT
BATT Leakage Current,
Freshness Seal Enabled
V
CC
= 0V, V
= 0V
OUT
Battery Leakage Current
(Note 3)
0.5
I
= 75mA
V
- 0.3
V
CC
- 0.125
- 0.050
- 0.5mV
OUT
CC
OUT Output Voltage in
Normal Mode
V
OUT
I
= 30mA (Note 4)
= 250µA (Note 4)
V
CC
- 0.12
V
CC
V
OUT
I
V
CC
- 0.001
V
CC
OUT
I
= 250µA
= 1mA
V
BATT
- 0.1
V
BATT
- 0.034
- 0.14
OUT
OUT Output Voltage in
Battery-Backup Mode
V
V
= 2.3V
V
OUT
BATT
I
V
OUT
BATT
20
V
-
CC
V
SW
> V > 1.75V (Note 5)
65
mV
CC
V
BATT
MAX793T/MAX795T
MAX793S/MAX795S
2.69
2.55
2.82
2.68
2.95
2.80
Battery Switch Threshold
(V falling)
CC
V
> V
CC
BATT
V
SW
V
(Note 6)
MAX793R/MAX795R/
MAX794
2.30
2.41
2.52
This value is identical to the reset threshold,
rising for V > V
V
CC
Battery Switch Threshold
V
CC
-
BATT
RST
(V rising) (Note 7)
CC
V
BATT
V
BATT
< V
25
65
mV
RST
2
_______________________________________________________________________________________
3 .0 V/3 .3 V Ad ju s t a b le Mic ro p ro c e s s o r
S u p e rvis o ry Circ u it s
34/MAX795
ELECTRICAL CHARACTERISTICS (continued)
(V
= 3.17V to 5.5V for the MAX793T/MAX795T, V
= 3.02V to 5.5V for the MAX793S/MAX795S, V
= 2.72V to 5.5V for the
CC
CC
CC
MAX793R/MAX794/MAX795R, V
= 3.6V, T = T
to T , unless otherwise noted. Typical values are at T = +25°C.)
MAX A
BATT
A
MIN
PARAMETER
SYMBOL
CONDITIONS
MAX793T/MAX795T
MIN
3.00
2.85
2.55
3.00
2.85
TYP
3.075
2.925
2.625
3.085
2.935
MAX
3.15
3.00
2.70
3.17
3.02
UNITS
V
Falling
MAX793S/MAX795S
MAX793R/MAX795R
MAX793T/MAX795T
MAX793S/MAX795S
MAX793R/MAX795R
CC
Reset Threshold (Note 8)
V
RST
V
V
CC
Rising
2.55
1.212
1.212
2.635
1.240
1.250
2.72
1.262
1.282
V
CC
Falling
Rising
RESET IN Threshold
(MAX794 only)
V
RST IN
V
V
CC
RESET IN Leakage Current
(MAX794 only)
-25
2
25
nA
ms
Reset Timeout Period
t
RP
V
CC
< 3.6V
140
200
280
LOWLINE-to-Reset
MAX793
30
5
45
60
25
Threshold, (V
-
V
LR
mV
LOWLINE
V ), V Falling
RST CC
MAX794
MAX793
MAX794
15
10
10
mV
mV
Low-Line Comparator
Hysteresis
MAX793T/MAX795T
MAX793S/MAX795S
MAX793R/MAX795R
MAX794
3.23
3.08
2.78
LOWLINE Threshold,
V
V
V
LL
V
CC
Rising
1.317
1.262
1.287
25
V
falling
rising
1.212
1.212
-25
1.240
1.250
2
PFI
PFI Input Threshold
PFI Input Current
V
TH
V
PFI
nA
PFI Hysteresis, PFI Rising
10
20
mV
BATT OK Threshold
(MAX793)
V
BOK
2.00
2.25
2.50
V
INPUT AND OUTPUT LEVELS
RESET Output Voltage High
V
I
=300µA, V = V
min
max
max
0.8V
0.86V
CC
V
V
OH
SOURCE
CC
RST
CC
BATT OK, BATT ON, WDO,
LOWLINE Output Voltage
High
V
OH
I
= 300µA, V = V
0.8V
0.86V
CC
SOURCE
CC
RST
CC
PFO Output Voltage High
V
OH
I
= 65µA, V = V
0.8V
CC
V
V
SOURCE
CC
RST
BATT ON Output
Voltage High
V
OH
I
= 100µA, V = 2.3V, V
= 3V 0.8V
SOURCE
CC
BATT BATT
RESET Output Leakage
Current (Note 9)
I
V
= V max
RST
-1
-1
µA
µA
LEAK
CC
PFO Output Short to GND
Current
I
SC
V
CC
= 3.3V, V = 0V
PFO
180
500
PFO, RESET, RESET, WDO,
LOWLINE Output Voltage
Low
I
= 1.2mA; RESET, LOWLINE tested
SINK
V
OL
with V = V
WDO tested with V = V
min; RESET, BATTOK,
0.08
0.2V
CC
V
CC
RST
max
CC
RST
_______________________________________________________________________________________
3
3 .0 V/3 .3 V Ad ju s t a b le Mic ro p ro c e s s o r
S u p e rvis o ry Circ u it s
ELECTRICAL CHARACTERISTICS (continued)
(V
= 3.17V to 5.5V for the MAX793T/MAX795T, V
= 3.02V to 5.5V for the MAX793S/MAX795S, V
= 2.72V to 5.5V for the
CC
CC
CC
MAX793R/MAX794/MAX795R, V
= 3.6V, T = T
to T , unless otherwise noted. Typical values are at T = +25°C.)
MAX A
BATT
A
MIN
PARAMETER
SYMBOL
CONDITIONS
= V = 1.0V, I = 40µA
SINK
MIN
TYP
0.13
0.17
MAX
0.3
UNITS
MAX79_C, V
BATT
CC
RESET Output Voltage Low
V
OL
V
MAX79_E, V
= V = 1.2V, I = 200µA
SINK
0.3
BATT
CC
BATT ON Output
Voltage Low
V
I
= 3.2mA, V = V
max
0.2V
CC
V
V
OL
SINK
CC
RST
V
0.7V
CC
All Inputs Including PFO
(Note 10)
IH
V
max < V < 5.5V
CC
RST
V
0.3V
CC
IL
MANUAL RESET INPUT
MR Pulse Width
t
MAX793/MAX794 only
MAX793/MAX794 only
100
25
50
75
70
ns
ns
MR
MR-to-Reset Delay
t
250
250
MD
MR Pull-Up Current
CHIP-ENABLE GATING
CE IN Leakage Current
MAX793/MAX794 only, MR = 0V
µA
I
Disable mode
±10
46
nA
LEAK
CE IN-to-CE OUT
Resistance
Enable mode, V = V
max
Ω
CC
RST
CE IN-to-CE OUT
Propagation Delay
V
= V
max, Figure 9
2
7
ns
V
CC
RST
V
= V
max, I
= -1mA,
CC
RST
OUT
V
0.8V
CC
OH
V
= V
CC
34/MAX795
CE IN
CE OUT Drive from CE IN
Reset to CE OUT High Delay
V
= V
max, I
= 1.6mA,
CC
RST
OUT
V
OL
0.2V
CC
V
= 0V
CE IN
10
µs
V
CE OUT Output Voltage
High (reset active)
V
OH
I
OH
= 500µA, V < 2.3V
0.8V
BATT
CC
WATCHDOG (MAX793/MAX794 only)
WDI Input Current
0V < V < 5.5V
-1
0.01
1.60
1
µA
sec
ns
CC
Watchdog Timeout Period
WDI Pulse Width
t
1.00
1.00
2.25
WD
Note 1:
V
supply current, logic input leakage, watchdog functionality (MAX793/MAX794), MR functionality (MAX793/MAX794),
CC
PFI functionality (MAX793/MAX794), state of RESET and RESET (MAX793/MAX794) tested at V
= 3.6V and V = 5.5V.
CC
BATT
The state of RESET is tested at V = V min.
CC
CC
Note 2: Tested at V
= 3.6V, V = 3.5V and 0V. The battery current will rise to 10µA over a narrow transition window around
BATT
CC
V
CC
= 1.9V.
Note 3: Leakage current into the battery is tested under the worst-case conditions at V = 5.5V, V
= 1.8V and V = 1.5V,
CC
CC
BATT
V
BATT
= 1.0V.
Note 4: Guaranteed by design.
Note 5: When V > V > V
, OUT remains connected to V until V drops below V
. The V -to-V
comparator
SW
CC
BATT
CC
CC
BATT
CC
BATT
has a small 15mV typical hysteresis to prevent oscillation. For V < 1.75V (typical), OUT switches to BATT regardless of
CC
V
.
BATT
Note 6: When V
> V > V , OUT remains connected to V until V drops below the battery switch threshold (V ).
CC SW CC CC SW
BATT
Note 7: OUT switches from BATT to V when V rises above the reset threshold, if V
> V . In this case, switchover back
CC
CC
BATT
RST
to V occurs at the exact voltage that causes reset to be asserted, however switchover occurs 200ms prior to reset. If
CC
V
BATT
< V , OUT switches from BATT to V when V exceeds V
.
RST
CC
CC
BATT
Note 8: The reset threshold tolerance is wider for V rising than for V falling to accommodate the 10mV typical hysteresis,
CC
CC
which prevents internal oscillation.
Note 9: The leakage current into or out of the RESET pin is tested with RESET not asserted (RESET output high impedance).
Note 10: PFO is normally an output, but is used as an input when activating the battery freshness seal.
4
_______________________________________________________________________________________
3 .0 V/3 .3 V/Ad ju s t a b le Mic ro p ro c e s s o r
S u p e rvis o ry Circ u it s
34/MAX795
__________________________________________Typ ic a l Op e ra t in g Ch a ra c t e ris t ic s
(T = +25°C, unless otherwise noted.)
A
BATT-TO-OUT ON-RESISTANCE
vs. TEMPERATURE
V
SUPPLY CURRENT vs. TEMPERATURE
(NORMAL OPERATING MODE)
V
-TO-OUT ON-RESISTANCE
vs. TEMPERATURE
CC
CC
3.0
2.8
160
140
120
100
80
70
60
50
MAX793/4, V = 5V
CC
I
= 30mA
OUT
V
= 3.0V
2.6
2.4
2.2
2.0
BATT
MAX795, V = 5V
CC
40
30
20
V
= 3.6V
V
= 3.0V
MAX793/4, V = 3.3V
BATT
CC
CC
V
= 3.3V
CC
MAX795, V = 3.3V
CC
1.8
1.6
1.4
V
= 5V
CC
60
10
0
I
V
= 250µA
= 0V
OUT
1.2
1.0
V
= V = V
OUT
V
= 5V
BATT CC
BATT
CC
40
-40 -20
0
20
40
60
80 100
-40 -20
0
20
40
60
80 100
-40 -20
0
20
40
60
80 100
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
BATTERY SUPPLY CURRENT vs.
TEMPERATURE (BATTERY-BACKUP MODE)
RESET COMPARATOR PROPAGATION DELAY
RESET TIMEOUT PERIOD
vs. TEMPERATURE
vs. TEMPERATURE (V FALLING)
CC
0.10
0.08
0.06
0.04
0.02
30
25
20
15
10
5
250
200
150
100
50
V
= 0V
= 3.6V
CC
V
BATT
V
CC
RISING FROM
OV TO V MAX
RST
0
0
0
-40 -20
0
20
40
60
80 100
-40 -20
0
20
40
60
80 100
-40 -20
0
20
40
60
80 100
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
MAX793
LOWLINE-TO-RESET THRESHOLD
vs. TEMPERATURE
MAX793/MAX794
LOWLINE COMPARATOR PROPAGATION DELAY
vs. TEMPERATURE
MAX793/MAX794
PFI THRESHOLD vs. TEMPERATURE
1.250
1.245
100
90
10
V
FALLING
40mV OVERDRIVE
CC
8
6
4
2
80
70
60
50
V
RISING
CC
1.240
1.235
40
30
20
V
FALLING
CC
10
0
1.230
0
-40 -20
0
20
40
60
80 100
-40 -20
0
20
40
60
80 100
-40 -20
0
20
40
60
80 100
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
_______________________________________________________________________________________
5
3 .0 V/3 .3 V Ad ju s t a b le Mic ro p ro c e s s o r
S u p e rvis o ry Circ u it s
____________________________Typ ic a l Op e ra t in g Ch a ra c t e ris t ic s (c o n t in u e d )
(T = +25°C, unless otherwise noted.)
A
MAX794
RESET IN THRESHOLD AND LOWLINE-TO-RESET IN
THRESHOLD vs. TEMPERATURE
CE IN-TO-CE OUT ON-RESISTANCE
vs. TEMPERATURE
MAX793
BATT OK THRESHOLD vs. TEMPERATURE
1.242
1.241
1.240
1.239
1.238
1.237
1.236
30
25
20
15
10
5
2.5
2.0
1.5
1.0
0.5
60
50
40
30
20
10
0
V
RESET IN
V
- V
LOWLINE RST
V
FALLING
V
FALLING
V = V MAX
CC RST
BATT
CC
0
0
-40 -20
0
20
40
60
80 100
-40 -20
0
20
40
60
80 100
-40 -20
0
20
40
60
80 100
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
MAX793/MAX794
MAX793/MAX794
RESET THRESHOLD vs.
TEMPERATURE (NORMALIZED)
WATCHDOG TIMEOUT PERIOD
vs. TEMPERATURE
BATTERY FRESHNESS SEAL
LEAKAGE CURRENT vs. TEMPERATURE
1.002
1.001
1.70
1.65
20
V
= 5.5V
= 0V
= 0V
BATT
34/MAX795
V
CC
V
OUT
15
1.000
0.999
0.998
0.997
0.996
1.60
1.55
10
5
V
FALLING
CC
1.50
0
-40 -20
0
20
40
60
80 100
-40 -20
0
20
40
60
80 100
-40 -20
0
20
40
60
80 100
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
MAX793/MAX794
PFI TO PFO PROPAGATION DELAY
vs. TEMPERATURE
10
8
6
4
2
V
PFI
FALLING
20mV OVERDRIVE
0
-40 -20
0
20
40
60
80 100
TEMPERATURE (°C)
6
_______________________________________________________________________________________
3 .0 V/3 .3 V Ad ju s t a b le Mic ro p ro c e s s o r
S u p e rvis o ry Circ u it s
34/MAX795
______________________________________________________________P in De s c rip t io n
PIN
NAME
FUNCTION
MAX793/
MAX794
MAX795
Supply Output for CMOS RAM. When V rises above the reset threshold or above
CC
1
2
1
2
OUT
V
V
CC
, OUT is connected to V through an internal P-channel MOSFET switch. When
BATT CC
falls below V and V
, BATT connects to OUT.
SW
BATT
V
CC
Main Supply Input
BATT OK
(MAX793)
Battery Status Output. High in normal operating mode when V
exceeds V
, other-
BATT
BOK
wise low. V
is checked continuously. Disabled and logic low while V is below V
.
BATT
CC
SW
3
4
—
—
RESET IN
(MAX794)
Reset Input. Connect to an external resistor divider to select the reset threshold. The
reset threshold can be programmed anywhere in the V to 5.5V range.
SW
Power-Fail Comparator Input. When PFI is less than V
or when V falls below V
,
PFT
CC
SW
PFI
PFO goes low; otherwise, PFO remains high (see Power-Fail Comparator section).
Connect to V if unused.
CC
Logic Output/External Bypass Switch-Driver Output. High when OUT switches to BATT.
Low when OUT switches to V . Connect the base/gate of PNP/PMOS transistor to
5
6
7
3
4
BATT ON
GND
CC
BATT ON for I
requirements exceeding 75mA.
OUT
Ground
Power-Fail Comparator Output. When PFI is less than V
or when V falls below
CC
PFT
—
PFO
V , PFO goes low; otherwise, PFO remains high. PFO is also used to enable the bat-
SW
tery freshness seal (see Battery Freshness Seal, and Power-Fail Comparator sections).
Manual Reset Input. A logic low on MR asserts reset. Reset remains asserted as long as
MR is low and for 200ms after MR returns high. The active-low input has an internal
70µA pull-up current. In can be driven from a TTL- or CMOS-logic line or shorted to
ground with a switch. Leave open if unused.
8
9
—
—
—
MR
WDO
WDI
Watchdog Output. WDO goes low if WDI remains either high or low for longer than the
watchdog timeout period. WDO returns high on the next transition of WDI. WDO is a
logic high for V < V < V , and low when V is below V .
SW
SW
CC
RST
CC
Watchdog Input. If WDI remains either high or low for longer than the watchdog timeout
period, the internal watchdog timer runs out and WDO goes low. WDO returns high on
the next transition of WDI. Connect WDO to MR to generate a reset due to a watchdog
fault.
10
11
12
5
6
CE IN
Chip-Enable Input. The input to the chip-enable gating circuit. Connect to GND if unused
Chip-Enable Output. CE OUT goes low only when CE IN is low and reset is not asserted.
If CE IN is low when reset is asserted, CE OUT will remain low for 10µs or until CE IN
goes high, whichever occurs first. CE OUT is pulled up to OUT.
CE OUT
13
14
—
—
RESET
Active-High Reset Output. Sources and sinks current. RESET is the inverse of RESET.
Early Power-Fail Warning Output. Low when V falls to V . This output can be used to
CC
LR
LOWLINE
generate an NMI to provide early warning of imminent power-failure.
Open-Drain, Active-Low Reset Output. Pulses low for 200ms when triggered, and stays
low whenever V is below the reset threshold or when MR is a logic low. It remains low
for 200ms after either V rises above the reset threshold, the watchdog triggers a reset
CC
(WDO connected to MR), or MR goes low to high.
CC
15
16
7
8
RESET
BATT
Backup-Battery Input. When V falls below V and V
, OUT switches from V to
BATT CC
CC
SW
BATT. When V rises above the reset threshold or above V
, OUT reconnects to
BATT
CC
V
. V
may exceed V . Connect V , OUT, and BATT together if no battery is
CC CC
CC BATT
used.
_______________________________________________________________________________________
7
3 .0 V/3 .3 V Ad ju s t a b le Mic ro p ro c e s s o r
S u p e rvis o ry Circ u it s
out period (t ), the state of MR is ignored if PFO is exter-
RP
_______________De t a ile d De s c rip t io n
nally forced low, to facilitate enabling the battery fresh-
ness seal. MR has an internal 70µA pull-up current, so it
can be left open if it is not used. This input can be driven
with TTL- or CMOS-logic levels, or with open-drain/collec-
tor outputs. Connect a normally open momentary switch
from MR to GND to create a manual-reset function; exter-
nal debounce circuitry is not required. If MR is driven
from long cables or the device is used in a noisy environ-
ment, connect a 0.1µF capacitor from MR to ground to
provide additional noise immunity.
Ge n e ra l Tim in g Ch a ra c t e ris t ic s
The MAX793/MAX794/MAX795 are designed for 3.3V
and 3V systems, and provide a number of supervisory
functions (see the Selector Guide on the front page).
Figures 1 and 2 show the typical timing relationships of
the various outputs during power-up and power-down
with typical V rise and fall times.
CC
Ma n u a l Re s e t In p u t (MAX7 9 3 /MAX7 9 4 )
Many microprocessor-based products require manual-
reset capability, allowing the operator, a test technician,
or external logic circuitry to initiate a reset. On the
MAX793/MAX794, a logic low on MR asserts reset. Reset
Re s e t Ou t p u t s
A microprocessor’s (µP’s) reset input starts the µP in a
known s ta te . The s e MAX793/MAX794/MAX795 µP
supervisory circuits assert a reset to prevent code exe-
c ution e rrors d uring p owe r-up , p owe r-d own, a nd
remains asserted while MR is low, and for t (200ms)
RP
after it returns high. During the first half of the reset time-
V
LL
V
RST
V
SW
V
CC
5µs
V
(MAX793/MAX794)
LOWLINE
34/MAX795
t
RP
V
RESET
(PULLED UP TO V )
CC
t
RP
V
RESET
(MAX793/MAX794)
V
BATT
V
CE OUT
t
/
RP 2
V
WDO
25µs
25µs
(MAX793/MAX794)
V
BOK
(MAX793)
PFO
t /
RP 2
(MAX793/MAX794)
25µs
(PFO FOLLOWS PFI)
BATT ON
25µs
SHOWN FOR V = 0V to 3.3V, V
= 3.6V, CE IN = GND.
CC
BATT
TYPICAL PROPAGATION DELAYS REFLECT A 40mV OVERDRIVE.
MAX794: V = V (V / V
)
RESET IN CC RST IN RST
Figure 1. Timing Diagram, V Rising
CC
8
_______________________________________________________________________________________
3 .0 V/3 .3 V Ad ju s t a b le Mic ro p ro c e s s o r
S u p e rvis o ry Circ u it s
34/MAX795
brownout conditions. RESET is guaranteed to be a
If a brownout condition occurs (V
dips below the
CC
log ic low for 0V < V
greater than 1V. Without a backup battery (V
< V
, p rovid e d V
is
=
reset threshold), RESET goes low. Each time RESET is
asserted, it stays low for the reset timeout period. Any
CC
RST
BATT
BATT
V
CC
= V
), RESET is guaranteed valid for V ≥ 1V.
time V
goes below the reset threshold, the internal
OUT
CC
CC
Once V
exceeds the reset threshold, an internal
timer restarts.
CC
timer keeps RESET low for the reset timeout period
The watchdog output (WDO) can also be used to initi-
ate a reset. See the Watchdog Output section.
(t ); after this interval, RESET becomes high imped-
RP
ance (Figure 2). RESET is an open-drain output, and
The RESET output is the inverse of the RESET output,
and it can both source and sink current.
requires a pull-up resistor to V
(Figure 3). Use a
CC
4.7kΩ to 1MΩ pull-up resistor that will provide sufficient
current to assure the proper logic levels to the µP.
V
LL
V
RST
V
CC
V
SW
V
LOWLINE
4µs
(MAX793/MAX794)
V
RESET
20µs
20µs
(RESET PULLED UP TO V
)
CC
V
RESET
(MAX793/MAX794)
25µs
V
CE OUT
V
BATT
10µs
V
WDO
(MAX793/MAX794)
25µs
25µs
V
BOK
(MAX793)
V
PFO
(MAX793/MAX794)
25µs
25µs
V
BATT
V
BATT ON
SHOWN FOR V = 3.3V to 0V, V
= 3.6V, CE IN = GND, PFI = V .
CC
CC
BATT
TYPICAL DELAY TIMES REFLECT A 40mV OVERDRIVE
MAX794: V = V (V / V
)
RESET IN CC RST IN RST
Figure 2. Timing Diagram, V Falling
CC
_______________________________________________________________________________________
9
3 .0 V/3 .3 V Ad ju s t a b le Mic ro p ro c e s s o r
S u p e rvis o ry Circ u it s
(OPTIONAL)
Si9433DY
SILICONIX
V
RST
V
RST
3.3V
D
S
0.1µF
0.1µF
V
CC
PMOS
R1
V
CC
BATT ON OUT
CMOS
RAM
RESET IN
CE OUT
t
RP
R2
V
CC
RESET
PFO
MAX794
ADDRESS
DECODER
CE IN
A0-A15
I/O
BATT
0.1µF
3.6V
WDI
PFO STATE LATCHED,
FRESHNESS SEAL ENABLED.
WDO
MR
(EXTERNALLY HELD AT 0V)
LOWLINE
NMI
V
CC
+5V SUPPLY
FAILURE
RESET PULLED UP TO V
CC
4.7k
PFO
+5V
Figure 4. Battery Freshness Seal Enable Timing
RESET
RESET
PFI
Using the standard application circuit (Figure 3), the
reset threshold may be programmed anywhere in the
R1
GND
+ 1
V
= V
RST RST IN
(
)
R2
range of V
(the battery switch threshold) to 5.5V.
SW
Reset is asserted when V falls below V
.
CC
SW
Ba t t e ry Fre s h n e s s S e a l
The MAX793/MAX794’s battery freshness seal discon-
nects the backup battery from internal circuitry until it is
needed. This allows an OEM to ensure that the backup
battery connected to BATT will be fresh when the final
product is put to use. To enable the freshness seal,
Figure 3. MAX794 Standard Application Circuit
34/MAX795
Re s e t Th re s h o ld
The MAX793T/MAX795T are intended for 3.3V systems
with a ±5% power-supply tolerance and a 10% systems
tolerance. Except when MR is asserted, reset will not
assert as long as the power supply remains above
3.15V (3.3V - 5%). Re s e t is g ua ra nte e d to a s s e rt
before the power supply falls below 3.0V (3.3V - 10%).
connect a battery to BATT, ground PFO, bring V
CC
above the reset threshold and hold it there until reset is
deasserted following the reset timeout period, then
bring V
back down again (Figure 4). Once the bat-
CC
The MAX793S/MAX795S are designed for 3.3V ±10%
power supplies. Except when MR is asserted, they are
guaranteed not to assert reset as long as the supply
remains above 3.0V (3.0V is just above 3.3V - 10%).
Reset is guaranteed to assert before the power supply
falls below 2.85V (3.3V - 14%).
tery freshness seal is enabled (disconnecting the back-
up b a tte ry from the inte rna l c irc uitry a nd a nything
connected to OUT), it remains enabled until V
is
CC
brought above V . Note that connecting PFO to MR
RST
will not interfere with battery freshness seal operation.
BATT OK Ou t p u t (MAX7 9 3 )
BATT OK indicates the status of the backup battery.
When reset is not asserted, the MAX793 checks the
The MAX793R/MAX795R are optimized to monitor 3.0V
±10% power supplies. Reset will not occur until V
CC
falls below 2.7V (3.0V - 10%), but is guaranteed to
occur before the supply falls below 2.55V (3.0V - 15%).
battery voltage continuously. If V
is below V
BATT
BOK
(2.0V min), BATT OK goes low; otherwise, it remains
pulled up to V . BATT OK also goes low when V
Program the MAX794’s reset threshold with an external
voltage divider to RESET IN. The reset-threshold toler-
ance will be a combination of the RESET IN tolerance
and the tolerance of the resistors used to make the
external voltage divider. Calculate the reset threshold
as follows:
CC
CC
goes below V
.
SW
Wa t c h d o g In p u t (MAX7 9 3 /MAX7 9 4 )
In the MAX793/MAX794, the watchdog circuit monitors
the µP’s activity. If the µP does not toggle the watch-
dog input (WDI) within 1.6sec, WDO goes low. The
internal 1.6sec timer is cleared and WDO returns high
V
RST
= V
(R1 / R2 + 1)
RST IN
10 ______________________________________________________________________________________
3 .0 V/3 .3 V Ad ju s t a b le Mic ro p ro c e s s o r
S u p e rvis o ry Circ u it s
34/MAX795
V
RST
V
CC
V
CC
4.7k
MAX793/MAX794
t
RP
WDO
TO µP
RESET
RESET
WDO
MR
V
CC
t
WD
WDI
10µs
WDO
RESET
WDI
t
RP
t
WP
t
RP
WDO CONNECTED TO µP INTERRUPT
RESET PULLED UP TO V
CC
Figure 5. Watchdog Timing Relationship
either when a reset occurs or when a transition (low-to-
high or high-to-low) takes place at WDI. As long as
reset is asserted, the timer remains cleared and does
not c ount. As s oon a s re s e t is re le a s e d or WDI
changes state, the timer starts counting (Figure 5).
WDI can detect pulses as short as 100ns. Unlike the
5V MAX690 family, the watchdog function cannot be
disabled.
Figure 6. Generating a Reset on Each Watchdog Fault
Ch ip -En a b le S ig n a l Ga t in g
Internal gating of chip-enable (CE) signals prevents erro-
neous data from corrupting CMOS RAM in the event of an
undervoltage condition. The MAX793/MAX794/MAX795
use a series transmission gate from CE IN to CE OUT
(Figure 7). During normal operation (reset not asserted),
the CE transmission gate is enabled and passes all CE
transitions. When reset is asserted, this path becomes
disabled, preventing erroneous data from corrupting the
CMOS RAM. The short CE propagation delay from CE IN
to CE OUT enables these µP supervisors to be used with
most µPs. If CE IN is low when reset asserts, CE OUT
remains low for typically 10µs to permit completion of the
current write cycle.
Wa t c h d o g Ou t p u t (MAX7 9 3 /MAX7 9 4 )
In the MAX793/MAX794, WDO remains high (WDO is
pulled up to V ) if there is a transition or pulse at WDI
CC
during the watchdog timeout period. WDO goes low if
no transition occurs at WDI during the watchdog timeout
period. The watchdog function is disabled and WDO is
a logic high when reset is asserted if V is above V
.
CC
SW
WDO is a logic low when V is below V
.
CC
SW
Chip-Enable Input
The CE transmission gate is disabled and CE IN is high
impedance (disabled mode) while reset is asserted.
If a system reset is desired on every watchdog fault,
s imp ly d iod e -OR c onne c t WDO to MR (Fig ure 6).
When a watchdog fault occurs in this mode, WDO goes
low, pulling MR low, which causes a reset pulse to be
issued. Ten microseconds after reset is asserted, the
watchdog timer clears and WDO returns high. This
delay results in a 10µs pulse at WDO, allowing external
During a power-down sequence when V
passes the
CC
reset threshold, the CE transmission gate disables and
CE IN immediately becomes high impedance if the volt-
a g e a t CE IN is hig h. If CE IN is low whe n re s e t
asserts, the CE transmission gate will disable at the
moment CE IN goes high, or 10µs after reset asserts,
whichever occurs first (Figure 8). This permits the cur-
rent write cycle to complete during power-down.
circuitry to “capture” a watchdog fault indication.
A
continuous high or low on WDI will cause 200ms reset
pulses to be issued every 1.6sec.
______________________________________________________________________________________ 11
3 .0 V/3 .3 V Ad ju s t a b le Mic ro p ro c e s s o r
S u p e rvis o ry Circ u it s
The propagation delay through the CE transmission
gate depends on V , the source impedance of the
CC
drive connected to CE IN, and the loading on CE OUT
(see the Chip-Enable Propagation Delay vs. CE OUT
Loa d Ca p a c ita nc e g ra p h in the Typ ic a l Op e ra ting
Characteristics). The CE propagation delay is produc-
tion tested from the 50% point on CE IN to the 50%
point on CE OUT using a 50Ω driver and 50pF of load
c a pa c ita nc e (Figure 9). For minimum p ropa ga tion
delay, minimize the capacitive load at CE OUT, and
use a low-output-impedance driver.
MAX793
MAX794
MAX795
OUT
P
CHIP-ENABLE
OUTPUT
CONTROL
RESET
GENERATOR
P
Chip-Enable Output
When the CE transmission gate is enabled, the imped-
ance of CE OUT is equivalent to a 46Ω resistor in series
with the source driving CE IN. In the disabled mode,
the transmission gate is off and an active pull-up con-
nects CE OUT to OUT (Figure 8). This pull-up turns off
when the transmission gate is enabled.
CE IN
CE OUT
N
Ea rly P o w e r-Fa il Wa rn in g
(MAX7 9 3 /MAX7 9 4 )
Figure 7. Chip-Enable Transmission Gate
Critical systems often require an early warning indicat-
ing that power is failing. This warning provides time for
the µP to store vital data and take care of any additional
“housekeeping” functions, before the power supply
gets too far out of tolerance for the µP to operate reli-
a b ly. The MAX793/MAX794 offe r two me thod s of
achieving this early warning. If access to the unregu-
lated supply is feasible, the power-fail comparator input
(PFI) c a n b e c onne c te d to the unre g ula te d s up p ly
The CE transmission gate remains disabled and CE IN
remains high impedance (regardless of CE IN activity)
for the first half of the reset timeout period (t / 2), any
time a reset is generated. While disabled, CE IN is
high impedance. When the CE transmission gate is
enabled, the impedance of CE IN appears as a 46Ω
resistor in series with the load at CE OUT.
34/MAX795
RP
V
RST
V
RST
V
RST
V
RST
V
CC
V
SW
V
SW
CE OUT
V
BATT
V
BATT
10µs
V
CC
t
RP
/2
t
RP
RESET
(PULLED TO V
)
CC
CE IN
V
BATT
= 3.6V
RESET PULLED UP TO V
CC
Figure 8. Chip-Enable Timing
12 ______________________________________________________________________________________
3 .0 V/3 .3 V Ad ju s t a b le Mic ro p ro c e s s o r
S u p e rvis o ry Circ u it s
34/MAX795
pulled to V . Use LOWLINE to provide an NMI to the
CC
µP when power begins to fall.
V
CC
V
In most battery-operated portable systems, reserve
energy in the battery provides ample time to complete
the s hutd own routine onc e the low-line wa rning is
encountered and before reset asserts. If the system
CC
BATT
3.6V
MAX793
MAX794
MAX795
must also contend with a more rapid V fall time, such
CC
25Ω EQUIVALENT
SOURCE IMPEDANCE
as when the main battery is disconnected or a high-
side switch is opened during normal operation, use
50Ω CABLE
capacitance on the V line to provide time to execute
the shutdown routine (Figure 11).
CC
CE OUT
CE IN
50Ω
First, calculate the worst-case time required for the sys-
tem to perform its shutdown routine. Then, with the worst-
case shutdown time, the worst-case load current, and the
50pF
C *
50Ω
L
GND
minimum low-line to reset threshold (V min), calculate
LR
the amount of capacitance required to allow the shut-
down routine to complete before reset is asserted:
*C INCLUDES LOAD CAPACITANCE AND SCOPE PROBE CAPACITANCE.
L
C
> I
x t
/ V
SHDN LR
HOLD
LOAD
Figure 9. CE Propagation Delay Test Circuit
whe re I
is the c urre nt b e ing dra ine d from the
LOAD
capacitor, V is the low-line to reset threshold differ-
LR
through a voltage divider, with the power-fail compara-
tor output (PFO) providing the NMI to the µP (Figure
10). If there is no easy access to the unregulated sup-
ply, the LOWLINE output can be used to generate an
NMI to the µP (see LOWLINE Output section).
ence (V - V
), and t
RST
is the time required for
LL
SHDN
the system to complete an orderly shutdown routine.
Power-Fail Comparator (MAX793/MAX794)
The MAX793/MAX794’s PFI input is compared to an
internal reference. If PFI is less than the power-fail
LOWLINE Output (MAX793/MAX794)
threshold (V ), PFO goes low. The power-fail com-
PFT
The low-line comparator monitors V
with a threshold
CC
parator is intended for use as an undervoltage detector
to signal a failing power supply (Figure 12). However,
the comparator does not need to be dedicated to this
function because it is completely separate from the rest
of the circuitry.
voltage typically 45mV above the reset threshold (10mV
of hysteresis) for the MAX793, and 15mV above RESET
IN (4mV of hysteresis) for the MAX794. For normal
operation (V above the reset threshold), LOWLINE is
CC
UNREGULATED
3.0V OR 3.3V
SUPPLY
REGULATOR
3.0V OR 3.3V
REGULATOR
TO µP NMI
LOWLINE
V
CC
C
HOLD
V
CC
MAX793
MAX794
MAX793
MAX794
R1
R2
TO µP NMI
PFO
PFI
C
> I
x t
V
LR
HOLD LOAD SHDN
GND
GND
Figure 10. Using the Power-Fail Comparator to Generate
Power-Fail Warning
Figure 11. Using LOWLINE to Provide Power-Fail Warning
to the µP
______________________________________________________________________________________ 13
3 .0 V/3 .3 V Ad ju s t a b le Mic ro p ro c e s s o r
S u p e rvis o ry Circ u it s
V
IN
3.0V OR 3.3V
3.0V OR 3.3V
V
V
CC
CC
R1
R2
R1
R2
MAX793
MAX794
MAX793
MAX794
PFI
PFO
PFI
PFO
MR
GND
GND
V
IN
V
CC
V
CC
PFO
PFO
V
IN
V
IN
V
L
V
TRIP
V
TRIP
V
H
0V
1
1
V
CC
R1 + R2
R2
+
–
V
= R2 (V + V
PFT
)
TRIP
PFH
V
= V
PFT
(
)
CC
TRIP
(
)
R1 R2
R1
WHERE V = 1.237V
PFT
1
1
V
V
PFH
= 10mV
R1 + R2
+
–
V = R2 (V
)
L
PFT
V = (V + V
)
(
)
H
PFT PFH
(
)
R1 R2
R1
NOTE: V
TRIP,
V ARE NEGATIVE
L
R2
(a)
(b)
Figure 12. Using the Power-Fail Comparator to Monitor an Additional Power Supply: (a) V Is Negative, (b) V Is Positive
IN
IN
34/MAX795
The power-fail comparator turns off and PFO goes low
when V falls below V on power-down. During the
V
is greater than V , or when V
falls below
BATT
CC
CC
1.75V (typ) regardless of the BATT voltage.
CC
SW
first half of the reset timeout period (t ), PFO is forced
RP
Switchover at V ensures that battery-backup mode is
SW
high, irrespective of V . At the beginning of the sec-
PFI
entered before V
gets too close to the 2.0V mini-
OUT
ond half of t , the power-fail comparator is enabled
RP
mum required to reliably retain data in most CMOS
RAM, (s witc hove r a t hig he r V volta g e s would
and PFO follows PFI. If the comparator is unused, con-
nect PFI to VCC and leave PFO unconnected. PFO may
be connected to MR so that a low voltage on PFI will
generate a reset (Figure 12b). In this configuration,
when the monitored voltage causes PFI to fall below
CC
decrease backup-battery life). When V
recovers,
CC
switchover is deferred either until V crosses V
if
CC
BATT
V
BATT
is below V
, or when V
rises above the
RST
CC
reset threshold (V
powe r-up switc hove r te c hnique p re ve nts V
) if V
is above V .
This
from
RST
BATT
RST
V , PFO pulls MR low, causing a reset to be assert-
PFT
CC
ed. Reset remains asserted as long as PFO holds MR
low, and for 200ms after PFO pulls MR high when the
monitored supply is above the programmed threshold.
charging the backup battery through OUT when using
an external transistor driven by BATT ON. OUT con-
nects to V
through a 4Ω (max) PMOS power switch
CC
when V crosses the reset threshold (Figure 13).
CC
Ba c k u p -Ba t t e ry S w it c h o ve r
In the event of a brownout or power failure, it may be
necessary to preserve the contents of RAM. With a
backup battery installed at BATT, the devices automati-
BATT ON (MAX7 9 3 /MAX7 9 4 )
BATT ON is high when OUT is connected to BATT.
Although BATT ON can be used as a logic output to
indicate the battery switchover status, it is most often
used as a gate or base drive for an external pass tran-
sistor for high-c urre nt a pp lic a tions (se e Driving a n
Exte rna l Switc h with BATT ON in the Ap p lic a tions
cally switch RAM to backup power when V
falls. In
CC
order to allow the backup battery (e.g., a 3.6V lithium
cell) to have a higher voltage than V , this family of µP
CC
supervisors (designed for 3.3V and 3V systems) does
not a lwa ys c onne c t BATT to OUT whe n V
is
BATT
Informa tion s e c tion). Whe n V
e xc e e d s V
on
CC
RST
greater than V
.
BATT connects to OUT (through a
CC
power-up, BATT ON sinks 3.2mA at 0.4V. In battery-
backup mode, this terminal sources 100µA from BATT.
140Ω switch) either when V falls below V and
CC
SW
14 ______________________________________________________________________________________
3 .0 V/3 .3 V Ad ju s t a b le Mic ro p ro c e s s o r
S u p e rvis o ry Circ u it s
34/MAX795
to V , the collector to OUT, and the base to BATT ON
CC
(Figure 14a). No current-limiting resistor is required,
but a resistor connecting the base of the PNP to BATT
3.3V
V
RST
ON can be used to limit the current drawn from V
prolonging battery life in portable equipment.
,
CC
V
CC
V
SW
If you are using a PMOS transistor, however, it must be
c onne c te d b a c kwa rd s from the tra d itiona l me thod .
Connect the gate to BATT ON, the drain to V , and
CC
the source to OUT (Figure 14b). This method orients
3.6V
3.6V
the body diode from V
to OUT and prevents the
3.3V
CC
backup battery from discharging through the FET when
its gate is high. Two PMOS transistors in the Siliconix
V
OUT
LITTLE FOOT™ series are specified with V down to
GS
V
BATT
= 3.6V
-2.7V. The Si9433DY has a maximum 100mΩ drain-
source on-resistance with 2.7V of gate drive and a 2A
drain-source current. The Si9434DY specifies a 60mΩ
drain-source on-resistance with 2.7V of gate drive and
a 5.1A drain-source current.
Figure 13. Battery Switchover Timing
Table 1. Input and Output Status in
Battery-Backup Mode
Us in g a S u p e rCa p ™ a s a Ba c k u p
P o w e r S o u rc e
PIN NAME
STATUS
Connected to BATT through an internal
Sup e rCa p s ™ a re c a p a c itors with e xtre me ly hig h
capacitance values (e.g., order of 0.47F) for their size.
Figure 15 shows two ways to use a SuperCap as a
backup power source. The SuperCap can be connect-
ed through a diode to the 3V input (Figure 15a); or, if a
5V s up p ly is a ls o a va ila b le , the Sup e rCa p c a n b e
charged up to the 5V supply (Figure 15b), allowing a
OUT
140Ω switch
V
CC
Disconnected from OUT
Pulled up to BATT
Logic low
BATT ON
BATT OK
PFI
Disabled
PFO
Logic low
longer backup period. Since V
can exceed V
BATT
CC
MR
Disabled, but still pulled up to V
while V
is above the reset threshold, there are no
CC
CC
special precautions when using these µP supervisors
with a SuperCap.
WDO
Logic low
Disabled
Logic low
WDI
RESET
RESET
BATT
Op e ra t io n w it h o u t a
Ba c k u p P o w e r S o u rc e
The s e µP s up e rvis ors we re d e s ig ne d for b a tte ry-
backed applications. If a backup battery is not used,
Pulled up to V
CC
Connected to OUT
Logic low
LOWLINE
CE IN
CE OUT
connect BATT, OUT, and V together, or use a differ-
CC
High impedance
Pulled to BATT
ent µP supervisor. See the µP Supervisory Circuits
table at the end of this data sheet.
__________Ap p lic a t io n s In fo rm a t io n
These µP supervisory circuits are not short-circuit pro-
Re p la c in g t h e Ba c k u p Ba t t e ry
The backup power source can be removed while V
CC
re ma ins va lid , without d a ng e r of trig g e ring a re s e t
pulse, provided that BATT is decoupled with a 0.1µF
tected. Shorting V
to ground, excluding power-up
OUT
transients such as charging a decoupling capacitor,
destroys the device. Decouple both V and BATT
capacitor to ground. As long as V
stays above the
CC
CC
re s e t thre s hold , b a tte ry-b a c kup mod e c a nnot b e
entered.
pins to ground by placing 0.1µF ceramic capacitors as
close to the device as possible.
Drivin g a n Ex t e rn a l S w it c h w it h BATT ON
BATT ON can be directly connected to the base of a
PNP transistor or the gate of a PMOS transistor. The
PNP connection is straightforward: connect the emitter
™ LITTLE FOOT is a trademark of Siliconix Inc.
SuperCap is a trademark of Baknor Industries.
______________________________________________________________________________________ 15
3 .0 V/3 .3 V Ad ju s t a b le Mic ro p ro c e s s o r
S u p e rvis o ry Circ u it s
PMOS FET
BODY DIODE
TO CMOS RAM
3.0V OR 3.3V
S
D
G
V
CC
BATT ON OUT
V
CC
BATT ON OUT
MAX793
MAX794
MAX795
MAX793
MAX794
MAX795
GND
GND
(a)
(b)
Figure 14. Driving an External Transistor with BATT ON
3.0V OR 3.3V
+5V
3.0V OR
3.3V
V
MAX793
MAX794
OUT
TO STATIC
RAM
CC
V
MAX793
MAX794
OUT
TO STATIC
RAM
CC
CC
34/MAX795
V
V
CC
1N4148
1N4148
0.47F
BATT
RESET
TO µP
BATT
RESET
TO µP
0.47F
GND
GND
(a)
Figure 15. Using a SuperCap™ as a Backup Source
(b)
The IC decides whether or not to enter freshness seal
mode during all reset timeout periods. During a power-
____________________________Erra t u m
Initial versions of the MAX793 and MAX794 have a
logic design error that can cause the loss of output volt-
up reset timeout period (which occurs when V
is
CC
raised above the MAX793’s reset threshold or the volt-
age on the MAX794’s RESET IN pin is raised above the
RESET IN threshold), the IC momentarily disconnects
the PFO pin from the comparator output and lightly
age (OUT) when V
is absent even though a backup
CC
battery is connected to the BATT input. Applications
that do not use the MR input (including all MAX795
a p p lic a tions ) a re una ffe c te d b y this p he nome non.
Also, applications that do not use PFO are unaffected if
pulls PFO up to V . The voltage level on the PFO pin
CC
is then tested and, if it is low, freshness seal mode is
chosen. (PFO is reconnected to the comparator output
before the end of the reset timeout period.)
PFI is tied to V
.
CC
The loss of output voltage is caused by the IC incor-
re c tly e nte ring the b a tte ry “fre s hne s s s e a l” mod e .
Normally, freshness seal mode is activated by ground-
ing PFO during a power-up reset timeout period. Then,
However, when a reset is initiated by MR, the PFO pin
incorrectly remains connected to the comparator output
during the entire timeout period and is not pulled up. If
the comparator is driving PFO low during an MR reset
the removal of V
powers the IC down without con-
CC
necting the backup battery to OUT.
16 ______________________________________________________________________________________
3 .0 V/3 .3 V Ad ju s t a b le Mic ro p ro c e s s o r
S u p e rvis o ry Circ u it s
34/MAX795
V
IN
V
IN
R1
R2
V
V
CC
R1
R2
CC
PFI
MAX793
MAX794
MAX793
MAX794
PFI
R3
R3
C1*
C1*
PFO
PFO
GND
GND
*OPTIONAL
*OPTIONAL
V
TO µP
TO µP
PFO
0V
PFO
0V
V
IN
IN
V
TRIP
V
H
V
L
V
H
0V
0V
V
TRIP
R1 + R2
V
= V
(
)
R1 + R2
R2
TRIP
PFT
R2
V
= V
PFT
(
)
TRIP
WHERE V = 1.237V
PFT
V
1
1
1
D
V
= 10mV
+
+
–
PFH
V = R1 (V + V )
PFT PFH
1
1
1
(
)
H
V = (V + V ) (R1)
H
PFT PFH
R3
R1 R2 R3
+
+
(
)
R1 R2 R3
WHERE V = 1.237V
PFT
1
1
1
V
CC
+
+
–
V = R1 V
PFT
(
)
L
V
= 10mV
PFH
R1 R2 R3
R3
V
D
= DIODE FORWARD VOLTAGE DROP
(a)
(b)
V = V
L
TRIP
Figure 16. Adding Hysteresis to the Power-Fail Comparator: (a) Symmetrical Hysteresis, (b) Hysteresis Only on Rising V
IN
timeout period (because PFI is below the PFI thresh-
old), the IC will test the voltage level on PFO, find that it
is low, and incorrectly decide to enter freshness seal
V
CC
mode. If V
is later removed, the backup battery will
CC
not be connected to OUT and any devices powered by
OUT will lose power.
V
CC
V
CC
Applications that do not use the PFO comparator need
not be affected by this problem. Simply connect PFI to
RESET
N
V
CC
and PFO will be driven high during all reset time-
RESET
out periods. Freshness seal mode can be entered only
when PFO is low.
RESET
GENERATOR
The IC is under revision to correct this problem. The
revised IC will disable PFO during all reset timeout peri-
ods including MR-initiated ones. This revision will not
affect applications that either do not use MR or do not
use PFO, but could affect applications that require the
use of the PFO output during MR-initiated reset timeout
periods. The revised ICs are expected to be available
in late 1996. For technical assistance, please contact
Ma xim Ap p lic a tions a t 1-800-998-8800 or a t
http:// www. maxim-ic.com.
µP
MAX793
MAX794
MAX795
GND
GND
Figure 17. Interfacing to µPs with Bidirectional Reset I/O
______________________________________________________________________________________ 17
3 .0 V/3 .3 V Ad ju s t a b le Mic ro p ro c e s s o r
S u p e rvis o ry Circ u it s
PFI. PFO can be used to generate an interrupt to the
µP or to cause reset to assert (Figure 12).
Ad d in g Hys t e re s is t o t h e P o w e r-Fa il
Co m p a ra t o r (MAX7 9 3 /MAX7 9 4 )
The power-fail comparator has a typical input hystere-
sis of 10mV. This is sufficient for most applications
where a power-supply line is being monitored through
an external voltage divider (see the section Monitoring
an Additional Power Supply).
In t e rfa c in g t o µP s w it h
Bid ire c t io n a l Re s e t P in s
Since the RESET output is open drain, the MAX793/
MAX794/MAX795 interface easily with µPs that have
bidirectional reset pins, such as the Motorola 68HC11.
Connecting the RESET output of the µP supervisor
directly to the RESET input of the microcontroller with a
single pull-up resistor allows either device to assert
reset (Figure 17).
If additional noise margin is desired, connect a resistor
between PFO and PFI as shown in Figure 16a. Select
the ratio of R1 and R2 such that PFI sees V
when
PFT
V
IN
falls to its trip point (V
). R3 adds the additional
TRIP
hysteresis and should typically be more than 10 times
the value of R1 or R2. The hysteresis window extends
Ne g a t ive -Go in g V
Tra n s ie n t s
CC
These supervisors are relatively immune to short-dura-
both above (V ) and below (V ) the original trip point
H
L
tion negative-going V transients (glitches) while issu-
CC
(V
TRIP
).
ing resets to the µP during power-up, power-down, and
brownout conditions. Therefore, resetting the µP when
Connecting an ordinary signal diode in series with R3,
as shown in Figure 16b, causes the lower trip point (V )
L
V
experiences only small glitches is usually not rec-
CC
to coincide with the trip point without hysteresis (V
),
TRIP
ommended.
so the entire hysteresis window occurs above V
.
TRIP
Figure 18 shows maximum transient duration vs. reset-
comparator overdrive, for which reset pulses are not
generated. The graph was produced using negative-
pulses, starting at 3.3V and ending below
the reset threshold by the magnitude indicated (reset
comparator overdrive). The graph shows the maximum
This method provides additional noise margin without
compromising the accuracy of the power-fail threshold
when the monitored voltage is falling. It is useful for
accurately detecting when a voltage falls past a thresh-
old. The current through R1 and R2 should be at least
1µA to ensure that the 25nA (max over temperature)
PFI input current does not shift the trip point. R3 should
be larger than 82kΩ so it does not load down the PFO
pin. Capacitor C1 is optional, and adds noise rejection.
going V
CC
34/MAX795
pulse width a negative-going V transient can typically
CC
Mo n it o rin g a n Ad d it io n a l P o w e r S u p p ly
These µP supervisors can monitor either positive or
negative supplies using a resistor voltage divider to
START
SET WDI
HIGH
100
90
80
70
60
50
40
30
PROGRAM
CODE
Subroutine or
Program Loop
SET WDI LOW
20
10
0
10 20 30 40 50 60 70 80 90 100
RETURN
RESET COMPARATOR OVERDRIVE, V - V (mV)
RST
CC
Figure 18. Maximum Transient Duration without Causing a
Reset Pulse vs. Reset Comparator Overdrive
Figure 19. Watchdog Flow Diagram
18 ______________________________________________________________________________________
3 .0 V/3 .3 V Ad ju s t a b le Mic ro p ro c e s s o r
S u p e rvis o ry Circ u it s
34/MAX795
have without causing a reset pulse to be issued. As
the amplitude of the transient increases (i.e., goes far-
ther below the reset threshold), the maximum allowable
_________________P in Co n fig u ra t io n s
pulse width decreases. Typically, a V transient that
goes 40mV below the reset threshold and lasts for
10µs or less will not cause a reset pulse to be issued.
CC
TOP VIEW
OUT
BATT
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
RESET
LOWLINE
RESET
CE OUT
CE IN
A 0.1µF bypass capacitor mounted close to the V
CC
pin provides additional transient immunity.
CC
(RESET IN) BATT OK
PFI
BATT ON
GND
MAX793
MAX794
Wa t c h d o g S o ft w a re Co n s id e ra t io n s
There is a way to help the watchdog timer monitor soft-
ware execution more closely, which involves setting
and resetting the watchdog input at different points in
the program rather than “pulsing” the watchdog input
high-low-high or low-high-low. This technique avoids a
“stuck” loop, in which the watchdog timer would con-
tinue to be reset within the loop, keeping the watchdog
from timing out. Figure 19 shows an example of a flow
diagram where the I/O driving the watchdog input is
set high at the beginning of the program, set low at the
beginning of every subroutine or loop, then set high
again when the program returns to the beginning. If
the program should “hang” in any subroutine, the prob-
lem would quickly be corrected, since the I/O is contin-
ually set low and the watchdog timer is allowed to time
out, causing a reset or interrupt to be issued.
PFO
WDI
MR
WDO
DIP / Narrow SO
BATT
RESET
CE OUT
CE IN
OUT
1
8
7
6
5
V
2
3
4
CC
MAX795
BATT ON
GND
DIP/SO
( ) ARE FOR MAX794
___________________Ch ip In fo rm a t io n
_Ord e rin g In fo rm a t io n (c o n t in u e d )
PART*
TEMP. RANGE
0°C to +70°C
0°C to +70°C
-40°C to +85°C
-40°C to +85°C
0°C to +70°C
0°C to +70°C
-40°C to +85°C
-40°C to +85°C
PIN-PACKAGE
16 Plastic DIP
16 Narrow SO
16 Plastic DIP
16 Narrow SO
8 Plastic DIP
8 SO
TRANSISTOR COUNT: 1271
MAX794CPE
MAX794CSE
MAX794EPE
MAX794ESE
MAX795_CPA
MAX795_CSA
MAX795_EPA
MAX795_ESA
8 Plastic DIP
8 SO
* The MAX793/MAX795 offer a choice of reset threshold voltage.
Select the letter corresponding to the desired reset threshold volt-
age range (T = 3.00V to 3.15V, S = 2.85V to 3.00V, R = 2.55V
to 2.70V) and insert it into the blank to complete the part number.
The MAX794’s reset threshold is adjustable.
______________________________________________________________________________________ 19
3 .0 V/3 .3 V Ad ju s t a b le Mic ro p ro c e s s o r
S u p e rvis o ry Circ u it s
________________________________________________________P a c k a g e In fo rm a t io n
INCHES
MILLIMETERS
DIM
E
MIN
MAX
0.200
–
MIN
–
MAX
5.08
–
A
–
E1
D
A1 0.015
A2 0.125
A3 0.055
0.38
3.18
1.40
0.41
1.14
0.20
0.13
7.62
6.10
2.54
7.62
–
0.175
0.080
0.022
0.065
0.012
0.080
0.325
0.310
–
4.45
2.03
0.56
1.65
0.30
2.03
8.26
7.87
–
A3
A2
A1
A
L
B
0.016
B1 0.045
0.008
D1 0.005
0.300
E1 0.240
0.100
eA 0.300
C
0° - 15°
E
C
e
e
B1
eA
eB
–
–
B
eB
L
–
0.400
0.150
10.16
3.81
0.115
2.92
D1
INCHES
MILLIMETERS
PKG. DIM
PINS
Plastic DIP
PLASTIC
DUAL-IN-LINE
PACKAGE
(0.300 in.)
MIN
MAX MIN
MAX
8
P
P
P
P
P
N
D
D
D
D
D
D
0.348 0.390 8.84
9.91
14
16
18
20
24
0.735 0.765 18.67 19.43
0.745 0.765 18.92 19.43
0.885 0.915 22.48 23.24
1.015 1.045 25.78 26.54
1.14 1.265 28.96 32.13
21-0043A
34/MAX795
INCHES
MILLIMETERS
DIM
MIN
0.053
MAX
0.069
0.010
0.019
0.010
0.157
MIN
1.35
0.10
0.35
0.19
3.80
MAX
1.75
0.25
0.49
0.25
4.00
A
D
A1 0.004
B
C
E
e
0.014
0.007
0.150
0°-8°
A
0.101mm
0.004in.
0.050
1.27
e
H
L
0.228
0.016
0.244
0.050
5.80
0.40
6.20
1.27
A1
C
B
L
INCHES
MILLIMETERS
DIM PINS
Narrow SO
SMALL-OUTLINE
PACKAGE
MIN MAX
MIN
MAX
5.00
8.75
8
0.189 0.197 4.80
D
D
D
E
H
14 0.337 0.344 8.55
16 0.386 0.394 9.80 10.00
(0.150 in.)
21-0041A
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
20 __________________Ma x im In t e g ra t e d P ro d u c t s , 1 2 0 S a n Ga b rie l Drive , S u n n yva le , CA 9 4 0 8 6 (4 0 8 ) 7 3 7 -7 6 0 0
© 1996 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
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