MAX792TC/D [MAXIM]
Microprocessor and Non-Volatile Memory Supervisory Circuits; 微处理器和非易失性存储器监控电路
| 型号： | MAX792TC/D |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Microprocessor and Non-Volatile Memory Supervisory Circuits |
| 文件： | 总16页 (文件大小：251K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-0147; Rev. 2; 6/98
Mic ro p ro c e s s o r a n d No n -Vo la t ile
Me m o ry S u p e rvis o ry Circ u it s
79/MAX820
Ge n e ra l De s c rip t io n
Fe a t u re s
The MAX792/MAX820 microprocessor (µP) supervisory
circuits provide the most functions for power-supply
and watchdog monitoring in systems without battery
backup. Built-in features include the following:
♦ Manual-Reset Input
♦ 200ms Power-OK/Reset Time Delay
♦ Independent Watchdog Timer—Preset or Adjustable
♦ On-Board Gating of Chip-Enable Signals
♦ Memory Write-Cycle Completion
1) µP reset: Assertion of RESET and RESET outputs dur-
ing power-up, power-down, and brownout condi-
tions. RESET is guaranteed valid for VCC down to 1V.
♦ 10ns (max) Chip-Enable Gate Propagation Delay
♦ Voltage Monitor for Overvoltage Warning
2) Manual-reset input.
3) Two-stage power-fail warning: A separate low-line
comparator compares VCC to a preset threshold
120mV above the reset threshold; the low-line and
reset thresholds can be programmed externally.
♦ ±2% Reset and Low-Line Threshold Accuracy
(MAX820, external programming mode)
Ord e rin g In fo rm a t io n
4) Watchdog fault output: Assertion of WDO if the watch-
dog input is not toggled within a preset timeout
period.
PART**
TEMP. RANGE
0°C to +70°C
0°C to +70°C
0°C to +70°C
PIN-PACKAGE
16 Plastic DIP
16 Narrow SO
Dice*
MAX792_CPE
MAX792_CSE
MAX792_C/D
5) Puls e d wa tc hd og outp ut: Ad va nc e wa rning of
impending WDO assertion from watchdog timeout
that causes hardware shutdown.
Ordering Information continued at end of data sheet.
* Dice are tested at T = +25°C, DC parameters only.
6) Write protection of CMOS RAM, EEPROM, or other
memory devices.
A
**These parts offer a choice of five different reset threshold volt-
ages. Select the letter corresponding to the desired nominal
reset threshold voltage and insert it into the blank to complete the
part number.
The MAX792 and MAX820 are identical, except the
MAX820 guarantees higher low-line and reset threshold
accuracy (±2%).
SUFFIX
RESET THRESHOLD (V)
Ap p lic a t io n s
Computers
Controllers
L
M
T
S
R
4.62
4.37
3.06
2.91
2.61
Intelligent Instruments
Critical µP Power Monitoring
Typ ic a l Op e ra t in g Circ u it
V
CC
0.1µF
3
V
V
CC
CC
13
14
CE OUT
4
5
RESET IN/INT
µP
RAM
MAX792
ADDRESS
DECODER
CE IN
OVO
LLIN/
REFOUT
A0-A15
6
10
1
LOW LINE
RESET
MR
NMI
7
8
OVI
RESET
9
SWT
GND
12
GND
________________________________________________________________ Maxim Integrated Products
1
For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800.
For small orders, phone 1-800-835-8769.
Mic ro p ro c e s s o r a n d No n -Vo la t ile
Me m o ry S u p e rvis o ry Circ u it s
ABSOLUTE MAXIMUM RATINGS
Input Voltage (with respect to GND)
.......................................................................-0.3V to +6V
Operating Temperature Ranges:
V
MAX792_C__/MAX820_C__................................0°C to +70°C
MAX792_E__/MAX820_E__ .............................-40°C to +85°C
MAX792_MJE__/MAX820_MJE__..................-55°C to +125°C
Storage Temperature Range .............................-65°C to +160°C
Lead Temperature (soldering, 10sec) .............................+300°C
CC
All Other Inputs.......................................-0.3V to (V + 0.3V)
CC
Input Current
GND ................................................................................25mA
All Other Outputs ............................................................25mA
Continuous Power Dissipation (T = +70°C)
A
Plastic DIP (derate 10.53mW/°C above +70°C) ..........842mW
Narrow SO (derate 9.52mW/°C above +70°C) ............762mW
CERDIP (derate 10.00mW/°C above +70°C)...............800mW
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
79/MAX820
(V = 2.65V to 5.5V, T = T to T
, unless otherwise noted.)
MAX
CC
A
MIN
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Operating Voltage Range
Supply Current
2.65
V
70
150
µA
RESET COMPARATOR
MAX792L, MAX820L
4.50
4.25
2.55
2.85
3.00
4.55
4.30
2.55
2.85
3.00
1.25
1.274
4.62
4.37
2.61
2.91
3.06
4.75
4.50
2.70
3.00
3.15
4.70
4.45
2.66
2.96
3.11
1.35
1.326
MAX792M, MAX820M
MAX792R, MAX820R
MAX792S, MAX820S
MAX792T, MAX820T
Reset Threshold Voltage—
Internal Threshold Mode
V
MAX820L, T = +25°C, V falling
CC
A
(V
TH
)
MAX820M, T = +25°C, V falling
CC
A
MAX820R, T = +25°C, V falling (Note 1)
CC
A
MAX820S, T = +25°C, V falling
CC
A
MAX820T, T = +25°C, V falling
CC
A
MAX792, V = 5V or V = 3V
1.30
1.30
Reset Threshold Voltage
External Threshold Mode (V
CC
CC
V
)
TH
MAX820, V = 5V or V = 3V
CC CC
RESET IN/INT Mode Threshold
(Note 2)
Internal threshold mode
60
mV
±0.01
±25
nA
V
RESET IN/INT Leakage Current
Reset Threshold Hysteresis
Reset Comparator Delay
0.016 x V
TH
V
falling
rising
70
200
0.01
0.1
µs
CC
Reset Active Timeout Period
V
CC
140
280
0.3
0.4
ms
I
= 50µA, V = 1V, V falling
CC
CC
SINK
I
= 1.6mA
SINK
V
V
RESET Output Voltage
I
= 1mA
V
- 1
SOURCE
CC
I
= 100µA
V
- 0.5
SOURCE
CC
I
= 1.6mA
0.1
0.4
SINK
RESET Output Voltage
I
= 1mA
V
- 1
SOURCE
CC
I
= 100µA
V
CC
- 0.5
SOURCE
2
_______________________________________________________________________________________
Mic ro p ro c e s s o r a n d No n -Vo la t ile
Me m o ry S u p e rvis o ry Circ u it s
79/MAX820
ELECTRICAL CHARACTERISTICS (continued)
(V = 2.65V to 5.5V, T = T
to T , unless otherwise noted.)
MAX
CC
A
MIN
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
LOW-LINE COMPARATOR
MAX792/MAX820L/M
MAX792/MAX820R/S/T
50
40
120
100
210
210
Low-Line Threshold Voltage
(Internal Threshold Mode)—V
mV
V
TH
MAX792, V = 5V OR V = 3V
1.25
1.274
1.30
1.30
1.35
1.326
CC
CC
Low-Line Threshold Voltage
(External Programming Mode)
MAX820, V = 5V OR V = 3V
CC
CC
Low-Line Hysteresis
(Internal Threshold Mode)
20
mV
LLIN/REFOUT Leakage Current
External Programming Mode
±0.01
450
±25
nA
µs
Low-Line Comparator Delay
V
CC
falling
I
= 3.2mA
0.4
50
SINK
V
LOWLINE Voltage
I
= 1µA
V
CC
- 1
SOURCE
Output source current, V = 5.5V
10
µA
LOWLINE Short-Circuit Current
CC
WATCHDOG FUNCTION
SWT connected to V
SWT connected to V
V
1.00
1.00
1.60
1.60
2.25
2.25
CC, CC = 5V
sec
ms
ns
V
CC, CC = 3V
4.7nF capacitor connected from SWT to GND
,
70
Watchdog Timeout Period
V
CC = 3V
4.7nF capacitor connected from SWT to GND
,
100
V
CC = 5V
V = 0V, V = V
IL
V
100
300
CC = 5V
Watchdog Input Pulse Width
IH
CC
V
CC = 3V
I
= 50µA, V = 1V, V falling
0.01
0.1
0.30
0.4
SINK
CC
CC
I
= 1.6mA
SINK
V
WDO Output Voltage
I
= 1mA
V
CC
- 1
SOURCE
I
= 100µA
V
CC
- 0.5
SOURCE
70
ns
WDPO to WDO Delay
WDPO Duration
0.5
1.7
0.01
0.1
6.0
0.3
0.4
ms
I
= 50µA, V = 1V, V falling
CC CC
SINK
I
= 1.6mA
SINK
V
WDPO Output Voltage
I
= 1mA
V
- 1
SOURCE
CC
I
= 100µA
V
CC
- 0.5
SOURCE
V
0.75 x V
CC
IH
V
CC
= 4.25V
V
IL
0.8
WDI Threshold Voltage
WDI Input Current
V
V
0.9 x V
CC
IH
V
CC
= 2.55V
V
IL
0.2
±1
µA
_______________________________________________________________________________________
3
Mic ro p ro c e s s o r a n d No n -Vo la t ile
Me m o ry S u p e rvis o ry Circ u it s
ELECTRICAL CHARACTERISTICS (continued)
(V = 2.65V to 5.5V, T = T to T
, unless otherwise noted.)
MAX
CC
A
MIN
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
OVERVOLTAGE COMPARATOR
OVI Input Threshold
V
= 5V or V = 3V
1.25
1.30
1.35
±25
0.4
V
CC
CC
OVI Leakage Current
±0.01
nA
I
= 3.2mA
SINK
V
µA
µs
OVO Output Voltage
OVO Short-Circuit Current
OVI to OVO Delay
I
= 1µA
V
- 1
CC
SOURCE
Output source current, V = 5.5V
10
13
55
50
CC
V
OD
= 100mV, OVI rising
= 100mV, OVI falling
V
OD
CHIP-ENABLE GATING
V
0.75 x V
IH
CC
V
= 4.25V
= 2.55V
CC
V
IL
0.8
79/MAX820
V
CE IN Threshold Voltage
V
IH
0.75 x V
CC
V
CC
V
IL
0.2
±1
Disabled mode
Enabled mode
±0.005
75
µA
CE IN Leakage Current
V
= 5V
= 3V
= 5V
= 3V
= 5V
= 3V
150
300
2.5
0.4
10
CC
Ω
CE IN to CE OUT Resistance
V
CC
150
V
CC
0.5
mA
ns
CE OUT Short-Circuit Current
Disabled mode, CE
= 0V
OUT
V
CC
0.05
0.2
6
V
CC
Chip-Enable Propagation Delay 50Ω source impedance driver,
(Note 3)
C
= 50pF
LOAD
V
CC
8
13
I
= -100µA
= 10µA
falling
V
- 1
Chip-Enable Output Voltage
High (Reset Active)
OUT
CC
V
I
V
CC
- 0.5
OUT
V
15
µs
Reset Active to CE OUT High
MANUAL RESET
CC
25
µs
µs
V
MR Minimum Pulse Width
12
1.3
23
MR to RESET Propagation Delay
MR Threshold Range
1.1
5
1.5
80
V
= 4.25V
CC
to V = 5.5V
µA
MR Pull-Up Current
MR = 0V
CC
V
CC
= 2.5V
1
Note 1: The minimum operating voltage is 2.65V; however, the device is guaranteed to operate down to its preset reset threshold.
Note 2: Pulling RESET IN/INT below 60mV selects internal threshold mode and connects the internal voltage divider to the reset
and low-line comparators. External programming mode allows an external resistor divider to set the low-line and reset
thresholds (see Figure 4).
Note 3: The Chip-Enable Propagation delay is measured from the 50% point at CE IN to the 50% point at CE OUT.
4
_______________________________________________________________________________________
Mic ro p ro c e s s o r a n d No n -Vo la t ile
Me m o ry S u p e rvis o ry Circ u it s
79/MAX820
__________________________________________Typ ic a l Op e ra t in g Ch a ra c t e ris t ic s
(T = +25°C, unless otherwise noted.)
A
OVERVOLTAGE COMPARATOR
PROPAGATION DELAY vs. TEMPERATURE
RESET COMPARATOR
PROPAGATION DELAY vs. TEMPERATURE
SUPPLY CURRENT vs. TEMPERATURE
100
70
60
80
70
SWT = VCC
ALL OUTPUTS
UNLOADED
90
V
= 5V
CC
80
70
60
50
V
CC
= 4V
50
60
V
CC
= 3V
40
30
20
40
30
50
40
V
TO V
OL
= 20mV
V
FALLING
IH
CC
V
CC
= 2V
V
15mV OVERDRIVE
EXTERNAL PROGRAMMING MODE
IN
10
0
OVERDRIVE = 15mV
-60 -30
0
30
60
90 120 150
-60 -30
0
30
60 90 120 150
-60 -30
0
30
60
90 120 150
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
LOW-LINE COMPARATOR
PROPAGATION DELAY vs. TEMPERATURE
NOMINAL WATCHDOG TIMEOUT
PERIOD vs. V
POWER-UP RESET DELAY
vs. TEMPERATURE
CC
300
250
3.0
600
500
2.5
2.0
V
= 5V
CC
200
150
100
400
300
V
CC
= 3V
1.5
1.0
200
100
V
FALLING
CC
50
0
15mV OVERDRIVE
EXTERNAL PROGRAMMING MODE
-60 -30
0
30
60 90 120 150
2
3
4
5
-60 -30
0
30
60
90 120 150
TEMPERATURE (°C)
V
CC
(V)
TEMPERATURE (°C)
_________________________________________________________________________________________________
5
Mic ro p ro c e s s o r a n d No n -Vo la t ile
Me m o ry S u p e rvis o ry Circ u it s
____________________________Typ ic a l Op e ra t in g Ch a ra c t e ris t ic s (c o n t in u e d )
(T = +25°C, unless otherwise noted.)
A
INTERNAL-MODE RESET THRESHOLD
vs. TEMPERATURE (NORMALIZED)
REF OUT VOLTAGE
vs. TEMPERATURE
CHIP-ENABLE ON-RESISTANCE
vs. TEMPERATURE
1.125
1.100
1.075
1.33
1.32
1.31
1.30
1.29
200
180
160
140
120
100
80
V
V
CE IN
= 3V
= 1.5V
CC
1.050
1.025
1.000
0.975
1.28
1.27
60
0.950
V
= 5V
= 2.5V
CC
THE RESET THRESHOLD IS SHOWN
NORMALIZED TO 1, REPRESENTING
ALL AVAILABLE MAX792/MAX820
40
V
CE IN
0.925
0.900
1.26
1.25
79/MAX820
RESET IN / INT = 0V
20
0
-60 -30
0
30
60
90 120 150
-60
-30
0
30
60
90 120 150
-60 -30
0
30
60
90 120 150
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
WATCHDOG TIMEOUT PERIOD
vs. SWT LOAD CAPACITANCE
CHIP-ENABLE PROPAGATION DELAY
vs. CE OUT LOAD CAPACITANCE
100k
10k
20
15
10
5
V
= +5V
= 0V TO 5V
CC
V
CE IN
DRIVER SOURCE
IMPEDANCE = 50Ω
V
CC
= 5V
1k
100
10
V
= 3V
CC
0
1n
10n
100n
1m
0
25 50 75 100 125 150 175 200 225 250
C
SWT
(F)
C
LOAD
(pF)
6
_______________________________________________________________________________________
Mic ro p ro c e s s o r a n d No n -Vo la t ile
Me m o ry S u p e rvis o ry Circ u it s
79/MAX820
______________________________________________________________P in De s c rip t io n
PIN
NAME
RESET
RESET
FUNCTION
Active-Low Reset Output goes low whenever V falls below the reset threshold in internal thresh-
CC
old programming mode, or RESET IN falls below 1.30V in external threshold programming mode.
RESET remains low for 200ms typ after the threshold is exceeded on power-up.
1
2
3
Reset is the inverse of RESET.
V
Input Supply Voltage
CC
Reset-Input/Internal-Mode Select. Connect this input to GND to select internal threshold mode.
Select external programming mode by pulling this input 600mV or higher through an external volt-
age divider.
4
5
RESET IN/INT
Low-Line Input/Reference Output connects directly to the low-line comparator in external program-
ming mode (RESET IN/INT ≥ 600mV). Connects directly to the internal 1.30V reference in internal
threshold mode (RESET IN/INT ≤60mV).
LLIN/REF OUT
Overvoltage Comparator Output goes low when OVI is greater than 1.30V. This is an uncommitted
comparator and has no effect on any other internal circuitry.
6
7
OVO
Inverting Input to the Overvoltage Comparator. When OVI is greater than 1.30V, OVO goes low.
OVI
Connect OVI to GND or V when not used.
CC
Set Watchdog-Timeout Input. Connect this input to V to select the default 1.6sec watchdog
CC
timeout period. Connect a capacitor between this input and GND to select another watchdog-
timeout period. Watchdog timeout period = k x (capacitor value in nF)mV, where k = 27 for
8
SWT
V
CC
= 5V and k = 16.2 for V = 3V. If the watchdog function is unused, connect SWT to V
.
CC
CC
Manual-Reset Input. This input can be tied to an external momentary pushbutton switch, or to a
logic gate output. Internally pulled up to V
9
MR
.
CC
Low-Line Output. LOW LINE goes low 120mV above the reset threshold in internal threshold mode,
or when LLIN/REFOUT goes below 1.30V in external programming mode.
10
LOW LINE
Watchdog Input. If WDI remains either high or low for longer than the watchdog timeout period,
11
12
13
WDI
GND
WDPO pulses low and WDO goes low. WDO remains low until the next transition at WDI. Connect to
GND or V if unused.
CC
Ground
Chip-Enable Output. CE OUT goes low only when CE IN is low and reset is not asserted. If CE IN is
low when reset is asserted, CE OUT will stay low for 15µs or until CE IN goes high, whichever
occurs first.
CE OUT
Chip-Enable Input—the input to the chip-enable transmission gate. Connect to GND or V if not
CC
used.
14
15
16
CE IN
WDO
Watchdog Output. WDO goes low if WDI remains either high or low longer than the watchdog time-
out period. WDO returns high on the next transition at WDI.
Watchdog-Pulse Output. Upon the absence of a transition at WDI, WDPO will pulse low for a mini-
mum of 500µs. WDPO precedes WDO by typically 70ns.
WDPO
_______________________________________________________________________________________
7
Mic ro p ro c e s s o r a n d No n -Vo la t ile
Me m o ry S u p e rvis o ry Circ u it s
De t a ile d De s c rip t io n
External Programming Mode
Connecting RESET IN/INT to a voltage above 600mV
selects external programming mode. In this mode, the
low-line and reset comparators disconnect from the inter-
nal voltage divider and connect to LLIN/REFOUT and
RESET IN/INT, respectively (Figure 1). This mode allows
flexibility in determining where in the operating voltage
range the NMI and reset are generated. Set the low-line
and reset thresholds with an external resistor divider, as in
Figure 4b or Figure 4c. RESET typically remains valid for
VCC down to 2.5V; RESET is guaranteed to be valid with
VCC down to 1V.
Ma n u a l-Re s e t In p u t
Many µP-based products require manual-reset capabil-
ity, allowing the operator to initiate a reset. The manu-
al/external-reset input (MR) can connect directly to a
switch without an external pull-up resistor or debounc-
ing network. MR internally connects to a 1.30V com-
parator, and has a high-impedance pull-up to VCC, as
shown in Figure 1. The propagation delay from assert-
ing MR to reset asserted is typically 12µs. Pulsing MR
low for a minimum of 25µs asserts the reset function
(see Reset Function section). The reset output remains
active as long as MR is held low, and the reset timeout
period begins after MR returns high (Figure 2). To pro-
vide extra noise immunity in high-noise environments,
pull MR up to VCC with a 100kΩ resistor.
Calculate the values for the resistor voltage divider in
Figure 4b using the following equations:
1) R3 = (1.30 x VCC MAX)/(VLOW LINE x IMAX
)
79/MAX820
2) R2 = [(1.30 x VCC MAX)/(VRESET x IMAX)] - R3
3) R1 = (VCC MAX/IMAX) - (R2 + R3).
Use MR as either a digital logic input or as a second low-
line c omp a ra tor. Norma l TTL/CMOS le ve ls c a n b e
wire-OR connected via pull-down diodes (Figure 3),
and open-drain/collector outputs can be wire-ORed
directly.
First choose the desired maximum current through the
voltage divider (IMAX) when VCC is at its highest (VCC
MAX). There are two things to consider here. First, IMAX
contributes to the overall supply current for the circuit, so
you would g e ne ra lly ma ke it a s s ma ll a s p os s ib le .
Second, IMAX cannot be too small or leakage currents will
adversely affect the programmed threshold voltages; 5µA
is often appropriate. Determine R3 after you have chosen
IMAX. Use the value for R3 to determine R2, then use both
R2 and R3 to determine R1.
Mo n it o rin g t h e Re g u la t e d S u p p ly
The MAX792/MAX820 offer two modes for monitoring
the regulated supply and providing reset and non-
maskable interrupt (NMI) signals to the µP: internal
threshold mode uses the factory preset low-line and
re s e t thre s hold s , a nd e xte rna l p rog ra mming mod e
allows the low-line and reset thresholds to be pro-
grammed externally using a resistor voltage divider
(Figure 4).
For example, to program a 4.75V low-line threshold and a
4.4V reset threshold, first choose IMAX to be 5µA when
VCC = 5.5V and substitute into equation 1.
R3 = (1.30 x 5.5)/(4.75 x 5E-6) = 301.05kΩ.
Internal Threshold Mode
301kΩ is the nearest standard 0.1% value. Substitute
Connecting the reset-input/internal-mode select pin
(RESET IN/INT) to ground selects internal threshold
mode (Figure 4a). In this mode, the low-line and reset
thresholds are factory preset by an internal voltage
divider (Figure 1) to the threshold voltages specified in
the Electrical Characteristics (Reset Threshold Voltage
and Low-Line Threshold Voltage). Connect the low-line
output (LOWLINE) to the µP NMI pin, and connect the
active-high reset output (RESET) or active-low reset
output (RESET) to the µP reset input pin.
into equation 2:
R2 = [(1.30 x 5.5)/(4.4 x 5E-6)] - 301kΩ = 23.95kΩ.
The nearest 0.1% resistor value is 23.7kΩ. Finally, sub-
stitute into equation 3:
R1 = (5.5/5E-6) - (23.7kΩ + 301kΩ) = 775kΩ.
The nearest 0.1% value resistor is 787kΩ. Determine the
actual low-line threshold by rearranging equation 1 and
plugging in the standard resistor values. The actual low-
line threshold is 4.75V and the actual reset threshold is
4.40V. An additional resistor allows the MAX792/MAX820
to monitor the unregulated supply and provide an NMI
before the regulated supply begins to fall (Figure 4c).
Additionally, the low-line input/reference-output pin
(LLIN/REFOUT) connects to the internal 1.30V refer-
ence in internal threshold mode. Buffer LLIN/REFOUT
with a high-impedance buffer to use it with external
circuitry. In this mode, when VCC is falling, LOWLINE is
guaranteed to be asserted prior to reset assertion.
Both of these thresholds will vary from circuit to circuit
with resistor tolerance, reference variation, and compara-
tor offset variation. The initial thresholds for each circuit
will also vary with temperature due to reference and off-
set drift. For highest accuracy, use the MAX820.
8
_______________________________________________________________________________________
Mic ro p ro c e s s o r a n d No n -Vo la t ile
Me m o ry S u p e rvis o ry Circ u it s
79/MAX820
V
CC
3
2
V
CC
RESET
*
RESET
COMPARATOR
4
RESET IN/
INT
RESET
GENERATOR
1
RESET
V
CC
5
9
LLIN/
10
REFOUT
LOW LINE
V
CC
V
CC
LOW-LINE
COMPARATOR
CHIP-ENABLE
OUTPUT
CONTROL
P
V
CC
MR
MANUAL
RESET
COMPARATOR
1.30V
V
CC
INTERNAL/
EXTERNAL
MODE
CONTROL
60mV
INTERNAL
EXTERNAL
P
13
14
CE IN
CE OUT
TIMEBASE FOR
RESET AND
WATCHDOG
N
16
15
WDPO
WDO
8
WATCHDOG
TIMER
SWT
WDI
11
WATCHDOG
TRANSITION
DETECTOR
V
CC
MAX792
MAX820
OVERVOLTAGE
COMPARATOR
6
OVO
7
OVI
12
* SWITCHES ARE SHOWN IN INTERNAL
THRESHOLD MODE POSITION
GND
Figure 1. Block Diagram
_______________________________________________________________________________________
9
Mic ro p ro c e s s o r a n d No n -Vo la t ile
Me m o ry S u p e rvis o ry Circ u it s
V
IN
25µs MIN
MR
3
V
CC
12µs TYP
RESET
4
2
RESET IN/INT
TO µP
RESET
CE IN OV
CE OUT
MAX792
LLIN/REFOUT
1
5
TO µP
RESET
15µs TYP
10
TO µP NMI
LOW LINE
Figure 2. Manual-Reset Timing Diagram
GND
12
MANUAL RESET
79/MAX820
9
MR
Figure 4a. Connection for Internal Threshold Mode
*
OTHER
V
IN
RESET
SOURCES
MAX792
MAX820
*
.
.
.
3
R1
R2
V
CC
2
TO µP
RESET IN/INT
RESET
RESET
*
DIODES NOT REQUIRED ON OPEN-DRAIN OUTPUTS
Figure 3. Diode "OR" connections allow multiple reset sources
to connect to MR.
MAX792
1
TO µP
LLIN/REFOUT
Low-Line Output
R3
10
In internal threshold mode, the low-line comparator
monitors VCC with a threshold voltage typically 120mV
above the reset threshold, and with 15mV of hysteresis.
For normal operation (VCC above the reset threshold),
LOWLINE is pulled to VCC. Use LOWLINE to provide an NMI
to the µP, as described in the previous section, when
VCC begins to fall (Figure 4).
TO µP NMI
LOW LINE
GND
12
R3 = 1.30V x V
CC MAX
x I
V
LOW LINE MAX
R2 = 1.30V x V
CC MAX
I
= THE MAXIMUM DESIRED CURRENT
THROUGH THE VOLTAGE DIVIDED.
R3
MAX
–
V
x I
RESET MAX
Re s e t Fu n c t io n
R1 = V
CC MAX
– (R2 + R3)
I
MAX
The MAX792/MAX820 provide both RESET and RESET
outputs. The RESET and RESET outputs ensure that the
µP powers up in a known state, and prevent code-exe-
c ution e rrors d uring p owe r-up , p owe r-d own, or
brownout conditions.
Figure 4b. Connection for External Threshold Programming Mode
When reset is asserted, all the internal counters are
reset, the watchdog output (WDO) and watchdog-pulse
output (WDPO) are set high, and the set watchdog-time-
out input (SWT) is set to (VCC - 0.6V) if it is not already
connected to VCC (for internal timeouts). The chip-
enable transmission gate is also disabled while reset is
asserted; the chip-enable input (CE IN) becomes high
impedance and the chip-enable output (CE OUT) is
The reset function will be asserted during the following
conditions:
1) VCC less than the programmed reset threshold.
2) MR less than 1.30V typ.
3) Reset remains asserted for 200ms typ after VCC
rises above the reset threshold or after MR has
exceeded 1.30V typ.
pulled up to VCC
.
10 ______________________________________________________________________________________
Mic ro p ro c e s s o r a n d No n -Vo la t ile
Me m o ry S u p e rvis o ry Circ u it s
79/MAX820
1
REGULATOR
TO µP RESET
RESET
10k
MAX792
MAX820
V
CC
R3
R4
2
RESET IN/INT
RESET
RESET
TO µP
R1
MAX792
MAX820
1
LLIN/REFOUT
TO µP
Figure 5. Adding an external pull-down resistor ensures RESET
R2
is valid with VCC down to GND.
10
LOW LINE
TO µP NMI
GND
VOLTAGE REGULATOR
V
= 1.3 R1 + R2
LOW LINE
(
)
R2
V
RESET
= 1.3 R3 + R4
(
)
3
V
CC
R4
Figure 4c. Alternative Connection for External Programming Mode
MAX792
MAX820
Reset Outputs (RESET and RESET)
7
OVI
The RESET output is active low and typically sinks 1.6mA
at 0.1V. When deasserted, RESET sources 1.6mA at typi-
cally VCC - 1.5V. The RESET output is the inverse of
RESET. RESET is guaranteed to be valid down to VCC = 1V,
a nd a n e xte rna l 10kΩ p ull-d own re s is tor on RESET
ensures that it will be valid with VCC down to GND
(Figure 5). As VCC goes below 1V, the gate drive to the
RESET output switch reduces accordingly, increasing the
rDS(ON) and the saturation voltage. The 10kΩ pull-down
resistor ensures that the parallel combination of switch
plus resistor will be around 10kΩ and the saturation
voltage will be below 0.4V while sinking 40µA. When
using an external pull-down resistor of 10kΩ, the high
state for the RESET output with VCC = 4.75V is typically
4.60V.
OVO
6
OVERVOLTAGE
1.30V
GND
12
Figure 6. Detecting an Overvoltage Condition
Wa t c h d o g Fu n c t io n
The watchdog monitors µP activity via the watchdog
input (WDI). If the µP becomes inactive, WDO and WDPO
are asserted. To use the watchdog function, connect
WDI to a µP bus line or I/O line. If WDI remains high or
low for long e r tha n the wa tc hd og time out p e riod
(1.6sec nominal), WDPO and WDO are asserted, indicat-
ing a software fault condition (see Watchdog-Pulse
Output and Watchdog Output sections).
Ove rvo lt a g e Co m p a ra t o r
The overvoltage comparator is an uncommitted com-
parator that has no effect on the operation of other chip
functions. Use this input to provide overvoltage indica-
tion by connecting a voltage divider from the input sup-
ply, as in Figure 6.
Connect OVI to ground if the overvoltage function is not
used. OVO goes low when OVI goes above 1.30V. With
OVI below 1.30V, OVO is actively pulled to VCC and can
source1µA.
Watchdog Input
If the watchdog function is unused, connect WDI to VCC
or GND. A change of state (high-to-low, low-to-high, or
a minimum 100ns pulse) at WDI during the watchdog
period resets the watchdog timer. The watchdog timer
______________________________________________________________________________________ 11
Mic ro p ro c e s s o r a n d No n -Vo la t ile
Me m o ry S u p e rvis o ry Circ u it s
MIN 100ns (V = 5V)
CC
MIN 300ns (V = 3V)
CC
1.6sec
V
CC
WDI
3
0.1µF
V
CC
V
CC
WDPO
µP POWER
MAX792
MAX820
70ns
1
WDO
RESET
I/O
RESET
11
16
WDI
WDPO
V
= 5V
CC
V
CC
Q
Q
CLOCK
CLEAR
15
9
WDO
D
MR
Figure 7. WDI, WDO and WDPO Timing Diagram
GND
12
TWO
+5V
*
CONSECUTIVE
WATCHDOG
FAULT
default is 1.6sec. Select alternative timeout periods by
connecting an external capacitor from SWT to GND
(see Selecting an Alternative Watchdog Timeout sec-
tion). When VCC is below the reset threshold, the watch-
dog function is disabled.
79/MAX820
0.1µF
INDICATION
REACTIVATE
* FOR SYSTEM RESET ON EVERY
WATCHDOG FAULT, OMIT THE
FLIP-FLOP, AND DIODE–OR
CONNECT WDO TO MR.
4.7k
Watchdog Output
WDO remains high if there is a transition or pulse at WDI
during the watchdog timeout period. The watchdog
function is disabled and WDO is a logic high when VCC
is below the reset threshold. If a system reset is desired
on every watchdog fault, simply diode-OR connect WDO
to MR (Figure 8). When a watchdog fault occurs in this
mode, WDO goes low, pulling MR low and causing a
reset pulse to be issued. As soon as reset is asserted,
the watchdog timer clears and WDO goes high. With
WDO connected to MR, a continuous high or low on WDI
will c a us e 200ms re s e t p uls e s to b e is s ue d e ve ry
1.6sec (SWT connected to VCC). When reset is not
a s s e rte d , if no tra ns ition oc c urs a t WDI d uring the
watchdog timeout period, WDO goes low 70ns after the
falling edge of WDPO and remains low until the next tran-
sition at WDI (Figure 7). A single additional flip-flop can
force the system into a hardware shutdown if there are
two successive watchdog faults (Figure 8). When the
MAX792/MAX820 are operated from a 5V supply, WDO
has a 2 x TTL output characteristic.
Figure 8. Two consecutive watchdog faults latch the system in
reset.
WDI, WDO remains low and the next WDPO following a
second watchdog timeout period clocks a logic low to
the Q outp ut, p ulling MR low a nd c a us ing the
MAX792/MAX820 latch in reset. If the watchdog timer is
reset by a transition at WDI, WDO will go high and the
flip-flop’s Q output will remain high. Thus a system
shutdown is only caused by two successive watchdog
faults.
Selecting an Alternative Watchdog Timeout Period
The SWT input controls the watchdog timeout period.
Connecting SWT to VCC selects the internal 1.6sec
watchdog timeout period. Select an alternative watch-
dog timeout period by connecting a capacitor between
SWT and GND. Do not leave SWT floating and do not
connect it to ground. The following formula determines
the watchdog timeout period:
Watchdog-Pulse Output
As described in the preceding section, WDPO can be
used as the clock input to an external D flip-flop. Upon
the absence of a watchdog edge or pulse at WDI at the
end of a watchdog timeout period, WDPO will pulse low
for 1.7ms. The falling edge of WDPO precedes WDO by
70ns. Since WDO is high when WDPO goes low, the flip-
flop’s Q output remains high after WDO goes low (Figure
8). If the watchdog timer is not reset by a transition at
Watchdog Timeout Period =
k x (capacitor value in nF)ms
where k = 27 for VCC = 3V, and k = 16.2 for VCC = 5V.
This applies for capacitor values in excess of 4.7nF. If
the watchdog function is unused, connect SWT to VCC
.
12 ______________________________________________________________________________________
Mic ro p ro c e s s o r a n d No n -Vo la t ile
Me m o ry S u p e rvis o ry Circ u it s
79/MAX820
Ch ip -En a b le S ig n a l Ga t in g
V
RESET
THRESHOLD
CC
The MAX792/MAX820 provide internal gating of chip-
enable (CE) signals, which prevents erroneous data
from corrupting CMOS RAM in the event of an under-
voltage condition. The MAX792/MAX820 use a series
transmission gate from CE IN to CE OUT (Figure 1).
CE IN
During normal operation (reset not asserted), the CE
transmission gate is enabled and passes all CE transi-
tions. When reset is asserted, this path becomes dis-
abled, preventing erroneous data from corrupting the
CMOS RAM. The 10ns max CE propagation delay from
CE IN to CE OUT enables the MAX792/MAX820 to be
used with most µPs. If CE IN is low when reset asserts,
CE OUT remains low for a short period to permit com-
pletion of the current write cycle.
CE OUT
15µs
70µs
70µs
RESET
RESET
Figure 9. Reset and Chip-Enable Timing
Chip-Enable Input
The CE transmission gate is disabled and CE IN is high
impedance (disabled mode) while reset is asserted.
+5V
3
During a power-down sequence when VCC passes the
reset threshold, the CE transmission gate disables and
CE IN immediately becomes high impedance if the volt-
age at CE IN is high. If CE IN is low when reset is assert-
ed, the CE transmission gate will disable at the moment
CE IN g oe s hig h or 15µs a fte r re s e t is a s s e rte d ,
whichever occurs first (Figure 9). This permits the cur-
rent write cycle to complete during power-down.
V
CC
MAX792
MAX820
14
13
CE IN
CE OUT
C
LOAD
50Ω DRIVER
GND
12
During a power-up sequence, the CE transmission gate
remains disabled and CE IN remains high impedance
regardless of CE IN activity, until reset is deasserted fol-
lowing the reset timeout period.
Figure 10. CE Propagation Delay Test Circuit
While disabled, CE IN is high impedance. When the CE
transmission gate is enabled, the impedance of CE IN
will appear as a 75Ω (VCC = 5V) resistor in series with
the load at CE OUT.
Chip-Enable Output
When the CE transmission gate is enabled, the imped-
ance of CE OUT is equivalent to 75Ω in series with the
source driving CE IN. In the disabled mode, the 75Ω
transmission gate is off and an active pull-up connects
from CE OUT to VCC. This source turns off when the
transmission gate is enabled.
The propagation delay through the CE transmission
gate depends on VCC, the source impedance of the
drive connected to CE IN, and the loading on CE OUT
(see the Chip-Enable Propagation Delay vs. CE OUT
Loa d Ca p a c ita nc e g ra p h in the Typ ic a l Op e ra ting
Characteristics). The CE propagation delay is produc-
tion tested from the 50% point on CE IN to the 50%
point on CE OUT using a 50Ω driver and 50pF of load
capacitance (Figure 10). For minimum propagation
delay, minimize the capacitive load at CE OUT, and use
a low-output-impedance driver.
Ap p lic a t io n s In fo rm a t io n
Connect a 0.1µF ceramic capacitor from VCC to GND,
as close to the device pins as possible. This reduces
the probability of resets due to high-frequency power-
supply transients. In a high-noise environment, addi-
tional bypass capacitance from VCC to ground may be
re q uire d . If long le a d s c onne c t to the c hip inp uts ,
ensure that these lines are free from ringing, etc., which
would forward bias the chip’s protection diodes.
______________________________________________________________________________________ 13
Mic ro p ro c e s s o r a n d No n -Vo la t ile
Me m o ry S u p e rvis o ry Circ u it s
+5V
R *
P
CE
CE
CE
CE
CE
CE
CE
CE
3
RAM 1
RAM 2
BUFFER
V
CC
TO OTHER
SYSTEM RESET
INPUTS
V
CC
MAX792
MAX820
3
V
V
CC
CC
14
13
CE IN
CE OUT
4.7k
µP
1
RESET
RESET
RAM 3
RAM 4
GND
12
MAX792
MAX820
GND
GND
12
* MAXIMUM R VALUE DEPENDS ON
P
THE NUMBER OF RAMS.
MINIMUM R VALUE IS 1kΩ
79/MAX820
P
ACTIVE-HIGH CE
LINES FROM LOGIC
Figure 12. Interfacing to µPs with Bidirectional RESET Pins
Figure 11. Alternate CE Gating
going V
CC
pulses, starting at 5V and ending below the
Alt e rn a t ive Ch ip -En a b le Ga t in g
re s e t thre s hold b y the ma g nitud e ind ic a te d (re s e t-
comparator overdrive). The graph shows the maximum
Using memory devices with both CE and CE inputs
allows the MAX792/MAX820 CE p rop a g a tion d e la y
to be bypassed. To do this, connect CE IN to ground,
pull up CE OUT to VCC, and connect CE OUT to the CE
input of each memory device (Figure 11). The CE input
of each memory device then connects directly to the
chip-select logic, which does not have to be gated by
the MAX792/MAX820.
pulse width a negative-going V
transient may typi-
CC
cally have without causing a reset pulse to be issued.
As the amplitude of the transient increases (i.e., goes
farther below the reset threshold), the maximum allow-
able pulse width decreases. Typically, a V
that goes 100mV below the reset threshold and lasts for
30µs or less will not cause a reset pulse to be issued.
transient
CC
A 100nF bypass capacitor mounted close to the V
CC
pin provides additional transient immunity.
In t e rfa c in g t o µP s w it h Bid ire c t io n a l
Re s e t In p u t s
µPs with bidirectional reset pins, such as the Motorola
68HC11 series, can contend with the MAX792/MAX820
RESET output. If, for example, the MAX792/MAX820 RESET
output is asserted high and the µP wants to pull it low,
indeterminate logic levels may result. To avoid this,
connect a 4.7kΩ resistor between the MAX792/MAX820
RESET outp ut a nd the µP re s e t I/O, a s in Fig ure 12.
Buffer the MAX792/MAX820 RESET output to other sys-
tem components.
100
V
= 5V
80
60
CC
T = +25°C
A
40
Ne g a t ive -Go in g V
Tra n s ie n t s
CC
While issuing resets to the µP during power-up, power-
down, and brownout conditions, these supervisors are
20
0
relatively immune to short-duration negative-going V
CC
transients (glitches). It is usually undesirable to reset
10
100
1000
10,000
the µP when V experiences only small glitches.
CC
RESET COMPARATOR OVERDRIVE, (V - VCC) (mV)
TH
Figure 13 shows maximum transient duration vs. reset-
comparator overdrive, for which reset pulses are not
generated. The graph was produced using negative-
Figure 13. Maximum Transient Duration without Causing a
Reset Pulse vs. Reset-Comparator Overdrive
14 ______________________________________________________________________________________
Mic ro p ro c e s s o r a n d No n -Vo la t ile
Me m o ry S u p e rvis o ry Circ u it s
79/MAX820
P in Co n fig u ra t io n
_Ord e rin g In fo rm a t io n (c o n t in u e d )
PART**
TEMP. RANGE
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-55°C to +125°C
-0°C to +70°C
-0°C to +70°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-55°C to +125°C
PIN-PACKAGE
16 Plastic DIP
16 Narrow SO
16 CERDIP
TOP VIEW
MAX792_EPE
MAX792_ESE
MAX792_EJE
MAX792_MJE
MAX820_CPE
MAX820_CSE
MAX820_EPE
MAX820_ESE
MAX820_EJE
MAX820_MJE
RESET
RESET
WDPO
16
1
2
3
4
5
6
7
8
WDO
15
16 CERDIP
V
CC
CE IN
14
MAX792
MAX820
16 Plastic DIP
16 Narrow SO
16 Plastic DIP
16 Narrow SO
16 CERDIP
RESET IN/INT
CE OUT
GND
13
12
11
10
9
LLIN/REFOUT
OVO
WDI
OVI
LOW LINE
MR
SWT
16 CERDIP
* Dice are tested at T = +25°C.
A
DIP/SO
**These parts offer a choice of five different reset threshold volt-
ages. Select the letter corresponding to the desired nominal
reset threshold voltage and insert it into the blank to complete
the part number.
___________________Ch ip To p o g ra p h y
SUFFIX
RESET THRESHOLD (V)
L
M
T
4.62
4.37
3.06
2.91
2.61
RESET
WDO
CE IN
RESET
WDPO
S
R
CE OUT
GND
V
CC
RESET IN/
INT
0. 078"
(1. 981mm)
LLIN/
REF OUT
OVO
WDI
OVI SWTMR LOW LINE
0. 070"
(1. 778mm)
TRANSISTOR COUNT: 950
SUBSTRATE CONNECTED TO V
CC
______________________________________________________________________________________ 15
Mic ro p ro c e s s o r a n d No n -Vo la t ile
Me m o ry S u p e rvis o ry Circ u it s
________________________________________________________P a c k a g e In fo rm a t io n
79/MAX820
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
16 ____________________Ma x im In t e g ra t e d P ro d u c t s , 1 2 0 S a n Ga b rie l Drive , S u n n yva le , CA 9 4 0 8 6 4 0 8 -7 3 7 -7 6 0 0
© 1998 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
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