MAX77812_V01 [MAXIM]
20A User-Configurable Quad-Phase Buck Converter;型号: | MAX77812_V01 |
厂家: | MAXIM INTEGRATED PRODUCTS |
描述: | 20A User-Configurable Quad-Phase Buck Converter |
文件: | 总69页 (文件大小:2886K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
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MAX77812
20A User-Configurable
Quad-Phase Buck Converter
General Description
Benefits and Features
● 20A Maximum Output Current (5A per Phase)
The MAX77812 is a quad-phase high-efficiency step-
down (buck) converter capable of delivering up to 20A
of maximum current. Programmable startup/shutdown
sequence and user-selectable phase configurations make
the MAX77812 ideal for powering the latest generations
of processors. With high-efficiency and small solution
size, the MAX77812 is optimized for space constrained
single-cell battery powered applications.
● V Range: 2.5V to 5.5V
IN
● V
Range: 0.250V to 1.525V with 5mV Steps
OUT
±0.5% Initial Output Accuracy with Differential Sensing
● 5 User-Selectable Phase Configurations
● 91% Peak Efficiency (V = 3.8V, V
●
= 1.1V)
OUT
IN
● Auto (SKIP/PWM) and Forced PWM Modes
● Enhanced Load Transient Response
The MAX77812 uses an adaptive on-time PWM control
scheme and it has SKIP and low-power SKIP modes for
improved light-load efficiency. A programmable current
limit reduces the overall solution footprint by optimizing
inductors size. Differential sensing provides high output
voltage accuracy, while enhanced transient response
(ETR) allows fast output voltage adjustments to load tran-
sients. Programmable soft-start/stop and ramp-up/down
slew rate provides control over an inrush current as the
regulator transitions between operating states.
● Programmable Ramp-Up/Down Slew Rates
● Programmable Startup/Shutdown Sequence
● UVLO, Short-Circuit, and Thermal Protections
● 2 User-Programmable General-Purpose Inputs
2
● 3.4MHz High Speed I C and 30MHz SPI Interface
● 3.408mm x 3.368mm, 64-Bump WLP Package
2
A 3.4MHz high-speed I C or 30MHz SPI interface with
Applications
● CPU/GPU, FPGAs, and DSPs Power Supply
● AR/VR Headsets and Game Consoles
● Li-ion Battery Powered Equipment
dedicated logic inputs provide full configurability and
control for system power optimization.
The MAX77812 is available in 3.408mm x 3.368mm,
64-bump 0.4mm pitch wafer-level package (WLP).
● Space Constrained Portable Electronics
Ordering Information appears at end of data sheet.
Typical Application Circuit
V
V
SYS
2.5V to 5.5V
SYS
SYS
DGND
AGND
IN12
1Φ
+
1Φ
+
1Φ
+
1Φ
5A
5A
2.5V to 5.5V
0.25V to 1.525V
10A
LX1
SNS1P
SNS1N
PGND1
5A
5A
2Φ
+
1Φ
+
MAX77812
MULTI-PHASE
BUCK
CE
10A
V
VIO
VIO
5A
5A
LX2
SNS2P
SNS2N
PGND2
1Φ
2Φ
+
10A
10A
IRQB
SCL
SDA/MOSI
MISO
SCS
3Φ
+
V
SYS
IN34
2Φ
15A
5A
2.5V to 5.5V
I2C_SPI_SEL
EN
LPM
WDTRSTB_IN
GPI0
GPI1
PH_CFG0
PH_CFG1
PH_CFG2
0.25V to 1.525V
5A
LX3
SNS3P
SNS3N
PGND3
LX4
SNS4P
SNS4N
PGND4
1Φ
4Φ
20A
0.25V to 1.525V
5A
PHASE-CONFIGURABLE
QUAD-OUTPUT
V
SYS
2.5V to 5.5V
19-8541; Rev 11; 12/20
MAX77812
20A User-Configurable
Quad-Phase Buck Converter
Absolute Maximum Ratings
SYS, VIO to AGND...............................................-0.3V to +6.0V
DGND to AGND....................................................-0.3V to +0.3V
SCL, SDA/MOSI, MISO, SCS, IRQB, CE, EN, LPM, GPI0, GPI1,
PGND1/2/3/4 to AGND.........................................-0.3V to +0.3V
SNS1P, SNS2P, SNS3P, SNS4P to AGND..-0.3V to (V
+ 0.3V)
SNS1N, SNS2N, SNS3N, SNS4N to AGND........-0.3V to +0.3V
IN_
WDTRSTB_IN to DGND...................... -0.3V to (V
PH_CFG0, PH_CFG1, PH_CFG2,
+ 0.3V)
Continuous Power Dissipation at T = +70°C
VIO
A
(derate 26.17mW/°C above +70°C) ..........................2094mW
Junction Temperature..................................................... +150°C
Storage Temperature Range............................ -65°C to +150°C
Soldering Temperature (reflow).......................................+260°C
I2C_SPI_SEL to AGND ...................... -0.3V to (V
IN12, IN34 to PGNDx............................. -0.3V to (V
+ 0.3V)
+ 0.3V)
+ 0.3V)
SYS
SYS
LX1/2/3/4 to PGNDx.................................-0.3V to (V
IN_
LX1/2/3/4 to PGNDx (Pulsed <10ns Voltage)......-3.0V to +7.0V
Note 1: LXx node has internal clamp diodes to PGNDx and INx. Applications that give forward bias to these diodes should ensure
that the total power loss does not exceed the power dissipation limit of IC package.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Recommended Operating Conditions
TYPICAL
RANGE
PARAMETER
SYMBOL
CONDITION
UNITS
Input Voltage Range
V
2.5 to 5.5
V
IN
For continuous operation at 5A (per phase), the junction
temperature (T ) is limited to +115°C. If the junction
temperature is higher than +115°C, the expected
lifetime at 5A continuous operation is reduced
J
Output Current Range
I
0 to 5
A
OUT
Junction Temperature
Range
T
-40 to +125
°C
J
Note: These limits are not guaranteed.
(Note 2)
Package Thermal Characteristics
WLP
Junction-to-Ambient Thermal Resistance (θ ) .......33.2°C/W
JA
Note 2: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer
board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.
Electrical Characteristics
Top-Level Electrical Characteristics
(V
= V
= +3.8V, V
= +1.8V, T = T = -40°C to +125°C, typical values are at T = T = +25°C)
SYS
INx
VIO
A
J
A
J
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
GLOBAL INPUT SUPPLY
Operating Voltage Range
Shutdown Supply Current
V
2.5
5.5
5
V
SYS
I
CE = low, T = +25°C
A
2
µA
SHDN
CE = high and all outputs are off,
Standby Current
I
25
µA
STBY
T
= +25°C
A
Maxim Integrated
│ 2
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MAX77812
20A User-Configurable
Quad-Phase Buck Converter
Electrical Characteristics (continued)
Top-Level Electrical Characteristics (continued)
(V
= V
= +3.8V, V
= +1.8V, T = T = -40°C to +125°C, typical values are at T = T = +25°C)
SYS
INx
VIO
A
J
A
J
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
4-phase configuration
(no switching)
120
I
I
I
I
I
LP_SKIP1
LP_SKIP2
LP_SKIP3
LP_SKIP4
LP_SKIP5
3 + 1-phase configuration
(no switching)
190
190
265
340
150
250
250
350
460
180
310
310
440
580
No Load Supply Current in Low
Power Skip Mode
2 + 2-phase configuration
(no switching)
µA
2 + 1 + 1-phase configuration
(no switching)
1 + 1 + 1 + 1-phase configuration
(no switching)
510
4-phase configuration
(no switching)
I
I
I
I
I
SKIP1
SKIP2
SKIP3
SKIP4
SKIP5
3 + 1-phase configuration
(no switching)
No Load Supply Current in Skip
Mode
2 + 2-phase configuration
(no switching)
µA
2 + 1 + 1-phase configuration
(no switching)
1 + 1 + 1 + 1-phase configuration
(no switching)
690
4-phase configuration
(no switching, ETR enabled)
I
I
I
I
I
SKIP_ETR1
SKIP_ETR2
SKIP_ETR3
SKIP_ETR4
SKIP_ETR5
3 + 1-phase configuration
(no switching, ETR enabled)
No Load Supply Current in Skip
Mode with ETR
2 + 2-phase configuration
(no switching, ETR enabled)
µA
2 + 1 + 1-phase configuration
(no switching, ETR enabled)
1 + 1 + 1 + 1-phase configuration
(no switching, ETR enabled)
870
V
UNDERVOLTAGE LOCKOUT
SYS
V
V
V
rising
2.375
2.50
2.15
2.625
V
Undervoltage Lockout
UVLO_R
SYS
SYS
V
Threshold
V
falling (default)
UVLO_F
SYS
THERMAL PROTECTION
Thermal Protection Threshold
Thermal Interrupt at 120°C
Thermal Interrupt at 140°C
T
T rising, 15°C hysteresis
165
120
140
°C
°C
°C
SHDN
INT120
INT140
J
T
T rising, 15°C hysteresis
J
T
T rising, 15°C hysteresis
J
Maxim Integrated
│ 3
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MAX77812
20A User-Configurable
Quad-Phase Buck Converter
Electrical Characteristics (continued)
Top-Level Electrical Characteristics (continued)
(V
= V
= +3.8V, V
= +1.8V, T = T = -40°C to +125°C, typical values are at T = T = +25°C)
SYS
INx
VIO
A
J
A
J
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
LOGIC AND CONTROL INPUTS
PH_CFG0, PH_CFG1, PH_CFG2,
I2C_SPI_SEL,
0.4
V
≤ 5.5V, T = +25°C
A
Input Low Level
V
SYS
V
IL
CE, EN, LPM, GPI0, GPI1,
0.3 x
WDTRSTB_IN, T = +25°C
A
V
VIO
PH_CFG0, PH_CFG1, PH_CFG2,
I2C_SPI_SEL,
1.2
V
≤ 5.5V, T = +25°C
A
Input High Level
V
SYS
V
IH
CE, EN, LPM, GPI0, GPI1,
0.7 x
WDTRSTB_IN, T = +25°C
A
V
VIO
PH_CFG0, PH_CFG1, PH_CFG2,
I2C_SPI_SEL, V
CE = 1.8V, T = +25°C
A
= 5.5V,
-1
+0.001
+0.001
0.1
+1
+1
SYS
CE, EN, LPM, GPI0, GPI1,
CE = 1.8V, T = +25°C
A
-1
Logic Input Leakage Current
I
µA
LK
PH_CFG0, PH_CFG1, PH_CFG2,
I2C_SPI_SEL, V
= 5.5V,
SYS
CE = 1.8V, T = +85°C (Note 4)
A
CE, EN, LPM, GPI0, GPI1,
0.1
CE = 1.8V, T = +85°C (Note 4)
A
IRQ Output Low Voltage
IRQ Output High Leakage
V
I
= 1mA
SINK
0.4
+1
V
OL
T
T
= +25°C
-1
0.001
0.1
A
A
I
µA
LK_OH
= +85°C (Note 4)
INTERNAL PULL-UP/DOWN RESISTANCE
WDTRSTB_IN Pullup Resistance
R
Pullup resistance to VIO
400
400
800
800
1600
1600
kΩ
kΩ
PU
PD
GPI0, GPI1, EN, LPM Pulldown
Resistance
R
Pulldown resistance to DGND
Maxim Integrated
│ 4
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MAX77812
20A User-Configurable
Quad-Phase Buck Converter
Electrical Characteristics (continued)
Quad-Phase Buck Electrical Characteristics
(V
= V
= +3.8V, V
= 0.85V, T = T = -40°C to +125°C, typical values are at T = T = +25°C
SYS
INx
OUTx
A
J
A
J
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
POWER SUPPLY
Input Voltage Range
V
2.5
V
V
V
INx
SYS
Programmable with 8-bit
resolution, 5mV/LSB
Output Voltage Range
V
0.25
1.525
OUT
DC OUTPUT VOLTAGE ACCURACY
Force PWM mode,
differential remote sensing,
V
≥ 0.65V, I
= 0mA,
-0.5
+0.5
%
OUT
OUT
C
= 64µF,
OUT(EFF)
T
= +25°C
A
Output Voltage Accuracy
V
ACC_INIT
Force PWM mode,
differential remote sensing,
0.45V ≤ V < 0.6V, I
=
OUT
-6
+6
mV
V/A
V/V
OUT
OUT(EFF)
0mA, C
= +25°C
= 64µF,
T
A
Forced PWM mode,
differential remote sensing,
= 0A to 5A,
Load Regulation
-0.001
I
OUT
C
= 64µF (Note 5)
OUT(EFF)
Forced PWM mode,
differential remote sensing,
Line Regulation
V
= 2.5V to 5.5V, V
-0.005
+0.005
INx
OUT
= Default, I
= 0mA,
OUT
C
= 64µF
OUT(EFF)
AC OUTPUT VOLTAGE ACCURACY
V
= 3.4V to 2.9V to 3.4V,
INx
t
= t
= 10µs, V
= 2A,
RISE
FALL
OUT
= 1.1V, I
OUT
Line Transient Response
V
L = 220nH (DCR = 9mΩ),
= 16µF
15
mV
DROOP
C
OUT(EFF)
(ESR = 5mΩ, ESL = 300pH)
per phase (Note 5)
SKIP/PWM mode, differential
remote sensing, V
=
OUT
1.1V, I
= 0.1A
OUT
to 4A (100A/µs), L = 220nH
Load Transient Response
V
45
mV
DROOP
(DCR = 9mΩ), C
=
OUT(EFF)
16µF (ESR = 5mΩ,
ESL = 300pH) per Phase
(Note 5)
Maxim Integrated
│ 5
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MAX77812
20A User-Configurable
Quad-Phase Buck Converter
Electrical Characteristics (continued)
Quad-Phase Buck Electrical Characteristics (continued)
(V
= V
= +3.8V, V
= 0.85V, T = T = -40°C to +125°C, typical values are at T = T = +25°C
SYS
INx
OUTx
A
J
A
J
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
RAMP RATE
B_SS_SR[2:0] = 000b
(Note 6)
1.25
2.5
5
B_SS_SR[2:0] = 001b
(Note 6)
B_SS_SR[2:0] = 010b
(Note 6)
B_SS_SR[2:0] = 011b
(Note 6)
Soft-Start Slew Rate
10
20
40
60
1.25
2.5
5
mV/µs
B_SS_SR[2:0] = 100b
(default) (Note 6)
B_SS_SR[2:0] = 101b
(Note 6)
B_SS_SR[2:0] = 110b or
111b (Note 6)
B_SD_SR[2:0] = 000b
(Note 6)
B_SD_SR[2:0] = 001b
(Note 6)
B_SD_SR[2:0] = 010b
(default) (Note 6)
B_SD_SR[2:0] = 011b
(Note 6)
Shutdown Slew Rate
10
20
40
60
mV/µs
B_SD_SR[2:0] = 100b
(Note 6)
B_SD_SR[2:0] = 101b
(Note 6)
B_SD_SR[2:0] = 110b or
111b (Note 6)
Maxim Integrated
│ 6
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MAX77812
20A User-Configurable
Quad-Phase Buck Converter
Electrical Characteristics (continued)
Quad-Phase Buck Electrical Characteristics (continued)
(V
= V
= +3.8V, V
= 0.85V, T = T = -40°C to +125°C, typical values are at T = T = +25°C
SYS
INx
OUTx
A
J
A
J
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
B_RU_SR[2:0] = 000b
(Note 6)
1.25
B_RU_SR[2:0] = 001b
(Note 6)
2.5
5
B_RU_SR[2:0] = 010b
(Note 6)
B_RU_SR[2:0] = 011b
(Note 6)
DVS Ramp-Up Slew Rate
10
20
40
60
1.25
2.5
5
mV/µs
B_RU_SR[2:0] = 100b
(default) (Note 6)
B_RU_SR[2:0] = 101b
(Note 6)
B_RU_SR[2:0] = 110b or
111b (Note 6)
B_RD_SR[2:0] = 000b
(Note 6)
B_RD_SR[2:0] = 001b
(Note 6)
B_RD_SR[2:0] = 010b
(default) (Note 6)
B_RD_SR[2:0] = 011b
(Note 6)
DVS Ramp-Down Slew Rate
10
20
40
60
mV/µs
B_RD_SR[2:0] = 100b
(Note 6)
B_RD_SR[2:0] = 101b
(Note 6)
B_RD_SR[2:0] = 110b or
111b (Note 6)
From EN signal to LXB
switching with bias on
(Note 6)
t
t
30
85
ON_DLY1
ON_DLY2
Turn-On Delay Time
µs
From EN signal to LXB
switching with bias off
(Note 5)
Maxim Integrated
│ 7
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MAX77812
20A User-Configurable
Quad-Phase Buck Converter
Electrical Characteristics (continued)
Quad-Phase Buck Electrical Characteristics (continued)
(V
= V
= +3.8V, V
= 0.85V, T = T = -40°C to +125°C, typical values are at T = T = +25°C
SYS
INx
OUTx
A
J
A
J
PARAMETER
POWER STAGE
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
RMS current per phase,
I
4000
5000
OUT(MAX)
OUT(MAX)
V
< 3.2V (Note 5)
IN
Maximum Output Current
mA
RMS current per phase,
I
3.2V ≤ V ≤ 5.5V (Note 5)
IN
I
I
I
I
I
Mx_ILIM[2:0] = 000b
Mx_ILIM[2:0] = 001b
Mx_ILIM[2:0] = 010b
Mx_ILIM[2:0] = 011b
Mx_ILIM[2:0] = 100b
3000
3600
4200
4800
5400
PLIM
PLIM
PLIM
PLIM
PLIM
PMOS Peak Current Limit
mA
Mx_ILIM[2:0] = 101b
(default)
I
4800
5200
6000
7200
9200
PLIM
I
I
I
I
I
I
I
Mx_ILIM[2:0] = 110b
Mx_ILIM[2:0] = 111b
Mx_ILIM[2:0] = 000b
Mx_ILIM[2:0] = 001b
Mx_ILIM[2:0] = 010b
Mx_ILIM[2:0] = 011b
Mx_ILIM[2:0] = 100b
6600
7200
2000
2400
2800
3200
3600
PLIM
PLIM
VLIM
VLIM
VLIM
VLIM
VLIM
NMOS Valley Current Limit
mA
Mx_ILIM[2:0] = 101b
(default)
I
3200
4000
4800
VLIM
I
I
Mx_ILIM[2:0] = 110b
Mx_ILIM[2:0] = 111b
Per phase
4400
4800
-1500
VLIM
VLIM
NLIM
3800
5800
NMOS Negative Current Limit
Switching Frequency
I
-2000
-1000
mA
V
= default, Forced
OUT
f
1.6
2.0
32
15
2.8
70
29
MHz
SW
PWM mode
High-Side PMOS
On-Resistance
R
R
INx to LXx, I
= -150mA
LXx
mΩ
mΩ
DSON(PMOS)
Low-Side NMOS
On-Resistance
LXx to PGNDx, I
150mA
=
LXx
DSON(NMOS)
Resistance from LXx to
PGNDx, per phase, output
disabled
LX Active Discharge Resistance
R
100
200
Ω
AD_LX
Maxim Integrated
│ 8
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MAX77812
20A User-Configurable
Quad-Phase Buck Converter
Electrical Characteristics (continued)
Quad-Phase Buck Electrical Characteristics (continued)
(V
= V
= +3.8V, V
= 0.85V, T = T = -40°C to +125°C, typical values are at T = T = +25°C
SYS
INx
OUTx
A
J
A
J
MIN
-1
PARAMETER
SYMBOL
CONDITIONS
TYP
MAX
UNITS
V
= 0V or 5.5V,
= +25°C
LXx
I
0.1
+1
LKG_LX
LKG_LX
T
A
LX Leakage Current
µA
V
= 0V or 5.5V,
= +85°C (Note 4)
LXx
I
1
T
A
Nominal Inductance
L
(Note 5)
220
16
nH
µF
NOM
Minimum Effective Output
Capacitance
0µA < I
< 5000mA per
OUT
C
OUT(EFF_MIN)
phase (Note 5)
EFFICIENCY AND OUTPUT RIPPLE
L = 220nH (DCR = 9mΩ),
C
= 16µF
OUT(EFF)
Peak Efficiency
η
90
75
%
%
PK
(ESR = 5mΩ, ESL = 300pH)
per Phase (Note 5)
I
= 5A, L = 220nH
OUT
(DCR = 9mΩ), C
=
OUT(EFF)
Heavy Load Efficiency
η
16µF (ESR = 5mΩ,
ESL = 300pH) per Phase
(Note 5)
HEAVY
Skip mode, I
= 0.1A,
OUT
L = 220nH (DCR = 9mΩ),
= 16µF (ESR
Skip Mode Output Ripple
V
C
10
mV
mV
RIP_SKIP
OUT(EFF)
P-P
P-P
= 5mΩ, ESL = 300pH) per
phase (Note 7)
Forced PWM mode,
differential remote sensing,
I
= 0.1A, L = 220nH
OUT
(DCR = 9mΩ), C
FPWM Mode Output Ripple
V
5
RIP_FPWM
OUT(EFF)
= 16µF (ESR = 5mΩ, ESL =
300pH) per phase (Note 7)
POWER OK COMPARATOR
Rising threshold
Falling threshold
90
85
Output POK Trip Level
%
90
Maxim Integrated
│ 9
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MAX77812
20A User-Configurable
Quad-Phase Buck Converter
Electrical Characteristics (continued)
2
I C Electrical Characteristics
(V
= V
= +3.8V, V
= +1.8V, T = T = -40°C to +125°C, typical values are at T = T = +25°C)
SYS
INx
VIO A J A J
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
POWER SUPPLY
VIO Supply Voltage Range
VIO Dynamic Supply Current
V
1.65
1.8
50
5
V
V
VIO
SYS
I
f
= f
= 1MHz
µA
µA
VIO
SCL
SDA
V
Dynamic Supply Current
I
SYS
SYS
SDA AND SCL I/O STAGES
0.7 x
SCL, SDA Input High Voltage
V
V
V
V
V
IH
V
VIO
0.3 x
SCL, SDA Input Low Voltage
SCL, SDA Input Hysteresis
V
IL
V
VIO
0.05 x
V
HYS
V
VIO
SCL, SDA Input Hysteresis in HS
Mode
0.1 x
V
HYS_HS
V
VIO
SDA Output Low Voltage
V
I
= 5mA
0.4
+1
V
OL
SINK
SCL, SDA Input Capacitance
C
10
+0.001
0.1
pF
I
T
T
= +25°C
-1
A
SCL, SDA Input Leakage Current
I
µA
LK
= +85°C (Note 4)
A
2
I C-COMPATIBLE INTERFACE TIMING (STANDARD, FAST AND FAST MODE PLUS) (Note 5)
Clock Frequency
f
0
1000
kHz
µs
SCL
Bus Free Time between STOP
and START Condition
t
0.5
BUSF
Hold Time (REPEATED) START
Condition
t
t
0.26
µs
HD_START
SCL Low Period
SCL High Period
t
0.5
µs
µs
LOW
t
0.26
HIGH
Setup Time REPEATED START
Condition
0.26
µs
SU_START
Data Hold Time
t
Transmit mode
0
450
ns
ns
ns
HD_DATA
Data Setup Time
t
50
SU_DATA
SCL, SDA Receiving Rise Time
t
120
120
R_REV
20 x
SCL, SDA Receiving Fall Time
t
ns
F_REV
V
/5.5
VIO
Maxim Integrated
│ 10
www.maximintegrated.com
MAX77812
20A User-Configurable
Quad-Phase Buck Converter
Electrical Characteristics (continued)
2
I C Electrical Characteristics (continued)
(V
= V
= +3.8V, V
= +1.8V, T = T = -40°C to +125°C, typical values are at T = T = +25°C)
SYS
INx
VIO
A
J
A
J
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
20 x
SCL, SDA Transmitting Fall Time
t
120
ns
F_TRA
V
/5.5
VIO
Setup Time for STOP Condition
Data Valid Time
t
0.26
µs
ns
ns
pF
SU_STOP
t
450
450
550
VD_DATA
Data Valid Acknowledge Time
Bus Capacitance
t
VD_ACK
C
B
Pulse Width of Suppressed
Spikes
t
50
ns
SP
2
I C-COMPATIBLE INTERFACE TIMING (HIGH-SPEED MODE, C = 100pF) (Note 5)
B
Clock Frequency
f
3.4
MHz
ns
SCL
Hold Time (REPEATED) START
Condition
t
t
160
HD_START
SCL LOW Period
SCL HIGH Period
t
160
60
ns
ns
LOW
t
HIGH
Setup Time REPEATED START
Condition
160
ns
SU_START
Data Hold Time
Data Setup Time
SCL Rise Time
t
0
70
ns
ns
ns
HD_DATA
t
10
10
SU_DATA
t
T
T
= +25°C
= +25°C
40
40
R_SCL
A
SCL Rise Time after REPEATED
START Condition and after
Acknowledge Bit
t
10
ns
R_SCL1
A
SCL Fall Time
t
T
T
T
= +25°C
= +25°C
= +25°C
10
10
40
40
40
ns
ns
ns
ns
pF
F_SCL
A
A
A
SDA Rise Time
t
R_SDA
SDA Fall Time
t
F_SDA
Setup Time for STOP Condition
Bus Capacitance
t
160
0
SU_STOP
C
100
10
B
Pulse Width of Suppressed
Spikes
t
ns
SP
Maxim Integrated
│ 11
www.maximintegrated.com
MAX77812
20A User-Configurable
Quad-Phase Buck Converter
Electrical Characteristics (continued)
2
I C Electrical Characteristics (continued)
(V
= V
= +3.8V, V
= +1.8V, T = T = -40°C to +125°C, typical values are at T = T = +25°C)
SYS
INx
VIO A J A J
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
2
I C-COMPATIBLE INTERFACE TIMING (HIGH-SPEED MODE, C = 400pF) (Note 5)
B
Clock Frequency
f
1.7
MHz
ns
SCL
Hold Time (REPEATED) START
Condition
t
t
160
HD_START
SCL Low Period
SCL High Period
t
320
120
ns
ns
LOW
t
HIGH
Setup Time REPEATED START
Condition
160
ns
SU_START
DATA Hold Time
DATA Setup Time
SCL Rise Time
t
0
150
ns
ns
ns
HD_DATA
t
10
20
SU_DATA
t
T
T
= +25°C
= +25°C
80
80
R_SCL
A
SCL Rise Time after REPEATED
START Condition and after
Acknowledge Bit
t
20
ns
R_SCL1
A
SCL Fall Time
t
T
T
T
= +25°C
= +25°C
= +25°C
20
20
80
80
80
ns
ns
ns
ns
pF
F_SCL
A
A
A
SDA Rise Time
t
R_SDA
SDA Fall Time
t
F_SDA
Setup Time for STOP Condition
Bus Capacitance
t
160
0
SU_STOP
C
400
10
B
Pulse Width of Suppressed
Spikes
t
ns
SP
Maxim Integrated
│ 12
www.maximintegrated.com
MAX77812
20A User-Configurable
Quad-Phase Buck Converter
Electrical Characteristics (continued)
SPI Electrical Characteristics
(V
= V
= +3.8V, V
= +1.8V, T = T = -40°C to +125°C, typical values are at T = T = +25°C)
SYS
INx
VIO
A
J
A
J
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
POWER SUPPLY AND I/O STAGES
VIO Supply Voltage Range
V
1.65
-1
1.8
+0.001
0.1
V
V
VIO
SYS
T
T
= +25°C
+1
Input Leakage Current
(SCS, SCL, MOSI)
I
I
,
IH_SPI
A
µA
= +85°C (Note 4)
IL_SPI
A
Input Capacitance
(SCS, SCL, MOSI)
C
10
pF
V
I
Input LOW Voltage
(SCS, SCL, MOSI)
0.3 x
V
IL
V
VIO
Input HIGH Voltage
(SCS, SCL, MOSI)
0.7 x
V
V
IH
V
VIO
Input Hysteresis
(SCS, SCL, MOSI)
0.1 x
V
VIO
V
HYS
MISO Output Low Voltage
V
I
I
= 1mA
0.2
+1
V
V
OL
OL
V
-
VIO
0.2
MISO Output High Voltage
V
= 1mA
OH
OH
High-impedance state,
= +25°C
-1
+0.001
0.1
T
A
MISO Leakage Current
I
µA
LK_HIZ
High-impedance state,
= +85°C (Note 4)
T
A
SPI INTERFACE TIMING (Note 5)
SPI Operating Frequency
f
26
30
MHz
ns
SCL
MOSI Input Valid to SCL Rising
Edge
t
10
10
SU_MOSI
MOSI Input Valid from SCL Rising
Edge
t
ns
ns
HD_MOSI
MISO Valid from SCL Rising
Edge
t
C = 50pF
9
D_MISO
L
MISO Rising/Falling Time
SCS Setup Time
t , t
C = 20pF
10
ns
ns
ns
ns
R
F
L
t
20
20
50
SU_SCS
t
HD_SCS
SCS Hold Time
Minimum SCS High Pulse Width
t
SCS_H(MIN)
Note 3: Limits are 100% production tested at T = +25°C. Limits over the operating temperature range are guaranteed through
A
correlation using statistical quality control methods.
Note 4: Guaranteed by ATE characterization. Not directly tested in production.
Note 5: Guaranteed by design. Not production tested.
Note 6: Guaranteed by design. Production tested through scan.
Note 7: Internal design target.
Maxim Integrated
│ 13
www.maximintegrated.com
MAX77812
20A User-Configurable
Quad-Phase Buck Converter
Typical Operating Characteristics
(V
= 3.8V, V
= 0.85V, I
= 0A, CE = high, 4-Phase (1 Output), FPWM = 0, LPM = 0, ETR = 0, L = 220nH, C
= (22µF +
SYS
OUT
OUT
OUT
0.1µF + 2 × 4.3µF), T = +25°C, unless otherwise noted.)
A
SHUTDOWN SUPPLY CURRENT
vs. INPUT VOLTAGE
STANDBY SUPPLY CURRENT
vs. INPUT VOLTAGE
OPERATING SUPPLY CURRENT
vs. INPUT VOLTAGE
toc01
toc02
toc03a
6
5
4
3
2
1
0
50
40
30
20
10
0
800
700
600
500
400
300
200
100
0
4-PHASE (1 OUTPUT)
LPM = 0
ETR = 0
CE = GND
ALL OUTPUTS OFF
-40°C
+85°C
+85°C
+25°C
+25°C
+25°C
-40°C
+85°C
-40°C
3
0
1
2
4
5
0
1
2
3
4
5
2.5
3
3.5
4
4.5
5
5.5
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
OPERATING SUPPLY CURRENT
vs. INPUT VOLTAGE
OPERATING SUPPLY CURRENT
vs. INPUT VOLTAGE
EFFICIENCY vs. OUTPUT CURRENT
(4-PHASE)
toc03b
toc03c
toc04a
800
700
600
500
400
300
200
100
0
800
700
600
500
400
300
200
100
90
80
70
60
50
40
30
20
10
0
4-PHASE (1 OUTPUT)
LPM = 1
VOUT = 0.6V
1-PHASE (4 OUTPUTS ON)
LPM = 0
ETR = 1
-40°C
+85°C
FPWM = 0
FPWM = 1
+25°C
VIN = 3.4V
+25°C
-40°C
VIN = 3.8V
VIN = 4.8V
+85°C
0.001
0.01
0.1
1
10
2.5
3
3.5
4
4.5
5
5.5
2.5
3
3.5
4
4.5
5
5.5
OUTPUT CURRENT (A)
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
EFFICIENCY vs. OUTPUT CURRENT
(3-PHASE)
toc04d
EFFICIENCY vs. OUTPUT CURRENT
(4-PHASE)
EFFICIENCY vs. OUTPUT CURRENT
(4-PHASE)
toc04b
toc04c
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
100
VOUT = 0.85V
VOUT = 1.1V
VOUT = 0.6V
90
80
70
60
50
40
30
20
10
0
FPWM = 0
FPWM = 1
FPWM = 0
FPWM = 0
VIN = 3V
FPWM = 1
VIN = 3.4V
VIN = 3.4V
VIN = 3.8V
VIN = 5V
VIN = 3.8V
VIN = 4.8V
VIN = 3.8V
VIN = 4.8V
VIN = 3.3V
FPWM = 1
0.001
0.01
0.1
1
10
0.001
0.01
0.1
1
10
0.001
0.01
0.1
1
10
OUTPUT CURRENT (A)
OUTPUT CURRENT (A)
OUTPUT CURRENT (A)
Maxim Integrated
│ 14
www.maximintegrated.com
MAX77812
20A User-Configurable
Quad-Phase Buck Converter
Typical Operating Characteristics (continued)
(V
= 3.8V, V
= 0.85V, I
= 0A, CE = high, 4-Phase (1 Output), FPWM = 0, LPM = 0, ETR = 0, L = 220nH, C
= (22µF +
SYS
OUT
OUT
OUT
0.1µF + 2 × 4.3µF), T = +25°C, unless otherwise noted.)
A
EFFICIENCY vs. OUTPUT CURRENT
(3-PHASE)
EFFICIENCY vs. OUTPUT CURRENT
EFFICIENCY vs. OUTPUT CURRENT
(2-PHASE)
toc04g
(3-PHASE)
toc04e
toc04f
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
VOUT = 0.85V
VOUT = 1.1V
VOUT = 0.6V
FPWM = 0
FPWM = 0
FPWM = 0
VIN = 3V
VIN = 3V
VIN = 3V
VIN = 3.8V
VIN = 5V
VIN = 3.8V
VIN = 3.8V
VIN = 5V
VIN = 3.3V
FPWM = 1
VIN = 3.3V
FPWM = 1
VIN = 3.3V
FPWM = 1
VIN = 5V
0.001
0.01
0.1
1
10
0.001
0.01
0.1
1
10
0.001
0.01
0.1
1
10
OUTPUT CURRENT (A)
OUTPUT CURRENT (A)
OUTPUT CURRENT (A)
EFFICIENCY vs. OUTPUT CURRENT
(2-PHASE)
EFFICIENCY vs. OUTPUT CURRENT
(2-PHASE)
EFFICIENCY vs. OUTPUT CURRENT
(1-PHASE)
toc04j
toc04h
toc04i
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
VOUT = 0.85V
VOUT = 1.1V
VOUT = 0.6V
FPWM = 0
FPWM = 0
FPWM = 0
VIN = 3V
VIN = 3V
VIN = 3V
VIN = 3.8V
VIN = 3.8V
VIN = 5V
VIN = 3.8V
VIN = 5V
VIN = 3.3V
FPWM = 1
VIN = 3.3V
FPWM = 1
VIN = 3.3V
FPWM = 1
VIN = 5V
0.001
0.01
0.1
1
10
0.001
0.01
0.1
1
10
0.001
0.01
0.1
1
OUTPUT CURRENT (A)
OUTPUT CURRENT (A)
OUTPUT CURRENT (A)
EFFICIENCY vs. OUTPUT CURRENT
(1-PHASE)
EFFICIENCY vs. OUTPUT CURRENT
(1-PHASE)
EFFICIENCY vs. OUTPUT CURRENT
(3-PHASE)
toc04m
toc04k
toc04l
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
VOUT = 0.85V
VOUT = 1.1V
VIN = 3.3V
FPWM = 1
FPWM = 0
VOUT = 1.5V
VOU T = 1V
FPWM = 0
VIN = 3V
VIN = 3V
VOU T = 0.75V
VOUT = 0.5V
VIN = 3.8V
VIN = 3.8V
VIN = 3.3V
FPWM = 1
VIN = 3.3V
FPWM = 1
VIN = 5V
VIN = 5V
0.001
0.01
0.1
1
0.001
0.01
0.1
1
0.01
0.1
1
10
OUTPUT CURRENT (A)
OUTPUT CURRENT (A)
OUTPUT CURRENT (A)
Maxim Integrated
│ 15
www.maximintegrated.com
MAX77812
20A User-Configurable
Quad-Phase Buck Converter
Typical Operating Characteristics (continued)
(V
= 3.8V, V
= 0.85V, I
= 0A, CE = high, 4-Phase (1 Output), FPWM = 0, LPM = 0, ETR = 0, L = 220nH, C
= (22µF +
SYS
OUT
OUT
OUT
0.1µF + 2 × 4.3µF), T = +25°C, unless otherwise noted.)
A
EFFICIENCY vs. OUTPUT CURRENT
(2-PHASE)
EFFICIENCY vs. OUTPUT CURRENT
(1-PHASE)
OUTPUT VOLTAGE vs. OUTPUT CURRENT
(4-PHASE)
toc04n
toc04o
toc05a
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
0.30
0.20
VIN = 3.3V
FPWM = 1
VIN = 3.3V
FPWM = 1
VOUT = 0.6V
FPWM = 0
0.10
VIN = 3.8V
VOUT = 1.5V
VOUT = 1.5V
0.00
VOU T = 1V
VOU T = 1V
VOU T = 0.75V
VOUT = 0.5V
-0.10
-0.20
-0.30
-0.40
-0.50
-0.60
-0.70
-0.80
VOU T = 0.75V
FPWM = 1
VIN = 3.4V
VOUT = 0.5V
VIN = 4.8V
0.001
0.01
0.1
1
10
0.01
0.1
1
10
0.01
0.1
1
OUTPUT CURRENT (A)
OUTPUT CURRENT (A)
OUTPUT CURRENT (A)
OUTPUT VOLTAGE vs. INPUT VOLTAGE
(4-PHASE)
toc06a
OUTPUT VOLTAGE vs. OUTPUT CURRENT
OUTPUT VOLTAGE vs. OUTPUT CURRENT
(4-PHASE)
(4-PHASE)
toc05b
toc05c
0.30
0.20
0.30
0.20
0.60
0.40
VOUT = 0.6V
FPWM = 0
VOUT = 0.85V
FPWM = 0
VOUT = 1.1V
FPWM = 0
2mA
10mA
1A
0.10
0.20
VIN = 3.4V
VIN = 3.4V
0.10
0.00
0.00
-0.10
-0.20
-0.30
-0.40
-0.50
0.00
-0.20
-0.40
-0.60
-0.80
-1.00
FPWM = 1
FPWM = 1
VIN = 3.8V
10A
20A
VIN = 3.8V
VIN = 4.8V
-0.10
-0.20
-0.30
VIN = 4.8V
0.001
0.01
0.1
1
10
2.5
3
3.5
4
4.5
5
5.5
0.001
0.01
0.1
1
10
OUTPUT CURRENT (A)
INPUT VOLTAGE (V)
OUTPUT CURRENT (A)
OUTPUT VOLTAGE vs. INPUT VOLTAGE
(4-PHASE)
OUTPUT VOLTAGE vs. INPUT VOLTAGE
(4-PHASE)
OUTPUT VOLTAGE vs. INPUT VOLTAGE
(4-PHASE)
toc06d
toc06b
toc06c
0.60
0.40
0.20
0.10
0.60
0.40
VOUT = 0.6V
FPWM = 1
VOUT = 1.1V
FPWM = 0
VOUT = 0.85V
FPWM = 0
2mA
10mA
1A
2mA
10mA
0.00
0.20
0.20
2mA
10mA
-0.10
-0.20
-0.30
-0.40
-0.50
-0.60
0.00
0.00
1A
1A
-0.20
-0.40
-0.60
-0.80
-1.00
-0.20
-0.40
-0.60
-0.80
10A
10A
20A
10A
20A
20A
2.5
3
3.5
4
4.5
5
5.5
2.5
3
3.5
4
4.5
5
5.5
2.5
3
3.5
4
4.5
5
5.5
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
Maxim Integrated
│ 16
www.maximintegrated.com
MAX77812
20A User-Configurable
Quad-Phase Buck Converter
Typical Operating Characteristics (continued)
(V
= 3.8V, V
= 0.85V, I
= 0A, CE = high, 4-Phase (1 Output), FPWM = 0, LPM = 0, ETR = 0, L = 220nH, C
= (22µF +
SYS
OUT
OUT
OUT
0.1µF + 2 × 4.3µF), T = +25°C, unless otherwise noted.)
A
OUTPUT VOLTAGE vs. INPUT VOLTAGE
(4-PHASE)
OUTPUT VOLTAGE vs. INPUT VOLTAGE
VOUT vs. CODE
(4-PHASE)
toc06e
toc06f
toc07
0.60
0.40
0.20
0.10
1.8
1.6
1.4
1.2
1
FPWM = 0
VOUT = 0.85V
FPWM = 1
VOUT = 1.1V
FPWM = 1
0.00
0.20
2mA
10mA
-0.10
-0.20
-0.30
-0.40
-0.50
-0.60
2mA
10mA
0.00
1A
0.8
0.6
0.4
0.2
0
-0.20
-0.40
-0.60
-0.80
1A
10A
20A
10A
20A
2.5
3
3.5
4
4.5
5
5.5
2.5
3
3.5
4
4.5
5
5.5
0
25 50 75 100 125 150 175 200 225 250
M1_VOUT CODE
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
OUTPUT VOLTAGE ACCURACY
(1-PHASE)
STARTUP INTO LOAD
STARTUP DELAY
toc07a
toc09a
toc08
2.0
1.5
1.0
0.5
0.0
-0.5
-1.0
IOUT = 1mA
FPWM = 1
DEBOUNCE TIME = 64µs
500mV/div
VOUT
VIN
200mV/div
(AC-
COUPLED)
VOUT
200mV/div
TA = -40°C
TA = +25°C
IOUT
2A/div
LX3
LX1
10V/div
10V/div
TA = +85°C
IIN
0.2A/div
2V/div
2V/div
EN
EN
50µs/div
100µs/div
0.250
0.500
0.750
1.000
1.250
1.500
OUTPUT VOLTAGE (V)
STARTUP INTO LOAD
STARTUP INTO LOAD
STARTUP INTO LOAD
toc09b
toc10a
toc10b
IOUT = 1A
IOUT = 10mA
IOUT = 5A
500mV/div
500mV/div
500mV/div
VOUT
VIN
VOUT
VIN
VOUT
500mV/div
(AC-
COUPLED)
200mV/div
(AC-
COUPLED)
500mV/div
(AC-
COUPLED)
VIN
IOUT
2A/div
0.2A/div
2V/div
IOUT
8A/div
2A/div
IOUT
8A/div
IIN
IIN
IIN
2A/div
2V/div
2V/div
EN
EN
EN
100µs/div
100µs/div
100µs/div
Maxim Integrated
│ 17
www.maximintegrated.com
MAX77812
20A User-Configurable
Quad-Phase Buck Converter
Typical Operating Characteristics (continued)
(V
= 3.8V, V
= 0.85V, I
= 0A, CE = high, 4-Phase (1 Output), FPWM = 0, LPM = 0, ETR = 0, L = 220nH, C
= (22µF +
SYS
OUT
OUT
OUT
0.1µF + 2 × 4.3µF), T = +25°C, unless otherwise noted.)
A
STARTUP INTO A SHORT
SHUTDOWN DELAY
STARTUP INTO LOAD
toc11
toc12
toc10c
IOUT = 16A
SS = 2.5mV/µs
500mV/div
VOUT
VOUT
500mV/div
500mV/div
(AC-
VOUT
200mV/div
VIN
COUPLED)
32A/div
2A/div
8A/div
5A/div
IOUT
IOUT
IIN
LX3
LX1
10V/div
10V/div
IIN
2V/div
2V/div
EN
EN
2V/div
EN
200µs/div
1ms/div
200µs/div
SOFT-STOP
SOFT-STOP
SOFT-STOP
toc13b
toc13c
toc13a
IOUT = 10mA
SOFT-STOP = ON
ACTIVE DISCHARGE = ON
IOUT = 10mA
SOFT-STOP = OFF
ACTIVE DISCHARGE = OFF
IOUT = 10mA
SOFT-STOP = ON
ACTIVE DISCHARGE = OFF
VOUT
200mV/div
VOUT
VOUT
200mV/div
200mV/div
LX3
LX1
LX3
LX1
LX3
LX1
10V/div
10V/div
10V/div
10V/div
10V/div
10V/div
2V/div
2V/div
2V/div
EN
EN
EN
50µs/div
1s/div
50µs/div
SOFT-STOP
OUTPUT RIPPLE
OUTPUT RIPPLE
toc14b
toc13d
toc14a
IOUT = 1mA
FPWM = 0
IOUT = 10mA
SOFT-STOP = OFF
IOUT = 10mA
FPWM = 0
ACTIVE DISCHARGE = ON
VOUT
VOUT
20mV/div
20mV/div
VOUT
200mV/div
LX3
LX1
10V/div
10V/div
5V/div
5V/div
5V/div
5V/div
LX3
LX1
LX3
LX1
EN
2V/div
1ms/div
100µs/div
50µs/div
Maxim Integrated
│ 18
www.maximintegrated.com
MAX77812
20A User-Configurable
Quad-Phase Buck Converter
Typical Operating Characteristics (continued)
(V
= 3.8V, V
= 0.85V, I
= 0A, CE = high, 4-Phase (1 Output), FPWM = 0, LPM = 0, ETR = 0, L = 220nH, C
= (22µF +
SYS
OUT
OUT
OUT
0.1µF + 2 × 4.3µF), T = +25°C, unless otherwise noted.)
A
OUTPUT RIPPLE
OUTPUT RIPPLE
OUTPUT RIPPLE
toc14c
toc14d
toc14e
IOUT = 1A
FPWM = 0
IOUT = 10A
FPWM = 0 OR 1
IOUT = 5A
FPWM = 0 OR 1
VOUT
10mV/div
VOUT
VOUT
20mV/div
10mV/div
5V/div
5V/div
5V/div
5V/div
LX3
LX1
5V/div
5V/div
LX3
LX1
LX3
LX1
5µs/div
2µs/div
2µs/div
OUTPUT RIPPLE
OUTPUT RIPPLE
OUTPUT RIPPLE
toc14h
toc14f
toc14g
IOUT = 1A
FPWM = 1
IOUT = 10mA
FPWM = 1
IOUT = 1mA
FPWM = 1
VOUT
VOUT
VOUT
10mV/div
20mV/div
20mV/div
5V/div
5V/div
LX3
LX1
LX3
LX1
5V/div
5V/div
5V/div
5V/div
LX3
LX1
2µs/div
2µs/div
2µs/div
DYNAMIC VOLTAGE SCALING
DYNAMIC VOLTAGE SCALING
DYNAMIC VOLTAGE SCALING
toc15b
toc15a
toc15d
VOUT = 0.8V TO 1.12V 1.25mV/µs
FPWM = 0
VOUT = 0.8V TO 1.12V 10mV/µs
FPWM = 0
VOUT = 0.8V TO 1.12V 1.25mV/µs
FPWM = 1
VOUT
VOUT
VOUT
200mV/div
200mV/div
200mV/div
LX3
LX1
LX4
10V/div
10V/div
10V/div
10V/div
10V/div
10V/div
10V/div
10V/div
LX3
LX1
LX4
LX3
LX1
LX4
10V/div
50µs/div
10µs/div
50µs/div
Maxim Integrated
│ 19
www.maximintegrated.com
MAX77812
20A User-Configurable
Quad-Phase Buck Converter
Typical Operating Characteristics (continued)
(V
= 3.8V, V
= 0.85V, I
= 0A, CE = high, 4-Phase (1 Output), FPWM = 0, LPM = 0, ETR = 0, L = 220nH, C = (22µF +
SYS
OUT
OUT
OUT
0.1µF + 2 × 4.3µF), T = +25°C, unless otherwise noted.)
A
DYNAMIC VOLTAGE SCALING
DYNAMIC VOLTAGE SCALING
toc15f
DYNAMIC VOLTAGE SCALING
toc15e
toc15g
VOUT = 0.8V TO 1.12V 10mV/µs
FPWM = 1
VOUT = 1.12V TO 0.8V 1.25mV/µs
FSREN = 1
VOUT = 0.8V TO 1.12V 40mV/µs
FPWM = 1
FPWM = 0
VOUT
VOUT
200mV/div
200mV/div
VOUT
200mV/div
LX3
LX1
LX4
10V/div
10V/div
10V/div
10V/div
LX3
LX1
LX4
10V/div
10V/div
10V/div
LX3
LX1
LX4
10V/div
10V/div
10µs/div
10µs/div
50µs/div
DYNAMIC VOLTAGE SCALING
DYNAMIC VOLTAGE SCALING
DYNAMIC VOLTAGE SCALING
toc15j
toc15h
toc15i
VOUT = 1.12V TO 0.8V 5mV/µs
VOUT = 1.12V TO 0.8V 5mV/µs
FSREN = 1
VOUT = 1.12V TO 0.8V 1.25mV/µs
FSREN = 0
FSREN = 0
FPWM = 0
FPWM = 0
FPWM = 0
VOUT
VOUT
VOUT
200mV/div
200mV/div
10V/div
200mV/div
LX3
LX1
LX4
LX3
LX1
LX4
10V/div
10V/div
10V/div
10V/div
10V/div
10V/div
LX3
LX1
LX4
10V/div
10V/div
500µs/div
50µs/div
500µs/div
LOAD TRANSIENT
(4-PHASE)
DYNAMIC VOLTAGE SCALING
DYNAMIC VOLTAGE SCALING
toc16a
toc15k
toc15l
VOUT = 1.12V TO 0.8V 40mV/µs
FSREN = 1
IOUT = 0A TO 5A 0.5A/µs, FPWM = 0
VOUT = 1.12V TO 0.8V 40mV/µs
FSREN = 0
FPWM = 0
FPWM = 0
VOUT
20mV/div
VOUT
200mV/div
VOUT
200mV/div
LX3
LX1
LX4
10V/div
10V/div
10V/div
LX3
LX1
10V/div
10V/div
IOUT
10A/div
5V/div
10V/div
LX4
LX1
200µs/div
20µs/div
500µs/div
Maxim Integrated
│ 20
www.maximintegrated.com
MAX77812
20A User-Configurable
Quad-Phase Buck Converter
Typical Operating Characteristics (continued)
(V
= 3.8V, V
= 0.85V, I
= 0A, CE = high, 4-Phase (1 Output), FPWM = 0, LPM = 0, ETR = 0, L = 220nH, C
= (22µF +
SYS
OUT
OUT
OUT
0.1µF + 2 × 4.3µF), T = +25°C, unless otherwise noted.)
A
LOAD TRANSIENT
LOAD TRANSIENT
(4-PHASE)
LOAD TRANSIENT
(4-PHASE)
(4-PHASE)
toc16c
toc16d
toc16b
IOUT = 0A TO 10A 0.5A/µs, FPWM = 1
IOUT = 0A TO 5A 0.5A/µs, FPWM = 1
IOUT = 0A TO 10A 0.5A/µs, FPWM = 0
VOUT
10mV/div
VOUT
10mV/div
VOUT
20mV/div
10A/div
5V/div
IOUT
10A/div
5V/div
IOUT
LX1
10A/div
5V/div
IOUT
LX1
LX1
20µs/div
200µs/div
200µs/div
LOAD TRANSIENT
(4-PHASE)
LOAD TRANSIENT
(4-PHASE)
LOAD TRANSIENT
(3-PHASE)
toc16e
toc16f
toc16g
IOUT = 0A TO 20A 0.5A/µs, FPWM = 0
ETR = 0
IOUT =0A TO 20A 0.5A/µs, FPWM = 1
VOUT = 1.1V, IOUT = 0.1A TO 12A 100A/µs
VOUT
VOUT
20mV/div
10mV/div
VOUT
20mV/div
10A/div
5V/div
IOUT
10A/div
5V/div
IOUT
IOUT
10A/div
LX1
LX1
200µs/div
50µs/div
200µs/div
LOAD TRANSIENT
(3-PHASE)
LOAD TRANSIENT
(2-PHASE)
LOAD TRANSIENT
(2-PHASE)
toc16h
toc16i
toc16j
ETR = 1
ETR = 0
ETR = 1
V
OUT = 1.1V, IOUT = 0.1A TO 12A 100A/µs
VOUT = 1.1V, IOUT = 0.1A TO 8A 100A/µs
VOUT = 1.1V, IOUT = 0.1A TO 8A 100A/µs
VOUT
20mV/div
10A/div
VOUT
VOUT
20mV/div
10A/div
20mV/div
10A/div
IOUT
IOUT
IOUT
50µs/div
50µs/div
50µs/div
Maxim Integrated
│ 21
www.maximintegrated.com
MAX77812
20A User-Configurable
Quad-Phase Buck Converter
Typical Operating Characteristics (continued)
(V
= 3.8V, V
= 0.85V, I
= 0A, CE = high, 4-Phase (1 Output), FPWM = 0, LPM = 0, ETR = 0, L = 220nH, C
= (22µF +
SYS
OUT
OUT
OUT
0.1µF + 2 × 4.3µF), T = +25°C, unless otherwise noted.)
A
LOAD TRANSIENT
LOAD TRANSIENT
(1-PHASE)
(1-PHASE)
SHORT-CIRCUIT RESPONSE
toc16k
toc16l
toc17
ETR = 0
ETR = 1
VOUT = 1.1V, IOUT = 0.1A TO 4A 100A/µs
VOUT = 1.1V, IOUT = 0.1A TO 4A 100A/µs
VOUT
500mV/div
VOUT
VOUT
20mV/div
10A/div
20mV/div
10A/div
IOUT
20A/div
5V/div
IOUT
IOUT
LX1
50µs/div
50µs/div
50µs/div
LINE TRANSIENT
LINE TRANSIENT
LINE TRANSIENT
toc18b
toc18a
toc18c
VOUT
20mV/div
1V/div
VOUT
20mV/div
1V/div
20mV/div
1V/div
VOUT
VIN
VIN
VIN
VIN = 3.2V TO 4.2V 30mV/µs
VIN = 3.2V TO 4.2V 30mV/µs
VIN = 3.2V TO 4.2V 30mV/µs
IOUT = 10mA
FPWM = 1
IOUT = 10mA
FPWM = 0
IOUT = 1A
FPWM = 0
100µs/div
100µs/div
100µs/div
LINE TRANSIENT
LINE TRANSIENT
toc18d
toc18e
VOUT
VOUT
20mV/div
1V/div
20mV/div
1V/div
VIN
VIN
VIN = 3.2V TO 4.2V 30mV/µs
VIN = 3.2V TO 4.2V 30mV/µs
IOUT = 1A
FPWM = 1
IOUT = 4A
FPWM = 0 OR 1
100µs/div
100µs/div
Maxim Integrated
│ 22
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MAX77812
20A User-Configurable
Quad-Phase Buck Converter
Bump Configuration
1
2
3
4
5
6
7
8
PGND
1
IN
12
IN
12
PGND
2
A
B
C
D
E
F
LX1
LX1
LX2
LX2
PGND
1
PGND
1
IN
12
IN
12
PGND
2
PGND
2
LX1
IRQB
VIO
LX2
EN
SNS
1N
SNS
1P
SNS
2P
SNS
2N
AGND
SCL
AGND
SYS
I2C_SPI_
SEL
WDTRSTB
_IN
SCS
CE
LPM
SDA/
MOSI
PH_
CFG0
PH_
CFG2
MISO
GPI0
GPI1
LX4
DGND
AGND
AGND
AGND
SNS
4N
SNS
4P
SNS
3P
PH_
CFG1
SNS
3N
AGND
PGND
4
PGND
4
IN
34
IN
34
PGND
3
PGND
3
G
H
LX3
LX3
PGND
4
IN
34
IN
34
PGND
3
LX4
LX4
LX3
BUCK
BIAS
9
DIGITAL
15
40
64 WLP (8 x 8 BUMP ARRAY, 0.4MM PITCH)
*TOP VIEW = WAFER BACK-SIDE VIEW (BUMPS ARE NOT VIEWABLE)
Maxim Integrated
│ 23
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MAX77812
20A User-Configurable
Quad-Phase Buck Converter
Bump Description
BUMP
A1, B1, B2
A2, A3, B3
A4, A5, B4, B5
A6, A7, B6
A8, B7, B8
NAME
FUNCTION
PGND1
LX1
Phase1 Power Ground
Phase1 Switch Node
IN12
Phase1/2 Input. Bypass to PGND1/2 with a 10µF capacitor.
Phase2 Switch Node
LX2
PGND2
Phase2 Power Ground
C1, C8, E5, E8,
F1, F8
AGND
SNS1N
IRQ
Analog Ground
C2
Phase1 Differential Negative Remote Sense Input
Interrupt Output. A 100kΩ external pullup resistor to VIO is required. High impedance when
CE = low.
C3
C4
C5
SNS1P
SNS2P
Phase 1 Differential Positive Remote Sense Input
Phase 2 Differential Positive Remote Sense Input
Global Enable Input (Active-High, Logically ORed with GLB_EN Function of GPIs). An 800kΩ
internal pulldown resistance to DGND. If this pin is not used, leave it unconnected.
C6
C7
D1
EN
SNS2N
SCL
Phase 2 Differential Negative Remote Sense Input
2
I C Clock Input. High impedance in off state. A 1.5kΩ~2.2kΩ of pullup resistor to VIO is
required.
D2
D3
SCS
VIO
Active-Low SPI Chip Select
IO Supply Voltage Input. Bypass to DGND with a 0.1µF capacitor.
Active-High Chip Enable Input.
2
CE = High (standby), I C interface is enabled and regulators are ready to be turned on.
D4
CE
CE = Low (shutdown), all regulators are turned off and all Type-O registers are reset to their
POR default values.
Active-Low Watchdog Timer Reset Input. An 800kΩ internal pullup resistance to VIO. If this
pin is not used, leave it unconnected.
D5
D6
WDTRSTB_IN
LPM
Global Low Power Mode Input (Active-High, Logically ORed with GLB_LPM Function of
GPIs). An 800kΩ internal pulldown resistance to DGND. If this pin is not used, leave it
unconnected.
Serial Interface Selection Input. Latches at V
I2C_SPI_SEL = Low: I C
POR.
SYS
2
D7
I2C_SPI_SEL
I2C_SPI_SEL = High (V
): SPI
SYS
D8
E1
E2
E3
E4
SYS
SDA/MOSI
MISO
System (Battery) Voltage Input. Bypass to AGND with a 1µF capacitor.
2
I C Data I/O. High Impedance in Off State. A 1.5kΩ~2.2kΩ of pullup resistor to VIO is
required. Configured as MOSI when SPI mode is selected.
SPI Data Output. High impedance in off state.
Active-High, General-Purpose Input. An 800kΩ internal pulldown resistance to DGND. If this
pin is not used, leave it unconnected.
GPI0
DGND
Digital Ground
Maxim Integrated
│ 24
www.maximintegrated.com
MAX77812
20A User-Configurable
Quad-Phase Buck Converter
Bump Description (continued)
BUMP
NAME
FUNCTION
Phase Configuration Selection Input. Latches at V
POR.
SYS
PH_CFG2 = low, PH_CFG1 = low, PH_CFG0 = low: 4 phase
PH_CFG2 = low, PH_CFG1 = low, PH_CFG0 = high (V ): 3 + 1 phase
SYS
E6
PH_CFG0
PH_CFG2 = low, PH_CFG1 = high (V
PH_CFG2 = low, PH_CFG1 = high (V
), PH_CFG0 = low: 2 + 2 phase
SYS
), PH_CFG0 = high (V
): 2 + 1 + 1 phase
SYS
SYS
PH_CFG2 = high (V
), PH_CFG1 = X, PH_CFG0 = X: 1 + 1 + 1 + 1 phase
SYS
Phase Configuration Selection Input. Latches at V
POR.
SYS
PH_CFG2 = low, PH_CFG1 = low, PH_CFG0 = low: 4 phase
PH_CFG2 = low, PH_CFG1 = low, PH_CFG0 = high (V ): 3 + 1 phase
SYS
E7
PH_CFG2
PH_CFG2 = low, PH_CFG1 = high (V
), PH_CFG0 = low: 2 + 2 phase
SYS
PH_CFG2 = low PH_CFG1 = high (V
), PH_CFG0 = high (V
): 2 + 1 + 1 phase
SYS
SYS
PH_CFG2 = high (V
), PH_CFG1 = X, PH_CFG0 = X: 1 + 1 + 1 + 1 phase
SYS
F2
F3
SNS4N
GPI1
Phase 4 Differential Negative Remote Sense Input
Active-High, General-Purpose Input. An 800kΩ internal pulldown resistance to DGND. If this
pin is not used, leave it unconnected.
F4
F5
SNS4P
SNS3P
Phase 4 Differential Positive Remote Sense Input
Phase 3 Differential Positive Remote Sense Input
Phase Configuration Selection Input. Latches at V
POR.
SYS
PH_CFG2 = low, PH_CFG1 = low, PH_CFG0 = low: 4 phase
PH_CFG2 = low, PH_CFG1 = low, PH_CFG0 = high (V ): 3 + 1 phase
SYS
F6
PH_CFG1
PH_CFG2 = low, PH_CFG1 = high (V
PH_CFG2 = low, PH_CFG1 = high (V
), PH_CFG0 = low: 2 + 2 phase
SYS
), PH_CFG0 = high (V
): 2 + 1 + 1 phase
SYS
SYS
PH_CFG2 = high (V
), PH_CFG1 = X, PH_CFG0 = X: 1 + 1 + 1 + 1 phase
SYS
F7
SNS3N
PGND4
LX4
Phase 3 Differential Negative Remote Sense Input
Phase 4 Power Ground
G1, G2, H1
G3, H2, H3
G4, G5, H4, H5
G6, H6, H7
G7, G8, H8
Phase 4 Switch Node
IN34
Phase 3/4 Input. Bypass to PGND3/4 with a 10µF capacitor.
Phase 3 Switch Node
LX3
PGND3
Phase 3 Power Ground
Maxim Integrated
│ 25
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MAX77812
20A User-Configurable
Quad-Phase Buck Converter
stay there until CE goes high. As the V
voltage rises
SYS
Detailed Description
above POR threshold (≈ 1.60V), the internal reference
and the integrated supply are enabled and the MAX77812
starts loading the default register values from the OTPs.
Top-Level System Management
System Faults
System Reset
The MAX77812 monitors the system for the following
faults:
When V
voltage drops below its POR threshold
SYS
(≈ 1.50V), all Type-S1 registers are reset to their POR
default values.
● Undervoltage lockout
● VIO fault
Off Reset
Undervoltage Lockout
Off reset occurs by any power-off or shutdown events.
This condition resets all Type-O registers to their POR
default values.
When the V
voltage falls below V
(2.15V typ),
SYS
UVLO_F
the MAX77812 enters into a shutdown state and UVLO
forces the MAX77812 to a dormant state until V volt-
age rises above the UVLO rising threshold (typically 2.5V).
Once the V voltage is higher than the UVLO rising
threshold, the MAX77812 comes out of shutdown mode
to be securely functional. The UVLO falling threshold is
programmable through I C, but it must be set lower than
SYS
Software Reset
All Type-O registers can be reset by writing ‘1’ to SW_
RST bit in REG_RESET register. This bit clears to ‘0’
upon reset.
SYS
2
Watchdog Timeout Reset (WDTRSTB_IN)
UVLO rising threshold to avoid unexpected behaviors.
In case the host processor fails to reset its watchdog
timer for any system issues, WDTRSTB_IN signal goes
low for about 100ms. When the MAX77812 detects that
WDTRSTB_IN is low longer than its debounce timer (pro-
grammable by WDT_DEB[2:0]), the output voltage setting
registers of all phases (Mx_VOUT[7:0]) reset to their POR
default values and the output voltages return to their POR
default values with given ramp-up/down slew rates.
VIO Fault
When the VIO supply falls below V
typ), the MAX77812 immediately goes into a shutdown
state and stays in this mode until IO supply rises beyond
(1.0V
TH_VIO_OK
V
threshold.
TH_VIO_OK
Thermal Protection
The MAX77812 has a centralized thermal protection
circuit which monitors temperature on the die. If the die
Chip Enable (CE)
temperature exceeds +165°C (T
), the MAX77812
When V
and V
supplies are valid, a logic-high on
SHDN
SYS
VIO
initiates a soft-stop for all the output(s) and all Type-O
registers are reset to their POR default values. However,
the MAX77812 should be able to communicate with the
host processor through the serial interface as long as
CE pin puts the MAX77812 into standby mode (enabled).
In standby mode, all user registers are accessible through
I C/SPI so that the host processor can overwrite the
2
default output voltages of regulators and each regulator
2
V
SYS
and V
supplies are within the operating range.
can be enabled by either I C/SPI or GPI input if applicable.
VIO
In case the die temperature drops by 15°C after the
thermal protection occurs, the MAX77812 recovers to the
normal state and the output(s) can be turned on again.
When CE pin goes high, the MAX77812 turns on the
internal bias circuitry which takes typically 50µs to be
settled. As soon as the bias is ready, all the regulators
are allowed to be turned on via I C/SPI or EN pins. In
case the regulators are enabled before the bias circuitry is
ready, the regulators require longer time to startup.
2
In addition to +165°C threshold, there are two additional
comparators which trip at +120°C and +140°C. Interrupts
are generated in the event the die temperature reaches
+120°C or +140°C.
When the CE pin is pulled low, the MAX77812 goes into
shutdown mode (disabled) and turns off all the regulators
regardless of EN pins. This event also resets all Type-O
registers to their POR default values.
Reset Conditions
Power-On Reset (POR)
When a valid system supply voltage is applied to the
device, the MAX77812 goes into shutdown mode and
Maxim Integrated
│ 26
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MAX77812
20A User-Configurable
Quad-Phase Buck Converter
Enable Control
Immediate Shutdown Events
Each master phase of the MAX77812 can be enabled and
disabled by a corresponding enable register bit (EN_Mx),
EN input and multifunction GPIs. The enable logic is an
‘OR’ logic of active enable logic signals. For example, the
Master1 is enabled when EN_M1 bit, GLB_EN or M1_EN
logic signal is set to ‘1’. When all active signals are ‘0’, the
corresponding master phase is turned off.
The following events initiate an immediate shutdown:
● V
● V
< SYS UVLO falling threshold (V
)
SYS
UVLO_F
< VIO OK threshold (V
)
VIO
TH_VIO_OK
The events in this category are associated with potentially
hazardous system states. Powering down the host
processor and resetting all Type-O registers help mitigate
any issues that can occur due to these potentially
hazardous conditions.
Startup and Shutdown Sequence
The MAX77812 supports programmable startup and
shutdown delay times between the master phases. The
startup and shutdown sequence is initiated by either
EN pin or GLB_EN function of GPIs. The startup and
shutdown delay times between the master phases are
programmable from 0ms to 62ms (32 steps).
Interrupt and Mask
The IRQ output is used to indicate to the host processor
that the status on the MAX77812 has changed. The IRQ
output asserts (goes low) anytime an unmasked interrupt
bit is triggered. The host processor reads the interrupt
source register (ADDR 0x01) and the interrupt registers
that are indicated by the interrupt source register to see
the cause of interrupt event. Note that the interrupt source
register is cleared when the corresponding interrupt regis-
ter group is read by the host processor.
The startup sequence is set by OTP bits as well as
STUP_DLYx registers and the Master 1 is always turned
on as soon as a startup sequence is initiated, while the
shutdown sequence is programmable by SHDN_DLYx
registers only and the delay times for all master phases
are programmable.
All the interrupt events are edge-triggered. Therefore, the
same interrupt is not generated repeatedly even though
the interrupt condition persists.
If any master phase(s) is(are) turned on by EN_Mx bit or
Mx_EN input before initiating startup or shutdown, global
startup or shutdown sequence does not affect the master
phase(s) already turned on or off.
Each interrupt register can be read at a time and all inter-
rupt bits are clear-on-read bits. The IRQ output de-asserts
(goes high) when all interrupt bits have been cleared. If
an interrupt is captured during the read sequence, IRQ
output is held low. When IRQ output is pulled low by an
unmasked interrupt event, IRQ output stays low until the
interrupt bit is cleared by the reading operation of the host
processor or the corresponding interrupt mask bit is set to
‘1’ (masked).
Figure 1 shows a typical startup and shutdown sequence.
For more detailed information on programming the
sequencer, refer to Application Note 6826: How to
Program Startup and Shutdown Sequence with
MAX77812.
EN PIN OR
GLB_EN
M1
M2
M3
M4
t
4
t
t
5
1
t
t
6
2
t
t
7
3
Figure 1. Startup and Shutdown Sequence
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MAX77812
20A User-Configurable
Quad-Phase Buck Converter
Each interrupt can be masked (disabled) by setting the
corresponding interrupt mask register bit.
The PWM comparator regulates VOUTx by modulating
off-time. A compensation ramp is fed to the positive
input of the PWM comparator and the negative input
is a voltage proportional to the actual output voltage
error added to the replicated AC current in the inductor.
The PWM comparator begins an on-time (and resets
the compensation ramp) when the error voltage plus
replicated AC inductor current becomes greater than the
ramp. When the calculated on-time expires, the off-time
automatically begins. One PWM comparator is used to
control all phases in multiphase configuration. The output
is demultiplexed by a phase scheduler which controls
the phase spacing of each switching stage (e.g., 2Φ is
spaced 180º apart, 3Φ is spaced 120º, 4Φ is spaced 90°).
Multiphase configurations permanently have all phases
activated and always switches in sequence during steady-
state operation (phases do not add or shed).
When the corresponding mask bit is set (masked), an
interrupt bit is not set for an interrupt event. As a result,
the IRQ output stays high. When the mask bit is cleared,
an active interrupt event at the time of clearing the mask
bit is captured, which results in pulling the IRQ output low.
Interrupt mask bits are set to ‘1’ by default and are reset
to the default values at power-off events.
Status
In addition to interrupt bits, the MAX77812 has read-only
STATUS bits. Those bits always represent the current sta-
tus of the device. It is highly recommended that the host
processor read STATUS bits whenever the MAX77812 is
initialized by the host processor. These STATUS bits do
not directly affect the state of interrupt bits.
The switching frequency (F ) of the adaptive on-time
SW
BUCK is variable and heavily influenced by the instanta-
neous load. More on-time pulses in a given time (higher
Quad-Phase Buck Regulator
The MAX77812 uses Maxim’s proprietary Quick-PWM™
adaptive on-time control scheme. Adaptive on-time con-
trol provides fast response to load transients, inherent
compensation to input voltage variation, and stable perfor-
mance at low duty cycles. On-times (high-side MOSFET
on) are controlled by the on-time generator circuit. This
circuit calculates an on-time based on the input voltage
F
) is observed as load increases. Fewer on-times in a
SW
given time (lower F ) is observed as load decreases.
SW
Phase/Output Configurations
The MAX77812 supports user-programmable phase con-
figuration by PH_CFG0, PH_CFG1 and PH_CFG2 input
logic state. The input logic state is latched at the POR
event.
(V ), the output voltage (V
INx
), and the target switch-
OUTx
ing frequency (F ). The on-time is modified (slightly
SW
All supported phase configurations are shown in Table 1.
Refer to Application Note 6804: Guidelines for the
MAX77812 User-Selectable Phase Configurations and
How to Select Them for a concise summary of all the
shortened or lengthened) by the phase current balancing
control circuit. Off-times (low-side MOSFET on) begin
when the on-time ends. Shoot-through current from INx to
PGNDx is avoided by introducing a brief period of dead-
time between switching events when neither MOSFET is
on. During the dead-time, the inductor current conducts
through the intrinsic body diode of the low-side MOSFET.
information
data sheet.
regarding phase configurations found in this
Table 1. User-Programmable Phase/Output Configurations
PH_CFG2
Low
PH_CFG1
Low
PH_CFG0
Low
PHASE CONFIGURATION
1 Output: 4-Phase (Master 1)
Low
Low
High
2 Outputs: 3-phase (Master 1) + 1-phase (Master 4)
2 Outputs: 2-phase (Master 1) + 2-phase (Master 3)
Low
High
Low
Low
High
High
3 Outputs: 2-phase (Master 1) + 1-phase (Master 3) + 1-phase (Master 4)
4 Outputs: 1-phase (Master 1) + 1-phase (Master 2) + 1-phase (Master 3) +
1-phase (Master 4)
High
X
X
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MAX77812
20A User-Configurable
Quad-Phase Buck Converter
Based on the selected phase configuration, the phase
selector generates the TON signals to each power stage
with different phase interleaving schemes and the master
phases are assigned as shown in Figure 2.
age of 0.4V when the regulator is enabled, the regulator
gracefully increases the capacitor voltage to the required
target voltage such as 1.0V. This is unlike other regulators
without the start into prebias feature where they can force
the output capacitor voltage to 0V before the soft-start
ramp begins.
Note that only registers for the master phase(s) are
activated and the slave phase(s) are controlled by the
corresponding master phase(s).
The buck regulator supports programmable soft-start rate
from 1.25mV/µs to 60mV/µs. The controlled soft-start rate
and buck regulator current limit (ILIM_PEAK) limit the
input inrush current to the output capacitor (IINRUSH).
IINRUSH = min (ILIM_PEAK & COUT x dv/dt). Note that
the input current of the buck regulator is lower than the
inrush current to the output capacitor by the ratio of output
to input voltage.
SKIP/Forced PWM Operation
In normal operating mode, buck automatically transitions
from skip mode to fixed frequency operation as the load
current increases. For operating modes where lowest
output ripple is required, Forced PWM switching behavior
can be enabled by writing ‘1’ to Mx_FPWM bit.
Low Power Mode
Output Voltage Setting
Each master includes LPM (low power mode) operation to
minimize the quiescent current when the host processor
is in sleep state. In LPM, the ETR (enhanced transient
response), ADT (adaptive dead-time control), and POK
comparator (POK = high) are disabled so that load tran-
sient response of the buck regulators are derated as the
trade-off. The LPM of each master can be enabled inde-
pendently by Mx_LPM bits.
The output voltage is programmable from 0.25V to 1.525V
in 5mV steps to allow fine adjustment to the processor
supply voltage under light load conditions to minimize
power loss within the processor. Each master phase have
three output voltage control registers. Mx_VOUT[7:0]
register is for normal operation and Mx_VOUT_D[7:0]
and Mx_VOUT_S[7:0] are used for voltage selection func-
tion by GPIx. See the *Multifunction GPIs* section. The
default output voltages are set by an OTP option at the
factory. The default output voltages can be overwritten by
changing the contents in Mx_VOUT[7:0] register prior to
enabling the regulator.
Startup and Soft-Start
When starting up buck regulator, the bias circuitry must
be enabled and provided with adequate time to settle. The
bias circuitry is guaranteed to settle within 250µs, at which
time, the buck regulators power-up sequence can com-
mence. Note that attempting to implement a power-up
sequence before the BIASOK signal is generated results
in all enabled regulators starting up at the same time.
For some applications, an output voltage higher than
1.525V is required. The MAX77812 supports higher out-
put voltage with the addition of an external voltage-divider
network. For more details, refer to Application Note
6823: Generating a Higher Output Voltage than 1.525V
Using the MAX77812.
The buck regulator supports starting into a prebiased out-
put. For example, if the output capacitor has an initial volt-
PHASE
CONFIGURATION
PHASE
SEQUENCE
ACTIVE CONTROL
REGISTERS
4
PH1 PH3 PH2 PH4
PH1 PH3 PH2 PH4
PH1 PH2 PH3 PH4
PH1 PH2 PH3 PH4
PH1 PH2 PH3 PH4
M1 NA NA NA
M1 NA NA M4
M1 NA M3 NA
M1 NA M3 M4
M1 M2 M3 M4
PH1
PH4
PH2
PH3
3 + 1
2 + 2
2 + 1 + 1
1 + 1 + 1 + 1
Figure 2. Buck Phase Configuration
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MAX77812
20A User-Configurable
Quad-Phase Buck Converter
Either the regulator remains enabled or the active dis-
charge function is disabled (Mx_AD = 0), the internal
resistor is disconnected from the output. If the active dis-
charge function is disabled, the output voltage decays at a
rate that is determined by the output capacitance and the
load current when the regulator is turned off.
Changing Output Voltage During Operation
In a typical smartphone or tablet application, there are
several power domains in which the operating frequency
of the processor is increased or decreased (DVFS). When
the operating frequency needs to be changed, it is expect-
ed that the buck regulator responds to a command to
change the output voltages to new target values quickly.
The high peak current limit, coupled with low inductance
and small output capacitance, allows the buck regulator
to respond to a positive step change in output voltage and
settle to the new target value quickly. The buck regulator
provides programmable ramp-up slew rates to accommo-
date different requirements.
Enhanced Transient Response
The MAX77812 features the enhanced transient response
(ETR) function to improve the output-voltage transient
responses with very fast load changes. When enabled,
the ETR function monitors the output voltage and detects
high dv/dt undershoot and overshoot separately.
When the negative ETR (NETR) is detected during
output-voltage undershoot, the buck controllers turn on all
master and slave phases assigned to the same output at
the same time (in-phase) until the NETR is de-asserted.
This allows the multi-phase buck converters (no signifi-
cant impact on single-phase buck) to pump up energy to
the output in order to recover from the undershoot quickly.
For a negative step change in output voltage, the set-
tling time is not critical. In Forced PWM mode (either
Mx_FPWM bit or Mx_FSREN bit is enabled), the negative
inductor current through NMOS discharges energy from
the output capacitor, which helps the output voltage to
decrease to the new target value faster. In skip mode, the
negative inductor current is not allowed so that the output
voltage settling time is dependent on the load current and
the output capacitance.
When the positive ETR (PETR) is detected, the buck
controllers turn off the corresponding low-side MOSFETs
to discharge excessive energy stored in the inductors,
which results in suppressing output-voltage overshoot.
When the PETR is released, the buck controllers operate
in FPWM mode for about 5ms before returning to normal
operation.
Output Voltage Slew Rate Control
The buck regulator supports programmable slew rate
control feature when increasing and decreasing the out-
put voltage. The ramp-up slew rate can be set to 1.25mV/
µs, 2.5mV/µs, 5mV/µs, 10mV/µs, 20mV/µs 40mV/µs or
60mV/µs independently via B_RU_SR[2:0] bits, while
the ramp-down slew rate is programmable to 1.25mV/
µs, 2.5mV/µs, 5mV/µs, 10mV/µs, 20mV/µs 40mV/µs or
60mV/µs through B_RD_SR[2:0].
Both NETR and PETR functions are enabled by default,
but they can be turned off to reduce quiescent current by
clearing the B_NETR_EN and B_PETR_EN bits in the
GLB_CFG3 register.
Inductor Selection
Remote Output Voltage Sensing
The buck regulator is optimized for 220nH to 470nH induc-
tors. The lower the inductor DCR, the higher the buck effi-
ciency is. Users need to trade off inductor size with DCR
value and choose a suitable inductor for the buck.
All phases support differential remote output voltage
sensing feature for improving point of load regulation.
Differential feedback (SNSxP and SNSxN) enables volt-
age sensing directly at the point of load, ensuring best
voltage regulation at the load, regardless of power plane
impedances.
Output Active Discharge
BUCK provides an internal 100Ω resistor for output active
discharge function. If the active discharge function is
enabled (Mx_AD = 1), the internal resistor discharges the
energy stored in the output capacitor to PGNDx whenever
the regulator is disabled.
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MAX77812
20A User-Configurable
Quad-Phase Buck Converter
Inductor Current Limit
Unused Outputs
A cycle-by-cycle current limit provides overcurrent protec-
tion by monitoring the current in the high-side and low-
Follow these guidelines when the application has unused
buck outputs:
side MOSFETs. The peak current limit (I
) triggers
PLIM
● Connected unused inputs (INx) to SYS.
during on-time and prevents the inductor current from
running away. If I trips, the on-time ends and the
● Leave unused LXx pins unconnected (open).
● Connect unused SNSxN and PGNDx pins to ground.
PLIM
low-side MOSFET turns on to reduce the inductor current
until it hits the valley current limit (I ). Once the cur-
VLIM
● Connect unused SNSxP pins to either input or
ground, depending on the state of the unused output
in the application:
rent falls to I , normal operation resumes. Note that
VLIM
the buck output current is limited to (I
+ I )/2.
VLIM
PLIM
For more detailed information, refer to Application Note
6820: How Overcurrent Protections Works in the
MAX77812.
• If the unused output can be enabled at any point
in the application, either by the global enable in-
put pin (EN) or a GPIx set to be a global enable,
connect the unused SNSxP to INx.
Input and Output Capacitor Selection
• If the unused output is disabled by default and
will never be enabled, connect the unused
SNSxP to ground.
The input capacitor, C , reduces the current peaks
drawn from the battery or input power source and reduces
IN
switching noise in the device. The impedance of C at
IN
Do not confuse unused outputs with unused phases.
Phases configured under a master controller in a multi-
phase configuration must connect according to Table 1.
the switching frequency should be kept very low. Ceramic
capacitors with X5R or X7R dielectrics are highly rec-
ommended due to their small size, low ESR, and small
temperature coefficients. For most applications a 10µF
capacitor is sufficient.
If possible, do not enable unused outputs. An unused out-
put with a floating LX pin might try switching the LX node
indefinitely (depending on the SNSxP connection), which
wastes supply current.
The output capacitor, C
, is required to keep the out-
OUT
put voltage ripple small and to ensure regulation loop
stability. C must have low impedance at the switching
OUT
PCB Trace Resistance
frequency. Ceramic capacitors with X5R or X7R dielectric
are highly recommended due to their small size, low ESR,
and small temperature coefficients. Due to the unique
feedback network, the output capacitance can be very
low. The recommended minimum output capacitance per
phase is 22µF.
The evaluation kit (and the typical PCB on which the
MAX77812 is expected to be designed in) utilize 1/3oz.
Cu, which is plated up to 0.5oz. 0.5oz. Cu has a typical
resistance of 1mΩ per square.
Table 2. Suggested Inductors
NOMINAL
INDUCTANCE
(nH)
TYPICAL DC
RESISTANCE
CURRENT
RATING (A)
-30% (∆L/L)
CURRENT
RATING [A]
∆T = +40°C RISE
DIMENSIONS
L x W x H
(mm)
MFGR.
SERIES
(mΩ)
Cyntec
TOKO
ALPS
HMLE20161B-R22MDR
DFE201610-E-R24N
GLULMR2201A
220
240
220
13
16
9
5.8
7.0
6.5
5.3
5.5
7.0
2.0 x 1.6 x 1.2
2.0 x 1.6 x 1.0
2.5 X 2.0 X 1.2
Table 3. Suggested Capacitors
NOMINAL
CAPACITANCE
RATED
VOLTAGE
(V)
DIMENSIONS
L x W x H
(mm)
TEMPERATURE
CHARACTERISTICS
CASE SIZE
(Imperial)
MFGR.
SERIES
(µF)
Murata
Murata
GRM188R60J106ME84
GRM188R60J226MEA0
10 ±20%
22 ±20%
6.3
6.3
X5R
X5R
0603
0603
1.6 x 0.8 x 0.8
1.6 x 0.8 x 0.8
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MAX77812
20A User-Configurable
Quad-Phase Buck Converter
Table 4. Multifunction GPI Configurations
GPIx_FUNC[3:0]
0000b
0001b
0010b
0011b
FUNCTION
GLB_EN
M1_EN
REMARK
Global Enable (Master 1 through Master 4)
Master 1 Enable
M2_EN
Master 2 Enable
M3_EN
Master 3 Enable
0100b
0101b
0110b
M4_EN
Master 4 Enable
GLB_VSEL
M1_VSEL
M2_VSEL
M3_VSEL
M4_VSEL
GLB_LPM
M1_LPM
M2_LPM
M3_LPM
M4_LPM
No function
Global Voltage Selection (Master 1 through Master 4)
Master 1 Voltage Selection
Master 2 Voltage Selection
Master 3 Voltage Selection
Master 4 Voltage Selection
Global Low Power Mode Select (Master 1 through Master 4)
Master 1 Low Power Mode Enable
Master 2 Low Power Mode Enable
Master 3 Low Power Mode Enable
Master 4 Low Power Mode Enable
—
0111b
1000b
1001b
1010b
1011b
1100b
1101b
1110b
1111b
Voltage Selection by GPI
The buck has two additional output voltage control reg-
isters (Mx_VOUT_D[7:0] and Mx_VOUT_S[7:0]) besides
one (Mx_VOUT[7:0]) for normal operation. Those two
additional registers are for storing the default output
voltage and the system sleep mode output voltage for a
specific host processor.
Multifunction GPIs
General Description
The MAX77812 has two general purpose inputs (GPI0
and GPI1) that can be configured as the enable of regu-
lators, the output voltage selection, the low power mode
control and no function. The function of these two inputs
2
is programmable through I C/SPI (GPI_FUNC register)
When GPIx are configured as voltage selection pins,
the output voltage of a specific regulator is set by Mx_
VOUT_D[7:0] and Mx_VOUT_S[7:0] registers based on
the input logic. For example, if GPI0_FUNC[3:0] = 0101b,
the output voltages of all the masters are set by Mx_
VOUT_D[7:0] and Mx_VOUT_S[7:0] when GPI0 = high
and GPI0 = low, respectively. In case the two GPIs are
configured as the same voltage selection function, those
inputs are ORed. During the output voltage transition, the
ramp-up/down slew rate is controlled by B_RU_SR[2:0]
and B_RD_SR[2:0]. Note that M1 thru M4 are defined by
PH_CFG0, PH_CFG1 and PH_CFG2 inputs.
on the fly. Application Note 6822: How to Use Multi-
Function GPIs? provides an in-depth look at program-
ming the GPIs for their various functions.
Enable Control by GPI
When the GPIx are configured as output enable pins, the
enable logic of a specific regulator is an ‘OR’ logic of the
GPIx and the corresponding enable register bit (Mx_EN).
For example, if GPI0_FUNC[3:0] = 0001b, the buck
Master 1 enable is controlled by GPI0 and M1_EN bit.
In case the two GPIs are configured as the same enable
function (i.e., GPI0_FUNC[3:0] = GPI1_FUNC[3:0] =
0010b), those inputs are ORed with M2_EN bit. GLB_EN
function (GPI0_FUNC[3:0] = 0000b) allows the host pro-
cessor to enable all the masters in sequence based on
STUP_DLYx registers. Note that M1 thru M4 are defined
by PH_CFG0, PH_CFG1 and PH_CFG2 inputs.
Low Power Mode by GPI
When GPIx are configured as low power mode enable
pins, the low power mode enable logic of a specific regula-
tor is an ‘OR’ logic of GPIx and the corresponding enable
register bit (Mx_LPM). For example, if GPI0_FUNC[3:0]
= 1011b, the buck Master 1 low power mode enable is
controlled by GPI0 and M1_LPM bit.
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MAX77812
20A User-Configurable
Quad-Phase Buck Converter
In case the two GPIs are configured as the same enable
function (i.e., GPI0_FUNC[3:0] = GPI0_FUNC[3:0] =
1100b), those inputs are ORed with M2_LPM bit. GLB_
LPM function (GPI0_FUNC[3:0] = 1010b) allows the host
processor to enable low power mode of all the masters
at the same time. Note that M1 thru M4 are defined by
PH_CFG0, PH_CFG1, and PH_CFG2 inputs.
System Configuration
The I C bus is a multimaster bus. The maximum number
of devices that can attach to the bus is only limited by bus
capacitance.
2
2
Figure 3 shows an example of a typical I C system. A
2
device on I C bus that sends data to the bus in called a
transmitter. A device that receives data from the bus is
called a receiver. The device that initiates a data transfer
and generates SCL clock signals to control the data
transfer is a master. Any device that is being addressed
by the master is considered a slave. When the MAX77812
2
I C Serial Interface
General Description
2
The I C-compatible 2-wire serial interface is used for
2
2
I C-compatible interface is operating, it is a slave on I C
bus and it can be both a transmitter and a receiver.
regulator on/off control, setting output voltages, and other
functions. See the Register Map section for details.
2
The I C serial bus consists of a bidirectional serial-data
Bit Transfer
2
line (SDA) and a serial clock (SCL). I C is an open-drain
One data bit is transferred for each SCL clock cycle. The
data on SDA must remain stable during the high portion of
SCL clock pulse. Changes in SDA while SCL is high are
control signals (START and STOP conditions).
bus. SDA and SCL require pullup resistors (500Ω or
greater). Optional 24Ω resistors in series with SDA and
SCL help to protect the device inputs from high voltage
spikes on the bus lines. Series resistors also minimize
crosstalk and undershoot on bus lines.
SDA
SCL
MASTER
SLAVE
SLAVE
TRANSMITTER/
RECEIVER
MASTER
TRANSMITTER/
RECEIVER
SLAVE
TRANSMITTER
TRANSMITTER/
RECEIVER
RECEIVER
Figure 3. Functional Logic Diagram for Communications Controller
SCL
SDA
DATA LINE STABLE
DATA VALID
CHANGE OF DATA
ALLOWED
2
Figure 4. I C Bit Transfer
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MAX77812
20A User-Configurable
Quad-Phase Buck Converter
When a STOP condition or incorrect address is detected,
the MAX77812 internally disconnects SCL from I C serial
interface until the next START condition, minimizing digital
noise and feedthrough.
START and STOP Conditions
When I C serial interface is inactive, SDA and SCL idle
high. A master device initiates communication by issuing
a START condition. A START condition is a high-to-low
transition on SDA with SCL high. A STOP condition is a
low-to-high transition on SDA, while SCL is high.
2
2
Acknowledge
2
Both the I C bus master and the MAX77812 (slave)
A START condition from the master signals the beginning
of a transmission to the MAX77812. The master terminates
transmission by issuing a NOT ACKNOWLEDGE followed
by a STOP condition.
generate acknowledge bits when receiving data. The
acknowledge bit is the last bit of each nine bit data packet.
To generate an ACKNOWLEDGE (A), the receiving
device must pull SDA low before the rising edge of the
acknowledge-related clock pulse (ninth pulse) and keep
it low during the high period of the clock pulse. To gener-
ate a NOT ACKNOWLEDGE (nA), the receiving device
allows SDA to be pulled high before the rising edge of the
acknowledge-related clock pulse and leaves it high during
the high period of the clock pulse.
A STOP condition frees the bus. To issue a series of
commands to the slave, the master can issue REPEATED
START (Sr) commands instead of a STOP command
in order to maintain control of the bus. In general, a
REPEATED START command is functionally equivalent
to a regular START command.
Monitoring the acknowledge bits allows for detection
of unsuccessful data transfers. An unsuccessful data
transfer occurs if a receiving device is busy or if a system
fault has occurred. In the event of an unsuccessful data
transfer, the bus master should reattempt communication
at a later time.
S
Sr
P
t
SU_START
SCL
SDA
t
SU_STOP
t
t
HD_START
HD_START
Slave Address
2
The I C slave address is set by buck phase configuration
as shown in Table 5. If two MAX77812 devices with the
same phase configuration need to be connected to the
2
same I C bus, contact a Maxim representative.
2
Figure 5. I C Start Stop
2
Table 5. I C Slave Address
SLAVE ADDRESS
(7-BIT)
SLAVE ADDRESS
SLAVE ADDRESS
(READ)
PH_CFG2
PH_CFG1
PH_CFG0
(WRITE)
MAX77812EWB+, MAX77812AEWB+, MAX77812BEWB+, MAX77812CEWB+, MAX77812DEWB+
Low
Low
Low
High
High
X
Low
High
Low
High
X
011 0000
011 0001
011 0010
011 0011
011 0100
0x60 (0110 0000)
0x62 (0110 0010)
0x64 (0110 0100)
0x66 (0110 0110)
0x68 (0110 1000)
0x61 (0110 0001)
0x63 (0110 0011)
0x65 (0110 0101)
0x67 (0110 0111)
0x69 (0110 1001)
Low
Low
Low
High
MAX77812FEWB+
Low
Low
Low
Low
High
Low
Low
High
High
X
Low
High
Low
High
X
011 1000
011 1001
011 1010
011 1011
011 1100
0x70 (0111 0000)
0x72 (0111 0010)
0x74 (0111 0100)
0x76 (0111 0110)
0x78 (0111 1000)
0x71 (0111 0001)
0x73 (0111 0011)
0x75 (0111 0101)
0x77 (0111 0111)
0x79 (0111 1001)
Maxim Integrated
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MAX77812
20A User-Configurable
Quad-Phase Buck Converter
S
SDA
SCL
1
1
1
2
0
3
0
4
0
5
0
6
0
7
R/nW
A
9
ACKNOWLEDGE
8
Figure 6. Slave Address Byte Example
bus capacitance and pullup resistance (C x R) slow the
bus operation. Therefore, when increasing bus speeds
the pullup resistance must be decreased to maintain a
reasonable time constant. See the Pullup Resistor Sizing
Clock Stretching
In general, the clock signal generation for I C bus is
the responsibility of the master device. I C specification
allows slow slave devices to alter the clock signal by
holding down the clock line. The process in which a slave
device holds down the clock line is typically called clock
stretching. The MAX77812 does not use any form of clock
stretching to hold down the clock line.
2
2
2
section of the I C revision 3.0 specification for detailed
guidance on the pullup resistor selection. In general, for
bus capacitance of 200pF, a 100kHz bus needs 5.6kΩ
pullup resistors, a 400kHz bus needs about a 1.5kΩ pullup
resistors, and a 1MHz bus needs 680Ω pullup resistors.
Note that the pullup resistor is dissipating power when the
open-drain bus is low. The lower the value of the pullup
General Call Address
The MAX77812 does not implement the I C speci-
fication general call address. If the MAX77812 sees
general call address (00000000b), it does not issue an
ACKNOWLEDGE (A).
2
2
resistor, the higher the power dissipation (V /R).
Operating in high-speed mode requires some special con-
2
siderations. For the full list of considerations, see the I C
3.0 specification. The major considerations with respect to
the MAX77812 are:
Communication Speed
The MAX77812 provides an I C 3.0-compatible (3.4MHz)
serial interface.
2
2
●
I C bus master use current source pullups to shorten
the signal rise times.
2
● I C Revision 3 Compatible Serial Communications
2
●
I C slave must use a different set of input filters
Channel
on its SDA and SCL lines to accommodate for the
higher bus speed.
• 0Hz to 100kHz (Standard Mode)
• 0Hz to 400kHz (Fast Mode)
• 0Hz to 1MHz (Fast Mode Plus)
• 0Hz to 3.4MHz (High-speed Mode)
●
The communication protocols need to utilize the
high-speed master code.
2
● Does not utilize I C Clock Stretching
At power-up and after each STOPcondition, the MAX77812
inputs filters are set for standard mode, fast mode, or fast
mode plus (i.e., 0Hz to 1MHz). To switch the input filters
for high-speed mode, use the high-speed master code
protocols that are described in the Protocols section.
Operating in standard mode, fast mode and fast mode
plus does not require any special protocols. The main
consideration when changing the bus speed through
this range is the combination of the bus capacitance and
pullup resistors. Higher time constants created by the
Maxim Integrated
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MAX77812
20A User-Configurable
Quad-Phase Buck Converter
(A) by pulling SDA low.
Communication Protocols
The MAX77812 supports both writing and reading from
its registers.
4) The master sends an 8-bit register pointer.
5) The slave acknowledges the register pointer.
6) The master sends a data byte.
Writing to a Single Register
2
Figure 7 shows the protocol for I C master device to write
7) The slave acknowledges the data byte. At the rising
edge of SCL, the data byte is loaded into its target
register and the data becomes active.
one byte of data to the MAX77812. This protocol is the
same as SMBus specification’s write byte protocol.
The write byte protocol is as follows:
8) The master sends a STOP condition (P) or a
REPEATED START condition (Sr). Issuing a P
ensures that the bus input filters are set for 1MHz or
slower operation. Issuing a REPEATED START (Sr)
leaves the bus input filters in their current state.
1) The master sends a START command (S).
2) The master sends the 7-bit slave address followed
by a write bit (R/W = 0).
3) The addressed slave asserts an ACKNOWLEDGE
LEGEND
MASTER TO
SLAVE
SLAVE TO
MASTER
*P FORCES THE BUS FILTERS TO SWITCH TO THEIR ≤ 1MHz MODE.
Sr LEAVES THE BUS FILTERS IN THEIR CURRENT STATE.
NUMBER
OF BITS
1
7
1
0
1
8
1
8
1
1
S
SLAVE ADDRESS
A
REGISTER POINTER
A
DATA
A
P or Sr *
R/nW
THE DATA IS LOADED INTO
THE TARGET REGISTER
AND BECOMES ACTIVE
DURING THIS RISING EDGE.
SDA
SCL
B1
7
B0
8
A
9
ACKNOWLEDGE
Figure 7. Writing to a Single Register with Write Byte Protocol
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MAX77812
20A User-Configurable
Quad-Phase Buck Converter
6) The master sends a data byte.
Writing to Sequential Registers
Figure 8 shows the protocol for writing to a sequential
registers. This protocol is similar to the write byte protocol,
except the master continues to write after it receives the
first byte of data. When the master is done writing it issues
a STOP or REPEATED START
7) The slave acknowledges the data byte. At the rising
edge of SCL, the data byte is loaded into its target
register and the data becomes active.
8) Steps 6 to 7 are repeated as many times as the
master requires.
The writing to sequential registers protocol is as follows:
1) The master sends a START command (S).
9) During the last acknowledge related clock pulse, the
master issues an ACKNOWLEDGE (A).
2) The master sends the 7-bit slave address followed
10) The master sends a STOP condition (P) or a
REPEATED START condition (Sr). Issuing a P
ensures that the bus input filters are set for 1MHz or
slower operation. Issuing a REPEATED START (Sr)
leaves the bus input filters in their current state.
by a write bit (R/W = 0).
3) The addressed slave asserts an ACKNOWLEDGE
(A) by pulling SDA low.
4) The master sends an 8-bit register pointer.
5) The slave acknowledges the register pointer.
LEGEND
MASTER TO
SLAVE
SLAVE TO
MASTER
*P FORCES THE BUS FILTERS TO SWITCH TO THEIR ≤ 1MHz MODE.
Sr LEAVES THE BUS FILTERS IN THEIR CURRENT STATE.
NUMBER
OF BITS
1
7
1
0
1
8
1
8
1
S
SLAVE ADDRESS
A
REGISTER POINTER X
A
DATA X
A
α
α
R/nW
NUMBER
OF BITS
8
1
8
1
DATA X+1
A
DATA X+2
A
REGISTER POINTER = X + 2
REGISTER POINTER = X + 1
8
α
1
NUMBER
OF BITS
8
1
1
DATA N-1
A
DATA N
A
P or Sr *
β
REGISTER POINTER = X + (N-2)
REGISTER POINTER = X + (N-1)
α
THE DATA IS LOADED INTO THE
TARGET REGISTER AND BECOMES
ACTIVE DURING THIS RISING EDGE.
SDA
SCL
B1
7
B0
8
A
9
B9
ACKNOWLEDGE
1
DETAIL: α
THE DATA IS LOADED INTO THE
TARGET REGISTER AND BECOMES
ACTIVE DURING THIS RISING EDGE.
SDA
SCL
B1
7
B0
8
A
9
ACKNOWLEDGE
DETAIL: β
Figure 8. Writing to Sequential Registers “X” to “N”
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MAX77812
20A User-Configurable
Quad-Phase Buck Converter
3) The addressed slave asserts an ACKNOWLEDGE
(A) by pulling SDA LOW.
Writing Multiple Bytes using Register-Data Pairs
2
Figure 9 shows the protocol for I C master device to write
multiple bytes to the MAX77812 using register-data pairs.
This protocol allows I C master device to address the
slave only once and then send data to multiple registers
in a random order. Registers may be written continuously
until the master issues a STOP condition.
4) The master sends an 8-bit register pointer.
5) The slave acknowledges the register pointer.
6) The master sends a data byte.
2
7) The slave acknowledges the data byte. At the rising
edge of SCL, the data byte is loaded into its target
register and the data will become active.
The “Multiple Byte Register-Data Pair” protocol is as follows:
1) The master sends a START command.
8) Steps 4 to 7 are repeated as many times as the
master requires.
2) The master sends the 7-bit slave address followed
by a write bit.
9) The master sends a STOP condition.
LEGEND
MASTER TO
SLAVE
SLAVE TO
MASTER
NUMBER
OF BITS
1
7
1
0
1
8
1
8
1
S
SLAVE ADDRESS
A
REGISTER POINTER X
A
DATA X
A
α
α
R/nW
NUMBER
OF BITS
8
1
8
1
REGISTER POINTER N
A
DATA N
A
NUMBER
OF BITS
8
1
8
1
1
REGISTER POINTER Z
A
DATA Z
A
P
β
THE DATA IS LOADED INTO THE
TARGET REGISTER AND BECOMES
ACTIVE DURING THIS RISING EDGE.
SDA
SCL
B1
7
B0
8
A
9
B9
ACKNOWLEDGE
1
DETAIL: α
THE DATA IS LOADED INTO THE
TARGET REGISTER AND BECOMES
ACTIVE DURING THIS RISING EDGE.
SDA
SCL
B1
7
B0
8
A
9
ACKNOWLEDGE
DETAIL: β
Figure 9. Writing to Multiple Registers with Multiple Byte Register Data Pairs Protocol
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MAX77812
20A User-Configurable
Quad-Phase Buck Converter
nal the slave that it wants more data. When the master has
all the data it requires, it issues a NOT ACKNOWLEDGE
(nA) and a STOP (P) to end the transmission.
Reading from a Single Register
2
I CmasterdevicereadsonebyteofdatatotheMAX77812.
This protocol is the same as SMBus specification’s read
byte protocol.
The continuous read from sequential registers protocol is
as follows:
The read byte protocol is as follows:
1) The master sends a START command (S).
1) The master sends a START command (S).
2) The master sends the 7-bit slave address followed
2) The master sends the 7-bit slave address followed
by a write bit (R/W = 0).
by a write bit (R/W = 0).
3) The addressed slave asserts an ACKNOWLEDGE
(A) by pulling SDA low.
3) The addressed slave asserts an ACKNOWLEDGE
(A) by pulling SDA low.
4) The master sends an 8-bit register pointer.
5) The slave acknowledges the register pointer.
4) The master sends an 8-bit register pointer.
5) The slave acknowledges the register pointer.
6) The master sends a REPEATED START command
(Sr).
6) The master sends a REPEATED START command
(Sr).
7) The master sends the 7-bit slave address followed
7) The master sends the 7-bit slave address followed
by a read bit (R/W = 1).
by a read bit (R/W = 1).
8) The addressed slave asserts an ACKNOWLEDGE
(A) by pulling SDA low.
8) The addressed slave asserts an ACKNOWLEDGE
(A) by pulling SDA low.
9) The addressed slave places 8 bits of data on the bus
9) The addressed slave places 8-bits of data on the bus
from the location specified by the register pointer.
from the location specified by the register pointer.
10) The master issues an ACKNOWLEDGE (A) signaling
the slave that it wishes to receive more data.
10) The master issues a NOT ACKNOWLEDGE (nA).
11) The master sends a STOP condition (P) or a
REPEATED START condition (Sr). Issuing a P
ensures that the bus. input filters are set for 1MHz or
slower operation. Issuing a REPEATED START (Sr)
leaves the bus input filters in their current state.
11) Steps 9 to 10 are repeated as many times as the
master requires. Following the last byte of data, the
master must issue a NOT ACKNOWLEDGE (nA) to
signal that it wishes to stop receiving data.
12) The master sends a STOP condition (P) or a
REPEATED START condition (Sr). Issuing a STOP
(P) ensures that the bus input filters are set for 1MHz
or slower operation. Issuing a REPEATED START
(Sr) leaves the bus input filters in their current state.
Note that every time the MAX77812 receives a STOP,
its register pointer is set to 0x00. If reading register 0x00
after a STOP has been issued, steps 1 to 6 in the above
algorithm can be skipped.
Reading from Sequential Registers
Note that every time the MAX77812 receives a STOP its
register pointer is set to 0x00. If reading register 0x00
after a STOP has been issued, steps 1 to 6 in the above
algorithm can be skipped.
Figure 10 shows the protocol for reading from sequential
registers. This protocol is similar to the read byte protocol
except the master issues an ACKNOWLEDGE (A) to sig-
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MAX77812
20A User-Configurable
Quad-Phase Buck Converter
2
The MAX77812 I C supports the HS mode extension
Engaging HS Mode for Operation Up to 3.4MHz
feature. The HS extension feature keeps the high-speed
operation even after STOP condition. This eliminates
Figure 11 shows the protocol for engaging HS mode
operation. HS mode operation allows for a bus operating
speed up to 3.4MHz.
2
the needs of HS master code issued by the I C master
2
controller when the I C master controller wants to stay in
The engaging HS mode protocol is as follows:
HS mode for multiple read/write cycles.
1) Begin the protocol while operating at a bus speed of
1MHz or lower.
As shown in the state diagram, the HS extension mode
can be enabled by setting HS_EXT bit in I C_CFG regis-
ter (ADDR 0x15) from LS mode only (entering HS exten-
sion mode from HS mode is not supported).
2
2) The master sends a START command (S).
3) The master sends the 8-bit master code of
00001xxxb where xxxb are don’t care bits.
SPI Slave Controller
4) The addressed slave issues a NOT
ACKNOWLEDGE (nA).
The serial interface includes a SPI slave controller and
2
the selection between I C and SPI slave controller is
5) The master can now increase its bus speed up to
3.4MHz and issue any read/write operation.
2
done by I C_SPI_SEL input pin. The SPI slave controller
requires a reset every time before the SPI master control-
ler starts a new frame. This can be done by setting SCS
(SPI chip select, active low) input high for more than 50ns.
When SCS is held high, the MISO output is in a high-
impedance state.
The master can continue to issue high-speed read/write
operations until a STOP (P) is issued. Issuing a STOP
(P) ensures that the bus input filters are set for 1MHz or
slower operation.
LEGEND
*P FORCES THE BUS FILTERS TO SWITCH TO THEIR ≤ 1MHz MODE.
Sr LEAVES THE BUS FILTERS IN THEIR CURRENT STATE.
MASTER TO
SLAVE
SLAVE TO
MASTER
NUMBER
OF BITS
1
7
1
0
1
8
1
1
7
1
1
1
8
1
S
SLAVE ADDRESS
A
REGISTER POINTER X A Sr SLAVE ADDRESS
A
DATA X
A
R/nW
R/W
NUMBER
OF BITS
8
1
8
1
8
1
DATA X+1
A
DATA X+2
A
DATA X+3
A
REGISTER POINTER = X + 2 REGISTER POINTER = X + 3
REGISTER POINTER = X + 1
NUMBER
OF BITS
8
1
8
1
8
1
1
P OR Sr*
DATA N-2
A
DATA N-1
A
DATA N
nA
REGISTER POINTER =
X + (N-2)
REGISTER POINTER =
X + (N-3)
Figure 10. Reading Continuously from Sequential Registers “X” to “N”
LEGEND
MASTER TO SLAVE
SLAVE TO MASTER
1
8
1
1
ANY READ/WRITE PROTOCOL
FOLLOWED BY Sr
ANY READ/WRITE PROTOCOL
FOLLOWED BY Sr
ANY READ/WRITE PROTOCOL
S
HS MASTER CODE
nA Sr
Sr
Sr
P
FAST MODE
HS MODE
FAST MODE
Figure 11. Engaging HS Mode
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MAX77812
20A User-Configurable
Quad-Phase Buck Converter
Features
General Description
The SPI slave controller has following features:
The SPI slave controller works with CKPOL = 0, CKPHA
= 0 setting in the SPI master controller. In other words,
idle state of SCL is low and the SPI controller samples
data in the rising edge of SCL. Besides single read/write
cycle, the SPI salve controller also supports multiple read/
write cycles.
●
●
●
●
Slave Only
Single Read/Write Support
Multiple Read/Write Support
Up to 30MHz (26MHz typ)
Figure 13, Figure 14, and Figure 15 show single and
multiple read/write frame structures.
HS MASTER
CODE
LS MODE
HS MODE
(HS_EXT = 0)
(HS_EXT = 0)
STOP
CONDITION
SET HS_EXT = 0
SET HS_EXT = 1
SET HS_EXT = 0
LS MODE
HS MODE
(HS_EXT = 1)
(HS_EXT = 1)
HS MASTER
CODE
2
Figure 12. I C Operating Mode State Diagram
SCS
···
···
···
···
t
SP_MOSI
t
t
SCS_H(MIN)
HD_SCS
t
SU_SCS
SCLK
MOSI
MISO
MSB
LSB
t
HD_MOSI
MSB
LSB
t
D_MISO
Figure 13. SPI Timing Diagram
LEGEND
MASTER TO
SLAVE
SLAVE TO
MASTER
1
0
1
1
0
0
4
10
8
8
MSB
MSB
MSB
RESERVED[3:0]
RESERVED[3:0]
READ
ADDR[9:0]
ADDR[9:0]
PACKET_LENGTH[7:0]
PACKET_LENGTH[7:0]
RDATA0[7:0] AT ADDR
WDATA0[7:0] AT ADDR
WRITE
Figure 14. SPI Single Read/Write Frame Structure
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MAX77812
20A User-Configurable
Quad-Phase Buck Converter
LEGEND
MASTER TO SLAVE
SLAVE TO MASTER
MSB
1
0
1
1
4
10
8
8
MSB
MSB
MULTIPLE READ
MULTIPLE WRITE
1 RESERVED[3:0]
1 RESERVED[3:0]
ADDR[9:0]
ADDR[9:0]
PACKET_LENGTH[7:0]
PACKET_LENGTH[7:0]
RDATA0[7:0] AT ADDR
WDATA0[7:0] AT ADDR
8
8
8
MSB
MSB
MSB
RDATA1[7:0] AT ADDR+1
WDATA1[7:0] AT ADDR+1
RDATA2[7:0] AT ADDR+2
WDATA2[7:0] AT ADDR+2
RDATA3[7:0] AT ADDR+3
WDATA3[7:0] AT ADDR+3
···
Figure 15. SPI Multiple Read/Write Frame Structure
For multiple read/write frame, PACKET_LENGTH[7:0]
bits determine the number of data bytes. The total length
of the multiple read/write frame is ‘32 + 8 x n’ bits, where
‘n’ is the packet length.
Frame Structure
Read/Write Bit (R/W)
The first bit indicates either read (0) or write (1) frame.
Single/Multiple Bit (S/M)
Data Bits (RDATA[7:0]/WDATA[7:0])
The second bit determines either single read/write frame
(0) or multiple read/write frame (1).
The SPI slave controller has 8-bit data bus. While the
slave controller is loading data onto MISO, it ignores the
data on MOSI. When MISO is inactive, it is held low by
the SPI slave controller.
Reserved Bits (RESERVED[3:0])
There are 4 reserved bits followed by read/write and
single/multiple bits. The MAX77812 SPI slave controller
ignores those bits.
Multiple Write Cycles
Figure 16 is the timing diagram of multiple write cycle.
The first data (WDATA0[7:0]) is written at ADDR[9:0] if
the address is valid. For the next data byte, the register
address automatically increases by one. The total number
of data bytes are determined by PACKET_LENGTH[7:0]
and the MAX77812 slave controller ignores the any data
bytes beyond the total number of data bytes (PACKET_
LENGTH[7:0] + 1). While the SPI master controller is
writing data onto MOSI, the SPI controller keeps MISO
to a low state.
Address Bits (ADDR[9:0])
The SPI master controller loads 10 address bits on MOSI,
however, the MAX77812 has only 8-bit address bus so
that the SPI slave controller ignores attempt to access to
overflowed addresses (beyond 0xFF).
Packet Length Bits (PACKET_LENGTH[7:0])
The length of single read/write frame is organized as
32-bit (packet length bits are ignored).
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MAX77812
20A User-Configurable
Quad-Phase Buck Converter
bytes (PACKET_LENGTH[7:0] + 1). While the SPI master
controller is writing data onto MOSI, the MAX77812 SPI
controller keeps MISO to a low state. When the SPI slave
controller loads the data on MISO, the data on MOSI are
ignored (don’t care) by the SPI slave controller.
Multiple Read Cycles
The timing diagram of multiple read cycle is shown
in Figure 17. The first data (RDATA0[7:0]) is read at
ADDR[9:0] if the address is valid. For the next data
byte, the register address automatically increases by
one. The total number of data bytes are determined by
PACKET_LENGTH[7:0] and the MAX77812 slave con-
troller stops loading data beyond the total number of data
In case the SPI master controller tries to read nonexisting
registers, the MAX77812 SPI slave controller returns zero
values (MISO = low).
SCS
1
2
3
4
5
6
7
8
14
15
16
17
23
24
25
31
32
33
39
40
SCL
MOSI
MISO
···
···
···
···
RESERVED[3:0]
ADDR[9:0]
PACKET_ LENGTH[7:0]
WDATA0[7:0]
WDATA1[7:0]
HI-Z
HI-Z
LOW
Figure 16. SPI Multiple Write Cycle
SCS
1
2
3
4
5
6
7
8
14
15
16
17
23
24
25
31
32
33
39
40
SCL
MOSI
MISO
···
···
···
···
PACKET_
LENGTH[7:0]
RESERVED[3:0]
ADDR[9:0]
DON’T CARE
HI-Z
HI-Z
RDATA0[7:0]
RDATA1[7:0]
LOW
Figure 17. SPI Multiple Read Cycle
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MAX77812
20A User-Configurable
Quad-Phase Buck Converter
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MAX77812
20A User-Configurable
Quad-Phase Buck Converter
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MAX77812
20A User-Configurable
Quad-Phase Buck Converter
REG_RESET Register Reset Control Register
ADDRESS
MODE
TYPE: O
RESET VALUE: 0x00
DESCRIPTION
0x00
W/C
BIT
NAME
POR
7:1
RESERVED
0000 000
Type-O Register Reset Control
0
SW_RST
0
1: Reset all Type-O registers to their POR default values.
This bit clears to ‘0’ upon reset.
INT_SRC Interrupt Source Register
ADDRESS
MODE
TYPE: O
RESET VALUE: 0x00
DESCRIPTION
0x01
BIT
7:2
1
R
NAME
POR
RESERVED
BUCK_INT
0000 00
0
0
1: Interrupt event on BUCK is detected
1: Interrupt event on TOPSYS is detected
0
TOPSYS_INT
INT_SRC_M Interrupt Source Mask Register
ADDRESS
MODE
TYPE: O
RESET VALUE: 0x02
DESCRIPTION
0x02
R/W
BIT
NAME
POR
7:4
RESERVED
0000 00
0: Enable BUCK_INT
1: Mask BUCK_INT
1
0
BUCK_INT_M
1
0
0: Enable TOPSYS_INT
1: Mask TOPSYS_INT
TOPSYS_INT_M
TOPSYS_INT TOPSYS Interrupt Register
ADDRESS
MODE
TYPE: S1
RESET VALUE: 0x00
DESCRIPTION
0x03
BIT
7:5
4
R/C
NAME
POR
RESERVED
WDTRSTB_INT
UVLO_INT
000
0
1: WDTRSTB interrupt has triggered.
1: UVLO interrupt has triggered.
3
0
2
TSHDN_INT
0
1: TSHDN interrupt has triggered.
1: TJCT_140C interrupt has triggered.
1: TJCT_120C interrupt has triggered.
1
TJCT_140C_INT
TJCT_120C_INT
0
0
0
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MAX77812
20A User-Configurable
Quad-Phase Buck Converter
TOPSYS_INT_M TOPSYS Interrupt Mask Register
ADDRESS
MODE
TYPE: O
RESET VALUE: 0x13
DESCRIPTION
0x04
R/W
BIT
NAME
POR
7:5
RESERVED
000
0: Enable WDTRSTB_INT.
1: Mask WDTRSTB_INT.
4
3
2
1
0
WDTRSTB_M
1
0
0
1
1
0: Enable UVLO_INT.
1: Mask UVLO_INT.
UVLO_M
TSHDN_M
0: Enable TSHDN_INT.
1: Mask TSHDN_INT.
0: Enable TJCT_140C_INT.
1: Mask TJCT_140C_INT.
TJCT_140C_M
TJCT_120C_M
0: Enable TJCT_120C_INT.
1: Mask TJCT_120C_INT.
TOPSYS_STAT TOPSYS Status Register
ADDRESS
MODE
TYPE: O
RESET VALUE: N/A
DESCRIPTION
0x05
R
BIT
NAME
POR
7:4
RESERVED
—
0: V
1: V
≥ V
< V
SYS
SYS
UVLO_F
UVLO_F
3
2
1
0
UVLO
—
—
—
—
0: Junction Temperature (T
1: Junction Temperature (T
) ≤ +165°C
) > +165°C
JCT
JCT
TSHDN
0: Junction Temperature (T
1: Junction Temperature (T CT) > +140
°C
) ≤ +140°C
JCT
TJCT_140C
TJCT_120C
J
0: Junction Temperature (T
1: Junction Temperature (T
) ≤ +120°C
) > +120°C
JCT
JCT
Maxim Integrated
│ 47
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MAX77812
20A User-Configurable
Quad-Phase Buck Converter
EN_CTRL Regulator Enable Control Register
ADDRESS
MODE
TYPE: O
RESET VALUE: 0x00
DESCRIPTION
0x06
R/W
BIT
NAME
POR
0: Disable BUCK Master 4 low power mode.
1: Enable BUCK Master 4 low power mode.
7
6
5
4
3
2
1
0
EN_M4_LPM
EN_M4
0
0: Disable BUCK Master 4 output.
1: Enable BUCK Master 4 output (‘OR’ logic with GPIx input).
0
0
0
0
0
0
0
0: Disable BUCK Master 3 low power mode.
1: Enable BUCK Master 3 low power mode.
EN_M3_LPM
EN_M3
0: Disable BUCK Master 3 output.
1: Enable BUCK Master 3 output (‘OR’ logic with GPIx input).
0: Disable BUCK Master 2 low power mode.
1: Enable BUCK Master 2 low power mode.
EN_M2_LPM
EN_M2
0: Disable BUCK Master 2 output.
1: Enable BUCK Master 2 output (‘OR’ logic with GPIx input).
0: Disable BUCK Master 1 low power mode.
1: Enable BUCK Master 1 low power mode.
EN_M1_LPM
EN_M1
0: Disable BUCK Master 1 output.
1: Enable BUCK Master 1 output (‘OR’ logic with GPIx input).
STUP_DLY1 Global Startup Delay Setting Register 1
ADDRESS
MODE
TYPE: O (OTP)
RESET VALUE: 0x00
DESCRIPTION
0x07
R/W
BIT
NAME
POR
0
Delay Time Step Selection
0: 1ms
1: 2ms
7
DLY_STEP
6:5
RESERVED
00
BUCK Master 2 Startup Delay Time Setting (Delay from Rising Edge
of EN Pin or GLB_EN)
0 0000b = 0ms
0 0001b = 1 x DLY_STEP
0 0010b = 2 x DLY_STEP
4:0
M2_STUP_DLY[4:0]
0 0000
·
·
·
·
·
·
1 1110b = 30 x DLY_STEP
1 1111b = 31 x DLY_STEP
Maxim Integrated
│ 48
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MAX77812
20A User-Configurable
Quad-Phase Buck Converter
STUP_DLY2 Global Startup Delay Setting Register 2
ADDRESS
MODE
TYPE: O (OTP)
RESET VALUE: 0x00
DESCRIPTION
0x08
R/W
BIT
NAME
POR
7:5
RESERVED
000
BUCK Master 3 Startup Delay Time Setting (Delay from Rising Edge
of EN Pin or GLB_EN)
0 0000b = 0ms
0 0001b = 1 x DLY_STEP
0 0010b = 2 x DLY_STEP
4:0
M3_STUP_DLY[4:0]
0 0000
·
·
·
·
·
·
1 1110b = 30 x DLY_STEP
1 1111b = 31 x DLY_STEP
STUP_DLY3 Global Startup Delay Setting Register 3
ADDRESS
MODE
TYPE: O (OTP)
RESET VALUE: 0x00
DESCRIPTION
0x09
R/W
BIT
NAME
POR
7:5
RESERVED
000
BUCK Master 4 Startup Delay Time Setting (Delay from Rising Edge
of EN Pin or GLB_EN)
0 0000b = 0ms
0 0001b = 1 x DLY_STEP
0 0010b = 2 x DLY_STEP
4:0
M4_STUP_DLY[4:0]
0 0000
·
·
·
·
·
·
1 1110b = 30 x DLY_STEP
1 1111b = 31 x DLY_STEP
SHDN_DLY1 Global Shutdown Delay Setting Register 1
ADDRESS
0x0A
BIT
MODE
TYPE: O
RESET VALUE: 0x00
DESCRIPTION
R/W
NAME
POR
7:5
RESERVED
000
BUCK Master 1 Shutdown Delay Time Setting (Delay from Falling
Edge of EN Pin or GLB_EN)
0 0000b = 0ms
0 0001b = 1 x DLY_STEP
0 0010b = 2 x DLY_STEP
4:0
M1_SHDN_DLY[4:0]
0 0000
·
·
·
·
·
·
1 1110b = 30 x DLY_STEP
1 1111b = 31 x DLY_STEP
Maxim Integrated
│ 49
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MAX77812
20A User-Configurable
Quad-Phase Buck Converter
SHDN_DLY2 Global Shutdown Delay Setting Register 2
ADDRESS
0x0B
BIT
MODE
TYPE: O
RESET VALUE: 0x00
DESCRIPTION
R/W
NAME
POR
7:5
RESERVED
000
BUCK Master 2 Shutdown Delay Time Setting (Delay from Falling
Edge of EN Pin or GLB_EN)
0 0000b = 0ms
0 0001b = 1 x DLY_STEP
0 0010b = 2 x DLY_STEP
4:0
M2_SHDN_DLY[4:0]
0 0000
·
·
·
·
·
·
1 1110b = 30 x DLY_STEP
1 1111b = 31 x DLY_STEP
SHDN_DLY3 Global Shutdown Delay Setting Register 3
ADDRESS
0x0C
BIT
MODE
TYPE: O
RESET VALUE: 0x00
DESCRIPTION
R/W
NAME
POR
7:5
RESERVED
000
BUCK Master 3 Shutdown Delay Time Setting (Delay from Falling
Edge of EN Pin or GLB_EN)
0 0000b = 0ms
0 0001b = 1 x DLY_STEP
0 0010b = 2 x DLY_STEP
4:0
M3_SHDN_DLY[4:0]
0 0000
·
·
·
·
·
·
1 1110b = 30 x DLY_STEP
1 1111b = 31 x DLY_STEP
SHDN_DLY4 Global Shutdown Delay Setting Register 4
ADDRESS
0x0D
BIT
MODE
TYPE: O
RESET VALUE: 0x00
DESCRIPTION
R/W
NAME
POR
7:5
RESERVED
000
BUCK Master 4 Shutdown Delay Time Setting (Delay from Falling
Edge of EN Pin or GLB_EN)
0 0000b = 0ms
0 0001b = 1 x DLY_STEP
0 0010b = 2 x DLY_STEP
4:0
M4_SHDN_DLY[4:0]
0 0000
·
·
·
·
·
·
1 1110b = 30 x DLY_STEP
1 1111b = 31 x DLY_STEP
Maxim Integrated
│ 50
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MAX77812
20A User-Configurable
Quad-Phase Buck Converter
WDTRSTB_DEB WDTRSTB_IN Input Debounce Time Setting Register
ADDRESS
0x0E
BIT
MODE
TYPE: O
RESET VALUE: 0x02
DESCRIPTION
R/W
NAME
POR
7:3
RESERVED
0000 0
WDTRSTB_IN Debounce Time Setting
000b = 0ms
001b = 0.8ms
010b = 1.6ms
011b = 3.2ms
2:0
WDT_DEB[2:0]
010
100b = 6.4ms
101b = 12.8ms
111b = 51.2ms
GPI_FUNC GPI Function Selection Register
ADDRESS
MODE
TYPE: O
RESET VALUE: 0x43
DESCRIPTION
0x0F
R/W
BIT
NAME
POR
GPI1 Function Selection
0000b: GLB_EN
0001b: M1_EN
0010b: M2_EN
0011b: M3_EN
0100b: M4_EN
1000b: M3_VSEL
1001b: M4_VSEL
1010b: GLB_LPM
1011b: M1_LPM
1100b: M2_LPM
7:4
GPI1_FUNC[3:0]
0100
0101b: GLB_VSEL 1101b: M3_LPM
0110b: M1_VSEL
0111b: M2_VSEL
1110b: M4_LPM
1111b: No Function
GPI0 Function Selection
0000b: GLB_EN
0001b: M1_EN
0010b: M2_EN
0011b: M3_EN
0100b: M4_EN
1000b: M3_VSEL
1001b: M4_VSEL
1010b: GLB_LPM
1011b: M1_LPM
1100b: M2_LPM
3:0
GPI0_FUNC[3:0]
0011
0101b: GLB_VSEL 1101b: M3_LPM
0110b: M1_VSEL
0111b: M2_VSEL
1110b: M4_LPM
1111b: No Function
Maxim Integrated
│ 51
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MAX77812
20A User-Configurable
Quad-Phase Buck Converter
GPI_DEB1 GPI Debounce Time Setting Register 1
ADDRESS
MODE
TYPE: O
RESET VALUE: 0x11
DESCRIPTION
0x10
R/W
BIT
NAME
POR
LPM Debounce Time Setting
0000b = 0µs
1000b = 512µs
0001b = 64µs
0010b = 128µs
0011b = 192µs
0100b = 256µs
0101b = 320µs
0110b = 384µs
0111b = 448µs
1001b = 576µs
1010b = 640µs
1011b = 704µs
1100b = 768µs
1101b = 832µs
1110b = 896µs
1111b = 960µs
7:4
LPM_DEB[3:0]
0001
EN Debounce Time Setting
0000b = 0µs
1000b = 512µs
0001b = 64µs
0010b = 128µs
0011b = 192µs
0100b = 256µs
0101b = 320µs
0110b = 384µs
0111b = 448µs
1001b = 576µs
1010b = 640µs
1011b = 704µs
1100b = 768µs
1101b = 832µs
1110b = 896µs
1111b = 960µs
3:0
EN_DEB[3:0]
0001
GPI_DEB2 GPI Debounce Time Setting Register 2
ADDRESS
MODE
TYPE: O
RESET VALUE: 0x11
0x11
R/W
BIT
NAME
POR
DESCRIPTION
GPI1 Debounce Time Setting
0000b = 0µs
1000b = 512µs
0001b = 64µs
0010b = 128µs
0011b = 192µs
0100b = 256µs
0101b = 320µs
0110b = 384µs
0111b = 448µs
1001b = 576µs
1010b = 640µs
1011b = 704µs
1100b = 768µs
1101b = 832µs
1110b = 896µs
1111b = 960µs
7:4
GPI1_DEB[3:0]
0001
GPI0 Debounce Time Setting
0000b = 0µs
1000b = 512µs
0001b = 64µs
0010b = 128µs
0011b = 192µs
0100b = 256µs
0101b = 320µs
0110b = 384µs
0111b = 448µs
1001b = 576µs
1010b = 640µs
1011b = 704µs
1100b = 768µs
1101b = 832µs
1110b = 896µs
1111b = 960µs
3:0
GPI0_DEB[3:0]
0001
Maxim Integrated
│ 52
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MAX77812
20A User-Configurable
Quad-Phase Buck Converter
GPI_PD_CTRL GPI Pulldown Resistor Control Register
ADDRESS
MODE
TYPE: O
RESET VALUE: 0x0F
0x12
R/W
BIT
NAME
POR
DESCRIPTION
7:4
RESERVED
0000
LPM Input Pulldown Resistor Enable Setting
3
2
1
0
LPM_PD
1
1
1
1
0: Disable
1: Enable
EN Input Pulldown Resistor Enable Setting
0: Disable
1: Enable
EN_PD
GPI1_PD
GPI0_PD
GPI1 Input Pulldown Resistor Enable Setting
0: Disable
1: Enable
GPI0 Input Pulldown Resistor Enable Setting
0: Disable
1: Enable
PROT_CFG Protection Configuration Register
ADDRESS
MODE
TYPE: O
RESET VALUE: 0x82
0x13
R/W
BIT
NAME
POR
1
DESCRIPTION
Thermal Protection Enable Control
0: Disable (TSHDN_INT is not disabled)
1: Enable
7
TSHDN_EN
RESERVED
6:3
000 0
V
UVLO Falling Threshold
SYS
000b = 1.95V
001b = 2.05V
010b = 2.15V
011b = 2.25V
100b = 2.35V
101b = 2.45V
110b = 2.55V
111b = Disabled
2:0
UVLO_F[2:0]
010
0x14: RESERVED
Maxim Integrated
│ 53
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MAX77812
20A User-Configurable
Quad-Phase Buck Converter
2
I2C_CFG I C Configuration Register
ADDRESS
0x15
BIT
MODE
TYPE: O
RESET VALUE: 0x00
DESCRIPTION
R/W
NAME
POR
NA
7:4
RESERVED
RESERVED
3:2
00
Write ‘00’
Register Data Pair Mode
1
0
PAIR
0
0
0: Disable (Sequential Mode)
1: Enable
HS Mode Extension
0: Disable HS mode extension (I C Rev. 4 Compliant).
1: Enable HS mode extension.
2
HS_EXT
(HS mode is extended during/after ‘STOP’ condition.)
0x16 – 0x1F: RESERVED
BUCK_INT Regulators Interrupt Register
ADDRESS
MODE
TYPE: S1
RESET VALUE: 0x00
DESCRIPTION
0x20
BIT
7:4
3
R/C
NAME
POR
RESERVED
M4_POK_INT
M3_POK _INT
M2_POK _INT
M1_POK _INT
0000
0
0
0
0
1: BUCK Master 4 POK interrupt has triggered.
1: BUCK Master 3 POK interrupt has triggered.
1: BUCK Master 2 POK interrupt has triggered.
1: BUCK Master 1 POK interrupt has triggered.
2
1
0
BUCK_INT_M BUCK Interrupt Mask Register
ADDRESS
MODE
TYPE: O
RESET VALUE: 0x0F
DESCRIPTION
0x21
R/W
BIT
NAME
POR
7:4
RESERVED
0000
0: Enable M4_POK _INT.
1: Mask M4_POK _INT.
3
2
1
0
M4_POK _M
1
1
1
1
0: Enable M3_ POK_INT.
1: Mask M3_POK_INT.
M3_POK_M
M2_POK_M
M1_POK_M
0: Enable M2_ POK_INT.
1: Mask M2_POK_INT.
0: Enable M1_POK_INT.
1: Mask M1_POK_INT.
Maxim Integrated
│ 54
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MAX77812
20A User-Configurable
Quad-Phase Buck Converter
BUCK_STAT BUCK Status Register
ADDRESS
MODE
TYPE: O
RESET VALUE: N/A
0x22
BIT
7:4
3
R
NAME
POR
DESCRIPTION
RESERVED
M4_POK
M3_POK
M2_POK
M1_POK
0000
0
0
0
0
BUCK Master 4 POK Status
BUCK Master 3 POK Status
BUCK Master 2 POK Status
BUCK Master 1 POK Status
2
1
0
M1_VOUT BUCK Master1 Output Voltage Setting Register
ADDRESS
MODE
TYPE: O
(OTP)
RESET VALUE: 0x50
RESET VALUE: 0x50
RESET VALUE: 0x46
RESET VALUE: 0x46
0x23
R/W
BIT
NAME
M1_VOUT[7:0]
POR
DESCRIPTION
BUCK Master 1 Output Voltage
7:0
01010000
M2_VOUT BUCK Master 2 Output Voltage Setting Register
ADDRESS
MODE
TYPE: O
(OTP)
0x24
R/W
BIT
NAME
M2_VOUT[7:0]
POR
DESCRIPTION
BUCK Master 2 Output Voltage
7:0
01010000
M3_VOUT BUCK Master 3 Output Voltage Setting Register
ADDRESS
MODE
TYPE: O
(OTP)
0x25
R/W
BIT
NAME
M3_VOUT[7:0]
POR
DESCRIPTION
BUCK Master 3 Output Voltage
7:0
01000110
M4_VOUT BUCK Master 4 Output Voltage Setting Register
ADDRESS
MODE
TYPE: O
(OTP)
0x26
R/W
BIT
NAME
M4_VOUT[7:0]
POR
DESCRIPTION
BUCK Master 4 Output Voltage
7:0
01000110
Maxim Integrated
│ 55
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MAX77812
20A User-Configurable
Quad-Phase Buck Converter
M1_VOUT_D BUCK Master 1 Default Output Voltage Setting Register
ADDRESS
MODE
TYPE: O
RESET VALUE: 0x78
0x27
R/W
BIT
NAME
POR
DESCRIPTION
Buck Master 1 Default Output Voltage. Sets the output voltage when
DVS = 1 through a GPI.
7:0
M1_VOUT_D[7:0]
0111 1000
M2_VOUT_D BUCK Master 2 Default Output Voltage Setting Register
ADDRESS
MODE
TYPE: O
RESET VALUE: 0x78
0x28
R/W
BIT
NAME
POR
DESCRIPTION
Buck Master 2 Default Output Voltage. Sets the output voltage when
DVS = 1 through a GPI.
7:0
M2_VOUT_D[7:0]
0111 1000
M3_VOUT_D BUCK Master 3 Default Output Voltage Setting Register
ADDRESS
MODE
TYPE: O
RESET VALUE: 0x78
0x29
R/W
BIT
NAME
POR
DESCRIPTION
Buck Master 3 Default Output Voltage. Sets the output voltage when
DVS = 1 through a GPI.
7:0
M3_VOUT_D[7:0]
0111 1000
M4_VOUT_D BUCK Master 4 Default Output Voltage Setting Register
ADDRESS
MODE
TYPE: O
RESET VALUE: 0x78
0x2A
R/W
BIT
NAME
POR
DESCRIPTION
Buck Master 4 Default Output Voltage. Sets the output voltage when
DVS = 1 through a GPI.
7:0
M4_VOUT_D[7:0]
0111 1000
M1_VOUT_S BUCK Master1 Sleep Mode Output Voltage Setting Register
ADDRESS
MODE
TYPE: O
RESET VALUE: 0x1E
0x2B
R/W
BIT
NAME
POR
DESCRIPTION
Buck Master 1 Sleep Mode Output Voltage. Sets the output voltage
when DVS = 0 through a GPI.
7:0
M1_VOUT_S[7:0]
0001 1110
M2_VOUT_S BUCK Master 2 Sleep Mode Output Voltage Setting Register
ADDRESS
MODE
TYPE: O
RESET VALUE: 0x1E
0x2C
R/W
BIT
NAME
POR
DESCRIPTION
Buck Master 2 Sleep Mode Output Voltage. Sets the output voltage
when DVS = 0 through a GPI.
7:0
M2_VOUT_S[7:0]
0001 1110
Maxim Integrated
│ 56
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MAX77812
20A User-Configurable
Quad-Phase Buck Converter
M3_VOUT_S BUCK Master 3 Sleep Mode Output Voltage Setting Register
ADDRESS
MODE
TYPE: O
RESET VALUE: 0x1E
0x2D
R/W
BIT
NAME
POR
DESCRIPTION
Buck Master 3 Sleep Mode Output Voltage. Sets the output voltage
when DVS = 0 through a GPI.
7:0
M3_VOUT_S[7:0]
0001 1110
M4_VOUT_S BUCK Master 4 Sleep Mode Output Voltage Setting Register
ADDRESS
MODE
TYPE: O
RESET VALUE: 0x1E
0x2E
R/W
BIT
NAME
POR
DESCRIPTION
Buck Master 4 Sleep Mode Output Voltage. Sets the output voltage
when DVS = 0 through a GPI.
7:0
M4_VOUT_S[7:0]
0001 1110
Buck Output Voltage Table
0x00 =
0x20 =
0x40 =
0x60 =
0x80 =
0xA0 =
0xC0 =
0xE0 =
0.25000V
0.41000V
0.57000V
0.73000V
0.89000V
1.05000V
1.21000V
1.37000V
0x01 =
0x21 =
0x41 =
0x61 =
0x81 =
0xA1 =
0xC1 =
0xE1 =
0.25500V
0.41500V
0.57500V
0.73500V
0.89500V
1.05500V
1.21500V
1.37500V
0x02 =
0x22 =
0x42 =
0x62 =
0x82 =
0xA2 =
0xC2 =
0xE2 =
0.26000V
0.42000V
0.58000V
0.74000V
0.90000V
1.06000V
1.22000V
1.38000V
0x03 =
0x23 =
0x43 =
0x63 =
0x83 =
0xA3 =
0xC3 =
0xE3 =
0.26500V
0.42500V
0.58500V
0.74500V
0.90500V
1.06500V
1.22500V
1.38500V
0x04 =
0x24 =
0x44 =
0x64 =
0x84 =
0xA4 =
0xC4 =
0xE4 =
0.27000V
0.43000V
0.59000V
0.75000V
0.91000V
1.07000V
1.23000V
1.39000V
0x05 =
0x25 =
0x45 =
0x65 =
0x85 =
0xA5 =
0xC5 =
0xE5 =
0.27500V
0.43500V
0.59500V
0.75500V
0.91500V
1.07500V
1.23500V
1.39500V
0x06 =
0x26 =
0x46 =
0x66 =
0x86 =
0xA6 =
0xC6 =
0xE6 =
0.28000V
0.44000V
0.60000V
0.76000V
0.92000V
1.08000V
1.24000V
1.40000V
0x07 =
0x27 =
0x47 =
0x67 =
0x87 =
0xA7 =
0xC7 =
0xE7 =
0.28500V
0.44500V
0.60500V
0.76500V
0.92500V
1.08500V
1.24500V
1.40500V
0x08 =
0x28 =
0x48 =
0x68 =
0x88 =
0xA8 =
0xC8 =
0xE8 =
0.29000V
0.45000V
0.61000V
0.77000V
0.93000V
1.09000V
1.25000V
1.41000V
0x09 =
0x29 =
0x49 =
0x69 =
0x89 =
0xA9 =
0xC9 =
0xE9 =
0.29500V
0.45500V
0.61500V
0.77500V
0.93500V
1.09500V
1.25500V
1.41500V
0x0A =
0x2A =
0x4A =
0x6A =
0x8A =
0xAA =
0xCA =
0xEA =
0.30000V
0.46000V
0.62000V
0.78000V
0.94000V
1.10000V
1.26000V
1.42000V
0x0B =
0x2B =
0x4B =
0x6B =
0x8B =
0xAB =
0xCB =
0xEB =
0.30500V
0.46500V
0.62500V
0.78500V
0.94500V
1.10500V
1.26500V
1.42500V
0x0C =
0x2C =
0x4C =
0x6C =
0x8C =
0xAC =
0xCC =
0xEC =
0.31000V
0.47000V
0.63000V
0.79000V
0.95000V
1.11000V
1.27000V
1.43000V
0x0D =
0x2D =
0x4D =
0x6D =
0x8D =
0xAD =
0xCD =
0xED =
0.31500V
0.47500V
0.63500V
0.79500V
0.95500V
1.11500V
1.27500V
1.43500V
Maxim Integrated
│ 57
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MAX77812
20A User-Configurable
Quad-Phase Buck Converter
Buck Output Voltage Table (continued)
0x0E =
0x2E =
0x4E =
0x6E =
0x8E =
0xAE =
0xCE =
0xEE =
0.32000V
0.48000V
0.64000V
0.80000V
0.96000V
1.12000V
1.28000V
1.44000V
0x0F =
0x2F =
0x4F =
0x6F =
0x8F =
0xAF =
0xCF =
0xEF =
0.32500V
0.48500V
0.64500V
0.80500V
0.96500V
1.12500V
1.28500V
1.44500V
0x10 =
0x30 =
0x50 =
0x70 =
0x90 =
0xB0 =
0xD0 =
0xF0 =
0.33000V
0.49000V
0.65000V
0.81000V
0.97000V
1.13000V
1.29000V
1.45000V
0x11 =
0x31 =
0x51 =
0x71 =
0x91 =
0xB1 =
0xD1 =
0xF1 =
0.33500V
0.49500V
0.65500V
0.81500V
0.97500V
1.13500V
1.29500V
1.45500V
0x12 =
0x32 =
0x52 =
0x72 =
0x92 =
0xB2 =
0xD2 =
0xF2 =
0.34000V
0.50000V
0.66000V
0.82000V
0.98000V
1.14000V
1.30000V
1.46000V
0x13 =
0x33 =
0x53 =
0x73 =
0x93 =
0xB3 =
0xD3 =
0xF3 =
0.34500V
0.50500V
0.66500V
0.82500V
0.98500V
1.14500V
1.30500V
1.46500V
0x14 =
0x34 =
0x54 =
0x74 =
0x94 =
0xB4 =
0xD4 =
0xF4 =
0.35000V
0.51000V
0.67000V
0.83000V
0.99000V
1.15000V
1.31000V
1.47000V
0x15 =
0x35 =
0x55 =
0x75 =
0x95 =
0xB5 =
0xD5 =
0xF5 =
0.35500V
0.51500V
0.67500V
0.83500V
0.99500V
1.15500V
1.31500V
1.47500V
0x16 =
0x36 =
0x56 =
0x76 =
0x96 =
0xB6 =
0xD6 =
0xF6 =
0.36000V
0.52000V
0.68000V
0.84000V
1.00000V
1.16000V
1.32000V
1.48000V
0x17 =
0x37 =
0x57 =
0x77 =
0x97 =
0xB7 =
0xD7 =
0xF7 =
0.36500V
0.52500V
0.68500V
0.84500V
1.00500V
1.16500V
1.32500V
1.48500V
0x18 =
0x38 =
0x58 =
0x78 =
0x98 =
0xB8 =
0xD8 =
0xF8 =
0.37000V
0.53000V
0.69000V
0.85000V
1.01000V
1.17000V
1.33000V
1.49000V
0x19 =
0x39 =
0x59 =
0x79 =
0x99 =
0xB9 =
0xD9 =
0xF9 =
0.37500V
0.53500V
0.69500V
0.85500V
1.01500V
1.17500V
1.33500V
1.49500V
0x1A =
0x3A =
0x5A =
0x7A =
0x9A =
0xBA =
0xDA =
0xFA =
0.38000V
0.54000V
0.70000V
0.86000V
1.02000V
1.18000V
1.34000V
1.50000V
0x1B =
0x3B =
0x5B =
0x7B =
0x9B =
0xBB =
0xDB =
0xFB =
0.38500V
0.54500V
0.70500V
0.86500V
1.02500V
1.18500V
1.34500V
1.50500V
0x1C =
0x3C =
0x5C =
0x7C =
0x9C =
0xBC =
0xDC =
0xFC =
0.39000V
0.55000V
0.71000V
0.87000V
1.03000V
1.19000V
1.35000V
1.51000V
0x1D =
0x3D =
0x5D =
0x7D =
0x9D =
0xBD =
0xDD =
0xFD =
0.39500V
0.55500V
0.71500V
0.87500V
1.03500V
1.19500V
1.35500V
1.51500V
0x1E =
0x3E =
0x5E =
0x7E =
0x9E =
0xBE =
0xDE =
0xFE =
0.40000V
0.56000V
0.72000V
0.88000V
1.04000V
1.20000V
1.36000V
1.52000V
0x1F =
0x3F =
0x5F =
0x7F =
0x9F =
0xBF =
0xDF =
0xFF =
0.40500V
0.56500V
0.72500V
0.88500V
1.04500V
1.20500V
1.36500V
1.52500V
Maxim Integrated
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MAX77812
20A User-Configurable
Quad-Phase Buck Converter
M1_CFG BUCK Master 1 Configuration Register
ADDRESS
MODE
TYPE: O
RESET VALUE: 0xD1
DESCRIPTION
0x2F
R/W
BIT
NAME
POR
BUCK Master 1 Output Active Discharge
7
M1_AD
1
0: Disable
1: Enable
BUCK Master 1 PMOS Peak/NMOS Valley Current Limit Setting
000b: 3.0A/2.0A
001b: 3.6A/2.4A
010b: 4.2A/2.8A
011b: 4.8A/3.2A
100b: 5.4A/3.6A
101b: 6.0A/4.0A
110b: 6.6A/4.4A
111b: 7.2A/4.8A
6:4
M1_ILIM[2:0]
101
2:3
1
RESERVED
M1_FPWM
00
0
Write ‘00’
BUCK Master 1 Forced PWM
0: Turn off Forced PWM
(Automatic skip mode operation under light load)
1: Turn on Forced PWM mode
BUCK Master 1 Falling Slew Rate Control
0: Disable
BUCK Master 1 operates in skip mode during the output voltage ramp-
down (only if M1_FPWM = 0). In skip mode, negative current through
the low-side FET is not allowed so that the output voltage falling slew
rate is a function of the output capacitance and the external load under
light load condition. If the load is heavy, the output voltage falling slew
rate is limited to the ramp-down slew rate set by B_RD_SR[1:0]. Note
that the internal feedback string always imposes a 2µA load on the
output.
0
M1_FSREN
1
1: Enable
BUCK Master 1 operates in Forced PWM mode during the output
voltage ramp-down. In Forced PWM mode, BUCK Master 1 can sink
current from the output capacitor to ensure that the output voltage
decreases at the ramp-down slew rate set by B_RD_SR[1:0]. To
ensure a smooth output voltage ramp-down, Forced PMW mode
remains engaged for 50µs after the output voltage decreases to its
target voltage.
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MAX77812
20A User-Configurable
Quad-Phase Buck Converter
M2_CFG BUCK Master 2 Configuration Register
ADDRESS
MODE
TYPE: O
RESET VALUE: 0xD1
DESCRIPTION
0x30
R/W
BIT
NAME
POR
BUCK Master 2 Output Active Discharge
7
M2_AD
1
0: Disable
1: Enable
BUCK Master 2 PMOS Peak/NMOS Valley Current Limit Setting
000b: 3.0A/2.0A
001b: 3.6A/2.4A
010b: 4.2A/2.8A
011b: 4.8A/3.2A
100b: 5.4A/3.6A
101b: 6.0A/4.0A
110b: 6.6A/4.4A
111b: 7.2A/4.8A
6:4
M2_ILIM[2:0]
101
2:3
1
RESERVED
M2_FPWM
00
0
Write ‘00’
BUCK Master 2 Forced PWM
0: Turn off Forced PWM
(Automatic skip mode operation under light load)
1: Turn on Forced PWM mode
BUCK Master 2 Falling Slew Rate Control
0: Disable
BUCK Master 2 operates in skip mode during the output voltage
ramp-down (only if M2_FPWM = 0). In skip mode, negative current
through the low-side FET is not allowed so that the output voltage
falling slew rate is a function of the output capacitance and the
external load under light load condition. If the load is heavy, the output
voltage falling slew rate is limited to the ramp-down slew rate set by
B_RD_SR[1:0]. Note that the internal feedback string always imposes
a 2µA load on the output.
0
M2_FSREN
1
1: Enable
BUCK Master 2 operates in Forced PWM mode during the output
voltage ramp-down. In Forced PWM mode, BUCK Master 2 can sink
current from the output capacitor to ensure that the output voltage
decreases at the ramp-down slew rate set by B_RD_SR[1:0]. To
ensure a smooth output voltage ramp-down, Forced PMW mode
remains engaged for 50µs after the output voltage decreases to its
target voltage.
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MAX77812
20A User-Configurable
Quad-Phase Buck Converter
M3_CFG BUCK Master 3 Configuration Register
ADDRESS
MODE
TYPE: O
RESET VALUE: 0xD1
DESCRIPTION
0x31
R/W
BIT
NAME
POR
BUCK Master 3 Output Active Discharge
7
M3_AD
1
0: Disable
1: Enable
BUCK Master 3 PMOS Peak/NMOS Valley Current Limit Setting
000b: 3.0A/2.0A
001b: 3.6A/2.4A
010b: 4.2A/2.8A
011b: 4.8A/3.2A
100b: 5.4A/3.6A
101b: 6.0A/4.0A
110b: 6.6A/4.4A
111b: 7.2A/4.8A
6:4
M3_ILIM[2:0]
101
2:3
1
RESERVED
M3_FPWM
00
0
Write ‘00’
BUCK Master 3 Forced PWM
0: Turn off Forced PWM
(Automatic skip mode operation under light load)
1: Turn on Forced PWM mode
BUCK Master 3 Falling Slew Rate Control
0: Disable
BUCK Master 3 operates in skip mode during the output voltage
ramp-down (only if M3_FPWM = 0). In skip mode, negative current
through the low-side FET is not allowed so that the output voltage
falling slew rate is a function of the output capacitance and the
external load under light load condition. If the load is heavy, the output
voltage falling slew rate will be limited to the ramp-down slew rate
set by B_RD_SR[1:0]. Note that the internal feedback string always
imposes a 2µA load on the output.
0
M3_FSREN
1
1: Enable
BUCK Master 3 operates in Forced PWM mode during the output
voltage ramp-down. In Forced PWM mode, BUCK Master 3 can sink
current from the output capacitor to ensure that the output voltage
decreases at the ramp-down slew rate set by B_RD_SR[1:0]. To
ensure a smooth output voltage ramp-down, Forced PMW mode
remains engaged for 50µs after the output voltage decreases to its
target voltage.
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MAX77812
20A User-Configurable
Quad-Phase Buck Converter
M4_CFG BUCK Master 4 Configuration Register
ADDRESS
MODE
TYPE: O
RESET VALUE: 0xD1
DESCRIPTION
0x32
R/W
BIT
NAME
POR
BUCK Master 4 Output Active Discharge
7
M4_AD
1
0: Disable
1: Enable
BUCK Master 4 PMOS Peak/NMOS Valley Current Limit Setting
000b: 3.0A/2.0A
001b: 3.6A/2.4A
010b: 4.2A/2.8A
011b: 4.8A/3.2A
100b: 5.4A/3.6A
101b: 6.0A/4.0A
110b: 6.6A/4.4A
111b: 7.2A/4.8A
6:4
M4_ILIM[2:0]
101
2:3
1
RESERVED
M4_FPWM
00
0
Write ‘00’
BUCK Master4 Forced PWM
0: Turn off Forced PWM
(Automatic skip mode operation under light load)
1: Turn on Forced PWM mode
BUCK Master 4 Falling Slew Rate Control
0: Disable
BUCK Master 4 operates in skip mode during the output voltage ramp-
down (only if M4_FPWM = 0). In skip mode, negative current through
the low-side FET is not allowed so that the output voltage falling slew
rate is a function of the output capacitance and the external load under
light load condition. If the load is heavy, the output voltage falling slew
rate is limited to the ramp-down slew rate set by B_RD_SR[1:0]. Note
that the internal feedback string always imposes a 2µA load on the
output.
0
M4_FSREN
1
1: Enable
BUCK Master 4 operates in Forced PWM mode during the output
voltage ramp-down. In Forced PWM mode, BUCK Master 4 can sink
current from the output capacitor to ensure that the output voltage
decreases at the ramp-down slew rate set by B_RD_SR[1:0]. To
ensure a smooth output voltage ramp-down, Forced PMW mode
remains engaged for 50µs after the output voltage decreases to its
target voltage.
Maxim Integrated
│ 62
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MAX77812
20A User-Configurable
Quad-Phase Buck Converter
GLB_CFG1 BUCK Global Configuration Register 1
ADDRESS
MODE
TYPE: O
RESET VALUE: 0x24
DESCRIPTION
0x33
BIT
7
R/W
NAME
POR
RESERVED
B_SD_SR[2:0]
RESERVED
0
Shutdown Slew Rate
000b: 1.25mV/µs
001b: 2.5mV/µs
010b: 5mV/µs
011b: 10mV/µs
100b: 20mV/µs
101b: 40mV/µs
110b: 60mV/µs
111b: 60mV/µs
6:4
010
3
0
Soft Start Slew Rate
000b: 1.25mV/µs
001b: 2.5mV/µs
010b: 5mV/µs
0:2
B_SS_SR[2:0]
100
011b: 10mV/µs
100b: 20mV/µs
101b: 40mV/µs
110b: 60mV/µs
111b: 60mV/µs
Maxim Integrated
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MAX77812
20A User-Configurable
Quad-Phase Buck Converter
GLB_CFG2 BUCK Global Configuration Register 2
ADDRESS
MODE
TYPE: O
RESET VALUE: 0x24
DESCRIPTION
0x34
BIT
7
R/W
NAME
POR
RESERVED
B_RD_SR[2:0]
RESERVED
0
Ramp-Down Slew Rate
000b: 1.25mV/µs
001b: 2.5mV/µs
010b: 5mV/µs
011b: 10mV/µs
100b: 20mV/µs
101b: 40mV/µs
110b: 60mV/µs
111b: 60mV/µs
6:4
010
3
0
Ramp-Up Slew Rate
000b: 1.25mV/µs
001b: 2.5mV/µs
010b: 5mV/µs
0:2
B_RU_SR[2:0]
100
011b: 10mV/µs
100b: 20mV/µs
101b: 40mV/µs
110b: 60mV/µs
111b: 60mV/µs
Maxim Integrated
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MAX77812
20A User-Configurable
Quad-Phase Buck Converter
GLB_CFG3 BUCK Global Configuration Register 3
ADDRESS
MODE
TYPE: O
RESET VALUE: 0x5F
0x35
R/W
BIT
7
NAME
POR
DESCRIPTION
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
0
1
0
1
1
1
6
5
4
3
2
Positive Enhanced Transient Response Control
1
0
B_PETR_EN
B_NETR_EN
1
1
0: Disable
1: Enable
Negative Enhanced Transient Response Control
0: Disable
1: Enable
0x36 – 0xFF: RESERVED
PCB Layout Guidelines
Careful circuit board layout is critical to low-power switch-
ing losses and clean stable operation.
For more details on PCB layout recommendations for the
MAX77812, refer to Application Note 6819: MAX77812
PCB Layout Guide.
Maxim Integrated
│ 65
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MAX77812
20A User-Configurable
Quad-Phase Buck Converter
Simplified Block Diagram
SYS
IN12
V
SYS
V
SYS
1µF
DGND
AGND
SBIAS,
REF,
UVLO,
TSHDN
10µF
0.22µH
0.22µH
LX1
PGND1
MAX77812
V
OUT1
CE
22µF
VIO
V
VIO
VIO
1.5kΩ x2
SNS1P
SNS1N
0.1µF
OTPs
IRQB
SCL
LX2
PGND2
22µF
SDA/MOSI
MISO
SNS2P
SNS2N
CONSTANT
ON- TIME
MULTI- PHASE
BUCK
ON / OFF
CONTROL
AND
IN34
SCS
V
SYS
10µF
2
I C / SPI
I2C_ SPI_SEL
EN
INTERFACE
0.22µH
0.22µH
LX3
V
V
OUT2
OUT3
PGND3
22µF
22µF
LPM
SNS3P
SNS3N
WDTRSTB_IN
GPI0
GPI1
LX4
PGND4
MULTIFUNCTION
GPIs
PH_CFG0
PH_CFG1
PH_CFG2
SNS4P
SNS4N
V
SYS
Maxim Integrated
│ 66
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MAX77812
20A User-Configurable
Quad-Phase Buck Converter
Ordering Information
DEFAULT OUTPUT VOLTAGE (V)
STARTUP DELAY TIME (ms)
2
I C SLAVE
PART
M2_STUP M3_STUP M4_STUP
ADDRESS
M1_VOUT M2_VOUT M3_VOUT M4_VOUT
_DLY
_DLY
_DLY
MAX77812EWB+T
MAX77812AEWB+T
MAX77812BEWB+T
MAX77812CEWB+T
MAX77812DEWB+T
MAX77812FEWB+T
0.650
0.700
1.120
0.720
0.720
0.620
0.650
0.700
1.120
1.495
1.200
1.100
0.600
0.800
0.920
0.820
0.900
0.900
0.600
1.100
0.950
0.820
0.750
1.495
0
0
0
5
3
0
0
0
0
1
6
0
0
2
0
3
9
0
0x60–0x69
0x60–0x69
0x60–0x69
0x60–0x69
0x60–0x69
0x70–0x79
+Denotes a lead(Pb)-free/RoHS-compliant package.
T = Tape and reel.
Package Information
For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”,
“#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing
pertains to the package regardless of RoHS status.
PACKAGE TYPE
PACKAGE CODE
OUTLINE NO.
LAND PATTERN NO.
Refer to
Application Note 1891:
Wafer-Level Packaging
(WLP) and Its Applications
64 WLP
W643C3+1
21-100087
Maxim Integrated
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MAX77812
20A User-Configurable
Quad-Phase Buck Converter
Revision History
REVISION REVISION
PAGES
CHANGED
DESCRIPTION
NUMBER
DATE
0
6/16
Initial release
—
Updated Applications section, updated Benefits and Features section, updated
MIN/TYP/MAX values in the Electrical Characteristics section and changed
inductor to 220nH, DCR = 16mΩ, added Cyntec information to Table 2,
1–14, 29,
32–36, 42, 43,
49, 56, 60–66
2
1
3/17
added I C slave addresses for OTP = 1 to Table 5, updated Figures 6─9 and
communication protocols description, updated GPI_FUNC, M1_CFG, M2_CFG,
M3_CFG, M4_CFG, GLB_CFG1, GLB_CFG2 registers in the Register Map
table, updated Typical Application Circuit
1, 2, 4–6, 8, 11, 12,
14, 15, 23, 25, 26,
31, 33-38, 42, 43,
46-48, 62–64
Updated Benefits and Features section and Register Map table, fixed various
typos
2
3
4
6/17
8/17
1/18
Updated title, Benefits and Features section, and Electrical Characteristics
table, corrected label error to Output Voltage Error (%) in Typical Operating
Characteristics, corrected errors to register name and removed error statement
in HS mode in Detailed Description section, removed inductor from Table 2,
corrected error in POR bits in the GPI_PD_CTRL GPI Pulldown Resistor Control
Register table
1, 10, 14, 16, 26,
29, 30, 38, 51
Updated Applications and Benefits and Features sections, added Simplified
Block Diagram, added LX1/2/3/4 pulsed ratings, updated Electrical
Characteristics tables, updated Detailed Description section, added ALPS
220nH, removed process information
1–4, 11, 15,
26–29, 30, 31, 38,
67
Updated General Description, Benefits and Features, and Applications sections,
renamed Typical Application Circuit and moved to page 1, updated Absolute
Maximum Ratings for LXx RMS current, updated Electrical Characteristics
tables, updated Typical Operating Characteristics global conditions and TOCs,
updated Detailed Description sections, Table 1, Figure 2, Table 5, corrected
errors in Registers information, renamed Simplified Block Diagram and updated
to 2+1+1 configuration, updated Ordering Information table
1–3, 14, 16, 17,
26, 28–30, 32, 34,
35, 47–50, 59–62,
66, 67
5
5/18
Corrected typo in Electrical Characteristics table and other sections, updated
Ordering Information table
1, 13, 22, 24–43,
53, 63, 65
6
7
7/18
6/19
Updated Table 5 and Ordering Information table
32, 65
14-15, 28-29, 63
14–22
Updated Typical Operating Characteristics global conditions and TOCs,
corrected label error to Output Voltage Error (%) in Typical Operating
Characteristics, updated Output Voltage Setting section, added Enhanced
Transient Response section, and added PCB Layout Guidelines section
8
9
8/19
9/19
Updated Typical Operating Characteristics section
Maxim Integrated
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MAX77812
20A User-Configurable
Quad-Phase Buck Converter
Revision History (continued)
REVISION REVISION
PAGES
CHANGED
DESCRIPTION
NUMBER
DATE
Updated Startup and Shutdown Sequence section, Phase/Output Configurations
section, Multifunction GPIs General Description section, Register Map table,
M1_VOUT_D, M2_VOUT_D, M3_VOUT_D, M4_VOUT_D, M1_VOUT_S,
M2_VOUT_S, M3_VOUT_S, and M4_VOUT_S register descriptions, and GLB_
CFG3 BUCK Global Configuration Register 3 table; added Inductor Current Limit
section and Unused Outputs section
27–28, 31–32, 45,
56–57, 65
10
4/20
Updated Absolute Maximum Ratings section, added Recommended Operating
Conditions table, and updated global conditions in Electrical Characteristics
tables
11
12/20
1–13
For pricing, delivery, and ordering information, please visit Maxim Integrated’s online storefront at https://www.maximintegrated.com/en/storefront/storefront.html.
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses
are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits)
shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
©
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.
2020 Maxim Integrated Products, Inc.
│ 69
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