MAX754CSE_技术文档

19-0197; Rev 1; 1/95

CCFL Ba c k lig h t a n d

LCD Co n t ra s t Co n t ro lle rs

3/MAX754

_______________Ge n e ra l De s c rip t io n

____________________________Fe a t u re s

♦ Drives Backplane and Backlight

♦ 4V to 30V Battery Voltage Range

♦ Low 500µA Supply Current

The MAX753/MAX754 drive cold-cathode fluorescent

lamps (CCFLs) and provide the LCD backplane bias

(contrast) power for color or monochrome LCD panels.

These ICs are designed specifically for backlit note-

book-computer applications.

♦ Digital or Potentiometer Control of CCFL

Brightness and LCD Bias Voltage

Both the backplane bias and the CCFL supply can be

shut down independently. When both sections are shut

down, supply current drops to 25µA. The LCD contrast

and CCFL brightness can be adjusted by clocking sep-

arate digital inputs or using external potentiometers.

LCD contrast and backlight brightness settings are pre-

served in their respective counters while in shutdown.

On p owe r-up , the LCD c ontra s t c ounte r a nd CCFL

brightness counter are set to one-half scale.

♦ Negative LCD Contrast (MAX753)

♦ Positive LCD Contrast (MAX754)

♦ Independent Shutdown of Backlight and

Backplane Sections

♦ 25µA Shutdown Supply Current

The ICs are powered from a regulated 5V supply. The

magnetics are connected directly to the battery, for

maximum power efficiency.

______________Ord e rin g In fo rm a t io n

The CCFL driver uses a Royer-type resonant architec-

ture. It can provide from 100mW to 6W of power to one

or two tubes. The MAX753 provides a negative LCD

bias voltage; the MAX754 provides a positive LCD bias

voltage.

PART

TEMP. RANGE

0°C to +70°C

-40°C to +85°C

0°C to +70°C

-40°C to +85°C

PIN-PACKAGE

16 Plastic DIP

16 Narrow SO

Dice*

MAX753CPE

MAX753CSE

MAX753C/D

MAX753EPE

MAX753ESE

MAX754CPE

MAX754CSE

MAX754C/D

MAX754EPE

MAX754ESE

16 Plastic DIP

16 Narrow SO

16 Plastic DIP

16 Narrow SO

Dice*

________________________Ap p lic a t io n s

Notebook Computers

Palmtop Computers

Pen-Based Data Systems

16 Plastic DIP

16 Narrow SO

Personal Digital Assistants

Portable Data-Collection Terminals

* Contact factory for dice specifications.

__________________P in Co n fig u ra t io n

TOP VIEW

V

LFB

DD

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

LADJ

LON

CON

BATT

LX

LDRV

PGND

CDRV

CS

MAX753

MAX754

CADJ

GND

REF

CFB

CC

DIP/SO

Block Diagram located at end of data sheet.

________________________________________________________________ Maxim Integrated Products

1

Ca ll t o ll fre e 1 -8 0 0 -9 9 8 -8 8 0 0 fo r fre e s a m p le s o r lit e ra t u re .

CCFL Ba c k lig h t a n d

LCD Co n t ra s t Co n t ro lle rs

ABSOLUTE MAXIMUM RATINGS

V

DD

to GND.................................................................-0.3V, +7V

Operating Temperature Ranges

PGND to GND.....................................................................±0.3V

BATT to GND.............................................................-0.3V, +36V

LX to GND............................................................................±50V

MAX75_C_ _ ........................................................0°C to +70°C

MAX75_E_ _......................................................-40°C to +85°C

Junction Temperature ......................................................+150°C

Storage Temperature Range .............................-65°C to +160°C

Lead Temperature (soldering, 10sec) .............................+300°C

CS to GND.....................................................-0.6V, (V + 0.3V)

DD

Inputs/Outputs to GND (LADJ, CADJ, LON,

CON, REF, CFB, CC, CDRV, LDRV, LFB) .....-0.3V, (V + 0.3V)

DD

Continuous Power Dissipation (T = +70°C)

A

Plastic DIP (derate 10.53mW/°C above +70°C) ...........842mW

Narrow SO (derate 8.70mW/°C above +70°C) .............696mW

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional

operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to

absolute maximum rating conditions for extended periods may affect device reliability.

ELECTRICAL CHARACTERISTICS

3/MAX754

(V

= 5V, BATT = 15V, CON = LON = 5V, LX = GND = PGND = 0V, I

= 0mA, a ll d ig ita l inp ut le ve ls a re 0V or 5V,

REF

DD

T

A

= T

to T , unless otherwise noted.)

MAX

MIN

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

SUPPLY AND REFERENCE

BATT Input Range

4

30

5.5

1.29

0.1

15

V

DD

Supply Range

4.5

REF Output Voltage

REF Line Regulation

REF Load Regulation

No external load

4V < V < 6V

1.21

1.25

V

%/V

mV

DD

0µA < I < 100µA

5

L

LON = CON = CS = LFB = CFB =

LADJ = CADJ = 5V

V

Quiescent Current

Shutdown Current

0.5

2

mA

µA

DD

LON = CON = CS = LFB = CFB = LADJ

= CADJ = LX = BATT = 0V (Note 1)

V

DD

25

40

DIGITAL INPUTS AND DRIVER OUTPUTS

Input Low Voltage

LON, CON, CADJ, LADJ; V = 4.5V

0.8

±1

V

DD

Input High Voltage

LON, CON, CADJ, LADJ; V = 5.5V

2.4

DD

Input Leakage Current

LON, CON, CADJ, LADJ; V = 0V or 5V

IN

µA

A

Driver Sink/Source Current

LDRV = CDRV = 2V

0.5

Output high

Output low

10

7

LDRV, CDRV;

= 4.5V

Driver On-Resistance

Ω

V

DD

CCFT CONTROLLER

Zero-Crossing-Comparator Threshold Voltage (CS)

Overcurrent-Comparator Threshold Voltage (CS)

CS Input Bias Current

-10

1.2

20

1.3

-5

mV

V

CS

= 0V

µA

Minimum, CFB = 5V

Maximum, CFB = 0V

32

85

5

47

VCO Frequency

DAC Resolution

kHz

Bits

115

Guaranteed monotonic

2

_______________________________________________________________________________________

CCFL Ba c k lig h t a n d

LCD Co n t ra s t Co n t ro lle rs

3/MAX754

ELECTRICAL CHARACTERISTICS (continued)

(V

= 5V, BATT = 15V, CON = LON = 5V, LX = GND = PGND = 0V, I

= 0mA, a ll d ig ita l inp ut le ve ls a re 0V or 5V,

REF

DD

T

A

= T

to T , unless otherwise noted.)

MAX

MIN

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

At full scale (DAC code = 31)

1210

1250

1290

At preset DAC, CON = 0V, CADJ = 5V

(code = 15)

Feedback Voltage (CFB)

745

320

782

343

820

mV

At zero scale (code = 0)

365

Feedback-Amplifier Input Bias Current

Feedback-Amplifier Unity-Gain Bandwidth

Feedback-Amplifier Slew Rate

±100

nA

MHz

V/µs

1

0.4

Source current, CFB = 0V, CC = 2.5V

Sink current, CFB = 5V, CC = 2.5V

50

Feedback-Amplifier Output Current

LCD CONTROLLER

µA

200

BATT = 4V

2

0.5

35

5

Switch On-Time

µs

BATT = 16V

1.5

70

Switching Period

DAC Resolution

BATT = 4V, LX = 0V

Guaranteed monotonic

At full scale (DAC code = 63)

µs

6

Bits

1200

1240

928

1280

963

At preset DAC, LON = 0V, LADJ = 5V

(code = 31)

MAX753 Feedback Voltage (REF-LFB)

MAX754 Feedback Voltage (LFB)

893

mV

At zero scale (code = 0)

595

625

655

At full scale (DAC code = 63)

1210

1250

1290

At preset DAC, LON = 0V, LADJ = 5V

(code = 31)

905

610

938

635

971

At zero scale (code = 0)

660

LFB Input Leakage Current

BATT Input Current

±150

nA

µA

LON = CON = CS = LFB = CFB = LADJ =

CADJ = LX = 0V

12

20

LON = CON = CS = LFB = CFB = LADJ =

CADJ = 0V, LX = BATT = 15V

LX Input Current

µA

TIMING (Note 2)

Reset Pulse Width (t )

110

0

ns

R

Reset Setup Time (t

)

RS

Reset Hold Time (t

)

0

RH

CADJ, LADJ High Width (t

)

100

SH

CADJ, LADJ Low Width (t

)

SL

CADJ Low to CON Low or

LADJ Low to LON Low (t

50

ns

)

SD

Note 1: Maximum shutdown current occurs at BATT = LX = 0V.

Note 2: Timing specifications are guaranteed by design and not production tested.

_______________________________________________________________________________________

3

CCFL Ba c k lig h t a n d

LCD Co n t ra s t Co n t ro lle rs

______________________________________________________________P in De s c rip t io n

1

NAME

FUNCTION

V

DD

5V Power-Supply Input

2

LADJ

LON

CON

CADJ

GND

REF

Digital Input for LCD Backplane Bias Adjustment. See Table 1.

Digital Input to Control LCD Bias Section. See Table 1.

Digital Input to Control CCFT Section. See Table 1.

Digital Input for CCFT Brightness Adjustment. See Table 1.

Analog Ground

3

4

5

6

7

Reference Voltage Output, 1.25V

8

CFB

CC

Inverting Input for the CCFT Error Amplifier

Output of the CCFT Error Amplifier

9

3/MAX754

10

11

12

13

14

15

16

CS

Connect to V

DD

CDRV

PGND

LDRV

LX

Leave unconnected

Power Ground Connection for LDRV

Gate-Driver Output. Drives LCD backplane N-channel MOSFET.

LCD Backplane Inductor Voltage-Sense Pin. Used to sense inductor voltage for on time determination.

Battery Connection. Used to sense battery voltage for on time determination.

Voltage Feedback for the LCD Backplane Section

BATT

LFB

D7B, a nd forms a volta g e a c ros s re s is tor R8. The

_______________Th e o ry o f Op e ra t io n

MAX753’s error amplifier compares the average of this

voltage to the output of its internal DAC. Adjusting the

DAC output from zero scale to full scale (digital control)

causes the error amplifier to vary the tube current from

a minimum to a maximum. The DAC’s transfer function

is shown in Figure 2.

CCFL In ve rt e r

The MAX753/MAX754’s CCFL inverter is designed to

d rive one or two c old -c a thod e fluore s c e nt la mp s

(CCFLs) with power levels from 100mW to 6W. These

lamps commonly provide backlighting for LCD panels

in portable computers.

On power-up or after a reset, the counter sets the DAC

output to mid scale. Each rising edge of CADJ (with

CON high) decrements the DAC output. When decre-

mented beyond full scale, the counter rolls over and

sets the DAC to the maximum value. In this way, a sin-

gle pulse applied to CADJ decreases the DAC set-

point by one step, and 31 pulses increase the set-point

by one step.

Drive Requirements for CCFL Tubes

CCFL backlights require a high-voltage, adjustable AC

power source. The MAX753/MAX754 generate this AC

waveform with a self-oscillating, current-fed, parallel

resonant circuit, also known as a Royer-type oscillator.

Figure 1 shows one such circuit. The Royer oscillator is

comprised of T1, C9, the load at the secondary, Q4,

and Q5. The circuit self-oscillates at a frequency deter-

mined by the effective primary inductance and capaci-

tance. Q4 and Q5 are self-driven by the extra winding.

The current source feeding the Royer oscillator is com-

prised of L1, D5, and the MAX758A. When current from

the current source increases, so does the lamp current.

The error amplifier’s output voltage controls the peak

current output of the MAX758A. The peak switch cur-

rent is therefore controlled by the output of the error

amplifier. The lower the error amplifier’s output, the

lower the peak current. Since the current through the

current source is related to the current through the

tube, the lower the error amplifier’s output, the lower the

tube current.

The lamp current is half-wave rectified by D7A and

4

_______________________________________________________________________________________

CCFL Ba c k lig h t a n d

LCD Co n t ra s t Co n t ro lle rs

3/MAX754

+5V, ±5%

UNREGULATED INPUT VOLTAGE

10

1

1, 15, 16

V+

15

CS

BATT

2

V

DD

SHDN

R16

D1B

D1A

C1

MAX754CSE

10, 11

3

GND

REF

4

5

3

2

CON

CADJ

LON

C2

C3

+5V CMOS

LOGIC

CONTROL

SIGNALS

D5

MAX758ACWE

LADJ

R17

12, 13, 14

7

LX

SS

D2B

D2A

8

CC

R2

R1

Q2

Q1

11

CDRV

L1

POSITIVE

CONTRAST

VOLTAGE

L2

14

D3

LX

7

REF

D4

8

12

T1

2

C4

13

12

R5

R6

LDRV

PGND

5

3,4

6

1

Q3

C10

R3

R10

16

LFB

C9

Q5

C6

R4

C8

Q4

D7B

6

9

GND

CC

D6A

D7A

R8

D6B

8

CFB

C7

R7

R18

C5

Figure 1. CCFL and Positive LCD Power Supply

_______________________________________________________________________________________

5

CCFL Ba c k lig h t a n d

LCD Co n t ra s t Co n t ro lle rs

In Figure 1, the MAX758A, L1, and D5 form a voltage-

controlled switch-mode current source. The current out

of L1 is proportional to the voltage applied to the SS

p in. The MAX758A c onta ins a c urre nt-mode p ulse -

wid th-mod ula ting b uc k re g ula tor tha t s witc he s a t

170kHz. The voltage on the SS pin sets the switch cur-

rent limit and thus sets the current out of L1.

1250

1221

1191

811

782

753

CCFL Current-Regulation Loop

Figure 3 shows a block diagram of the regulation loop,

which maintains a fixed CCFL average lamp current

despite changes in input voltage and lamp impedance.

This loop regulates the average value of the half-wave

rectified lamp current. The root mean square lamp cur-

rent is related to, but not equal to, the average lamp

current. Assuming a sinusoidal lamp current, select R8

as follows:

402

372

343

3/MAX754

πV

REF

R8 =

0 1

2

3

14 15 16

29 30 31

2 I

LAMP,RMS

DAC CODE

where V

= 1.25V and I

is the desired full-

REF

LAMP,RMS

scale root mean square lamp current.

MID SCALE

FULL SCALE

ZERO SCALE

Figure 2. CCFT DAC Transfer Function

CON CADJ

LOGIC AND

5-BIT COUNTER

MAX754

MAX758A

SWITCH-MODE

VOLTAGE CONTROLLED

CURRENT SOURCE

FULL-SCALE = 1.250V

HALF-SCALE = 0.782V

ZERO-SCALE = 0.343V

SS

5-BIT VOLTAGE

OUTPUT DAC

I

BUCK

ERROR

AMPLIFIER

CC

CENTER-TAP

ROYER

OSCILLATOR

C10

CFB

TRANSISTOR

EMITTERS

C5

R18

R8

Figure 3. CCFL Tube Current-Regulation Loop

6

_______________________________________________________________________________________

CCFL Ba c k lig h t a n d

LCD Co n t ra s t Co n t ro lle rs

3/MAX754

V

(t)

TAP

C10

V

TAP, PK

V

SEC

(t)

I

(t)

V

(t)

LAMP

t

T

Figure 4. Simple Model of the CCFL

Figure 5. Voltage at the Center Tap of T1

The minimum operating input voltage is determined by

the transformer turns ratio (n), the lamp operating volt-

pulse-frequency-modulation (PFM) switching regulator.

The MAX753 adds a simple diode-capacitor voltage

inverter to the switching regulator.

age (V

), and the ballast capactor (C10). Using a

LAMP

simple model of the CCFL (see Figure 4) we can calcu-

late what the T1 center-tap voltage will be at maximum

lamp current. The voltage on the CCFL is in phase with

Constant-Current PFM Control Scheme

The LCD bias generators in these devices use a con-

stant-peak-current PFM control scheme. Figure 6, which

shows the MAX754’s boost switching regulator, illus-

trates this control method. When Q3 closes (Q3 “on”) a

voltage equal to BATT is applied to the inductor, caus-

ing current to flow from the battery, through the inductor

and switch, and to ground. This current ramps up linear-

ly, storing energy in the inductor’s magnetic field. When

Q3 opens, the inductor voltage reverses, and current

flows from the battery, through the inductor and diode,

and into the output capacitor. The devices regulate the

output voltage by varying how frequently the switch is

opened and closed.

the c urre nt throug h it. Le t us d e fine I

(t) =

LAMP

√2I

c os (ωt) a nd V (t) = √2V

LAMP LAMP,RMS

LAMP,RMS

cos(ωt); then the peak voltage at the center tap will be

as follows:

2 I

LAMP,RMS

nωC10sin(φ)

V

= −

TAP,PK

where,

−I

LAMP,RMS

ωC10V

−1

φ = tan

LAMP,RMS

,

n is the secondary-to-primary turns ratio of T1, and ω is

the frequency of Royer oscillation in radians per sec-

ond. The voltage on the center tap of T1 is a full-wave

rectified sine wave (see Figure 5). The average voltage

The MAX753/MAX754 not only regulate the output volt-

age, but also maintain a constant peak inductor cur-

rent, regardless of the battery voltage. The ICs vary the

switch on-time to produce the constant peak current,

and vary its off-time to ensure that the inductor current

reaches zero at the end of each cycle.

at V

must equal the average voltage at the LX node

TAP

of the MAX758A, since there cannot be any DC voltage

on inductor L1; thus the minimum operating voltage

must be greater than the average voltage at V

.

TAP

The internal circuitry senses both the output voltage

and the voltage at the LX node, and turns on the MOS-

FET only if: 1) The output voltage is out of regulation,

and 2) the voltage at LX is less than the battery voltage.

The first condition keeps the output in regulation, and

the second ensures that the inductor current always

resets to zero (i.e., the part always operates in discon-

tinuous-conduction mode).

LCD Bia s Ge n e ra t o rs

The MAX753/MAX754’s LCD bias generators provide

adjustable output voltages for powering LCD displays.

The MAX753’s LCD converter generates a negative

output, while the MAX754’s generates a positive output.

The MAX753/MAX754 employ a constant-peak-current

_______________________________________________________________________________________

7

CCFL Ba c k lig h t a n d

LCD Co n t ra s t Co n t ro lle rs

BATTERY

INPUT

C2

10µF

+5V INPUT

L2

33µH

C1

0.22µF

POSITIVE

LCD-BIAS

OUTPUT

D3

1N5819

2

3

1

15

BATT

14

LX

LADJ LON

V

DD

LDRV

LFB

13

16

Q3

ON-TIME

LOGIC

OFF-TIME

LOGIC

C6

10µF

35V

R3

R4

ON/OFF

CONTROL

PULSE-SKIP

COMPARATOR

PRESET

6-BIT COUNTER

3/MAX754

CLK

V

DAC

MAX754

6-BIT DAC

FULL-SCALE OUTPUT = 1.250V

HALF-SCALE OUTPUT = 0.938V

ZERO-SCALE OUTPUT = 0.635V

PGND

12

GND

6

Figure 6. MAX754 Positive LCD-Bias Generator

Table 1. CCFL Circuit Component Descriptions

ITEM

DESCRIPTION

Integrating Capacitor. 1 / (C5 x R18) sets the dominant pole for the feedback loop, which regulates the lamp

current. Set the dominant pole at least two decades below the Royer frequency to eliminate the AC compo-

nent of the voltage on R8. For example, if your Royer is oscillating at 50kHz = 314159rad/s, you should set

1 / (C5 x R18) ≤ 3142rad/s.

C5

Integrating Resistor. The output source-current capability of the CC pin (50µA) limits how small R18 can be.

Do not make R18 smaller than 70kΩ, otherwise CC will not be able to servo CFB to the DAC voltage (i.e., the

integrator will not be able to integrate) and the loop will not be able to regulate.

R18

R8

R8 converts the half-wave rectified lamp current into a voltage. The average voltage on R8 is not equal to the

root mean square voltage on R8. The accuracy of R8 is important since it, along with the MAX754 reference,

sets the full-scale lamp current. Use a ±1%-accurate resistor.

D7A and D7B half-wave rectify the CCFL lamp current. Half-wave rectification of the lamp current and then

averaging is a simple way to perform AC-to-DC conversion. D7A and D7B’s forward voltage drop and speed

are unimportant; they do not need to pass currents larger than about 10mA, and their reverse breakdown

voltage can be as low as 10V.

D7A, D7B

CCFL

The circuit of Figure 1, with the components shown in the bill of materials (Table 4), will drive a 500V

oper-

RMS

ating cold-cathode fluorescent lamp at 6W of power with a +12V input voltage. The lower the input voltage,

the less power the circuit can deliver.

8

_______________________________________________________________________________________

CCFL Ba c k lig h t a n d

LCD Co n t ra s t Co n t ro lle rs

3/MAX754

Table 1. CCFL Circuit Component Descriptions (continued)

ITEM

DESCRIPTION

The ballast capacitor linearizes the CCFL impedance and guarantees no DC current through the lamp. 15pF

will work with just about any lamp. Depending on the lamp, you can try higher values, but this may cause the

regulation loop to become unstable. Larger values of C10 allow the circuit to operate with lower input volt-

ages. Don’t forget that C10 must be a high-voltage capacitor and cannot be polarized. A lamp with a

C10

1500V

maximum strike voltage will require C10 to withstand 1500 x √2 = 2121V.

RMS

T1 must have high primary inductance (greater than 30µH), otherwise an inflated value of C9 will be required

in order to keep the Royer frequency below 60kHz (the maximum allowed by most lamps). A higher T1 sec-

ondary-to-primary turns ratio allows lower-voltage operation, but increases the size of the transformer.

T1

You must select a value for C9 high enough to keep the lamp current reasonably sinusoidal and yet low

enough that T1’s core does not saturate. For the Sumida EPS207 with a 171:1 turns ratio, choose a 0.22µF

L

MAG

C9

value for C9. The characteristic impedance of the resonant tank equals

, where L

is the mag-

MAG

netizing inductance of T1. The characteristic impedance is defined as the ratio of the voltage across the par-

allel LC circuit divided by the current flowing between the inductor and capacitor. This circulating current is

not delivered to the load. If C9 has too large a value, it will cause excessive circulating currents, which will in

turn saturate the core of T1. It’s easy to tell when you have excess circulating current in the resonant tank,

because when you touch T1 you burn your finger. However, reducing the value of C9 decreases tank Q,

which increases the harmonic content of the lamp-current waveform. If the lamp-current waveform does not

look sinusoidal, then the circuit may not regulate to the right root mean square current.

C9

R10 sets the base current for Q4 and Q5. If you choose too large a value for R10, Q4 and Q5 will overheat.

Too small a value will waste base current and slightly degrade efficiency. The optimal value will depend on

how much power you are trying to deliver to the lamp. 510Ω is a good “always works but may not be the most

efficient” value for use with the FMMT619 transistors from ZETEX.

R10

This resistive divider senses the voltage at the center tap of T1. When the CC pin on the MAX758A rises

above 1.25V, the internal switch turns off, interrupting power to the Royer oscillator and limiting the open-lamp

transformer center-tap voltage.

R5, R6

D6B, C7, and R7 form a soft-start clamp, which limits the rate-of-rise of the peak current in the MAX758A.

Make sure R7 is at least 100kΩ so it does not excessively load the CC pin.

D6B, C7, R7

D6A, R17

D6A and R17 are also part of the soft-start clamp. The voltage on the SS pin controls the peak current in the

MAX758A’s switch. Make sure R17 is at least 100kΩ so it does not excessively load the CC pin.

L1

D5

C2

Inductor for the Switching-Current Source. Use a 47µH to 150µH inductor with a 1A to 1.5A saturation current.

Schottky Catch Diode. Use a 1A to 1.5A Schottky diode with low forward-voltage power.

Supply Bypass Capacitor. Use low-ESR capacitor.

_______________________________________________________________________________________

9

CCFL Ba c k lig h t a n d

LCD Co n t ra s t Co n t ro lle rs

Table 2. CCFL Circuit Design Example (Note 1)

PARAMETER

CCFL Specifications

Strike Voltage (V )

SYMBOL

MIN

TYP

MAX

UNITS

V

S,RMS

1100

1500

V

RMS

S

Discharging Tube Current (I )

I

0.001376

0.005

A

RMS

L

LAMP,RMS

Discharging Tube Voltage (V )

L

V

435

V

RMS

LAMP,RMS

LCD Contrast Voltage Specifications

Bias Voltage

V

16.3

32.6

V

A

LCD

Output Current

I

0.0245

LCD

Royer Specifications

T1 Turns Ratio (Sec/Pri) (Note 2)

T1 Resonating Inductance (Note 2)

C9 Value (Note 3)

n

171

L

0.000045

2.2E-07

H

F

MAG

C

RES

BAL

w

3/MAX754

C10 Value

C

1.5E-11

F

Royer Frequency

317820.86

rad/s

MAX754 Specifications

Reference Voltage

V

REF

1.25

V

Second Volts Constant

CCFL Circuit Calculations

R8 Current-Sensing Resistor

Secondary Voltage Phase vs. Tube Voltage

T1 Center-Tap Peak Voltage

Secondary Limit Voltage

T1 Center-Tap Limit Peak Voltage

R5/R6

sV

0.000008

2.4E-05

sV

R8

555.36037

-1.1776341

9.3903817

1350

Ω

phi

Radian

V

PEAK

TAP,PK

V

LIM

V

RMS

11.164844

0.1341944

V

PEAK

R

Ω/Ω

OTP,RATIO

LCD Circuit Calculations

V

IN(min)

Full-Load Switching Period

T

FL

1.639E-06

0.0398724

s

H

L2 Inductance

L2

1.96E-05

5.978103

2.4E-05

1.22704

L2 Peak Currrent

R4/R3

A

Ω/Ω

LCD,RATIO

Application Circuit Operating Range

Input Voltage

V

IN

18

V

Note 1: To perform your own calculations for the parameters given in Table 2 (Design Example), use the equations given in Table

3 (Design Equations).

Note 2: T1 = Sumida’s EPS207

Note 3: C9 = Wima’s SMD 7.3 __/63

10 ______________________________________________________________________________________

CCFL Ba c k lig h t a n d

LCD Co n t ra s t Co n t ro lle rs

3/MAX754

Table 3. Spreadsheet Design Equations

PARAMETER

SYMBOL

MIN

TYP

MAX

CCFL Specifications

Strike Voltage (V )

V

S,RMS

1100

1500

S

= 0.28 *

LAMP,RMS(max)

Discharging Tube Current (I )

I

0.005

L

LAMP,RMS

I

Discharging Tube Voltage (V )

L

V

435

LAMP,RMS

LCD Contrast Voltage Specifications

Bias Voltage

V

LCD

= V

/ 2

32.6

LCD(max)

Output Current

I

0.0245

LCD

Royer Specifications

T1 Turns Ratio (Sec/Pri)

T1 Resonating Inductance

C9 Value

n

171

L

0.000045

2.2E-07

1.5E-11

MAG

C

RES

BAL

w

C10 Value

C

Royer Frequency

= SQRT [1 / (L

* C

)]

RES

MAG

MAX754 Specifications

Reference Voltage

V

REF

1.25

Second Volts Constant

CCFL Circuit Calculations

sV

0.000008

2.4E-05

= PI() * V

* SQRT(2) /

REF

R8 Current-Sensing Resistor

R8

(2 * I

)

LAMP,RMS(max)

Secondary Voltage Phase vs. Tube

Voltage

= ATAN (-I

/

)

LAMP,RMS(max)

phi

(C

* w * + V

BAL

LAMP,RMS

= -SQRT(2) * I

(C * w * SIN(phi)) / n

/

LAMP,RMS(max)

T1 Center-Tap Peak Voltage

V

TAP,PK

BAL

Secondary Limit Voltage

T1 Center-Tap Limit Peak Voltage

R5/R6

V

= V

* 0.9

LIM

S,RMS(max)

= SQRT(2) * V

/ n

LIM

R

= V

/ (D25 - 0.6 - V

)

OTP,RATIO

REF

LCD Circuit Calculations

= sV(min) / V

+ sV(min) /

IN(min)

V

IN(min)

Full-Load Switching Period

T

FL

(V

LCD(max)

- V

)

IN(min)

= sV(min) ^ 2 / (2 * T

*

)

FL

L2 Inductance

L2

= L2(max) * 0.8

V

* I

LCD(max) LCD(min)

L2 Peak Currrent

= sV(max) / L2(min)

R4/R3

R

= V

/ (V

- V

REF

)

LCD,RATIO

REF

LCD(max)

Application Circuit Operating Range

Input Voltage

V

IN

= (2 / PI()) * V

18

TAP,PK

______________________________________________________________________________________ 11

CCFL Ba c k lig h t a n d

LCD Co n t ra s t Co n t ro lle rs

Table 4. Bill of Materials

RESISTOR

R1

VALUE (Ω)

100,000

1,000,000

40,200

TOLERANCE (%)

±10

±1

R2

R3

R4

±1

R5

100,000

13,300

±1

R6

±1

R7

100,000

549

±10

±1

R8

R10

R16

R17

R18

680

±5

100,000

±10

±5

3/MAX754

WORKING

VOLTAGE (V)

CAPACITOR

VALUE (µF)

CHARACTERISTICS

C1

C2

C3

C4

C5

C6

C7

C8

C9

C10

0.1

22

6

20

6

Low ESR

0.1

0.01

10

6

Non-polarized

50

6

1

30

63

3000

22

1.5E-5

High voltage

SURFACE-

MOUNT PART

NUMBER

OTHER

COMPONENTS

BREAKDOWN

VOLTAGE (V)

GENERIC

PART NO.

PACKAGE

MANUFACTURER

Q1

Q2

CMPTA06

CMPT2907A

MMFT3055ELT1

FMMT619

SOT-23

D-64

80

60

50

75

50

75

20

75

MPSA06

2N2907

3055EL

Central Semi.

Motorola

Q3

Q4

Zetex

Q5

FMMT619

Zetex

D1A

D1B

D2A

D2B

D3

CMPD4150

EC10QS05

CMPD4150

EC10QS02L

CMPD4150

1N4150

1N5819

1N4150

1N5817

1N4150

Central Semi.

Nihon

D4

SOT-23

D-64

Central Semi.

Nihon

D5

D6A

D6B

D7A

D7B

SOT-23

Central Semi.

Note: For T1, Use Sumida EPS207. Request No. USC-145, Special No. 6358-JP5-010.

12 ______________________________________________________________________________________

CCFL Ba c k lig h t a n d

LCD Co n t ra s t Co n t ro lle rs

3/MAX754

Positive LCD Bias: MAX754

The voltage-regulation loop is comprised of resistors R3

and R4, the pulse-skip comparator, the internal DAC,

the on-time and off-time logic, and the external power

components. The comparator compares a fraction of

the output voltage to the voltage generated by an on-

chip 6-bit DAC. The part regulates by keeping the volt-

age at LFB equal to the DAC’s output voltage. Thus,

you can set the output to different voltages by varying

the DAC’s output.

1250

1240

1230

947

938

928

Varying the DAC output voltage (digital control) adjusts

the external voltage from 50% to 100% of full scale. On

power-up or after a reset, the counter sets the DAC out-

put to mid scale. Each rising edge of LADJ (with LON

high) decrements the DAC output. When decremented

beyond zero scale, the counter rolls over and sets the

DAC to the maximum value. In this way, a single pulse

applied to LADJ decreases the DAC set point by one

step, and 63 pulses increase the set point by one step.

655

645

635

0 1

2

30 31 32

61 62 63

DAC CODE

The MAX754’s DAC transfer function is shown in Figure 7.

The following equation relates the switching regulator’s

regulated output voltage to the DAC’s voltage:

MID SCALE

FULL SCALE

ZERO SCALE

Figure 7. MAX754 LCD DAC Transfer Function

R3

V

= V

1 +

OUT

DAC

R4

hand side to -V

. This voltage is more negative than

HIGH

the output, forcing D3 to conduct, and transferring

c ha rge from the flying c a pa c itor C15 to the output

capacitor C6. This charge transfer happens quickly,

resulting in a voltage spike at the output due to the

p roduc t of the outp ut c a pa c itor’s e quiva le nt se rie s

resistance (ESR) and the current that flows from C15 to

C6. To limit this drop, resistor R19 has been placed in

series with D3. R19 limits the rate of current flow. At the

end of this cycle, the flying capacitor has been dis-

charged to 30V + Vd.

Table 5 is the logic table for the LADJ and LON inputs,

which control the internal DAC and counter. As long as the

timing specifications for LADJ and LON are observed, any

sequence of operations can be implemented.

Negative LCD Bias: MAX753

The LCD bias generator of the MAX753 (Figure 8) gen-

erates its negative output by combining the switching

regulator of the MAX754 with a simple diode-capacitor

voltage inverter. To best understand the circuit, look at

the p a rt in a s te a d y-s ta te c ond ition. As s ume , for

instance, that the output is being regulated to -30V, and

that the battery voltage is +10V. When Q3 turns on, two

things occur: current ramps up in the inductor, just like

with the boost converter; and the charge on C15 (trans-

ferred from the inductor on the previous cycle) is trans-

ferred to C6, boosting the negative output. At the end of

the cycle, the voltage on C15 is 30V + Vd, where Vd is

the forward voltage drop of Schottky diode D3, and 30V

is the magnitude of the output.

If BATT(MAX) (i.e., either the fully charged battery volt-

a g e , or the wa ll-c ub e volta g e ) is g re a te r tha n

|V

(MIN)|, tie the cathode of D8 to BATT instead of

OUT

GND, a s s hown b y the d a s he d line s in Fig ure 8.

Efficiency is lower with this method, so tie the cathode

of D8 to GND whenever possible.

The MAX753’s regulation loop is similar to that of the

MAX754. The MAX753, however, uses different power

components, and its feedback resistors are returned to

the reference (1.25V) rather than ground.

When the MOSFET turns off, the inductor’s energy is

transferred to capacitor C15, charging the capacitor to

The MAX753’s PFM comparator compares a fraction of

the output voltage to the voltage generated by the on-

chip 6-bit DAC. The part regulates by keeping the volt-

age at LFB equal to the DAC’s output voltage. Thus,

you can set the LCD bias voltage to different voltages

by varying the DAC’s output.

a positive voltage (V

this instance, diode D8 allows current to flow from the

right-hand side of the flying capacitor (C15) to ground.

) that is higher than |V_OUT|. In

HIGH

Whe n the MOSFET turns on, the le ft-ha nd s id e of

capacitor C15 is clamped to ground, forcing the right-

______________________________________________________________________________________ 13

CCFL Ba c k lig h t a n d

LCD Co n t ra s t Co n t ro lle rs

Table 5. Logic-Signal Truth Table

CCF CONTROL

LON

LADJ

CON

CADJ

CCFT STATUS

CCFT DAC

Hold

X

0

1

0

1

Off

On

X

Reset

Hold

X

0

0→1

X

Dec

LCD BIAS CONTROL

LON

LADJ

CON

X

CADJ

LCD STATUS

LCD DAC

Hold

0

1

0

1

X

Off

On

X

Reset

Hold

0

X

3/MAX754

0→1

X

Dec

Hold = maintain last DAC value in counter

Reset = set DAC counter to half scale

Dec = decrement DAC counter one step

Off = section turned off, sleep state

On = section turned on

X = don’t care

Table 6. Component Suppliers

MANUFACTURER

ADDRESS

PHONE

FAX

145 Adams Ave.

Hauppauge, NY 11788

Central Semiconductor

(516) 435-1110

(516) 435-1824

6000 Park of Commerce Blvd.

Boca Raton, FL 33287

Coiltronics

Maxim

(407) 241-7876

(408) 737-7600

(407) 241-9339

(408) 737-7194

120 San Gabriel Dr.

Sunnyvale, CA 94025

c/o Quantum Marketing

12900 Rolling Oaks Rd.

Twin Oaks, CA 93518

Nihon (NIEC)*

Sumida

(805) 867-2555

(708) 956-0666

(914) 347-2474

(516) 543-7100

(805) 867-2698

(708) 956-0702

(914) 347-7230

(516) 864-7630

5999 New Wilke Rd., Suite 110

Rolling Meadows, IL 60008

2269 Saw Mill River Rd., Suite 400

P.O. Box 217

Elmsford, NY 10523

Wima

87 Modular Ave.

Commack, NY 11725

Zetex

* Contact John D. Deith, ask for “Maxim Discount” on orders less than 5k units.

14 ______________________________________________________________________________________

CCFL Ba c k lig h t a n d

LCD Co n t ra s t Co n t ro lle rs

3/MAX754

BATTERY

INPUT

ALTERNATE

D8 CONNECTION

(SEE TEXT)

C2

+5V INPUT

10µF

L2

33µH

C1

0.22µF

NEGATIVE

LCD-BIAS

OUTPUT

C15

1µF

R19

D3

2

3

1

15

BATT

14

LX

2.2Ω 1N5819

LADJ LON

V

DD

D8

1N5819

LDRV

LFB

13

16

ON-TIME

LOGIC

OFF-TIME

LOGIC

Q3

C6

10µF

35V

R3

R4

ON/OFF

CONTROL

PULSE-SKIP

COMPARATOR

V

DD

PRESET

6-BIT COUNTER

CLK

V

DAC

MAX753

6-BIT DAC

7

REF

GND

6

PGND

12

C4

0.22µF

Figure 8. MAX753 Negative LCD-Bias Generator

The MAX753’s DAC transfer function is shown in Figure 9.

The following equation relates the switching regulator’s

regulated output voltage to the DAC’s voltage (REF - LFB):

1240

1230

1220

R3

V

= REF − 1 +

REF − LFB

(

)

OUT

R4

937

928

918

The value REF - LFB (and not LFB) is specified in the

Electrical Characteristics . The most negative output

voltage occurs for the largest value of REF - LFB.

The MAX753’s c omb ina tion b oos t c onve rte r a nd

charge-pump inverter was chosen over a conventional

buck-boost inverter because it allows the use of low-

cost N-channel MOSFETs instead of more expensive P-

channel ones. Additionally, its efficiency is 5% to 10%

better than a standard buck-boost inverter.

645

635

625

0 1

2

30 31 32

61 62 63

DAC CODE

MID SCALE

FULL SCALE

ZERO SCALE

* DAC OUTPUT VOLTAGE = REF - LFB

Figure 9. MAX753 LCD DAC Transfer Function

______________________________________________________________________________________ 15

CCFL Ba c k lig h t a n d

LCD Co n t ra s t Co n t ro lle rs

_____________________Blo c k Dia g ra m

___________________Ch ip To p o g ra p h y

V

DD

BATT

LFB

LX

2

3

15

14

LADJ

LON

BATT

LX

LADJ

LDRV

LFB

13

OFF-TIME

LOGIC

ON-TIME

LOGIC

CONTROL

LON

CON

CLK PRESET

6-BIT

COUNTER

LDRV

PGND

PULSE-SKIP

COMPARATOR

CADJ

16

1

0. 112"

(2. 845mm)

CDRV

6-BIT

D/A CONVERTER

V

DD

3/MAX754

7

MAX753/MAX754

REF

GND

5-BIT

D/A CONVERTER

ERROR

AMPLIFIER

11

CDRV

CC

REF

CS

CFB

5-BIT

COUNTER

8

CFB

CC

CS

0. 076"

(1. 930mm)

9

CLK PRESET

10

LOGIC

TRANSISTOR COUNT: 321;

SUBSTRATE CONNECTED TO V

CONTROL

.

DD

REF

CON

CADJ

PGND

12

GND

6

4

5

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are

implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

16 __________________Ma x im In t e g ra t e d P ro d u c t s , 1 2 0 S a n Ga b rie l Drive , S u n n yva le , CA 9 4 0 8 6 (4 0 8 ) 7 3 7 -7 6 0 0

Printed USA

is a registered trademark of Maxim Integrated Products.


型号：	MAX754CSE
厂家：	MAXIM INTEGRATED PRODUCTS
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MAX754CSE [MAXIM]

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