MAX7031 [MAXIM]
Low-Cost, 308MHz, 315MHz, and 433.92MHz FSK Transceiver with Fractional-N PLL; 低成本， 308MHz ， 315MHz的，和433.92MHz的FSK收发器，带有N分频PLL
| 型号： | MAX7031 |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Low-Cost, 308MHz, 315MHz, and 433.92MHz FSK Transceiver with Fractional-N PLL |
| 文件： | 总19页 (文件大小：651K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-3707; Rev 0; 5/05
Low-Cost, 308MHz, 315MHz, and 433.92MHz
FSK Transceiver with Fractional-N PLL
General Description
Features
The MAX7031 crystal-based, fractional-N transceiver is
designed to transmit and receive FSK data at factory-
preset carrier frequencies of 308MHz†, 315MHz, or
433.92MHz with data rates up to 33kbps (Manchester
encoded) or 66kbps (NRZ encoded). This device gen-
erates a typical output power of +10dBm into a 50Ω
load, and exhibits typical sensitivity of -110dBm. The
MAX7031 features separate transmit and receive pins
(PAOUT and LNAIN) and provides an internal RF switch
that can be used to connect the transmit and receive
pins to a common antenna.
♦ +2.1V to +3.6V or +4.5V to +5.5V Single-Supply
Operation
♦ Single-Crystal Transceiver
♦ Factory-Preset Frequency (No Serial Interface
Required)
♦ FSK Modulation
♦ Factory-Preset FSK Frequency Deviation
♦ +10dBm Output Power into 50Ω Load
♦ Integrated TX/RX Switch
The MAX7031 transmit frequency is generated by a 16-
bit, fractional-N, phase-locked loop (PLL), while the
receiver’s local oscillator (LO) is generated by an inte-
ger-N PLL. This hybrid architecture eliminates the need
for separate transmit and receive crystal reference
oscillators because the fractional-N PLL is preset to be
10.7MHz above the receive LO. Retaining the fixed-N
PLL for the receiver avoids the higher current-drain
requirements of a fractional-N PLL and keeps the
receiver current drain as low as possible.
♦ Integrated Transmit and Receive PLL, VCO, and
Loop Filter
♦ > 45dB Image Rejection
♦ Typical RF Sensitivity*: -110dBm
♦ Selectable IF Bandwidth with External Filter
♦ RSSI Output with High Dynamic Range
♦ < 12.5mA Transmit-Mode Current
♦ < 6.7mA Receive-Mode Current
♦ < 800nA Shutdown Current
The fractional-N architecture of the MAX7031 transmit
PLL allows the transmit FSK signal to be preset for
exact frequency deviations, and completely eliminates
the problems associated with oscillator-pulling FSK sig-
nal generation. All frequency-generation components
are integrated on-chip, and only a crystal, a 10.7MHz IF
filter, and a few discrete components are required to
implement a complete antenna/digital data solution.
♦ Fast-On Startup Feature, < 250µs
♦ Small, 32-Pin, Thin QFN Package
*0.2% BER, 4kbps Manchester-encoded data, 280kHz IF BW
The MAX7031 is available in a small, 5mm x 5mm, 32-
pin, thin QFN package, and is specified to operate in
the automotive -40°C to +125°C temperature range.
†Consult factory for availability.
Ordering Information
TEMP
RANGE
PKG
CODE
PART
PIN-PACKAGE
Applications
2-Way Remote Keyless Entry
-40°C to
+125°C
MAX7031_ATJ__
32 Thin QFN-EP** T3255-3
Security Systems
Home Automation
**EP = Exposed paddle.
Note: The MAX7031 is available with factory-preset operating
frequencies. See the Selector Guide for complete part num-
bers.
Remote Controls
Remote Sensing
Smoke Alarms
Garage-Door Openers
Local Telemetry Systems
Pin Configuration, Selector Guide, Typical Application
Circuit, and Functional Diagram appear at end of data sheet.
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
Low-Cost, 308MHz, 315MHz, and 433.92MHz
FSK Transceiver with Fractional-N PLL
ABSOLUTE MAXIMUM RATINGS
HV to GND..........................................................-0.3V to +6.0V
Continuous Power Dissipation (T = +70°C)
A
IN
PAV , AV , DV to GND................................-0.3V to +4.0V
ENABLE, T/R, DATA, AGC0, AGC1,
AUTOCAL to GND................................-0.3V to (HVIN + 0.3)V
All Other Pins to GND ..............................-0.3V to (_VDD + 0.3)V
32-Pin Thin QFN (derate 21.3mW/°C
DD
DD
DD
above +70°C).............................................................1702mW
Operating Temperature Range .........................-40°C to +125°C
Storage Temperature Range.............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(Typical Application Circuit, 50Ω system impedance, PAV
= AV
= DV
= HV = +2.1V to +3.6V, f = 308MHz, 315MHz, or
DD
DD
DD
IN
RF
433.92MHz, T = -40°C to +125°C, unless otherwise noted. Typical values are at PAV
= AV
= DV
= HV = +2.7V, T = +25°C,
A
DD
DD
DD
IN
A
unless otherwise noted.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
HV , PAV , AV , and DV connected
DD
MIN
TYP
MAX
UNITS
IN
DD
DD
Supply Voltage (3V Mode)
V
2.1
2.7
3.6
V
DD
to power supply
PAV , AV , and DV unconnected
DD
DD
DD
Supply Voltage (5V Mode)
HV
4.5
5.0
5.5
V
IN
from HV , but connected together
IN
f
f
= 315MHz
= 434MHz
11.6
12.4
6.4
19.1
20.4
8.4
RF
Transmit mode
(Note 2)
RF
mA
Receiver 315MHz
Receiver 434MHz
T
A
< +85°C,
6.7
8.7
typ at +25°C
(Note 3)
Deep-sleep (3V mode)
Deep-sleep (5V mode)
Receiver 315MHz
0.8
8.8
Supply Current
I
µA
DD
2.4
10.9
8.7
6.8
mA
T
A
< +125°C,
Receiver 434MHz
7.0
8.8
typ at +125°C
(Note 2)
Deep-sleep (3V mode)
Deep-sleep (5V mode)
8.0
34.2
39.3
µA
V
14.9
3.0
Voltage Regulator
V
HV = 5V, I
= 15mA
LOAD
REG
IN
DIGITAL I/O
0.9
x HV
Input-High Threshold
Input-Low Threshold
V
(Note 2)
(Note 2)
V
V
IH
IN
0.1
V
IL
x HV
IN
AGC0-1, AUTOCAL, ENABLE, T/R, DATA
(HV = 5.5V)
Pulldown Sink Current
Output Low Voltage
Output High Voltage
20
µA
V
IN
V
I
= 500µA
0.15
OL
SINK
HV
IN
V
I
= 500µA
V
OH
SOURCE
- 0.26
2
_______________________________________________________________________________________
Low-Cost, 308MHz, 315MHz, and 433.92MHz
FSK Transceiver with Fractional-N PLL
AC ELECTRICAL CHARACTERISTICS
(Typical Application Circuit, 50Ω system impedance, PAV
= AV
= DV
= HV = +2.1V to +3.6V, f = 308MHz, 315MHz. or
DD
DD
DD IN RF
433.92MHz, T = -40°C to +125°C, unless otherwise noted. Typical values are at PAV = AV = DV = HV = +2.7V, T = +25°C,
A
DD
DD
DD
IN
A
unless otherwise noted.) (Note 1)
PARAMETER
GENERAL CHARACTERISTICS
Frequency Range
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
308/315/433.92
MHz
dBm
Maximum Input Level
P
0
RFIN
f
f
= 315MHz
= 434MHz
32
RF
Transmit Efficiency (Note 5)
%
30
RF
ENABLE or T/R transition low to high,
transmitter frequency settled to within
50kHz of the desired carrier
200
ENABLE or T/R transition low to high,
transmitter frequency settled to within 5kHz
of the desired carrier
Power-On Time
t
µs
350
250
ON
ENABLE transition low to high, or T/R
transition high to low, receiver startup time
(Note 4)
RECEIVER
0.2% BER, 4kbps
315MHz
-110
Manchester data rate,
280kHz IF BW, FSK
Sensitivity
dBm
dB
434MHz
-107
46
50kHz deviation
Image Rejection
POWER AMPLIFIER
T
T
= +25°C (Note 3)
4.6
3.9
10.0
6.7
15.5
A
= +125°C, PAV
= AV
= DV
=
DD
A
DD
DD
HV = +2.1V (Note 2)
Output Power
P
K
IN
dBm
OUT
T
= -40°C, PAV
= AV
= DV
= HV
DD IN
A
DD
DD
13.1
15.8
= +3.6V (Note 3)
Maximum Carrier Harmonics
Reference Spur
With output matching network
-40
-50
dBc
dBc
PHASE-LOCKED LOOP
Transmit VCO Gain
340
-68
-98
340
-80
-90
200
500
MHz/V
dBc/Hz
MHz/V
dBc/Hz
VCO
10kHz offset, 200kHz loop BW
1MHz offset, 200kHz loop BW
Transmit PLL Phase Noise
Receive VCO Gain
10kHz offset, 500kHz loop BW
1MHz offset, 500kHz loop BW
Transmit PLL
Receive PLL Phase Noise
Loop Bandwidth
kHz
Receive PLL
_______________________________________________________________________________________
3
Low-Cost, 308MHz, 315MHz, and 433.92MHz
FSK Transceiver with Fractional-N PLL
AC ELECTRICAL CHARACTERISTICS (continued)
(Typical Application Circuit, 50Ω system impedance, PAV
= AV
= DV
= HV = +2.1V to +3.6V, f = 308MHz, 315MHz. or
DD
DD
DD IN RF
433.92MHz, T = -40°C to +125°C, unless otherwise noted. Typical values are at PAV = AV = DV = HV = +2.7V, T = +25°C,
A
DD
DD
DD
IN
A
unless otherwise noted.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Reference Frequency Input Level
0.5
V
P-P
LOW-NOISE AMPLIFIER/MIXER (Note 7)
f
RF
f
RF
f
RF
f
RF
f
RF
f
RF
= 315MHz
= 434MHz
= 315MHz
= 434MHz
= 315MHz
= 434MHz
1 - j4.7
1 - j3.3
50
LNA Input Impedance
Z
Normalized to 50Ω
High-gain state
Low-gain state
INLNA
45
Voltage-Conversion Gain
dB
13
9
High-gain state
Low-gain state
-42
-6
Input-Referred 3rd-Order
Intercept Point
IIP3
dBm
Ω
Mixer Output Impedance
330
LO Signal Feedthrough to
Antenna
-100
dBm
RSSI
Input Impedance
330
10.7
10
Ω
Operating Frequency
3dB Bandwidth
f
IF
MHz
MHz
mV/dB
Gain
15
FSK DEMODULATOR
Conversion Gain
2.0
mV/kHz
ANALOG BASEBAND
Maximum Data Filter Bandwidth
Maximum Data Slicer Bandwidth
50
kHz
kHz
100
Maximum Peak Detector
Bandwidth
50
kHz
Manchester coded
33
66
Maximum Data Rate
kbps
Nonreturn to zero (NRZ)
CRYSTAL OSCILLATOR
Crystal Frequency
(f - 10.7)
RF
f
MHz
XTAL
/ 24
50
2
Maximum Crystal Inductance
mH
ppm/V
pF
Frequency Pulling by V
DD
Crystal Load Capacitance
(Note 6)
4.5
4
_______________________________________________________________________________________
Low-Cost, 308MHz, 315MHz, and 433.92MHz
FSK Transceiver with Fractional-N PLL
AC ELECTRICAL CHARACTERISTICS (continued)
(Typical Application Circuit, 50Ω system impedance, PAV
= AV
= DV
= HV = +2.1V to +3.6V, f = 308MHz, 315MHz. or
DD
DD
DD IN RF
433.92MHz, T = -40°C to +125°C, unless otherwise noted. Typical values are at PAV = AV = DV = HV = +2.7V, T = +25°C,
A
DD
DD
DD
IN
A
unless otherwise noted.) (Note 1)
Note 1: Supply current, output power, and efficiency are greatly dependent on board layout and PAOUT match.
Note 2: 100% tested at T = +125°C. Guaranteed by design and characterization over temperature.
A
Note 3: Guaranteed by design and characterization. Not production tested.
Note 4: Time for final signal detection; does not include baseband filter settling.
Note 5: Efficiency = P
/ (V
x I ).
DD DD
OUT
Note 6: Dependent on PC board trace capacitance.
Note 7: Input impedance is measured at the LNAIN pin. Note that the impedance at 315MHz includes the 12nH inductive degenera-
tion from the LNA source to ground. The impedance at 434MHz includes a 10nH inductive degeneration connected from
the LNA source to ground. The equivalent input circuit is 50Ω in series with ~2.2pF. The voltage conversion is measured
with the LNA input-matching inductor, the degeneration inductor, and the LNA/mixer tank in place, and does not include the
IF filter insertion loss.
Typical Operating Characteristics
(Typical Operating Circuit, PAV
= AV
= DV
= HV = +3.0V, f = 433.92MHz, IF BW = 280kHz. 4kbps Manchester
DD IN RF
DD
DD
encoded, 0.2% BER deviation = 50kHz, T = +25°C, unless otherwise noted.)
A
RECEIVER
SUPPLY CURRENT vs. RF FREQUENCY
SUPPLY CURRENT vs. SUPPLY VOLTAGE
FSK MODE
DEEP-SLEEP CURRENT vs. TEMPERATURE
7.0
6.9
6.8
6.7
6.6
6.5
6.4
7.4
7.2
7.0
6.8
6.6
6.4
6.2
6.0
18
16
14
12
10
8
+125°C
+125°C
V
V
V
= +3.6V
= +3.0V
= +2.1V
CC
CC
CC
+85°C
+85°C
+25°C
+25°C
-40°C
6
-40°C
4
2
0
300
325
350
375
400
425
450
2.1
2.4
2.7
3.0
3.3
3.6
-40
-15
-10
35
60
85
110
RF FREQUENCY (MHz)
SUPPLY VOLTAGE (V)
TEMPERATURE (°C)
_______________________________________________________________________________________
5
Low-Cost, 308MHz, 315MHz, and 433.92MHz
FSK Transceiver with Fractional-N PLL
Typical Operating Characteristics (continued)
(Typical Operating Circuit, PAV
= AV
= DV
= HV = +3.0V, f
= 433.92MHz, IF BW = 280kHz. 4kbps Manchester
RF
DD
DD
DD
IN
encoded, 0.2% BER deviation = 50kHz, T
= +25°C, unRlesEsCothEeIrVwiEseRnoted.)
A
BIT-ERROR RATE
SENSITIVITY vs. TEMPERATURE
SENSITIVITY vs. FREQUENCY DEVIATION
vs. AVERAGE INPUT POWER
100
-100
-102
-104
-106
-108
-110
-112
-94
-96
280kHz IF BW
280kHz IF BW
0.2% BER
280kHz IF BW
0.2% BER
10
f
= 434MHz
RF
-98
f
= 434MHz
RF
-100
-102
-104
-106
-108
1
0.1
0.2% BER
f
= 315MHz
RF
f
= 315MHz
RF
0.01
-116 -114 -112 -110 -108 -106 -104
AVERAGE INPUT POWER (dBm)
-40
-15
10
35
60
85
110
1
10
100
TEMPERATURE (°C)
FREQUENCY DEVIATION (kHz)
RSSI vs. RF INPUT POWER
RSSI AND DELTA vs. IF INPUT POWER
FSK DEMODULATOR OUTPUT
vs. IF FREQUENCY
MAX7031 toc08
3.5
1.8
2.1
1.8
1.5
1.2
0.9
0.6
0.3
0
1.6
1.2
0.8
0.4
0
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
2.5
1.5
RSSI
HIGH-GAIN MODE
0.5
-0.5
-1.5
-2.5
-3.5
AGC SWITCH
POINT
DELTA
LOW-GAIN MODE
AGC HYSTERESIS: 3dB
-130 -110 -90 -70 -50 -30 -10
RF INPUT POWER (dBm)
10
-90
-70
-50
-30
-10
10
10.4 10.5 10.6 10.7 10.8 10.9 11.0
IF FREQUENCY (MHz)
IF INPUT POWER (dBm)
SYSTEM GAIN vs. IF FREQUENCY
IMAGE REJECTION vs. TEMPERATURE
NORMALIZED IF GAIN vs. IF FREQUENCY
50
40
30
20
10
0
48
46
44
42
0
-4
UPPER SIDEBAND
f
= 434MHz
RF
f
= 315MHz
RF
FROM RFIN
45dB IMAGE
-8
TO MIXOUT
REJECTION
f
= 434MHz
RF
-12
-16
-20
LOWER SIDEBAND
-10
-20
0
5
10
15
20
25
30
-40
-15
10
35
60
85
110
1
10
100
IF FREQUENCY (MHz)
TEMPERATURE (°C)
IF FREQUENCY (MHz)
6
_______________________________________________________________________________________
Low-Cost, 308MHz, 315MHz, and 433.92MHz
ASK Transceiver with Fractional-N PLL
Typical Operating Characteristics (continued)
(Typical Operating Circuit, PAV
= AV
= DV
= HV = +3.0V, f = 433.92MHz, IF BW = 280kHz. 4kbps Manchester
RF
DD
DD
DD
IN
encoded, 0.2% BER deviation = 50kHz, T = +25°C, unless otherwise noted.)
A
RECEIVER
S11 SMITH PLOT OF RFIN
S11 vs. RF FREQUENCY
0
-6
434MHz
-12
433.92MHz
-18
-24
400MHz
500MHz
200
250
300
350
400
450
500
RF FREQUENCY (MHz)
INPUT IMPEDANCE
vs. INDUCTIVE DEGENERATION
INPUT IMPEDANCE
vs. INDUCTIVE DEGENERATION
MAX7031 toc16
MAX7031 toc15
90
80
70
60
50
40
30
20
-150
-160
-170
-180
-190
-200
-210
-220
90
80
70
60
50
40
30
20
-220
-230
-240
-250
-260
-270
-280
-290
f
= 434MHz
RF
f
= 315MHz
RF
IMAGINARY
IMPEDANCE
IMAGINARY
IMPEDANCE
REAL IMPEDANCE
REAL IMPEDANCE
1
10
100
1
10
INDUCTIVE DEGENERATION (nH)
100
INDUCTIVE DEGENERATION (nH)
PHASE NOISE vs. OFFSET FREQUENCY
PHASE NOISE vs. OFFSET FREQUENCY
-50
-60
-50
-60
f = 434MHz
RF
f
= 315MHz
RF
-70
-70
-80
-80
-90
-90
-100
-110
-120
-100
-110
-120
100
1k
10k
100k
1M
10M
100
1k
10k
100k
1M
10M
OFFSET FREQUENCY (Hz)
OFFSET FREQUENCY (Hz)
_______________________________________________________________________________________
7
Low-Cost, 308MHz, 315MHz, and 433.92MHz
FSK Transceiver with Fractional-N PLL
Typical Operating Characteristics (continued)
(Typical Operating Circuit, PAV
= AV
= DV
= HV = +3.0V, f = 433.92MHz, IF BW = 280kHz. 4kbps Manchester
RF
DD
DD
DD
IN
encoded, 0.2% BER deviation = 50kHz, T = +25°C, unless otherwise noted.)
A
TRANSMITTER
SUPPLY CURRENT
vs. SUPPLY VOLTAGE
SUPPLY CURRENT vs. OUTPUT POWER
SUPPLY CURRENT vs. SUPPLY VOLTAGE
12
17
15
13
11
9
16
14
12
10
8
f
= 434MHz
f
= 315MHz
RF
RF
f
= 315MHz
RF
11
10
9
T
= +85°C
A
T
= +85°C
A
T
= +125°C
A
T
= +125°C
8
A
T
= -40°C
A
T
= -40°C
A
7
T
= +25°C
A
6
5
T
= +25°C
A
4
-14
-10
-6
-2
2
6
10
2.1
2.4
2.7
3.0
3.3
3.6
2.1
2.4
2.7
3.0
3.3
3.6
AVERAGE OUTPUT POWER (dBm)
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
SUPPLY CURRENT vs. OUTPUT POWER
OUTPUT POWER vs. SUPPLY VOLTAGE
OUTPUT POWER vs. SUPPLY VOLTAGE
14
12
10
8
14
12
10
8
14
13
12
11
10
9
f
= 315MHz
f
= 434MHz
RF
RF
f
= 434MHz
RF
T
= -40°C
A
T
= -40°C
A
T
= +25°C
A
T
= +25°C
A
T
= +125°C
A
8
T
= +125°C
A
T
= +85°C
7
A
6
6
T
= +85°C
A
6
5
4
4
-14
-10
-6
-2
2
6
10
2.1
2.4
2.7
3.0
3.3
3.6
2.1
2.4
2.7
3.0
3.3
3.6
AVERAGE OUTPUT POWER (dBm)
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
EFFICIENCY vs. SUPPLY VOLTAGE
EFFICIENCY vs. SUPPLY VOLTAGE
40
35
30
25
20
40
35
30
25
20
f
= 315MHz
f
= 434MHz
RF
RF
T
= -40°C
A
T
= -40°C
A
T
= +25°C
A
T
= +25°C
= +85°C
A
T
A
T
= +85°C
A
T
= +125°C
A
T
= +125°C
A
2.1
2.4
2.7
3.0
3.3
3.6
2.1
2.4
2.7
3.0
3.3
3.6
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
8
_______________________________________________________________________________________
Low-Cost, 308MHz, 315MHz, and 433.92MHz
ASK Transceiver with Fractional-N PLL
Typical Operating Characteristics (continued)
(Typical Operating Circuit, PAV
= AV
= DV
= HV = +3.0V, f
= 433.92MHz, IF BW = 280kHz. 4kbps Manchester
RF
DD
DD
DD
IN
= +25°C, uTnlResAs oNthSerMwisIeTnToEteRd.)
encoded, 0.2% BER deviation = 50kHz, T
A
PHASE NOISE vs. OFFSET FREQUENCY
(TRANSMIT MODE)
PHASE NOISE vs. OFFSET FREQUENCY
(TRANSMIT MODE)
-40
-50
-40
-50
f
= 315MHz
f
= 434MHz
RF
RF
-60
-60
-70
-70
-80
-80
-90
-90
-100
-110
-120
-130
-140
-100
-110
-120
-130
-140
100
1k
10k
100k
1M
10M
100
1k
10k
100k
1M
10M
OFFSET FREQUENCY (Hz)
OFFSET FREQUENCY (Hz)
REFERENCE SPUR MAGNITUDE
vs. SUPPLY VOLTAGE
FREQUENCY STABILITY
vs. SUPPLY VOLTAGE
-40
-45
-50
-55
-60
-65
-70
10
8
6
434MHz
315MHz
f
f
= 315MHz
= 434MHz
RF
RF
4
2
0
-2
-4
-6
-8
-10
2.1
2.4
2.7
3.0
3.3
3.6
2.1
2.4
2.7
3.0
3.3
3.6
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
_______________________________________________________________________________________
9
Low-Cost, 308MHz, 315MHz, and 433.92MHz
FSK Transceiver with Fractional-N PLL
Pin Description
PIN
NAME
PAV
FUNCTION
Power-Amplifier Supply Voltage. Bypass to GND with 0.01µF and 220pF capacitors placed as close
to the pin as possible.
1
DD
Envelope-Shaping Output. ROUT controls the power-amplifier envelope’s rise and fall times. Connect
ROUT to the PA pullup inductor or optional power-adjust resistor. Bypass the inductor to GND as
close to the inductor as possible with 680pF and 220pF capacitors as shown in the Typical
Application Circuit.
2
ROUT
Transmit/Receive Switch Throw. Drive T/R high to short TX/RX1 to TX/RX2. Drive T/R low to disconnect
TX/RX1 from TX/RX2. Functionally identical to TX/RX2.
3
4
5
TX/RX1
TX/RX2
PAOUT
Transmit/Receive Switch Pole. Typically connected to ground. See the Typical Application Circuit.
Power-Amplifier Output. Requires a pullup inductor to the supply voltage (or ROUT if envelope
shaping is desired), which can be part of the output-matching network to an antenna.
Analog Power-Supply Voltage. AV
is connected to an on-chip +3.0V regulator in 5V operation.
DD
6
7
8
AV
DD
Bypass AV
to GND with a 0.1µF and 220pF capacitor placed as close to the pin as possible.
DD
LNAIN
Low-Noise Amplifier Input. Must be AC-coupled.
Low-Noise Amplifier Source for External Inductive Degeneration. Connect an inductor to GND to set
the LNA input impedance.
LNASRC
Low-Noise Amplifier Output. Must be connected to AV
to MIXIN+.
through a parallel LC tank filter. AC-couple
DD
9
LNAOUT
10
11
12
13
14
15
16
17
18
19
20
21
MIXIN+
MIXIN-
MIXOUT
IFIN-
Noninverting Mixer Input. Must be AC-coupled to the LNA output.
Inverting Mixer Input. Bypass to AV with a capacitor as close to the LNA LC tank filter as possible.
DD
330Ω Mixer Output. Connect to the input of the 10.7MHz filter.
Inverting 330Ω IF Limiter Amplifier Input. Bypass to GND with a capacitor.
Noninverting 330Ω IF Limiter Amplifier Input. Connect to the output of the 10.7MHz IF filter.
Minimum-Level Peak Detector for Demodulator Output
Maximum-Level Peak Detector for Demodulator Output
Inverting Data Slicer Input
IFIN+
PDMIN
PDMAX
DS-
DS+
Noninverting Data Slicer Input
OP+
Noninverting Op-Amp Input for the Sallen-Key Data Filter
Data-Filter Feedback Node. Input for the feedback capacitor of the Sallen-Key data filter.
Buffered Received-Signal-Strength-Indicator Output
DF
RSSI
Transmit/Receive. Drive high to put the device in transmit mode. Drive low or leave unconnected to
put the device in receive mode. It is internally pulled down.
22
23
T/R
Enable. Drive high for normal operation. Drive low or leave unconnected to put the device into
shutdown mode.
ENABLE
24
25
DATA
N.C.
Receiver Data Output/Transmitter Data Input
No Connection. Do not connect to this pin.
Digital Power-Supply Voltage. Bypass to GND with a 0.01µF and 220pF capacitor placed as close to
the pin as possible.
26
DV
DD
High-Voltage Supply Input. For 3V operation, connect HV to AV , PAV , and DV . For 5V
IN
DD
DD
DD
27
HV
operation, tie only HV to 5V. Bypass HV to GND with a 0.01µF and 220pF capacitor placed as
IN
IN
IN
close to the pin as possible.
10 ______________________________________________________________________________________
Low-Cost, 308MHz, 315MHz, and 433.92MHz
FSK Transceiver with Fractional-N PLL
Pin Description (continued)
PIN
28
29
30
31
32
EP
NAME
FUNCTION
AUTOCAL Enable for FSK demodulator autocalibration (~1min cycle). Bypass to GND with a 10pF capacitor.
AGC1
AGC0
XTAL1
XTAL2
GND
AGC Enable/Dwell Time Control 1. See Table 1. Bypass to GND with a 10pF capacitor.
AGC Enable/Dwell Time Control 0 (LSB). See Table 1. Bypass to GND with a 10pF capacitor.
Crystal Input 1. Bypass to GND if XTAL2 is driven by an AC-coupled external reference.
Crystal Input 2. XTAL2 can be driven from an external AC-coupled reference.
Exposed Paddle. Solder evenly to the board’s ground plane for proper operation.
where L
PARASITICS
= L5 + L
and C
= C9 +
TOTAL
PARASITICS
TOTAL
Detailed Description
C
.
The MAX7031 308MHz, 315MHz, and 433.92MHz
CMOS transceiver and a few external components pro-
vide a complete transmit and receive chain from the
antenna to the digital data interface. This device is
designed for transmitting and receiving FSK data. All
transmit frequencies are generated by a fractional-N-
based synthesizer, allowing for very fine frequency
L
and C
include inductance and
PARASITICS
PARASITICS
capacitance of the PC board traces, package pins,
mixer input impedance, LNA output impedance, etc.
These parasitics at high frequencies cannot be
ignored, and can have a dramatic effect on the tank fil-
ter center frequency. Lab experimentation should be
done to optimize the center frequency of the tank. The
parasitic capacitance is generally 5pF to 7pF.
steps in increments of f
/ 4096. The receive local
XTAL
oscillator (LO) is generated by a traditional integer-N-
based synthesizer. Depending on component selec-
tion, data rates as high as 33kbps (Manchester
encoded) or 66kbps (NRZ encoded) can be achieved.
Automatic Gain Control (AGC)
When the AGC is enabled, it monitors the RSSI output.
When the RSSI output reaches 1.28V, which corre-
sponds to an RF input level of approximately -55dBm,
the AGC switches on the LNA gain-reduction attenua-
tor. The attenuator reduces the LNA gain by 36dB,
thereby reducing the RSSI output by about 540mV to
740mV. The LNA resumes high-gain mode when the
RSSI output level drops back below 680mV (approxi-
mately -59dBm at the RF input) for a programmable
interval called the AGC dwell time (see Table 1). The
AGC has a hysteresis of approximately 4dB. With the
AGC function, the RSSI dynamic range is increased.
AGC is not necessary for most FSK applications.
Receiver
Low-Noise Amplifier (LNA)
The LNA is a cascode amplifier with off-chip inductive
degeneration that achieves approximately 30dB of volt-
age gain that is dependent on both the antenna-match-
ing network at the LNA input, and the LC tank network
between the LNA output and the mixer inputs.
The off-chip inductive degeneration is achieved by
connecting an inductor from LNASRC to AGND. This
inductor sets the real part of the input impedances at
LNAIN, allowing for a more flexible match for low-input
impedances such as a PC board trace antenna. A
nominal value for this inductor with a 50Ω input imped-
ance is 12nH at 315MHz and 10nH at 434MHz, but the
inductance is affected by PC board trace length.
LNASRC can be shorted to ground to increase sensitiv-
ity by approximately 1dB, but the input match must
then be reoptimized.
AGC Dwell Time Settings
The AGC dwell timer holds the AGC in a low-gain state
for a set amount of time after the power level drops
below the AGC switching threshold. After that set
amount of time, if the power level is still below the AGC
threshold, the LNA goes into high-gain state.
The LC tank filter connected to LNAOUT consists of L5
and C9 (see the Typical Application Circuit). Select L5
and C9 to resonate at the desired RF input frequency.
The resonant frequency is given by:
1
f =
2π L
× C
TOTAL
TOTAL
______________________________________________________________________________________ 11
Low-Cost, 308MHz, 315MHz, and 433.92MHz
FSK Transceiver with Fractional-N PLL
then combines these signals to achieve a typical 46dB
Table 1. AGC Dwell Time Settings for
of image rejection over the full temperature range. Low-
MAX7031
side injection is required as high-side injection is not
possible due to the on-chip image rejection. The IF out-
put is driven by a source follower, biased to create a
driving impedance of 330Ω to interface with an off-chip
330Ω ceramic IF filter. The voltage conversion gain dri-
ving a 330Ω load is approximately 20dB. Note that the
MIXIN+ and MIXIN- inputs are functionally identical.
AGC1 AGC0
DESCRIPTION
AGC disabled, high gain selected
K = 11, short dwell time
0
0
1
1
0
1
0
1
K = 14, medium dwell time
K = 20, long dwell time
Integer-N, Phase-Locked Loop (PLL)
The MAX7031 utilizes a fixed integer-N PLL to generate
the receive LO. All PLL components, including the loop
filter, voltage-controlled oscillator, charge pump, asyn-
chronous 24x divider, and phase-frequency detector
are internal. The loop bandwidth is approximately
500kHz. The relationship between RF, IF, and reference
frequencies is given by:
The MAX7031 uses the two AGC control pins (AGC0
and AGC1) to enable or disable the AGC and set three
user-controlled dwell timer settings. The AGC dwell
time is dependent on the crystal frequency and the bit
settings of the AGC control pins. To calculate the dwell
time, use the following equation:
K
2
Dwell Time =
f
= (f - f ) / 24
RF IF
REF
f
XTAL
Intermediate Frequency (IF)
where K is an integer in decimal, determined by the
control pin settings shown in Table 1.
The IF section presents a differential 330Ω load to pro-
vide matching for the off-chip ceramic filter. The inter-
nal six AC-coupled limiting amplifiers produce an
overall gain of approximately 65dB, with a bandpass fil-
ter-type response centered near the 10.7MHz IF fre-
quency with a 3dB bandwidth of approximately 10MHz.
The RSSI circuit demodulates the IF to baseband by
producing a DC output proportional to the log of the IF
signal level with a slope of approximately 15mV/dB.
For example, a receiver operating at 315MHz has a
crystal oscillator frequency of 12.679MHz. For K = 11
(AGC setting = 0, 1), the dwell timer is 162µs; for K =
14 (AGC setting = 1, 0), the dwell timer is 1.3ms; for K
= 20 (AGC setting = 1, 1), the dwell time is 83ms.
Mixer
A unique feature of the MAX7031 is the integrated
image rejection of the mixer. This eliminates the need
for a costly front-end SAW filter for many applications.
The advantage of not using a SAW filter is increased
sensitivity, simplified antenna matching, less board
space, and lower cost.
FSK Demodulator
The FSK demodulator uses an integrated 10.7MHz PLL
that tracks the input RF modulation and converts the
frequency deviation into a voltage difference. The PLL
is illustrated in Figure 1. The input to the PLL comes
from the output of the IF limiting amplifiers. The PLL
control voltage responds to changes in the frequency
of the input signal with a nominal gain of 2.0mV/kHz.
For example, an FSK peak-to-peak deviation of 50kHz
The mixer cell is a pair of double-balanced mixers that
perform an IQ downconversion of the RF input to the
10.7MHz intermediate frequency (IF) with low-side
injection (i.e., f = f - f ). The image-rejection circuit
LO
RF IF
FSK
DEMOD
MAX7031
TO FSK BASEBAND FILTER
AND DATA SLICER
PHASE
DETECTOR
IF
CHARGE
PUMP
LOOP
FILTER
100kΩ
100kΩ
LIMITING
AMPS
10.7MHz VCO
2.0mV/kHz
DS+
OP+
DF
C
C
F1
F2
Figure 1. FSK Demodulator PLL Block Diagram
Figure 2. Sallen-Key Lowpass Data Filter
12 ______________________________________________________________________________________
Low-Cost, 308MHz, 315MHz, and 433.92MHz
FSK Transceiver with Fractional-N PLL
MAX7031
MAX7031
PEAK
DET
PEAK
DET
DATA
SLICER
DATA
SLICER
DATA
DS-
DS+
R
DATA
PDMAX
PDMIN
R
R
C
C
C
Figure 3. Generating Data Slicer Threshold Using a Lowpass
Filter
Figure 4. Generating Data Slicer Threshold Using the Peak
Detectors
generates a 100mV
control voltage is then filtered and sliced by the base-
band circuitry.
signal on the control line. This
The configuration shown in Figure 2 can create a
Butterworth or Bessel response. The Butterworth filter
offers a very-flat-amplitude response in the passband
and a rolloff rate of 40dB/decade for the two-pole filter.
The Bessel filter has a linear phase response, which
works well for filtering digital data. To calculate the
value of the capacitors, use the following equations,
along with the coefficients in Table 2:
P-P
The FSK demodulator PLL requires calibration to over-
come variations in process, voltage, and temperature.
This is done by using the AUTOCAL pin, or by cycling
the ENABLE pin. If the AUTOCAL pin is a logic 1, cali-
bration occurs approximately every minute. If the
AUTOCAL pin is a logic 0, calibration occurs only after
the MAX7031 is enabled.
b
C
C
=
F1
a(100kΩ)(π)(f )
c
Data Filter
The data filter for the demodulated data is implemented
as a 2nd-order, lowpass Sallen-Key filter. The pole
locations are set by the combination of two on-chip
resistors and two external capacitors. Adjusting the
value of the external capacitors changes the corner fre-
quency to optimize for different data rates. Set the cor-
ner frequency in kHz to approximately 2 times the
fastest expected Manchester data rate in kbps from the
transmitter (1.0 times the fastest expected NRZ data
rate). Keeping the corner frequency near the data rate
rejects any noise at higher frequencies, resulting in an
increase in receiver sensitivity.
a
=
F2
4(100kΩ)(π)(f )
c
where f is the desired 3dB corner frequency.
C
For example, choose a Butterworth filter response with
a corner frequency of 5kHz:
1.000
C
C
=
≈ 450pF
F1
F2
(1.414)(100kΩ)(3.14)(5kHz)
1.414
=
≈ 225pF
(4)(100kΩ)(3.14)(5kHz)
Choosing standard capacitor values changes C to
F1
470pF and C to 220pF. In the Typical Application
F2
and C
Table 2. Coefficients to Calculate C
F1
Circuit, C
are named C16 and C17,
F2
F1
and C
F2
respectively.
FILTER TYPE
a
b
Butterworth
(Q = 0.707)
1.414
1.000
Bessel
(Q = 0.577)
1.3617
0.618
______________________________________________________________________________________ 13
Low-Cost, 308MHz, 315MHz, and 433.92MHz
FSK Transceiver with Fractional-N PLL
Data Slicer
The data slicer takes the analog output of the data filter
and converts it to a digital signal. This is achieved by
using a comparator and comparing the analog input to
a threshold voltage. The threshold voltage is set by the
voltage on the DS- pin, which is connected to the nega-
tive input of the data-slicer comparator.
switch occurs, or by forcing the peak detectors to track
the baseband filter output voltage until all internal cir-
cuits are stable following an enable pin low-to-high
transition. The peak detectors exhibit a fast attack/slow
decay response. This feature allows for an extremely
fast startup or AGC recovery.
Transmitter
Numerous configurations can be used to generate the
data-slicer threshold. For example, the circuit in Figure
3 shows a simple method using only one resistor and
one capacitor. This configuration averages the analog
output of the filter and sets the threshold to approxi-
mately 50% of that amplitude. With this configuration,
the threshold automatically adjusts as the analog signal
varies, minimizing the possibility for errors in the digital
data. The values of R and C affect how fast the thresh-
old tracks the analog amplitude. Be sure to keep the
corner frequency of the RC circuit much lower (about
10 times) than the lowest expected data rate.
Power Amplifier (PA)
The PA of the MAX7031 is a high-efficiency, open-
drain, Class C amplifier. The PA with proper output-
matching network can drive a wide range of antenna
impedances, which includes a small-loop PC board
trace and a 50Ω antenna. The output-matching network
for a 50Ω antenna is shown in the Typical Application
Circuit. The output-matching network suppresses the
carrier harmonics and transforms the antenna imped-
ance to an optimal impedance at PAOUT (pin 5). The
optimal impedance at PAOUT is 250Ω.
When the output-matching network is properly tuned,
the PA transmits power with a high overall efficiency of
up to 32%. The efficiency of the PA itself is more than
46%. The output power is set by an external resistor at
PAOUT, and is also dependent on the external antenna
and antenna-matching network at the PA output.
With this configuration, a long string of NRZ zeros or
ones can cause the threshold to drift. This configuration
works best if a coding scheme, such as Manchester
coding, which has an equal number of zeros and ones,
is used.
Figure 4 shows a configuration that uses the positive and
negative peak detectors to generate the threshold. This
configuration sets the threshold to the midpoint between
a high output and a low output of the data filter.
Envelope Shaping
The MAX7031 features an internal envelope-shaping
resistor, which connects between the open-drain output
of the PA and the power supply. The envelope-shaping
resistor slows the turn-on/turn-off of the PA. Envelope
shaping is not necessary for FSK. For most applica-
Peak Detectors
The maximum peak detector (PDMAX) and minimum
peak detector (PDMIN), with resistors and capacitors
shown in Figure 4, create DC output voltages equal to
the high- and low-peak values of the filtered demodulat-
ed signal. The resistors provide a path for the capaci-
tors to discharge, allowing the peak detectors to
dynamically follow peak changes of the data filter out-
put voltages.
tions, the PA pullup inductor should be tied to PAV
instead of ROUT.
DD
Fractional-N Phase-Locked Loop (PLL)
The MAX7031 utilizes a fully integrated, fractional-N
PLL for its transmit frequency synthesizer. All PLL com-
ponents, including the loop filter, are integrated inter-
nally. The loop bandwidth is approximately 200kHz.
The maximum and minimum peak detectors can be
used together to form a data slicer threshold voltage at
a value midway between the maximum and minimum
voltage levels of the data stream (see the Data Slicer
section and Figure 4). Set the RC time constant of the
peak-detector combining network to at least 5 times the
data period.
Power-Supply Connections
The MAX7031 can be powered from a 2.1V to 3.6V sup-
ply or a 4.5V to 5.5V supply. If a 4.5V to 5.5V supply is
used, then the on-chip linear regulator reduces the 5V
supply to the 3V needed to operate the chip.
To operate the MAX7031 from a 3V supply, connect
If there is an event that causes a significant change in
the magnitude of the baseband signal, such as an AGC
gain switch or a power-up transient, the peak detectors
may “catch” a false level. If a false peak is detected,
the slicing level is incorrect. The MAX7031 peak detec-
tors correct these problems by temporarily tracking the
incoming baseband filter voltage when an AGC state
PAV , AV , DV , and HV to the 3V supply. When
DD
DD
DD
IN
using a 5V supply, connect the supply to HV only and
IN
connect AV , PAV , and DV together. In both
DD
DD
DD
cases, bypass PAV , DV , and HV to GND with a
DD
DD
IN
0.01µF and 220pF capacitor and bypass AV
with a 0.1µF and 220pF capacitor. Bypass T/R,
to GND
DD
14 ______________________________________________________________________________________
Low-Cost, 308MHz, 315MHz, and 433.92MHz
FSK Transceiver with Fractional-N PLL
ENABLE, DATA, AGC0-1, and AUTOCAL with 10pF
capacitors to GND. Place all bypass capacitors as
close to the respective pins as possible.
In actuality, the oscillator pulls every crystal. The crys-
tal’s natural frequency is really below its specified fre-
quency, but when loaded with the specified load
capacitance, the crystal is pulled and oscillates at its
specified frequency. This pulling is already accounted
for in the specification of the load capacitance.
Transmit/Receive Antenna Switch
The MAX7031 features an internal SPST RF switch that,
when combined with a few external components, allows
the transmit and receive pins to share a common
antenna (see the Typical Application Circuit). In receive
mode, the switch is open and the power amplifier is
shut down, presenting a high impedance to minimize
the loading of the LNA. In transmit mode, the switch
closes to complete a resonant tank circuit at the PA
output and forms an RF short at the input to the LNA. In
this mode, the external passive components couple the
output of the PA to the antenna to protect the LNA input
from strong transmitted signals.
Additional pulling can be calculated if the electrical
parameters of the crystal are known. The frequency
pulling is given by:
C
2
1
+ C
1
6
m
f
=
−
x 10
P
C
C
+ C
SPEC
CASE
LOAD
CASE
where:
f is the amount the crystal frequency is pulled in ppm.
P
Cm is the motional capacitance of the crystal.
The switch state is controlled by the T/R pin (pin 22).
Drive T/R high to put the device in transmit mode; drive
T/R low to put the device in receive mode.
C
C
C
is the case capacitance.
CASE
SPEC
LOAD
is the specified load capacitance.
is the actual load capacitance.
Crystal Oscillator (XTAL)
The XTAL oscillator in the MAX7031 is designed to pre-
sent a capacitance of approximately 3pF between the
XTAL1 and XTAL2 pins. In most cases, this corre-
sponds to a 4.5pF load capacitance applied to the
external crystal when typical PC board parasitics are
added. It is very important to use a crystal with a
load capacitance that is equal to the capacitance of
the MAX7031 crystal oscillator plus PC board para-
sitics. If a crystal designed to oscillate with a different
load capacitance is used, the crystal is pulled away
from its stated operating frequency, introducing an
error in the reference frequency. Crystals designed to
operate with higher differential load capacitance
always pull the reference frequency higher.
When the crystal is loaded as specified, i.e., C
SPEC
=
LOAD
C
, the frequency pulling equals zero.
Chip Information
Pin Configuration
PROCESS: CMOS
TOP VIEW
24 23 22 21 20 19 18 17
25
26
27
28
29
30
31
32
N.C.
DV
PDMAX
PDMIN
IFIN+
16
15
14
13
DD
HV
IN
AUTOCAL
IFIN-
12 MIXOUT
MAX7031
AGC1
AGC0
XTAL1
XTAL2
11
MIXIN-
10
MIXIN+
9
LNAOUT
1
7
8
2
3
4
6
5
THIN QFN
______________________________________________________________________________________ 15
Low-Cost, 308MHz, 315MHz, and 433.92MHz
FSK Transceiver with Fractional-N PLL
Typical Application Circuit
AGC0
AGC1
AUTOCAL
V
DD
Y1
V
DD
3.0V
C18
C19
C20
C21
DD
C23
C24
V
DD
32
31
30
29
28
27
26
25
1
2
PAV
24
23
22
21
DATA
DATA
ENABLE
T/R
C22
ROUT
ENABLE
R3*
TRANSMIT/
RECEIVE
3
4
5
TX/RX1
TX/RX2
C2
C1
RSSI
DF
L1
MAX7031
20
19
PAOUT
C3
C5
V
DD
L2
EXPOSED
PADDLE
6
OP+
DS+
DS-
C4
AV
DD
C16
C17
C6
L6
C7
18
17
C8
L3
7
8
LNAIN
LNASRC
L4
9
10
11
12
13
C13
15
16
14
R1
C15
C10
C12
V
C9
DD
L5
R2
IN GND
Y2
OUT
C14
C11
*OPTIONAL POWER-ADJUST RESISTOR
Selector Guide
CARRIER
FSK DEVIATION
PART
MAX7031LATJ
FREQUENCY (MHz) FREQUENCY (kHz)
308
315
51.413
15.477
49.528
17.221
51.663
MAX7031MATJ15
MAX7031MATJ50
MAX7031HATJ17
MAX7031HATJ51
315
433.92
433.92
16 ______________________________________________________________________________________
Low-Cost, 308MHz, 315MHz, and 433.92MHz
FSK Transceiver with Fractional-N PLL
Table 3. Component Values for Typical Application Circuit
VALUE FOR
433.92MHz RF
VALUE FOR
315MHz RF
COMPONENT
DESCRIPTION
C1
C2
220pF
680pF
6.8pF
6.8pF
10pF
220pF
680pF
12pF
10%
10%
C3
5%
C4
10pF
5%
C5
22pF
5%
C6
220pF
0.1µF
220pF
0.1µF
10%
C7
10%
C8
100pF
1.8pF
100pF
220pF
100pF
1500pF
0.047µF
0.047µF
470pF
220pF
220pF
0.01µF
100pF
100pF
220pF
0.01µF
0.01µF
22nH
100pF
2.7pF
100pF
220pF
100pF
1500pF
0.047µF
0.047µF
470pF
220pF
220pF
0.01µF
100pF
100pF
220pF
0.01µF
0.01µF
27nH
5%
C9
0.1pF
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
C21
C22
C23
C24
L1
5%
10%
5%
10%
10%
10%
10%
10%
10%
10%
5%
5%
10%
10%
10%
Coilcraft 0603CS
Coilcraft 0603CS
Coilcraft 0603CS
Coilcraft 0603CS
Murata LQW18A
Coilcraft 0603CS
5%
L2
22nH
30nH
L3
22nH
30nH
L4
10nH
12nH
L5
16nH
30nH
L6
68nH
100nH
100kΩ
100kΩ
0Ω
R1
100kΩ
100kΩ
0Ω
R2
5%
R3
—
Crystal, 4.5pF load
capacitance
Y1
17.63416MHz
12.67917MHz
Y2
10.7MHz ceramic filter
10.7MHz ceramic filter
Murata SFECV10.7 series
Note: Component values vary depending on PC board layout.
______________________________________________________________________________________ 17
Low-Cost, 308MHz, 315MHz, and 433.92MHz
FSK Transceiver with Fractional-N PLL
Functional Diagram
LNAOUT MIXIN+ MIXIN-
10 11
MIXOUT
12
IFIN+ IFIN-
9
14
13
IF LIMITING
AMPS
0°
7
8
LNAIN
LNA
FSK
DEMODULATOR
Σ
LNASRC
90°
RSSI
DF
20
I
Q
100kΩ
100kΩ
RX VCO
19
21
OP+
RX
RSSI
FREQUENCY
DIVIDER
DATA FILTER
18 DS+
XTAL1
XTAL2
31
32
TX
CRYSTAL
OSCILLATOR
PHASE
DETECTOR
FREQUENCY
DIVIDER
15 PDMIN
CHARGE
PUMP
PDMAX
DS-
16
17
TX VCO
∆Σ
MODULATOR
3.0V
REGULATOR
HV
IN
27
6
LOOP FILTER
RX
DATA
AV
DD
EXPOSED
PADDLE
AGC0
30
29
28
24
MAX7031
PA
AGC1
DIGITAL LOGIC
AUTOCAL
DATA
23
ENABLE
5
2
1
3
22
T/R
26
DV
4
ROUT
PAV
PAOUT
TX/RX1
TX/RX2
DD
DD
18 ______________________________________________________________________________________
Low-Cost, 308MHz, 315MHz, and 433.92MHz
FSK Transceiver with Fractional-N PLL
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
D2
D
b
0.10 M
C A B
C
L
D2/2
D/2
k
L
MARKING
AAAAA
E/2
E2/2
C
(NE-1) X
e
L
E2
E
PIN # 1 I.D.
0.35x45°
DETAIL A
e/2
PIN # 1
I.D.
e
(ND-1) X
e
DETAIL B
e
L
C
L
C
L
L1
L
L
e
e
0.10
C
A
0.08
C
C
A3
A1
PACKAGE OUTLINE,
16, 20, 28, 32, 40L THIN QFN, 5x5x0.8mm
1
-DRAWING NOT TO SCALE-
I
21-0140
2
COMMON DIMENSIONS
20L 5x5 28L 5x5
EXPOSED PAD VARIATIONS
D2 E2
MIN. NOM. MAX. MIN. NOM. MAX.
3.00 3.10 3.20 3.00 3.10 3.20
3.00 3.10 3.20 3.00 3.10 3.20
PKG.
SYMBOL MIN. NOM. MAX. MIN. NOM. MAX. MIN. NOM. MAX. MIN. NOM. MAX. MIN. NOM. MAX.
16L 5x5
32L 5x5
40L 5x5
L
DOWN
BONDS
ALLOWED
YES
NO
exceptions
PKG.
CODES
±0.15
A
0.70 0.75 0.80 0.70 0.75 0.80 0.70 0.75 0.80 0.70 0.75 0.80 0.70 0.75 0.80
0.02 0.05 0.02 0.05 0.02 0.05 0.02 0.05 0.02 0.05
0.20 REF. 0.20 REF. 0.20 REF. 0.20 REF. 0.20 REF.
T1655-2
T1655-3
**
**
**
**
A1
0
0
0
0
0
A3
b
T1655N-1 3.00 3.10 3.20 3.00 3.10 3.20
NO
0.25 0.30 0.35 0.25 0.30 0.35 0.20 0.25 0.30 0.20 0.25 0.30 0.15 0.20 0.25
4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10
4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10
T2055-3
T2055-4
T2055-5
T2855-3
3.00 3.10 3.20 3.00 3.10 3.20
3.00 3.10 3.20 3.00 3.10 3.20
YES
D
E
NO
**
YES
3.15 3.25 3.35 3.15 3.25 3.35 0.40
e
0.80 BSC.
0.25
0.65 BSC.
0.25
0.50 BSC.
0.25
0.50 BSC.
0.25
0.40 BSC.
3.15 3.25 3.35 3.15 3.25 3.35
YES
YES
NO
**
**
**
k
-
-
-
-
-
-
-
-
0.25 0.35 0.45
T2855-4
T2855-5
2.60 2.70 2.80 2.60 2.70 2.80
2.60 2.70 2.80 2.60 2.70 2.80
3.15 3.25 3.35 3.15 3.25 3.35
L
0.30 0.40 0.50 0.45 0.55 0.65 0.45 0.55 0.65 0.30 0.40 0.50 0.40 0.50 0.60
L1
-
-
-
-
-
-
-
-
-
-
-
-
0.30 0.40 0.50
NO
YES
YES
T2855-6
T2855-7
**
**
N
ND
NE
16
4
4
20
5
28
7
32
8
8
40
10
10
2.80
2.60 2.70
2.60 2.70 2.80
5
7
T2855-8
3.15 3.25 3.35 3.15 3.25 3.35 0.40
WHHB
WHHC
WHHD-1
WHHD-2
-----
JEDEC
T2855N-1 3.15 3.25 3.35 3.15 3.25 3.35
NO
YES
NO
YES
NO
**
**
**
**
**
**
3.20
3.00 3.10 3.20
T3255-3
T3255-4
T3255-5
3.00 3.10
3.00 3.10 3.20 3.00 3.10 3.20
3.20
NOTES:
3.00 3.10
3.00 3.10 3.20
1. DIMENSIONING & TOLERANCING CONFORM TO ASME Y14.5M-1994.
2. ALL DIMENSIONS ARE IN MILLIMETERS. ANGLES ARE IN DEGREES.
3. N IS THE TOTAL NUMBER OF TERMINALS.
T3255N-1 3.00 3.10 3.20 3.00 3.10 3.20
T4055-1 3.20 3.30 3.40 3.20 3.30 3.40
YES
**SEE COMMON DIMENSIONS TABLE
4. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL
CONFORM TO JESD 95-1 SPP-012. DETAILS OF TERMINAL #1 IDENTIFIER ARE
OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE TERMINAL #1
IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE.
5. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN
0.25 mm AND 0.30 mm FROM TERMINAL TIP.
6. ND AND NE REFER TO THE NUMBER OF TERMINALS ON EACH D AND E SIDE RESPECTIVELY.
7. DEPOPULATION IS POSSIBLE IN A SYMMETRICAL FASHION.
8. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS.
9. DRAWING CONFORMS TO JEDEC MO220, EXCEPT EXPOSED PAD DIMENSION FOR
T2855-3 AND T2855-6.
10. WARPAGE SHALL NOT EXCEED 0.10 mm.
11. MARKING IS FOR PACKAGE ORIENTATION REFERENCE ONLY.
12. NUMBER OF LEADS SHOWN ARE FOR REFERENCE ONLY.
13. LEAD CENTERLINES TO BE AT TRUE POSITION AS DEFINED BY BASIC DIMENSION "e", ±0.05.
PACKAGE OUTLINE,
16, 20, 28, 32, 40L THIN QFN, 5x5x0.8mm
2
-DRAWING NOT TO SCALE-
21-0140
I
2
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 19
© 2005 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products, Inc.
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