MAX695CWE+T [MAXIM]
Power Supply Management Circuit, Fixed, 1 Channel, CMOS, PDSO16, SOP-16;
| 型号： | MAX695CWE+T |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Power Supply Management Circuit, Fixed, 1 Channel, CMOS, PDSO16, SOP-16 光电二极管 |
| 文件： | 总18页 (文件大小：875K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MAX690–MAX695
Microprocessor Supervisory Circuits
General Description
Benefits and Features
● Supervisory Function Integration Saves Board Space
while Fully Protecting Microprocessor-Based Systems
• Precision Voltage Monitor
The MAX690 family of supervisory circuits reduces the
complexity and number of components required for
power supply monitoring and battery control functions in
microprocessor systems. These include µP reset and
backup-battery switchover, watchdog timer, CMOS RAM
write protection, and power-failure warning. The MAX690
family significantly improves system reliability and accu-
racy compared to that obtainable with separate ICs or
discrete components.
- 4.65V (MAX690, MAX691, MAX694, MAX695)
- 4.40V (MAX692, MAX693)
• Power OK/Reset Time Delay
- 50ms, 200ms, or Adjustable
• Watchdog Timer
- 100ms, 1.6s, or Adjustable
• Battery Backup Power Switching
• Voltage Monitor for Power Fail or Low Battery
Warning
The MAX690, MAX692, and MAX694 are supplied in
8-pin packages and provide four functions:
● A reset output during power-up, power-down, and
• Minimum External Component Count
brownout conditions.
● Low Power Consumption in Battery Backup Mode
Extends Battery Life
● Battery backup switching for CMOS RAM, CMOS
microprocessor or other low power logic.
• 1µA Standby Current
● A Reset pulse if the optional watchdog timer has not
● Onboard Gating of Chip Enable Signals Protects
been toggled within a specified time.
Against Erroneous Data Written to RAM During Low
● A 1.3V threshold detector for power fail warning, low
battery detection, or to monitor a power supply other
than +5V.
V
Events
CC
Applications
● Computers
● Controllers
● Intelligent Instruments
● Automotive Systems
● Critical µP Power Monitoring
TheMAX691,MAX693,andMAX695aresuppliedin16-pin
packages and perform all MAX690, MAX692, MAX694
functions, plus:
● Write protection of CMOS RAM or EEPROM.
● Adjustable reset and watchdog timeout periods.
● Separate outputs for indicating a watchdog timeout,
Ordering information appears at end of data sheet.
backup-battery switchover, and low V
.
Pin Configurations
CC
TOP VIEW
V
1
2
3
4
8
7
6
5
V
BATT
OUT
Typical Operating Circuit
MAX690
MAX692
MAX694
V
RESET
WDI
CC
GND
PFI
PFO
+5V
V
V
V
POWER TO
CMOS RAM
µP
POWER
CC
OUT
BATT
V
1
2
3
4
5
6
7
8
16 RESET
15 RESET
14 WDO
13 CE IN
12 CE OUT
11 WDI
BATT
µP
SYSTEM
V
OUT
MAX690
V
CC
MAX691
MAX693
MAX695
RESET
PFO
µP RESET
PFI
GND
BATT ON
LOW LINE
OSC IN
µP NMI
WDI
I/O
LINE
GND
10 PFO
OSC SEL
9 PFI
MAX690 TYPICAL APPLICATION
19-0218; Rev 5; 4/15
MAX690–MAX695
Microprocessor Supervisory Circuits
Absolute Maximum Ratings
Terminal Voltage (with respect to GND)
Power Dissipation
V
V
...................................................................-0.3V to +6.0V
8-Pin Plastic DIP
(derate 5mW/°C above +70°C) ....................................400mV
8-Pin CERDIP
(derate 8mW/°C above +85°C) ....................................500mV
16-Pin Plastic DIP
(derate 7mW/°C above +70°C) ....................................600mV
16-Pin Small Outline
CC
...............................................................-0.3V to +6.0V
BATT
All Other Inputs (Note 1) ................... -0.3V to (V
Input Current
+ 0.5V)
OUT
V
V
...............................................................................200mA
.............................................................................50mA
CC
BATT
GND ...............................................................................20mA
Output Current
(derate 7mW/°C above +70°C) ....................................600mV
16-Pin CERDIP
V
.....................................................Short circuit protected
OUT
All Other Outputs............................................................20mA
Rate-of-Rise, V , V ..............................................100V/µs
Operating Temperature Range
(derate 10mW/°C above +85°C) ..................................600mV
Storage Temperature Range............................ -65°C to +160°C
Lead Temperature (Soldering, 10s)...................................300°C
BATT CC
C suffix................................................................0°C to +70°C
E suffix............................................................ -40°C to +85°C
M suffix ......................................................... -55°C to +125°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Electrical Characteristics
V
= full operating range, V
= 2.8V, T = +25°C, unless otherwise noted.)
CC
BATT A
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
BATTERY BACKUP SWITCHING
Operating Voltage Range
(MAX690, MAX691, MAX694, MAX695 V
4.75
2.0
4.5
2.0
5.5
4.25
5.5
)
CC
Operating Voltage Range (MAX690, MAX691,
MAX694, MAX695 V
)
BATT
V
Operating Voltage Range
(MAX692, MAX693 V
)
CC
Operating Voltage Range
4.0
(MAX692, MAX693 V
)
BATT
V
-
V
-
CC
0.3
CC
0.1
I
I
I
= 1mA
OUT
OUT
OUT
V
Output Voltage
V
V
OUT
OUT
V
CC
0.5
-
V
0.25
-
CC
= 50mA
= 250µA, V
V
V
BATT
- 0.02
BATT
V
in Battery Backup Mode
< V
- 0.2V
CC
BATT
- 0.1
I
I
= 1mA
2
5
10
OUT
Supply Current (Excluded I
)
mA
µA
OUT
= 50mA
3.5
0.6
OUT
Supply Current in Battery Backup Mode
V
= 0V, V
= 2.8V
1
CC
BATT
T
= +25°C
-0.1
-1.0
+0.02
A
A
Battery Standby Current
(+ = Discharge, - = Charge)
5.5V > V
CC
>
µA
T
= full operating
V
+ 1V
+0.02
BATT
range
Power-up
Power-down
70
50
Battery Switchover Threshold
mV
(V
- V
)
CC
BATT
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MAX690–MAX695
Microprocessor Supervisory Circuits
Electrical Characteristics (continued)
V
= full operating range, V
= 2.8V, T = +25°C, unless otherwise noted.)
CC
BATT A
PARAMETER
CONDITIONS
MIN
TYP
MAX
0.4
UNITS
mV
V
Battery Switchover Hysteresis
BATT ON Output Voltage
20
I
= 3.2mA
SINK
BATT ON = V
= 4.5V sink current
25
1
mA
µA
OUT
BATT ON Output Short-Circuit Current
BATT ON = 0V source current
0.5
25
RESET AND WATCHDOG TIMER
MAX690, MAX691,
MAX694, MAX695
4.5
4.65
4.75
4.5
T
= full
A
Reset Voltage Threshold
V
operating range
MAX692, MAX693
4.25
4.4
40
Reset Threshold Hysteresis
mV
ms
Reset Timeout Delay (MAX690/MAX691/
MAX692/MAX693)
Figure 6, OSC SEL HIGH, V
Figure 6, OSC SEL HIGH, V
= 5V
= 5V
35
50
70
CC
Reset Timeout Delay (MAX694/MAX695)
140
1.0
200
1.6
280
2.25
140
ms
s
CC
Long period, V
= 5V
= 5V
CC
Watchdog Timeout Period, Internal Oscillator
Short period, V
Long period
Short period
70
100
ms
CC
3840
768
200
4097
1025
Clock
Cycles
Watchdog Timeout Period, External Clock
Minimum WDI Input Pulse Width
V
= 0.4, V = 0.8V
CC
ns
V
IL
IH
I
I
I
I
= 1.6mA, V
= 4.25V
0.4
0.4
SINK
CC
RESET and LOW LINE Output Voltage
= 1µA, V
= 1µA, V
= 5V
3.5
SOURCE
CC
= 1.6mA
SINK
RESET and WDO Output Voltage
V
µA
V
= 5V
3.5
1
SOURCE
CC
Output Short-Circuit Current
WDI Input Threshold Logic-Low
WDI Input Threshold Logic-High
RESET, RESET, WDO, LOW LINE
3
25
V
= 5V (Note 2)
= 5V (Note 2)
0.8
CC
CC
V
3.5
-50
1.2
WDI = V
20
50
OUT
WDI Input Current
µA
WDI = 0V
-15
POWER-FAIL DETECTOR
PFI Threshold
V
= 5V, T = full
1.3
1.4
±25
0.4
V
nA
V
CC
A
PFI Current
±0.01
I
I
= 3.2mA
SINK
PFO Output Voltage
= 1µA
3.5
1
V
SOURCE
PFO Short Circuit Source Current
PFI = V , PFO = 0V
3
25
µA
IH
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MAX690–MAX695
Microprocessor Supervisory Circuits
Electrical Characteristics (continued)
V
= full operating range, V
= 2.8V, T = +25°C, unless otherwise noted.)
CC
BATT A
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
CHIP ENABLE GATING
V
V
0.8
IL
CE IN Thresholds
V
3.0
IH
CE IN Pullup Current
3
µA
I
I
I
= 3.2mA
0.4
SINK
CE OUT Output Voltage
= 3.0mA
V
- 1.5
V
SOURCE
SOURCE
OUT
= 1µA, V
= 0V
V
- 0.05
50
CC
OUT
CE Propagation Delay
OSCILLATOR
V
= 5V
200
ns
CC
OSC IN Input Current
OSC SEL Input Pullup Current
OSC IN Frequency Range
±2
5
µA
µA
OSC SEL = 0V
OSC SEL = 0V
0
250
kHz
OSC IN Frequency
with External Capacitor
4
kHz
C
= 47pF
OSC
Note 1: The input voltage limits on PFI and WDI may be exceeded provided the input current is limited to less than 10mA.
Note 2: WDI is guaranteed to be in the mid-level (inactive) state if WDI is floating and V is in the operating voltage range. WDI is
CC
internally biased to 38% of V
with an impedance of approximately 125kΩ.
CC
Pin Description
PIN
MAX690/
MAX692/
MAX694
MAX691/
MAX693/
MAX695
NAME
FUNCTION
2
8
3
1
V
The +5V Input
Backup Battery Input. Connect to Ground if a backup battery is not used.
The higher of V or V is internally switched to V . Connect V
CC
V
BATT
to V
CC
if
CC
BATT
OUT
OUT
1
3
2
4
V
OUT
V
and V
are not used. Connect a 0.1µF or larger bypass capacitor to V
.
OUT
OUT
BATT
GND
0V Ground Reference for All Signals
RESET goes low whenever V falls below either the reset voltage threshold or the
CC
V
input voltage. The reset threshold is typically 4.65V for the MAX690/691/694/695,
BATT
and 4.4V for the MAX692 and MAX693. RESET remains low for 50ms after V
returns
CC
7
15
RESET
to 5V, (except 200ms in MAX694/695). RESET also goes low for 50ms if the Watchdog
Timer is enabled but not serviced within its timeout period. The RESET pulse width can
be adjusted as shown in Table 1.
Watchdog Input (WDI). WDI is a three level input. If WDI remains either high or low for
longer than the watchdog timeout period, RESET pulses low and WDO goes low. The
Watchdog Timer is disabled when WDI is left floating or is driven to mid-supply. The
timer resets with each transition at the Watchdog Timer input.
6
4
11
9
WDI
PFI
Noninverting Input to the Power-Fail Comparator. When PFI is less than 1.3V, PFO
goes low. Connect PFI to GND or V
when not used. See Figure 1.
OUT
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MAX690–MAX695
Microprocessor Supervisory Circuits
Pin Description (continued)
PIN
MAX690/
MAX692/
MAX694
MAX691/
MAX693/
MAX695
NAME
FUNCTION
Output of the Power-Fail Comparator. It goes low when PFI is less than 1.3V. The
5
10
13
12
PFO
CE IN
comparator is turned off and PFO goes low when V
is below V
.
BATT
CC
—
—
CE Gating Circuit Input. Connect to GND or V
if not used.
OUT
CE OUT goes low only when CE IN is low and V
is above the reset threshold (4.65V
CC
CE OUT
for MAX691 and MAX695, 4.4V for MAX693). See Figure 6.
BATT ON goes high when V is internally switched to the V
input. It goes low
BATT
OUT
when V
is internally switched to V . The output typically sinks 25mA and can
OUT
CC
—
5
BATT ON
directly drive the base of an external PNP transistor to increase the output current
above the 50mA rating of V
.
OUT
LOW LINE goes low when V
falls below the reset threshold. It returns high as soon
CC
—
—
6
LOW LINE
as V
rises above the reset threshold. See Figure 6, Reset Timing.
CC
16
RESET
Active-High Output. It is the inverse of RESET.
When OSC SEL is unconnected or driven high, the internal oscillator sets the reset time
delay and watchdog timeout period. When OSC SEL is low, the external oscillator input,
OSC IN, is enabled. OSC SEL has a 3µA internal pullup. See Table 1.
—
8
OSC SEL
When OSC SEL is low, OSC IN can be driven by an external clock to adjust both the
reset delay and the watchdog timeout period. The timing can also be adjusted by
connecting and external oscillator to this pin. See Figure 8. When OSC SEL is high or
floating, OSC IN selects between fast and slow Watchdog timeout periods.
—
7
OSC IN
The Watchdog Output (WDO). WDO goes low if WDI remains either high or low for
longer than the watchdog timeout period. WDO is set high by the next transition at WDI.
If WDI is unconnected or at mid-supply, WDO remains high. WDO also goes high when
LOW LINE goes low.
—
14
WDO
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MAX690–MAX695
Microprocessor Supervisory Circuits
power-up RESET pulse lasts 50ms* to allow for this
oscillator start-up time. The manual reset switch and
the 0.1µF capacitor connected to the reset bus can be
omitted if manual reset is not needed. An inverted, active
high, RESET output is also supplied.
Typical Applications
MAX691, MAX693, and MAX695
A typical connection for the MAX691/693/695 is shown
in Figure 1. CMOS RAM is powered from V
. V
is
OUT OUT
internally connected to V
when 5V power is present,
CC
Power-Fail Detector
or to V
when V
is less than the battery voltage.
BATT
CC
The MAX691/93/95 issues a nonmaskable interrupt (NMI)
to the microprocessor when a power failure occurs. The
+5V power line is monitored via two external resistors
connected to the power-fail input (PFI). When the volt-
age at PFI falls below 1.3V, the power-fail output (PFO)
drives the processor’s NMI input low. If a power-fail
threshold of 4.8V is chosen, the microprocessor will
V
can supply 50mA from V , but if more current
OUT
CC
is required, an external PNP transistor can be added.
When V is higher than V , the BATT ON output
goes low, providing 25mA of base drive for the external
transistor. When V is lower than V , an internal
200Ω MOSFET connects the backup battery to V
CC
BATT
CC
BATT
.
OUT
The quiescent current in the battery backup mode is 1µA
have the time when V
fails from 4.8V to 4.65V to save
maximum when V
is between 0V and V –700mV.
BATT
CC
CC
data into RAM. An earlier power-fail warning can be
generated if the unregulated DC input of the 5V regulator
is available for monitoring.
Reset Output
A voltage detector monitors V
and generates a RESET
CC
output to hold the microprocessor’s Reset line low when
is below 4.65V (4.4V for MAX693). An internal
RAM Write Protection
V
CC
The MAX691/MAX693/MAX695 CE OUT line drives the
Chip Select inputs of the CMOS RAM. CE OUT follows
monostable holds RESET low for 50ms* after V
rises
CC
above 4.65V (4.4V for MAX693). This prevents repeated
toggling of RESET even if the 5V power drops out and
recovers with each power line cycle.
CE IN as long as V
is above the 4.65V (4.4V for
CC
MAX693) reset threshold. If V
falls below the reset
CC
threshold, CE OUT goes high, independent of the logic
level at CE IN. This prevents the microprocessor from
writing erroneous data into RAM during power-up, power-
down, brownouts, and momentary power interruptions.
The crystal oscillator normally used to generate the clock
for microprocessors takes several milliseconds to start.
Since most microprocessors need several clock cycles
to reset, RESET must be held low until the micropro-
cessor clock oscillator has started. The MAX690 family
The LOW LINE output goes low when V
falls below
CC
4.65V (4.4V for MAX693).
*200ms for MAX695
+5V
V
CC
INPUT
0.1µF
0.1µF
3
5
V
BATT ON
CC
2
1
9
V
V
OUT
CMOS
RAM
BATT
3V
12
13
CE OUT
CE IN
BATTERY
ADDRESS
DECODE
PFI
MAX691
MAX693
MAX695
A0-A15
11
10
15
4
WDI
PFO
I/O
NMI
GND
7
8
OSC IN
NO CONNECTION
RESET
RESET
OSC SEL
RESET
LOW LINE
WDO
14
MICROPROCESSOR
0.1µF
6
AUDIBLE
ALARM
SYSTEM STATUS INDICATORS
OTHER SYSTEM RESET SOURCES
Figure 1. MAX691/693/695 Typical Application
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MAX690–MAX695
Microprocessor Supervisory Circuits
application. Operation is much the same as with the
MAX691/MAX693/MAX695 (Figure 1), but in this case, the
power- fail input (PFI) monitors the unregulated input to the
7805 regulator. The MAX690/MAX694 RESET output goes
Watchdog Timer
The microprocessor drives the WATCHDOG INPUT
(WDI) with an I/O line. When OSC IN and OSC SEL are
unconnected, the microprocessor must toggle the WDI
pin once every 1.6s to verify proper software execution. If
a hardware or software failure occurs such that WDI not
toggled the MAX691/MAX693 will issue a 50ms* RESET
pulse after 1.6s. This typically restarts the microproces-
sor’s power-up routine. A new RESET pulse is issued
every 1.6s until the WDI is again strobed.
low when V
falls below 4.65V. The RESET output of the
CC
MAX692 goes low when V
drops below 4.4V.
CC
The current consumption of the battery-backed-up power
bus must be less than 50mA. The MAX690/MAX692/
MAX694 does not have a BATT ON output to drive an
external transistor. The MAX690/MAX692/MAX694 also
does not include chip enable gating circuitry that is avail-
able on the MAX690/MAX692/MAX694. In many systems
though, CE gating is not needed since a low input to
the microprocessor RESET line prevents the processor
from writing to RAM during power-up and power-down
transients.
The WATCHDOG OUTPUT (WDO) goes low if the
watchdog timer is not serviced within its timeout period.
Once WDO goes low it remains low until a transition
occurs at WDI. The watchdog timer feature can be dis-
abled by leaving WDI unconnected. OSC IN and OSC
SEL also allow other watchdog timing options, as shown
in Table 1 and Figure 8.
The MAX690/MAX692/MAX694 watchdog timer has a
fixed 1.6s timeout period. If WDI remains either low or
high for more than 1.6s, a RESET pulse is sent to the
microprocessor. The watchdog timer is disabled if WDI is
left unconnected.
MAX690, MAX692, and MAX694
The 8 pin MAX690, MAX692, and MAX694 have most
of the features of the MAX691, MAX693, and MAX695.
Figure 2 shows the MAX690/MAX692/MAX694 in a typical
*200ms for MAX695
POWER
TO
CMOS
RAM
MICRO-
PROCESSOR
POWER
+8V
+5V
7805
3-TERMINAL
REGULATOR
0.1µF
2
1
V
V
OUT
CC
0.1µF
MAX690
MAX692
MAX694
8
7
V
BATT
MICROPROCESSOR
4
PFI
RESET
PFO
RESET
5
6
NMI
WDI
I/O LINE
GND
3
Figure 2. MAX690/692/694 Typical Application
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MAX690–MAX695
Microprocessor Supervisory Circuits
levels required for battery backup of CMOS RAM or other
Detailed Description
low power CMOS circuitry. When V
equals V
the
CC
BATT
Battery-Switchover and V
The battery switchover circuit compares V
OUT
supply current is typically 12µA. When V
is between
CC
to the V
BATT
0V and (V
- 700mV) the typical supply current is only
CC
BATT
input, and connects V
occurs when V
CC
to whichever is higher. Switchover
is 50mV greater than V as V falls,
BATT
600nA typical, 1µA maximum.
OUT
CC
rises (see
The MAX690/MAX691/MAX694/MAX695 operate with
battery voltages from 2.0V to 4.25V while MAX692/
MAX693 operate with battery voltages from 2.0V to
4.0V. High value capacitors can also be used for short-
term memory backup. External circuitry is required to
ensure that the capacitor voltage does not rise above
the reset threshold, and that the charging resistor does
not discharge the capacitor when in backup mode. The
MAX691A and the MAX791 provide solutions requiring
fewer external components.
and V
is 70mV more than V
as V
CC
BATT
CC
Figure 4). The switchover comparator has 20mV of hyster-
esis to prevent repeated, rapid switching if V falls very
CC
slowly or remains nearly equal to the battery voltage.
When V is higher than V , V is internally
CC
BATT
CC
switched to V
via a low saturation PNP transis-
OUT
tor. V
has 50mA output current capability. Use an
OUT
external PNP pass transistor in parallel with internal tran-
sistor if the output current requirement at V exceeds
OUT
50mA or if a lower V -V
voltage differential is
CC OUT
A small charging current of typically 10nA (0.1µA max)
desired. The BATT ON output (MAX691/MAX693/MAX695
only) can directly drive the base of the external transistor.
flows out of the V
terminal. This current varies with the
BATT
amount of current that is drawn from V
but its polarity
OUT
It should be noted that the MAX690–MAX695 need only
supply the average current drawn by the CMOS RAM if
there is adequate filtering. Many RAM data sheets specify
a 75mA maximum supply current, but this peak current
is such that the backup battery is always slightly charged,
and is never discharged while V is in its operating volt-
CC
age range. This extends the shelf life of the backup battery
by compensating for its self-discharge current. Also note
that this current poses no problem when lithium batteries
are used for backup since the maximum charging current
(0.1µA) is safe for even the smallest lithium cells.
spike lasts only 100ns. A 0.1µF bypass capacitor at V
OUT
supplies the high instantaneous current, while V
need
OUT
only supply the average load current, which is much less.
A capacitance of 0.1µF or greater must be connected to
If the battery-switchover section is not used, connect
the V
terminal to ensure stability.
OUT
V
to GND and connect V to V . Table 2 shows
OUT CC
BATT
A 200Ω MOSFET connects V
input to V
during
OUT
the state of the inputs and output in the low power battery
backup mode.
BATT
battery backup. This MOSFET has very low input-to-
output differential (dropout voltage) at the low current
V
BATT
1
5
BATT ON
2
+
-
V
OUT
3
V
CC
12
6
CHIP ENABLE OUTPUT
LOW LINE
13
CHIP-ENABLE INPUT
+
-
15
16
*
RESET
RESET
*4.4V (MAX693)
4.65V
RESET GENERATOR
7
TIMEBASE FOR RESET
AND
OSC IN
8
OSC SEL
WATCHDOG
14
10
WATCHDOG
TIMER
WATCHDOG OUTPUT
POWER FAIL OUTPUT
11
WATCHDOG TRANSITION
DETECTOR
WATCHDOG INPUT
9
POWER FAIL
INPUT
+
-
1.3V
4
GROUND
Figure 3. MAX691/MAX693/MAX695 Block Diagram
Maxim Integrated
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MAX690–MAX695
Microprocessor Supervisory Circuits
V
CC
+5V
TO CMOS
RAM AND
REALTIME
V
V
OUT
CC
CLOCK
0.1F
V
IN
CC
P CHANNEL
MOSFET
BASE DRIVE
100
mV
+
-
BATT ON
(MAX691, MAX693, MAX695 ONLY)
3V
BATTERY
INPUT
-
700
mV
INTERNAL
SHUTDOWN
SIGNAL WHEN
+
-
LOW IQ MODE
SELECT
+
V
> V + 0.7V
BATT
CC
Figure 4. Battery-Switchover Block Diagram
Reset Output
CE Gating and RAM Write Protection
RESET is an active-low output which goes low when-
ever V falls below 4.5V (MAX690/MAX691/MAX694/
The MAX691/MAX693/MAX695 use two pins to control
the Chip Enable or Write inputs of CMOS RAMs. When
CC
MAX695) or 4.25V (MAX692/MAX693). It will remain low
V
is +5V, CE OUT is a buffered replica of CE IN, with
CC
until V rises above 4.75V (MAX690/691/694/695) or 4.5V
a 50ns propagation delay. If V
input falls below 4.65V
CC
CC
(MAX692/MAX693) for milliseconds*. See Figures 5 and 6.
(4.5V min, 4.75V max) an internal gate forces CE OUT
high, independent of CE IN. The MAX693 CE OUT goes
The guaranteed minimum and maximum thresholds of
MAX690/MAX691/MAX694/MAX695 are 4.5V and 4.75V,
while the guaranteed thresholds of the MAX692/MAX693
are 4.25V and 4.5V. The MAX690/MAX691/MAX694/
MAX695 is compatible with 5V supplies with a +10%, -5%
tolerance while the MAX692/MAX693 is compatible with
5V ±10% supplies. The reset threshold comparator has
approximately 50mV of hysteresis, with a nominal thresh-
old of 4.65V in the MAX690/MAX691/MAX694/MAX695,
and 4.4V in the MAX692/MAX693.
high whenever V
is below 4.4V (4.25V min, 4.5V max).
CC
The CE output of both devices is also forced high when
is less than V . (See Figure 5.)
V
CC
BATT
CE OUT typically drives the CE, CS, or Write input of
battery backed up CMOS RAM. This ensures the integ-
rity of the data in memory by preventing write operations
when V
is at and invalid level. Similar protection of
CC
EEPROMs can be achieved by using the CE OUT to
drive the Store or Write inputs of an EEPROM, EAROM,
or NOVRAM.
The response time of the reset voltage comparator is
about 100µs. V
glitches do not activate the RESET output.
should be bypassed to ensure that
If the 50ns typical propagation delay of CE OUT is too
long, connect CE IN to GND and use the resulting CE
OUT to control a high speed external logic gate. A second
alternative is to AND the LOW LINE output with the CE or
WR signal. An external logic gate and the RESET output
of the MAX690/MAX692/MAX694 can also be used for
CMOS RAM write protection.
CC
RESET also goes low if the watchdog timer is enabled
and WDI remains either high or low longer than the watch-
dog timeout period. RESET has an internal 3µA pullup,
and can either connect to and open collector Reset bus
or directly drive a CMOS gate without and external pullup
resistor.
*200ms for MAX694 and MAX695
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MAX690–MAX695
Microprocessor Supervisory Circuits
CE IN
CE OUT
LOW LINE
V
CC
RESET
POWER-ON
RESET
METAL
LINK
TRIMMED
RESISTORS
+
-
RESET RESET
RESET
Q
R
TIME
1.3V
WATCHDOG
FROM
WATCHDOG
TIMER
10 kHz CLOCK
FROM TIMEBASE
SECTION
Figure 5. Reset Block Diagram
4.7V
4.6V
4.7V
4.6V
V
CC
50ms*
50ms*
RESET
OUTPUT
LOW LINE
OUTPUT
CE IN
CE IN
V
OUT
- V
BATT
*200ms FOR MAX694 AND MAX695
Figure 6. Reset Timing
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MAX690–MAX695
Microprocessor Supervisory Circuits
at the end of reset, whether the reset was caused by
1.3V Comparator and Power-Fail Warning
lack of activity on WDI or by V
falling below the reset
CC
The power-fail input (PFI) is compared to an internal
1.3V reference. The power-fail output (PFO) goes low
when the voltage at PFI is less than 1.3V. Typically, PFI is
driven by an external voltage divider which senses either
the unregulated DC input to the system’s 5V regulator or
the regulated 5V output. The voltage divider ratio can be
chosen such that the voltage at PFI falls below 1.3V sev-
eral milliseconds before the +5V supply falls below 4.75V.
PFO is normally used to interrupt the microprocessor so
threshold. If WDI remains either high or low, reset pulses
will be issued every 1.6s. The watchdog monitor can be
deactivated by floating the watchdog input (WDI).
The watchdog output (WDO, MAX691/MAX693/MAX695
only) goes low if the watchdog timer times out and
remains low until set high by the next transition on the
watchdog input. WDO is also set high when V
goes
CC
below the reset threshold.
that data can be stored in RAM before V
falls below
CC
The watchdog timeout period is fixed at 1.6s and the
reset pulse width is fixed at 50ms* on the 8-pin MAX690/
MAX692/MAX694. The MAX691/MAX693/MAX695 allow
these times to be adjusted per Table 1. Figures 8 shows
various oscillator configurations.
4.75V and the RESET output goes low (4.5V for MAX692/
MAX693).
The power-fail detector can also monitor the backup bat-
tery to warn of a low battery condition. To conserve bat-
tery power, the power-fail detector comparator is turned
The internal oscillator is enabled when OSC SEL is
floating. In this mode, OSC IN selects between the
1.6s and 100ms watchdog timeout periods. In either
case, immediately after a reset the timeout period 1.6s.
This gives the microprocessors time to reintialize the
system. If OSC IN is low, then the 100ms watchdog
period becomes effective after the first transition of WDI.
The software should be written such that the I/O port
driving WDI is left in its power-up reset state until the ini-
tialization routines are completed and the microprocessor
is able to toggle WDI at the minimum watchdog timeout
period of 70ms.
off and PFO is forced when V
is lower than V
CC
BATT
input voltage.
Watchdog Timer and Oscillator
The watchdog circuit monitors the activity of the micro-
processor. If the microprocessor does not toggle the
Watchdog Input (WDI) within the selected timeout period,
a 50ms* RESET pulse is generated. Since many systems
cannot service the watchdog timer immediately after a
reset, the MAX691/MAX693/MAX695 has a longer time-
out period after reset is issued. The normal timeout period
becomes effective following the first transition of WDI after
RESET has gone high. The watchdog timer is restarted
*200ms for MAX694
10.24 kHz FROM INTERNAL OSCILLATOR
OR EXTERNALLY SET FREQUENCY FROM
OSC IN PIN
PRESCALER
Q6
WATCHDOG INPUT
V
CC
2.7V
WATCHDOG TIMEOUT SELECT
HI IF WATCHDOG
INPUT IS FLOATING
+
-
RESET
COUNTER
WATCHDOG
WATCHDOG
COUNTER
TIMEOUT
Q11
-
SELECTOR
Q13
LOGIC
Q15
R
Q10/12
R
+
1.0V
GOES HIGH AT THE
END OF WATCHDOG
TIMEOUT PERIOD
TRANSACTION
DETECTOR
FOR EACH TRANSITION
S
R
S
Q
R
S
LOW LINE
(HI IF V < 4.65V)
CC
WATCHDOG
FAULT FF
RESET
FLIP FLOP
LONG/SHORT
LOW
LINE
FF
Q
Q
R
Q
RESET RESET
WATCHDOG OUTPUT
Figure 7. Watchdog Timer Block Diagram
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MAX690–MAX695
Microprocessor Supervisory Circuits
EXTERNAL CLOCK
OSC SEL
EXTERNAL OSCILLATOR
8
7
8
OSC SEL
MAX691
MAX693
MAX695
MAX691
MAX693
MAX695
0 TO 250kHz
7
OSC IN
OSC IN
C
OSC
INTERNAL OSCILLATOR
1.6s WATCHDOG
INTERNAL OSCILLATOR
100ms WATCHDOG
8
7
8
7
N.C.
N.C.
N.C.
OSC SEL
OSC SEL
MAX691
MAX693
MAX695
MAX691
MAX693
MAX695
OSC IN
OSC IN
Figure 8. Oscillator Circuits
Table 1. MAX691/MAX693/MAX695 Reset Pulse Width and Watchdog Timeout Selections
WATCHDOG TIMEOUT PERIOD
RESET TIMEOUT PERIOD
OSC SEL
OSC IN
IMMEDIATELY
NORMAL
MAX691/MAX693
MAX695
AFTER REST
Low
External Clock Input
External Capacitor
1024 clks
4096 clks
512 clks
2048 clks
Low
400ms/47pF x C
1.6s/47pF x C
200ms/47pF x C
800ms/47pF x C
Floating
Floating
Low
100ms
1.6s
1.6s
1.6s
50ms
50ms
200ms
200ms
Floating
Note 1: The MAX690/MAX692/MAX694 watchdog timeout period is fixed at 1.6s nominal, the MAX690/692 reset pulse width is fixed
at 50ms nominal and the MAX694 is 200ms nominal.
Note 2: When the MAX691 OSC SEL pin is low, OSC IN can be driven by an external clock signal or an external capacitor can be
connected between OSC IN and GND. The nominal internal oscillator frequency is 6.55kHz. The nominal oscillator frequency
with capacitor is:
120,000
f
(Hz) =
OSC
C(pF)
Note 3: See Electrical Characteristics table for minimum and maximum timing values.
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MAX690–MAX695
Microprocessor Supervisory Circuits
Adding Hysteresis
to the Power Fail Comparator
Application Hints
Other Uses of the Power-Fail Detector
Since the power fail comparator circuit is noninvert-
ing, hysteresis can be added by connecting a resistor
between the PFO output and the PFI input as shown in
Figure 12. When PFO is low, resistor R3 sinks current
from the summing junction at the PFI pin. When PFO is
high, the series combination of R3 and R4 source current
into the PFI summing junction.
In Figure 9, the power-fail detector is used to initiate a
system reset when V
falls to 4.85V. Since the thresh-
CC
old of the power-fail detector is not as accurate as the
onboard reset-voltage detector, a trimpot must be used
to adjust the voltage detection threshold. Both the PFO
and RESET outputs have high sink current capability and
only 10µA of source current drive. This allows the two
outputs to be connected directly to each other in a wired
OR fashion.
Alternate Watchdog Input Drive Circuits
The Watchdog feature can be enabled and disabled
under program control by driving WDI with a three-state
buffer (Figure 13). The drawback to this circuit is that a
software fault may be erroneously three-state the buffer,
thereby preventing the MAX690 from detecting that the
microprocessor is no longer working. In most cases a bet-
ter method is to extend the watchdog period rather than
disabling the watchdog. See Figure 14. When the control
input is high, the OSC SEL pin is low and the watchdog
timeout is set by the external capacitor. A 0.01µF capaci-
tor sets a watchdog timeout delay of 100s. When the
control input is low the OSC SEL pin is high, selecting
the internal oscillator. The 100ms or the 1.6s period is
chosen, depending on which diode in Figure 14 is used.
The overvoltage detector circuit in Figure 10 resets the
microprocessor whenever the nominal 5V V
is above
CC
5.5V. The battery monitor circuit (Figure 11) shows the
status of the memory backup battery. If desired, the CE
OUT can be used to apply a test load to the battery. Since
CE OUT is forced high during the battery backup mode,
the test load will not be applied to the battery while it is in
use even if the microprocessor is not powered.
+5V
+5V
V
CC
V
CC
TO µP
RESET
INPUT
TO µP
RESET
INPUT
29.4kΩ
2kΩ
35.7kΩ
2kΩ
RESET
PFO
RESET
PFO
MAX690
MAX691
MAX692
MAX693
MAX694
MAX695
MAX690
MAX691
MAX692
MAX693
MAX694
MAX695
PFI
PFI
N-CHANNEL
10kΩ
10kΩ
GND
GND
Figure 9. Externally Adjustable V
Reset Threshold
Figure 10. Reset on Overvoltage or Undervoltage
CC
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MAX690–MAX695
Microprocessor Supervisory Circuits
7V TO 15V
+5V
V
CC
7805
MAX690
MAX691
MAX692
MAX693
MAX694
MAX695
R4
10kΩ
+5V
PFO
R1
75kΩ
V
LOW BATTERY
SIGNAL TO
µP I/O PIN
CC
PFO
V
BATT
MAX690
MAX691
MAX692
MAX693
MAX694
MAX695
10MΩ
10MΩ
PFI
GND
PFI
R2
13kΩ
R3
300kΩ
TO P
LOW
FROM µP
I/O PIN
CE OUT
CE IN
APPLIES
LOAD
TO BATTERY
GND
R1 R1
R
L
V
= 9.125V
V
= 1.3V 1 +
+
)
H
H
(
R2 R3
V = 7.9V
L
R1 (5V -1.3V) R1
-
HYSTERESIS = 1.23V
V = 1.3V 1 +
L
(
)
R2 1.3V (R3 + R4)
R1
HYSTERESIS 5V x
R3
ASSUMING R4 < < R3
Figure 11. Backup VBattery Monitor with Optional Test Load
Figure 12. Adding Hysteresis to the Power-Fail Voltage
Comparator
+5V
+5V
V
CC
V
LOW = INTERNAL
WATCHDOG TIMEOUT
CC
OSC SEL
MAX690
MAX691
MAX692
MAX693
MAX694
MAX695
HI = EXTERNAL
WATCHDOG
TIMEOUE
MAX691
MAX693
WATCHDOG
STROBE
EN
WDI
OSC IN
CONNECT FOR
100ms TIMEOUT
WHEN INTERNAL
TIMEOUT IS
WATCHDOG
DISABLE
GND
GND
SELECTED
CONNECT FOR
1.6s INTERNAL
TIMEOUT
Figure 13. Disabling the Watchdog Under Program Control
Figure 14. Selecting Internal or External Watchdog Timeout
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MAX690–MAX695
Microprocessor Supervisory Circuits
Table 2. Input and Output Status In Battery Backup Mode
V
, V
V
is connected to V
via internal MOSFET.
OUT
BATT OUT
BATT
RESET
Logic-low
RESET
Logic-high. The open circuit output voltage is equal to V
.
OUT
LOW LINE
BATT ON
Logic-low
Logic-high
WDI is internally disconnected from its internal pullup and does not source or sink current as long as its input
WDI
voltage is between GND and V
. The input voltage does not affect the source current.
OUT
WDO
PFI
Logic-high
The power-fail comparator is turned off and the power-fail input voltage has no effect on the power-fail output.
Logic-low
PFO
CE IN is internally disconnected from its internal pullup and does not source or sink current as long as its input
CE IN
voltage is between GND and V
. The input voltage does not affect the source current.
OUT
CE OUT
OSC IN
Logic-high
OSC IN is ignored.
OSC SEL is ignored.
OSC SEL
Approximately 12µA is drawn from the V
The supply current is 1µA maximum when V
input when V
is between V
+100mV and V
- 700mV.
BATT
BATT
CC
BATT
V
CC
is less than V
- 700mV.
CC
BATT
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MAX690–MAX695
Microprocessor Supervisory Circuits
Ordering Information
PART
MAX690CPA
MAX690C/D
MAX690EPA
MAX690EJA
MAX690MJA
MAX691CPE
MAX691CWE
MAX691C/D
MAX691EPE
MAX691EWE
MAX691EJE
MAX691MJE
MAX692C/D
MAX692CPA
MAX692EPA
MAX692EJA
MAX692MJA
MAX693C/D
TEMP RANGE
PIN-PACKAGE
8 Lead Plastic DIP
Dice*
PART
MAX693CPE
MAX693CWE
MAX693EPE
MAX693EJE
MAX693EWE
MAX693MJE
MAX694C/D
MAX694CPA
MAX694EPA
MAX694EJA
MAX694MJA
MAX695C/D
MAX695CPE
MAX695CWE
MAX695EPE
MAX695EJE
MAX695EWE
MAX695MJE
TEMP RANGE
0°C to +70°C
0°C to +70°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
PIN-PACKAGE
0°C to +70°C
0°C to +70°C
-40°C to +85°C
-40°C to +85°C
16 Lead Plastic DIP
16 Lead Wide SO
16 Lead Plastic DIP
16 Lead CERDIP
16 Lead Wide SO
8 Lead Plastic DIP
8 Lead CERDIP
-55°C to +125°C 8 Lead CERDIP
0°C to +70°C
0°C to +70°C
0°C to +70°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
16 Lead Plastic DIP
16 Lead Wide SO
Dice*
-55°C to +125°C 16 Lead CERDIP
0°C to +70°C
0°C to +70°C
-40°C to +85°C
-40°C to +85°C
Dice
8 Lead Plastic DIP
8 Lead Plastic DIP
8 Lead CERDIP
16 Lead Plastic DIP
16 Lead Wide SO
16 Lead CERDIP
-55°C to +125°C 8 Lead CERDIP
-55°C to +125°C 16 Lead CERDIP
0°C to +70°C
0°C to +70°C
0°C to +70°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
Dice
0°C to +70°C
0°C to +70°C
-40°C to +85°C
-40°C to +85°C
Dice
16 Lead Plastic DIP
16 Lead Wide SO
16 Lead Plastic DIP
16 Lead CERDIP
16 Lead Wide SO
8 Lead Plastic DIP
8 Lead Plastic DIP
8 Lead CERDIP
-55°C to +125°C 8 Lead CERDIP
0°C to +70°C Dice
*Contact factory for dice specifications.
-55°C to +125°C 16 Lead CERDIP
Devices in PDIP and SO packages are available in both leaded and lead-free packaging. Specify lead free by adding the + symbol at
the end of the part number when ordering. Lead free not available for CERDIP package.
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MAX690–MAX695
Microprocessor Supervisory Circuits
Package Information
Chip Topography
For the latest package outline information and land patterns
(footprints), go to www.maximintegrated.com/packages. Note
that a “+”, “#”, or “-” in the package code indicates RoHS status
only. Package drawings may show a different suffix character, but
the drawing pertains to the package regardless of RoHS status.
V
V
V
RESET
16
RESET
CC
OUT
2
BATT
3
1
15
PACKAGE
TYPE
PACKAGE OUTLINE
LAND
PATTERN NO.
CODE
NO.
14
13
12
WDO
21-0043
21-0045
21-0043
21-0042
21-0043
8 PDIP
8 CEDIP
P8-2
—
—
—
—
—
CE IN
J8-2
0.122”
CE OUT
16 PDIP
P16-1
W16-1
P16-1
(3.098 mm)
16 Wide SO
16 CERDIP
4
5
GND
BATT
ON
6
7
8
9
10 11
LOW LINE
OSC OSC PFI PFO WDI
IN SEL
0.086”
(2.184 mm)
Maxim Integrated
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MAX690–MAX695
Microprocessor Supervisory Circuits
Revision History
REVISION
NUMBER
REVISION
DATE
PAGES
CHANGED
DESCRIPTION
Revised Benefits and Features section
5
4/15
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim Integrated’s website at www.maximintegrated.com.
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses
are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits)
shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
©
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.
2015 Maxim Integrated Products, Inc.
│ 18
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