MAX6959 [MAXIM]
2-Wire Interfaced, 3V to 5.5V, 4-Digit, 9-Segment LED Display Drivers with Keyscan; 2线接口， 3V至5.5V ， 4位，9段LED显示驱动器，带有键扫描
| 型号： | MAX6959 |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | 2-Wire Interfaced, 3V to 5.5V, 4-Digit, 9-Segment LED Display Drivers with Keyscan |
| 文件： | 总19页 (文件大小：270K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-2634; Rev 0; 10/02
2-Wire Interfaced, 3V to 5.5V, 4-Digit,
9-Segment LED Display Drivers with Keyscan
General Description
Features
o 400kbps 2-Wire Serial Interface
o 3V to 5.5V Operation
The MAX6958/MAX6959 compact multiplexed com-
mon-cathode display drivers interface microprocessors
to seven-segment numeric LED digits, or discrete LEDs
through an SMBus™- and I2C-compatible 2-wire serial
interface. The 2-wire serial interface uses fixed
0.8V/2.1V logic thresholds for compatibility with 2.5V
and 3.3V systems when the display driver is powered
from a 5V supply.
o Drive 4 Digits plus 4 or 8 Discrete LEDs
o Drive Common-Cathode LED Digits
o 23mA Constant-Current LED Segment Drive
o Hexadecimal Decode/No-Decode Digit Selection
o 64-Step Digital Brightness Control
The MAX6958/MAX6959 drive up to four 7-segment
digits, with decimal points, plus four discrete LEDs, or
four 7-segment digits and eight discrete LEDs if the
digits’ decimal points are not used, or up to 36 discrete
LEDs. The MAX6959 also includes two input ports, one
or both of which may be configured as a key-switch
reader, which automatically scans and debounces a
matrix of up to eight switches. Key-switch status is
obtained by polling internal status registers or by con-
figuring the MAX6959 interrupt output.
o Slew-Rate-Limited Segment Drivers Reduced EMI
o Debounces Up to Eight Switches with n-Key
Rollover (MAX6959 Only)
o IRQ Output When a Key Input Is Debounced
(MAX6959 Only)
o 20µA Low-Power Shutdown (Data Retained)
o Automotive Temperature Range (-40°C to +125°C)
o Compact 16-Pin PDIP and QSOP Packages
Other on-chip features include a hexadecimal font for
seven-segment displays, multiplex scan circuitry,
anode and cathode drivers, and static RAM that stores
each digit. The peak segment current for the display
digits is set internally to 23mA. Display intensity is
adjusted using a 64-step internal digital brightness con-
trol. The MAX6958/MAX6959 include a low-power shut-
down mode, a scan-limit register that allows the user to
display from one to four digits, and a test mode, which
forces all LEDs on. The LED drivers are slew-rate-limit-
ed to reduce EMI.
Ordering Information
TEMP
SLAVE
PIN-
PART
RANGE
ADDRESS PACKAGE
MAX6958AAEE -40°C to +125°C 0111000 16 QSOP-EP*
MAX6958AAPE -40°C to +125°C 0111000 16 DIP
Ordering Information continued at end of data sheet.
*EP = Exposed pad.
Typical Operating Circuit
The MAX6958/MAX6959 are available in 16-pin PDIP
and QSOP packages and are fully specified over the
-40°C to +125°C automotive temperature range.
8
8
8
8
µC
8
DIG0–DIG3
SEG0–SEG8
SDA
SCL
IRQ
SDA
SCL
Applications
5V
V+
IRQ/SEG9
Set-Top Boxes
Panel Meters
White Goods
Audio/Video Equipment
Vending Machines
Industrial Controls
MAX6959
INPUT1
INPUT2
GND
Key0
DIG0/SEG0
DIG1/SEG1
DIG2/SEG2
DIG3/SEG3
DIG4/SEG4
DIG5/SEG5
DIG6/SEG6
DIG7/SEG7
Key1
Key2
Key3
Key4
Key5
Key6
Key7
Pin Configuration, Functional Diagram, and Typical
Application Circuit appear at end of data sheet.
SMBus is a trademark of Intel Corp.
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
2-Wire Interfaced, 3V to 5.5V, 4-Digit,
9-Segment LED Display Drivers with Keyscan
ABSOLUTE MAXIMUM RATINGS
Voltage (with respect to GND)
Continuous Power Dissipation (T = +70°C)
A
V+, SCL, SDA.......................................................-0.3V to +6V
All Other Pins............................................-0.3V to (V+ + 0.3V)
Current
16-Pin DIP (derate at 10.5mW/°C above +70°C).........842mW
16-Pin QSOP (derate at 8.34mW/°C above +70°C).....667mW
Operating Temperature Range
DIG0/SEG0–DIG3/SEG3 Sink Current ..........................275mA
DIG0/SEG0–SEG9 Source Current .................................30mA
SCL, SDA, INPUT1, INPUT2 ...........................................20mA
MAX695_ (T
to T
)...............................-40°C to +125°C
MIN
MAX
Junction Temperature......................................................+150°C
Storage Temperature Range.............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(V+ = 3V to 5.5V, T = T
to T
, unless otherwise noted. Typical values are at V+ = 5V, T = +25°C.) (Note 1)
MAX A
A
MIN
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
5.5
UNITS
Operating Supply Voltage
V+
3
V
T
T
T
= +25°C
20
50
A
A
A
Shutdown mode, all
digital inputs at V+
Shutdown Supply Current
Operating Supply Current
I
µA
SHDN
= T
to +85°C
125
6.7
MIN
= +25°C
5.9
Intensity set to full,
no display load
connected, INPUT1
and INPUT2 open
circuit
I+
mA
T
= T
to T
7.5
A
MIN
MAX
Display Scan Rate
f
4 digits scanned
T
T
T
T
T
T
= T
= T
to T
to T
510
30.3
-19
780
41
1050
63
Hz
ms
SCAN
t
DEBOUNCE
A
A
A
A
A
A
MIN
MAX
MAX
Keyscan Debounce Time
MIN
= +25°C
= T to T
-23
-29
V
= 2.4V,
LED
V+ = 4.5V to 5.5V
-18
-30
MIN
MAX
MAX
Segment Drive Source Current
Segment Current Slew Rate
I
mA
SEG
= +25°C
= T to T
-16
-29.5
-30.5
V
= 2V,
LED
V+ = 3V to 5.5V
-15.5
MIN
∆I
/∆t
SEG
11
4
mA/µs
%
Segment Drive Current Matching
∆I
SEG
LOGIC INPUTS AND OUTPUTS
Input Leakage Current SCL
and SDA
I
, I
-1
+1
µA
V
IH IL
Logic High Input Voltage SCL,
SDA
V
2.1
IH
Logic Low Input Voltage SCL,
SDA
V
0.8
+1
V
IL
Input Leakage Current INPUT1,
INPUT2
I
, I
INPUT_ = V+
-1
µA
V
INH INL
Logic High Input Voltage INPUT1,
INPUT2
0.7 ✕
V+
V
INH
Logic Low Input Voltage INPUT1,
INPUT2
0.3 ✕
V+
V
V
INL
2
_______________________________________________________________________________________
2-Wire Interfaced, 3V to 5.5V, 4-Digit,
9-Segment LED Display Drivers with Keyscan
DC ELECTRICAL CHARACTERISTICS (continued)
(V+ = 3V to 5.5V, T = T
to T
, unless otherwise noted. Typical values are at V+ = 5V, T = +25°C.) (Note 1)
MAX A
A
MIN
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Pullup to V+ INPUT1, INPUT2
I
26.5
µA
PULLUP
I
I
I
= 6mA, T = -40°C to +85°C
0.4
0.4
0.4
SINK
SINK
SINK
A
IRQ/SEG9, SDA Output Low
Voltage
V
V
V
OLBK
= 4mA, T = T
A
to T
MAX
MIN
SDA Output Low Voltage
V
= 6mA
OL(SDA)
TIMING CHARACTERISTICS
(V+ = 3V to 5.5V, T = T
to T
, Figure 1, unless otherwise noted.) (Note 1)
MAX
A
MIN
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Serial Clock Frequency
f
400
kHz
SCL
Bus Free Time Between a STOP
and a START Condition
t
1.3
0.6
µs
µs
BUF
Hold Time (Repeated) START
Condition
t
HD, STA
Repeated START Setup Time
STOP Condition Setup Time
Data Hold Time
t
0.6
0.6
µs
µs
µs
ns
µs
µs
SU, STA
SU, STO
HD, DAT
t
t
(Note 3)
0.9
Data Setup Time
t
100
1.3
0.6
SU, DAT
SCL Clock Low Period
SCL Clock High Period
t
LOW
t
HIGH
Rise Time of Both SDA and SCL
Signals, Receiving
20 +
t
(Notes 2, 4)
(Notes 2, 4)
300
300
250
ns
ns
R
0.1C
B
Fall Time of Both SDA and SCL
Signals, Receiving
20 +
0.1C
t
t
F
F
B
20 +
Fall Time of SDA Transmitting
(Notes 2, 5)
(Note 6)
ns
ns
pF
0.1C
B
Pulse Width of Spike Suppressed
t
SP
50
Capacitive Load for Each Bus
Line
C
400
B
Note 1: All parameters tested at T =+25°C. Specifications over temperature are guaranteed by design.
A
Note 2: Guaranteed by design.
Note 3: A master device must provide a hold time of at least 300ns for the SDA signal (referred to V of the SCL signal) in order to
IL
bridge the undefined region of SCL’s falling edge.
Note 4: C = total capacitance of one bus line in pF. t and t measured between 0.3V+ and 0.7V+.
B
R
F
Note 5: I
≤ 6mA. C = total capacitance of one bus line in pF. t and t measured between 0.3V+ and 0.7V+.
SINK
B R F
Note 6: Input filters on the SDA and SCL inputs suppress noise spikes less than 50ns.
_______________________________________________________________________________________
3
2-Wire Interfaced, 3V to 5.5V, 4-Digit,
9-Segment LED Display Drivers with Keyscan
Typical Operating Characteristics
(V+ = 5V, LED forward voltage = 2.4V, T = +25°C, unless otherwise noted.)
A
SCAN RATE (f
vs. TEMPERATURE
)
KEYSCAN DEBOUNCE TIME (t
vs. TEMPERATURE
)
DEBOUNCE
SCAN RATE (f
vs. SUPPLY VOLTAGE
)
SCAN
SCAN
800
795
790
785
780
775
770
765
760
755
42.5
42.0
41.5
41.0
40.5
40.0
790
785
780
775
770
765
760
3V
5.5V
5V
4.5V
4.5V
5V
5.5V
3V
-40 -20
0
20 40 60 80 100 120
-40 -20
0
20 40 60 80 100 120
3.0
3.5
4.0
4.5
5.0
5.5
TEMPERATURE (°C)
TEMPERATURE (°C)
SUPPLY VOLTAGE (V)
KEYSCAN DEBOUNCE TIME (t
)
SEGMENT SOURCE CURRENT
vs. SUPPLY VOLTAGE
SEGMENT SOURCE CURRENT
vs. SUPPLY VOLTAGE
DEBOUNCE
vs. SUPPLY VOLTAGE
42.2
42.0
41.8
41.6
41.4
41.2
41.0
40.8
40.6
40.4
25
20
15
10
5
25
20
15
10
5
V
= 2.4V
V
= 2V
LED
LED
0
0
3.0
3.5
4.0
4.5
5.0
5.5
4.50
4.75
5.00
5.25
5.50
3.0
3.5
4.0
4.5
5.0
5.5
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
INPUT PULLUP CURRENT
vs. TEMPERATURE
WAVEFORM AT DIG0/SEG0,
FULL INTENSITY
45
40
35
30
25
20
15
10
5
5.5V
5V
4.5V
3V
V
/
DIG0
SEG0
1V/div
0
-40 -20
0
20 40 60 80 100 120
200µs/div
TEMPERATURE (°C)
4
_______________________________________________________________________________________
2-Wire Interfaced, 3V to 5.5V, 4-Digit,
9-Segment LED Display Drivers with Keyscan
Pin Description
PIN
NAME
FUNCTION
MAX6958
MAX6959
1
2
3
1
2
SDA
SCL
Serial Data I/O
Serial Clock Input
—
SEG9
Segment Output. Segment driver sourcing current to a display anode.
Interrupt or Segment Output. May be segment driver sourcing current to a display
anode, or open-drain interrupt output, or open-drain logic output.
—
3
IRQ/SEG9
Digit and Segment Drivers. Digit X outputs sink current from the display common
cathode when acting as digit drivers. Segment X drivers source current to the display
anodes. Segment/digit drivers are high impedance when turned off.
4–7, 11–15
4–7, 11–15
DIGX, SEGX
8
8
GND
N.C.
Ground
9, 10
—
No Connect. Connect to V+ or leave open.
General-Purpose Input Port 1 with Internal Pullup. May be configured as general-
purpose logic input or keyscan input. Connect to V+ or leave open if unused.
—
9
INPUT1
General-Purpose Input Port 2 with Internal Pullup. May be configured as general-
purpose logic input or keyscan input. Connect to V+ or leave open if unused.
—
10
16
INPUT2
V+
16
Positive Supply Voltage
MAX6958/MAX6959 can also drive multidigit LED dis-
plays that have the segments individually pinned for
each digit.
Detailed Description
The MAX6958/MAX6959 serially interfaced display dri-
vers drive up to: four 7-segment digits plus four dis-
crete LEDs if the decimal points are used, or four
7-segment digits plus eight discrete LEDs if the deci-
mal points are not used, or 36 discrete LEDs. Table 1
lists the display connection scheme.
To connect four single-digit displays to the MAX6958/
MAX6959, connect cathode outputs DIG0/SEG0–
DIG3/SEG3 to the cathodes of the four display digits as
shown in Table 1 (CC0–CC3). Drive eight additional
LEDs with SEG0 to SEG7. Four of the eight LEDs can
be the decimal point (DP) segments of the four dis-
plays, and the other four can be discrete LED indica-
tors.
The MAX6958/MAX6959 include the hexadecimal font
map for seven-segment displays. The seven-segment
LED digits can be controlled directly or programmed to
use the hexadecimal font. Direct segment control
allows the MAX6958/MAX6959 to drive bar graphs and
discrete LED indicators.
To connect two dual-digit displays to the MAX6958/
MAX6959, connect cathode outputs DIG0/SEG0 and
DIG1/SEG1 to the cathodes of the first dual digit.
Connect DIG2/SEG2 and DIG3/SEG3 to the cathodes
of the second dual digit. SEG0 to SEG3 can only drive
discrete LEDs, not digit DP segments. SEG4 to SEG7
can drive the DP segments if required. Bicolor single-
digit displays are connected and treated as dual-digit
displays, each digit being one of the two colors.
The MAX6958/MAX6959 use a multiplexing scheme that
minimizes the connections between the driver and LED
display. The MAX6958/MAX6959 can drive monocolor
and bicolor single-digit type displays, and monocolor
dual-digit displays. Dual-digit displays internally
wire together the equivalent segments for each digit,
requiring only eight segment pins instead of 16. The
Table 1. Standard Driver Connection to LED Displays
DIG0/SEG0 DIG1/SEG1 DIG2/SEG2 DIG3/SEG3 SEG 4 SEG 5 SEG 6 SEG 7 SEG 8 SEG 9/IRQ
LED Digit 0
LED Digit 1
LED Digit 2
LED Digit 3
CC0
SEG 0
CC1
SEG g
SEG g
CC2
SEG f
SEG f
SEG 2
CC3
SEG e SEG d SEG c SEG b SEG a
SEG e SEG d SEG c SEG b SEG a
SEG e SEG d SEG c SEG b SEG a
SEG e SEG d SEG c SEG b SEG a
SEG 4
SEG 5
SEG 6
SEG 7
SEG 1
SEG g
SEG g
SEG f
SEG f
SEG 3
_______________________________________________________________________________________
5
2-Wire Interfaced, 3V to 5.5V, 4-Digit,
9-Segment LED Display Drivers with Keyscan
SDA
t
BUF
t
SU, STA
t
SU, DAT
t
HD, DAT
t
t
SU, STO
HD, STA
t
LOW
SCL
t
HIGH
t
HD, STA
t
t
F
R
START
CONDITION
REPEATED START
CONDITION
STOP
START
CONDITION CONDITION
Figure 1. 2-Wire Serial Interface Timing Details
The MAX6958/MAX6959 SDA line operates as both an
input and an open-drain output. A pullup resistor, typi-
cally 4.7kΩ, is required on the SDA bus. The MAX6958/
MAX6959 SCL line operates only as an input. A pullup
resistor, typically 4.7kΩ, is required on the SCL bus if
there are multiple masters on the 2-wire interface, or if
the master in a single-master system has an open-drain
SCL output.
Differences Between MAX6958
and MAX6959
The MAX6958/MAX6959 have the same LED drive
capability, four common-cathode digits of nine seg-
ments per digit. The MAX6959 additionally contains two
logic input ports, INPUT1 and INPUT2. Each input port
can be individually configured as either a general-pur-
pose input port that is read through the serial interface,
or as a keyscan input. In keyscan mode, the input is
used to read and automatically debounce four key
switches. A maximum of eight key switches can be
read if both INPUT1 and INPUT2 are assigned to
keyscanning.
Each transmission consists of a START condition
(Figure 2) sent by a master, followed by the MAX6958/
MAX6959 7-bit slave address plus R/W bit (Figure 3), 1
or more data bytes, and finally a STOP condition
(Figure 2).
The MAX6958's SEG9 output is preconfigured as the
9th LED segment output. The IRQ/SEG9 output on the
MAX6959 can be configured as either an open-drain
logic output or the 9th segment output. This logic out-
put serves as either a general-purpose logic output, set
through the serial interface, or an interrupt (IRQ) output
that alerts a microcontroller of debounced key-switch
events. Key-switch status can also be obtained by
polling the internal status registers at any time.
Start and Stop Conditions
Both SCL and SDA remain high when the interface is
not busy. A master signals the beginning of a transmis-
sion with a START (S) condition by transitioning SDA
from high to low while SCL is high. When the master
has finished communicating with the slave, it issues a
STOP (P) condition by transitioning the SDA from low to
high while SCL is high. The bus is then free for another
transmission (Figure 2).
Use the Option bit in the configuration register to detect
whether a MAX6958 or MAX6959 is present. The option
bit allows host software to establish whether a high-end
front panel (using the MAX6959 for keyscan support) or
a low-end panel (using a MAX6958 and no key switch-
es) is fitted to a product.
SDA
SCL
S
P
Serial Interface
START
STOP
CONDITION
Serial Addressing
The MAX6958/MAX6959 operate as a slave that sends
and receives data through a 2-wire interface. The inter-
face uses a serial data line (SDA) and a serial clock line
(SCL) to achieve bidirectional communication between
master(s) and slave(s). A master, typically a microcon-
troller, initiates all data transfers to and from the
MAX6958/MAX6959, and generates the SCL clock that
synchronizes the data transfer (Figure 1).
CONDITION
Figure 2. Start and Stop Conditions
6
_______________________________________________________________________________________
2-Wire Interfaced, 3V to 5.5V, 4-Digit,
9-Segment LED Display Drivers with Keyscan
SDA
0
1
1
1
0
0
R/W
ACK
A0
MSB
LSB
SCL
Figure 3. Slave Address
CLOCK PULSE FOR
ACKNOWLEDGMENT
START
CONDITION
SDA
SCL
1
2
8
9
NOT ACKNOWLEDGE
SCL
SDA
DATA STABLE, CHANGE OF
DATA VALID
DATA ALLOWED
ACKNOWLEDGE
Figure 4. Bit Transfer
Figure 5. Acknowledge
Bit Transfer
The MAX6958/MAX6959 are available in one of two
possible slave addresses (see Table 2 and Ordering
Information). The first 6 bits (MSBs) of the MAX6958/
MAX6959 slave address are always 011100. Slave
address bit A0 is internally hardwired to either GND in
the MAX695_A_, or V+ in the MAX695_B_. A maximum
of two MAX6958/MAX6959 devices can share a bus.
One data bit is transferred during each clock pulse.
The data on the SDA line must remain stable while SCL
is high (Figure 4).
Acknowledge
The acknowledge bit is a clocked 9th bit that the recipi-
ent uses to handshake receipt of each byte of data
(Figure 5). Thus, each byte transferred effectively
requires 9 bits. The master generates the 9th clock
pulse, and the recipient pulls down SDA during the
acknowledge clock pulse, such that the SDA line is sta-
ble low during the high period of the clock pulse. When
the master is transmitting to the MAX6958/MAX6959,
the MAX6958/MAX6959 generate the acknowledge bit
because the MAX6958/MAX6959 are the recipients.
When the MAX6958/MAX6959 are transmitting to the
master, the master generates the acknowledge bit
because the master is the recipient.
Message Format for Writing
A write to the MAX6958/MAX6959 comprises the trans-
mission of the MAX6958/MAX6959s’ slave address with
the R/W bit set to zero, followed by at least 1 byte of
information. The first byte of information is the com-
mand byte, which determines the register that stores
the next byte written to the MAX6958/MAX6959. If a
STOP condition is detected after the command byte is
received, the MAX6958/MAX6959 take no further action
(Figure 6) beyond storing the command byte.
Table 2. MAX6958/MAX6959 Address Map
Slave Address
The MAX6958/MAX6959 have a 7-bit-long slave
address (Figure 3). The eighth bit following the 7-bit
slave address is the R/W bit. Set the R/W bit low for a
write command and high for a read command.
MAX6958/MAX6959 DEVICE ADDRESS
SLAVE ADDRESS
BIT A0
A6
0
A5
1
A4
1
A3
1
A2
0
A1
0
A0
0
MAX695_A_
MAX695_B_
0
1
1
1
0
0
1
COMMAND BYTE IS STORED ON RECEIPT OF STOP CONDITION
D15
D14
D13
D12
D11
D10
D9
D8
ACKNOWLEDGE FROM
MAX6958/MAX6959
S
SLAVE ADDRESS
0
A
COMMAND BYTE
A
P
ACKNOWLEDGE FROM
MAX6958/MAX6959
R/W
Figure 6. Command Byte Received
_______________________________________________________________________________________
7
2-Wire Interfaced, 3V to 5.5V, 4-Digit,
9-Segment LED Display Drivers with Keyscan
ACKNOWLEDGE FROM MAX6958/MAX6959
ACKNOWLEDGE FROM MAX6958/MAX6959
HOW CONTROL BYTE AND DATA BYTE MAP INTO
MAX6958/MAX6959s' REGISTERS
ACKNOWLEDGE FROM
D15 D14 D13 D12 D11 D10 D9 D8
D7 D6 D5 D4 D3 D2 D1 D0
MAX6958/MAX6959
A
P
S
SLAVE ADDRESS
0
A
COMMAND BYTE
A
DATA BYTE
1 BYTE
R/W
AUTOINCREMENT MEMORY WORD ADDRESS
Figure 7. Command and Single Data Byte Received
ACKNOWLEDGE FROM MAX6958/MAX6959
D15 D14 D13 D12 D11 D10 D9 D8
ACKNOWLEDGE FROM MAX6958/MAX6959
HOW CONTROL BYTE AND DATA BYTE MAP INTO
MAX6958/MAX6959s' REGISTERS
ACKNOWLEDGE FROM
D7 D6 D5 D4 D3 D2 D1 D0
MAX6958/MAX6959
A
P
S
SLAVE ADDRESS
0
A
COMMAND BYTE
A
DATA BYTE
n BYTES
R/W
AUTOINCREMENT MEMORY WORD ADDRESS
Figure 8. n Data Bytes Received
ACKNOWLEDGE FROM THE MASTER
NOT ACKNOWLEDGE FROM MASTER
HOW THE MAX6958/MAX6959 SENDS DATA
TO THE MASTER
D15 D14 D13 D12 D11 D10 D9 D8
D7 D6 D5 D4 D3 D2 D1 D0
ACKNOWLEDGE FROM MAX6958/MAX6959
A
P
S
SLAVE ADDRESS
1
A
FIRST DATA BYTE
A
DATA BYTE
n BYTES
R/W
AUTOINCREMENT MEMORY WORD ADDRESS
AUTOINCREMENT MEMORY WORD ADDRESS
Figure 9. Reading n Data Bytes from the MAX6958/MAX6959
Bytes received after the command byte are data bytes.
The first data byte goes into the internal register of the
MAX6958/MAX6959 as selected by the command byte
(Figure 7).
each data byte read using the same rules as for a write
(Table 3). A read is initiated by first configuring the
MAX6958/MAX6959s’ command byte with a write com-
mand (Figure 6). The master can now read n consecu-
tive bytes from the MAX6958/MAX6959. The master
acknowledges receipt of each read byte during the
acknowledge clock pulse. The master must acknowl-
edge all consecutive bytes received except the last
byte. The final read byte must be followed by a not
acknowledge from the master and then a stop condi-
tion (Figure 9). The first data byte is read from the reg-
ister addressed by the initialized command byte
(Figure 8). Reset the address pointer when performing
read-after-write verification because the stored byte
address is autoincremented after the write. The
address pointer does not autoincrement if it points to
register 01111111 (Table 3).
The address pointer in the MAX6958/MAX6959 autoin-
crements after each data byte. If multiple data bytes
are transmitted before a STOP condition is detected,
these bytes are stored in subsequent MAX6958/
MAX6959 internal registers (Figure 8), unless the
address pointer has reached address 01111111. The
address pointer does not autoincrement once address
01111111 has been reached (Table 3).
Message Format for Reading
The MAX6958/MAX6959 are read using the internally
stored command byte as an address pointer the same
way the stored command byte is used as an address
pointer for a write. The pointer autoincrements after
Table 4 is the register address map.
8
_______________________________________________________________________________________
2-Wire Interfaced, 3V to 5.5V, 4-Digit,
9-Segment LED Display Drivers with Keyscan
Command Address Autoincrementing
Table 3. Command Address
Autoincrement Behavior
Address autoincrementing allows the MAX6958/
MAX6959 to be configured with the shortest number of
transmissions by minimizing the number of times the
command byte needs to be sent. The address pointer
stored in the MAX6958/MAX6959 increments after each
data byte is written or read, unless the address equals
01111111 (Table 3).
COMMAND BYTE
ADDRESS RANGE
AUTOINCREMENT BEHAVIOR
00000000 to
01111110
Command byte address autoincrements
after byte read or written
Command byte address remains at
01111111 after byte written or read
01111111
Digit Type Registers
The MAX6958/MAX6959 store display data in five regis-
ters. The four digit registers each control the seven
numeric segments of a seven-segment digit, but not
the DP segments. The segments register controls eight
individual LEDs, which can be any mix of discrete LEDs
and any or all of the DP segments of the four 7-seg-
ment digits (Table 5) (Figure 10).
Operation with Multiple Masters
If the MAX6958/MAX6959 are operated on a 2-wire
interface with multiple masters, a master reading the
MAX6958/MAX6959 should use a repeated start
between the write, which sets the MAX6958/MAX6959s’
address pointer, and the read(s) that takes the data
from the location(s) set by the address pointer. It is
possible for master 2 to take over the bus after master
1 has set up the MAX6958/MAX6959s’ address pointer
but before master 1 has read the data. If master 2 sub-
sequently changes the MAX6958/MAX6959s’ address
pointer, then master 1's delayed read may be from an
unexpected location.
a
f
b
c
g
e
dp
d
Figure 10. Segment Labeling for 7-Segment Display
Table 4. Register Address Map
COMMAND ADDRESS
HEX
CODE
REGISTER
D15
D14
0
D13
0
D12
0
D11
0
D10
0
D9
0
D8
0
No-op
0
0
0
0
0
0
0
0
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
Decode mode
0
0
0
0
0
0
1
Intensity
0
0
0
0
0
1
0
Scan limit
0
0
0
0
0
1
1
Configuration
0
0
0
0
1
0
0
Factory reserved. Do not write to this register.
GPIO (MAX6959 only)
Display test
0
0
0
0
1
0
1
0
0
0
0
1
1
0
0
0
0
0
1
1
1
Read key debounced (MAX6959 only)
A write to this register is ignored.
0
0
0
0
0
0
0
0
1
1
0
1
0
0
0
0
0x08
0x0C
Read key pressed (MAX6959 only)
A write to this register is ignored.
Digit 0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
1
0
0
1
0
1
0
0x20
0x21
0x22
0x23
0x24
Digit 1
Digit 2
Digit 3
Segments
_______________________________________________________________________________________
9
2-Wire Interfaced, 3V to 5.5V, 4-Digit,
9-Segment LED Display Drivers with Keyscan
Table 5. No-Decode Mode Data Bits and Corresponding Segment Lines
REGISTER DATA
ADDRESS
CODE (HEX)
DIGIT/SEGMENT REGISTER
D7
D6
D5
D4
D3
D2
D1
D0
Digit 0
Digit 1
0x20
0x21
0x22
0x23
0x24
X
SEG a
SEG a
SEG a
SEG a
SEG 6
SEG b
SEG b
SEG b
SEG b
SEG 5
SEG c
SEG c
SEG c
SEG c
SEG 4
SEG d
SEG d
SEG d
SEG d
SEG 3
SEG e
SEG e
SEG e
SEG e
SEG 2
SEG f
SEG f
SEG f
SEG f
SEG 1
SEG g
SEG g
SEG g
SEG g
SEG 0
X
X
Digit 2
Digit 3
X
Segments
SEG 7
The digit registers and segments register use 1 bit to
set the state of one segment. Each bit is high to turn a
segment on, or low to turn it off (Table 6).
In hexadecimal code-decode mode, the decoder looks
only at the lower nibble of the data in the digit register
(D3–D0), disregarding bits D7–D4. Table 7 lists the hexa-
decimal code font. When no decode is selected, data
bits D7–D0 correspond to the segment lines of the
MAX6958/MAX6959. Table 8 shows the one-to-one pair-
ing of each data bit to the appropriate segment line.
Table 6. No-Decode Mode Data Bits and
Corresponding Segment Lines
REGISTER BIT
SEGMENT BEHAVIOR
Segment off
Initial Power-Up
On initial power-up, all control registers are reset, the
display is blanked, and the MAX6958/MAX6959 enter
shutdown mode (Table 9). At power-up, the MAX6958/
MAX6959 are initially set to scan four digits, do not
decode data in the digit registers or scan key switches
(MAX6959 only), and the intensity register is set to a
low value (4/64 intensity).
0
1
Segment on
Decode-Mode Register
The decode-mode register sets hexadecimal code
(0–9, A–F) or no-decode operation for each digit. Each
bit in the register corresponds to one digit. Logic high
selects hexadecimal decoding while logic low bypass-
es the decoder. Digits can be set for decode or no
decode in any combination. Bit assignment and exam-
ples of the decode mode control register format are
shown in Table 7.
Table 7. Decode-Mode Register Examples
REGISTER DATA
ADDRESS
CODE (HEX)
HEX
CODE
DECODE MODE
D7
X
D6
X
D5
X
D4
D3
D2
D1
D0
Bit assignment for each digit
0x01
0x01
0x01
—
X
Digit 3 Digit 2 Digit 1 Digit 0
—
No decode for digits 3–0
X
X
X
X
0
0
0
0
0
0
0
1
0xX0
0xX1
—
Hexadecimal decode for digit
0; no decode for digits 3–1
X
X
X
X
—
—
X
—
X
—
X
—
X
—
0
—
1
—
1
—
1
Hexadecimal decode for digits
2–0; no decode for digit 3
0x01
0xX7
Hexadecimal decode for digit
3; no decode for digits 2–0
0x01
—
X
—
X
X
—
X
X
—
X
X
—
X
1
—
1
0
—
1
0
—
1
0
—
1
0xX8
—
—
Hexadecimal decode for digits
3–0
0x01
0xXF
10 ______________________________________________________________________________________
2-Wire Interfaced, 3V to 5.5V, 4-Digit,
9-Segment LED Display Drivers with Keyscan
Table 8. Seven-Segment Mapping Decoder for Hexadecimal Font
REGISTER DATA
D3 D1
ON SEGMENTS = 1
7-SEGMENT
CHARACTER
D7–D4
D2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
D0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
a
1
0
1
1
0
1
1
1
1
1
1
0
1
0
1
1
b
1
1
1
1
1
0
0
1
1
1
1
0
0
1
0
0
c
1
1
0
1
1
1
1
1
1
1
1
1
0
1
0
0
d
1
0
1
1
0
1
1
0
1
1
0
1
1
1
1
0
e
1
0
1
0
0
0
1
0
1
0
1
1
1
1
1
1
f
g
0
0
1
1
1
1
1
0
1
1
1
1
0
1
1
1
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
0
0
0
1
1
1
0
1
1
1
1
1
0
1
1
Table 9. Initial Power-Up Register Status
REGISTER DATA
ADDRESS
CODE (HEX)
REGISTER
POWER-UP CONDITION
D7
X
D6
X
D5
X
D4
X
D3
0
D2
0
D1
0
D0
0
Decode mode
Intensity
No decode for digits 3–0
4/64 intensity
0x01
0x02
0x03
0x04
X
X
0
0
0
1
0
0
Scan limit
Display 4 digits: 0 1 2 3
Shutdown enabled
X
X
X
X
X
X
1
1
Configuration
X
X
0
X
X
X
D bit
X
0
IRQ/SEG9 is a segment output
(not IRQ or logic output);
INPUT2 and INPUT1 are logic
inputs; IRQ flag is clear
GPIO*
0x06
1
0
0
0
0
X
0
Display test
Normal operation
0x07
0x08
0x0C
0x20
0x21
0x22
0x23
0x24
X
0
0
X
X
X
X
0
X
0
0
0
0
0
0
0
X
0
0
0
0
0
0
0
X
0
0
0
0
0
0
0
X
0
0
0
0
0
0
0
X
0
0
0
0
0
0
0
X
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Key debounced* No key detected as debounced
Key pressed*
Digit 0
No key detected as pressed
Blank digit (because not decoded)
Blank digit (because not decoded)
Blank digit (because not decoded)
Blank digit (because not decoded)
Blank segments
Digit 1
Digit 2
Digit 3
Segments
*MAX6959 only.
______________________________________________________________________________________ 11
2-Wire Interfaced, 3V to 5.5V, 4-Digit,
9-Segment LED Display Drivers with Keyscan
scanned. Since the number of scanned digits affects
the display brightness, the scan-limit register should
not be used to blank portions of the display (such as
leading zero suppression).
Configuration Register
Use the configuration register to enter and exit shut-
down, check device type, and globally clear the digit
data (Tables 10–13). The S bit selects shutdown or nor-
mal operation (read/write). The D bit reports whether
the device is a MAX6958 or a MAX6959 (read only).
The R bit clears all the digit and segment data (data is
not stored-transient bit)
Intensity Register
An internal pulse-width modulator controlled by the
intensity register provides digital control of display
brightness. The modulator scales the average segment
current in 63 steps from a maximum of 63/64 down to
1/64 of the 23mA peak current. The minimum interdigit
blanking time is set to 1/64 of a cycle (Figure 11 and
Table 15).
Scan-Limit Register
The scan-limit register sets the number of digits dis-
played, from one to four (Table 14). A bicolor digit is
connected as two monocolor digits. The scan-limit reg-
ister also limits the number of keys that can be
Table 10. Configuration Register Format
REGISTER DATA
ADDRESS
CODE (HEX)
MODE
D7
D6
D5
D4
D3
D2
D1
D0
Configuration register
0x04
X
X
R
X
X
X
D
S
Table 11. Shutdown Control (S Data Bit D0) Format
REGISTER DATA
ADDRESS
MODE
CODE (HEX)
0x04
D7
X
D6
X
D5
R
D4
X
D3
X
D2
X
D1
D
D0
0
Shutdown mode
Normal operation
0x04
X
X
R
X
X
X
D
1
Table 12. Device Readback (D Data Bit D1) Format
REGISTER DATA
ADDRESS
MODE
CODE (HEX)
D7
X
D6
X
D5
R
D4
X
D3
X
D2
X
D1
0
D0
S
MAX6958
MAX6959
0x04
0x04
X
X
R
X
X
X
1
S
Table 13. Global Clear Digit Data (R Data Bit D5) Format
REGISTER DATA
ADDRESS
MODE
CODE (HEX)
0x04
D7
X
D6
X
D5
0
D4
X
D3
X
D2
X
D1
D
D0
S
Digit and segment data are unaffected
Digit and segment data are cleared
0x04
X
X
1
X
X
X
D
S
Table 14. Scan-Limit Register Format
REGISTER DATA
ADDRESS
CODE (HEX)
HEX
CODE
SCAN LIMIT
D7
X
D6
D5
X
D4
X
D3
X
D2
X
D1
0
D0
Display digit 0 and segments 0, 4
0x03
0x03
0x03
X
X
X
0
1
0
0xX0
0xX1
0xX2
Display digits 0, 1 and segments 0, 1, 4, 5
Display digits 0, 1, 2 and segments 0, 1, 2, 4, 5, 6
X
X
X
X
X
0
X
X
X
X
X
1
Display digits 0, 1, 2, 3 and segments 0, 1, 2, 3, 4,
5, 6, 7
0x03
X
X
X
X
X
X
1
1
0xX3
12 ______________________________________________________________________________________
2-Wire Interfaced, 3V to 5.5V, 4-Digit,
9-Segment LED Display Drivers with Keyscan
Table 15. Global Intensity Register Format
TYPICAL SEGMENT
CURRENT (mA)
ADDRESS
CODE (HEX)
DUTY CYCLE
D7
D6
D5
D4
D3
D2
D1
D0 HEX CODE
1/64 (min on)
2/64
0.36
0.72
1.08
1.44
1.80
2.16
—
0x02
0x02
0x02
0x02
0x02
0x02
0x02
0x02
0x02
0x02
0x02
0x02
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0
0
0
0
0
—
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
—
0
1
1
1
1
0
0
0
1
0x00
0x01
0x02
0x03
0x04
0x05
—
3/64
0
0
1
0
4/64
0
0
1
1
5/64
0
0
0
0
6/64
0
0
0
1
—
—
1
—
1
—
1
—
1
60/64
21.56
21.92
22.28
22.64
22.64
0x3B
0x3C
0x3D
0x3E
0x3F
61/64
1
1
0
0
62/64
1
1
0
1
63/64
1
1
1
0
63/64 (max on)
1
1
1
1
START OF
NEXT CYCLE
ONE COMPLETE 1.28ms MULTIPLEX CYCLE AROUND 4 DIGITS
DIGIT 1 DIGIT 2
DIGIT 0
DIGIT 3
DIGIT 0
DIGIT 0 CATHODE
DRIVER INTENSITY
SETTINGS
DIGIT 0's 320µs MULTIPLEX TIMESLOT
HIGH-Z
LOW
1/64th
(MIN ON)
HIGH-Z
LOW
LOW
2/64th
3/64th
HIGH-Z
HIGH-Z
61/64th
62/16th
63/64th
LOW
LOW
LOW
LOW
HIGH-Z
HIGH-Z
HIGH-Z
63/64th
(MAX ON)
MINIMUM 5µs INTERDIGIT BLANKING INTERVAL
ANODE (LIT)
CURRENT SOURCE ENABLED
HIGH-Z
HIGH-Z
ANODE (UNLIT)
HIGH-Z
HIGH-Z
Figure 11. Multiplex Timing Diagram
______________________________________________________________________________________ 13
2-Wire Interfaced, 3V to 5.5V, 4-Digit,
9-Segment LED Display Drivers with Keyscan
The keyscanning circuit utilizes the LED’s common-
cathode driver outputs as the keyscan drivers. The out-
puts DIG0/SEG0 to DIG3/SEG3 pulse low for nominally
320µs sequentially as the displays are multiplexed. The
actual low time varies from 5µs to 315µs due to pulse-
width modulation from 1/64th to 63/64th for intensity
control. The timing diagram (Figure 14) shows the typi-
cal situation when all four LED cathode drivers are used.
The maximum eight keys can be scanned only if the
scan-limit register is set to scan the maximum four dig-
its. If fewer than four digits are driven, then only (2 x n)
switches can be scanned, where n is the number of dig-
its (1, 2, 3, or 4) set in the scan-limit register (Table 14).
Ports and Key Scanning
(MAX6959 Only)
The MAX6959 features two input ports, INPUT1 and
INPUT2. These two ports can be used as general-pur-
pose logic inputs, or configured to perform automatic
keyscanning. Both ports have internal pullup resistors
enabled in shutdown and normal operation for both
general-purpose input mode and keyscanning mode.
The ports can be read using the 2-wire interface.
The keyscan logic uses one or both of the INPUT1 and
INPUT2 logic inputs (Figure 12). An interrupt output that
flags key presses is optional. The interrupt flag can be
read (polled) through the serial interface instead, allow-
ing IRQ/SEG9 to be used as an open-drain general-
purpose logic output or as a segment driver.
The keyscan cycle loops continuously over time, with
all eight keys experiencing a full keyscanning
debounce over 41ms (Figure 14). A key press is
debounced and an interrupt issued if at least one key
that was not pressed in a previous cycle is found
pressed during both sampling periods. The keyscan
circuit detects any combination of keys pressed during
each debounce cycle (n-key rollover).
One small-signal diode is required per key switch when
more than one key is connected to INPUT1 or INPUT2.
The diodes prevent two simultaneous key switch
depressions from shorting digit drivers together. For
example, if KEY0 and KEY1 were pressed together
(Figure 12) and the diodes were not fitted, DIG0/SEG0
and DIG1/SEG1 would be shorted together and the
LED multiplexing would be incorrect. These diodes can
be common-anode dual diodes in SOT23 like BAW56.
A diode is not required for a single key connection to
INPUT1 or INPUT2. Therefore, up to two key switches
can be automatically debounced without adding
diodes (Figure 13).
Port Configuration Register
(MAX6959 Only)
The port configuration register configures INPUT1,
INPUT2, and IRQ/SEG9 ports for the MAX6959 (Table 16).
IRQ/SEG9 can be set to either an LED segment output
(driving four multiplexed LED segments), or an open-
drain logic output. The open-drain logic output can be
configured as either an IRQ output controlled by the
keyscan circuitry, or as a general-purpose logic output
controlled through the 2-wire interface. Connect a
Resistors R1 and R2 are required if the MAX6959 is
operated with V+ greater than 4V. R1 and R2 are
optional if V+ is between 3V and 4V.
DIG0/SEG0
Key0
Key1
Key2
Key3
Key4
Key5
Key6
Key7
Key4
DIG1/SEG1
DIG2/SEG2
DIG3/SEG3
DIG0/SEG0
Key0
V+
R1
39kΩ
INPUT1
V+
R2
39kΩ
V+
R1
39kΩ
INPUT2
4.7kΩ
INPUT1
V+
R2
39kΩ
IRQ/SEG9
MICROCONTROLLER INTERRUPT
INPUT2
4.7kΩ
IRQ/SEG9
MICROCONTROLLER INTERRUPT
Figure 13. Keyscanning Two Keys Without Diodes
14 ______________________________________________________________________________________
Figure 12. Maximum Keyscan Configuration
2-Wire Interfaced, 3V to 5.5V, 4-Digit,
9-Segment LED Display Drivers with Keyscan
t
DEBOUNCE
THE FIRST HALF OF A 41ms KEYSCAN CYCLE
THE SECOND HALF OF A 41ms KEYSCAN CYCLE
1.28ms MULTIPLEX 1.28ms MULTIPLEX 1.28ms MULTIPLEX 1.28ms MULTIPLEX
1.28ms MULTIPLEX 1.28ms MULTIPLEX 1.28ms MULTIPLEX 1.28ms MULTIPLEX
1.28ms MULTIPLEX 1.28ms MULTIPLEX
CYCLE 15 CYCLE 16
CYCLE 1
CYCLE 2
CYCLE 3
CYCLE 4
CYCLE 15
CYCLE 16
CYCLE 1
CYCLE 2
5µs TO 315µs DIGIT PERIOD
DIG0/SEG0
DIG1/SEG1
DIG2/SEG2
DIG3/SEG3
INPUT1
Key0 Key1 Key2 Key3
Key0 Key1 Key2 Key3
Key4 Key5 Key6 Key7
INPUT2
Key4 Key5 Key6 Key7
A
B
C
D
E
A
FIRST TEST OF KEYS
SECOND TEST OF KEYS
INTERRUPT ASSERTED IF REQUIRED
KEY DEBOUNCED REGISTER UPDATED
START OF NEXT KEYSCAN CYCLE
Figure 14. Keyscan Timing Diagram
pullup resistor from IRQ/SEG9 to a voltage no greater
than 5.5V when configuring IRQ/SEG9 as an interrupt
or logic output.
pullups are always enabled, even in shutdown. Ensure
these inputs are either close to V+ or open circuit for
minimum shutdown supply current. If both INPUT1 and
INPUT2 are assigned to keyscan, then eight keys can
be debounced. If only INPUT1 or INPUT2 is assigned
to keyscan, then only four keys can be debounced.
INPUT1 and INPUT2 can be individually configured as
either general-purpose logic inputs or as keyscan
inputs. In either mode, the input structure is the same—
CMOS logic inputs with internal pullup resistors. The
Table 16. Port Configuration Register Format
REGISTER DATA
ADDRESS
MODE
CODE
(HEX)
D7 D6 D5
D4
D3
D2
D1
D0
This is the bit assignment:
Read back
IRQ/SEG9
configuration configuration
Read back
INPUT 2
Read back
INPUT 1
configuration
INPUT2
logic level
INPUT1
logic level
IRQ status
(1 = interrupt)
Read GPIO register
0x06
0x06
Configure
INPUT 2:
Configure
INPUT 1:
Configure
IRQ/SEG9
Write GPIO register
X
X
X
0 = logic input 0 = logic input
1 = keyscan 1 = keyscan
Here are the IRQ/SEG9 allocation options, determined by the settings of D7, D6, D5:
output
IRQ/SEG9 is logic 0 output
IRQ/SEG9 is logic 1 output
0x06
0x06
0
0
0
0
0
1
X
X
X
X
X
X
X
X
X
X
IRQ/SEG9 is active-low
IRQ
0x06
0x06
0x06
0
0
1
1
1
X
0
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
IRQ/SEG9 is active-high
IRQ
IRQ/SEG9 is segment
driver
______________________________________________________________________________________ 15
2-Wire Interfaced, 3V to 5.5V, 4-Digit,
9-Segment LED Display Drivers with Keyscan
Key Debounced Register (MAX6959 Only)
The key debounced register shows which keys have
been detected as debounced by the keyscanning cir-
cuit (Table 17). Each bit in the register corresponds to
one key switch. The bit is set to 1 if the switch has been
correctly debounced since the last key debounced reg-
ister read operation.
detected as pressed by the keyscanning circuit during
the last test. Reading the key pressed register does not
clear either the key pressed register, or the key
debounced register, and does not clear the IRQ output.
The key pressed register is read only. A write to
address 0x0C is ignored.
Display Test Register
The display test register operates in two modes: normal
and display test (Table 19). Display test mode turns on
all LEDs by overriding, but not altering, all control and
digit registers (including the shutdown register) except
for the port configuration register. The duty cycle while
in display test mode is 28/64.
Reading the key debounced register clears the register
(after the data has been read) so that future key presses
can be identified. If the key debounced register is not
read, the keyscan data accumulates. There is no FIFO
register in the MAX6959. Key-press order, or whether a
key has been pressed more than once, cannot be
determined unless the key debounced register is read
after each interrupt and before completion of the next
keyscan cycle.
Applications Information
Driving Bicolor LEDs
Bicolor digits combine a red and a green die for each
display element, so that the element displays red or
green (or orange), depending on which die (or both) is
lit. The MAX6958/MAX6959 treat a bicolor digit as two
monocolor digits.
Reading the key debounced register clears the IRQ
output. If a key is pressed and held down, the key is
reported as debounced (and an IRQ is issued) only
once. The key must be detected as released by the
keyscanning circuit before it is debounced again.
The key debounced register is read only. A write to
address 0x08 is ignored.
Low-Voltage Operation
The MAX6958/MAX6959 are guaranteed to drive a 23mA
segment current into 2.4V (or lower) LEDs when operat-
ed from a supply voltage of 4.5V to 5.5V. Operating the
MAX6958/MAX6959 from a supply voltage lower than
4.5V reduces the LED drive current. The drivers drive at
least 15.5mA segment current into 2V (or lower) LEDs
when operated from a 3V supply voltage.
Key Pressed Register (MAX6959 Only)
The key pressed register shows which keys have been
detected as pressed by the keyscanning circuit during
the last test. Each bit in the register corresponds to one
key switch. The bit is set if the switch has been detect-
ed as pressed by the keyscanning circuit during the
last test. The bit is cleared if the switch has not been
Table 17. Key Debounced Register Format
REGISTER DATA
WITH APPROPRIATE SWITCH NAMED BELOW
ADDRESS
KEY DEBOUNCED REGISTER
CODE (HEX)
D7
D6
D5
D4
D3
D2
D1
D0
Key debounced register
0x08
Key7 Key6 Key5 Key4 Key3 Key2 Key1 Key0
Table 18. Key Pressed Register Format
REGISTER DATA
WITH APPROPRIATE SWITCH NAMED BELOW
ADDRESS
CODE (HEX)
KEY PRESSED REGISTER
D7
D6
D5
D4
D3
D2
D1
D0
Key pressed register
0x0C
Key7 Key6 Key5 Key4 Key3 Key2 Key1 Key0
Table 19. Display Test Register
REGISTER DATA
ADDRESS
CODE (HEX)
MODE
D7
X
D6
X
D5
X
D4
X
D3
X
D2
X
D1
X
D0
0
Normal operation
Display test mode
0x07
0x07
X
X
X
X
X
X
X
1
16 ______________________________________________________________________________________
2-Wire Interfaced, 3V to 5.5V, 4-Digit,
9-Segment LED Display Drivers with Keyscan
For a 16-pin DIP package (T = 1/0.0105 = +95.2°C/W
Computing Power Dissipation
JA
from Absolute Maximum Ratings), the maximum
Determine the MAX6958/MAX6959 upper-limit power
allowed ambient temperature T is given by:
A
dissipation (P ) with the following equation:
D
T
= T + (P ✕ T ) = +150°C
A D JA
P = (V+ ✕ I+) + (V+ - V
D
) (DUTY ✕ I ✕ N)
SEG
J(MAX)
LED
= T + (0.652 ✕ 95.2°C/W)
A
where:
V+ = supply voltage
I+ = operating supply current
DUTY = duty cycle set by intensity register
N = number of segments driven (worst case is nine)
Therefore, T = +87.9°C.
A
Power Supplies
The MAX6958/MAX6959 operate from a single 3V to
5.5V power supply. Bypass V+ with a 0.1µF capacitor
to GND, as close to the device as possible. Bypass V+
with an additional 10µF capacitor if the MAX6958/
MAX6959 are not close to the board input’s bulk
decoupling capacitor.
V
= LED forward voltage at I
LED
SEG
SEG
I
= peak segment current
P = power dissipation, in mW if currents are in mA
D
Dissipation example:
Chip Information
TRANSISTOR COUNT: 17,340
I
= 23mA, N = 9, DUTY = 63/64, V
= 2.2V,
SEG
V+ = 5.25V
LED
PROCESS: CMOS
P = 5.25V (5.9mA) + (5.25V - 2.2V)
D
(63/64 ✕ 23mA ✕ 9) = 0.652W
Ordering Information (continued)
Functional Diagram
TEMP
RANGE
SLAVE
ADDRESS PACKAGE
PIN-
PART
IRQ
PORTS AND
KEYSCAN
MULTIPLEX
KEYSCAN AND
PORT CONTROL
MAX6958BAEE -40°C to +125°C 0111001 16 QSOP
MAX6958BAPE -40°C to +125°C 0111001 16 DIP
MAX6959AAEE -40°C to +125°C 0111000 16 QSOP
MAX6959AAPE -40°C to +125°C 0111000 16 DIP
MAX6959BAEE -40°C to +125°C 0111001 16 QSOP
MAX6959BAPE -40°C to +125°C 0111001 16 DIP
OSCILLATOR
CURRENT
REFERENCE
PWM INTENSITY
CONTROL
LED
DRIVER
4 LED DIGITS
MULTIPLEX
LOGIC
DISPLAY RAM
AND HEX ROM
CONFIGURATION
REGISTERS
SDA
SCL
2-WIRE SERIAL INTERFACE
______________________________________________________________________________________ 17
2-Wire Interfaced, 3V to 5.5V, 4-Digit,
9-Segment LED Display Drivers with Keyscan
Pin Configuration
Typical Application Circuit
TOP VIEW
SDA
1
2
3
4
5
6
7
8
16 V+
9
9
9
9
SCL
(IRQ/SEG9) SEG9
DIG0/SEG0
DIG1/SEG1
DIG2/SEG2
DIG3/SEG3
GND
15 SEG8
14 SEG7
µC
MAX6958/
MAX6959
13 SEG6
9
DIG0–DIG3
SEG0–SEG9
12 SEG5
SDA
SCL
SDA
SCL
11 SEG4
5V
10 (INPUT2)/N.C.
V+
MAX6959
9
(INPUT1)/N.C.
0.1µF
QSOP/DIP
INPUT1
INPUT2
GND
( ) MAX6959 ONLY
39kΩ
39kΩ
Key0
DIG0/SEG0
DIG1/SEG1
DIG2/SEG2
DIG3/SEG3
DIG0/SEG0
DIG1/SEG1
DIG2/SEG2
DIG3/SEG3
Key1
Key2
Key3
Key4
Key5
Key6
Key7
18 ______________________________________________________________________________________
2-Wire Interfaced, 3V to 5.5V, 4-Digit,
9-Segment LED Display Drivers with Keyscan
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 19
© 2002 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
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