MAX691EPE+ [MAXIM]
Power Supply Management Circuit, Fixed, 1 Channel, CMOS, PDIP16, LEAD FREE, PLASTIC, DIP-16;
| 型号： | MAX691EPE+ |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Power Supply Management Circuit, Fixed, 1 Channel, CMOS, PDIP16, LEAD FREE, PLASTIC, DIP-16 微处理器 监控 |
| 文件： | 总16页 (文件大小：158K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-0094; Rev 7a; 12/96
Mic ro p ro c e s s o r S u p e rvis o ry Circ u it s
1693L/AX80M
_______________Ge n e ra l De s c rip t io n
____________________________Fe a t u re s
♦ 200ms Power-OK/Reset Timeout Period
The MAX691A/MAX693A/MAX800L/MAX800M micro-
processor (µP) supervisory circuits are pin-compatible
upgrades to the MAX691, MAX693, and MAX695. They
improve performance with 30µA supply current, 200ms
typ re s e t a c tive d e la y on p owe r-up , a nd 6ns c hip -
enable propagation delay. Features include write pro-
tection of CMOS RAM or EEPROM, separate watchdog
outputs, backup-battery switchover, and a RESET out-
put that is valid with VCC down to 1V. The MAX691A/
MAX800L have a 4.65V typical reset-threshold voltage,
and the MAX693A/MAX800M’s reset threshold is 4.4V
typical. The MAX800L/MAX800M guarantee power-fail
accuracies to ±2%.
♦ 1µA Standby Current, 30µA Operating Current
♦ On-Board Gating of Chip-Enable Signals,
10ns Max Delay
♦ MaxCap™ or SuperCap™ Compatible
♦ Guaranteed RESET Assertion to VCC = +1V
♦ Voltage Monitor for Power-Fail or Low-Battery
Warning
♦ Power-Fail Accuracy Guaranteed to ±2%
(MAX800L/M)
♦ Available in 16-Pin Narrow SO and Plastic
DIP Packages
________________________Ap p lic a t io n s
______________Ord e rin g In fo rm a t io n
Computers
Controllers
PART
TEMP. RANGE
0°C to +70°C
PIN-PACKAGE
16 Plastic DIP
16 Narrow SO
16 Wide SO
Dice*
MAX691ACPE
MAX691ACSE
MAX691ACWE
MAX691AC/D
MAX691AEPE
MAX691AESE
MAX691AEWE
MAX691AEJE
MAX691AMJE
Intelligent Instruments
Automotive Systems
Critical µP Power Monitoring
0°C to +70°C
0°C to +70°C
0°C to +70°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-55°C to +125°C
16 Plastic DIP
16 Narrow SO
16 Wide SO
16 CERDIP
__________Typ ic a l Op e ra t in g Circ u it
5V
REGULATOR
+8V
16 CERDIP
0.1µF
Ordering Information continued on last page.
* Dice are specified at T = +25 °C, DC parameters only.
A
3
5
1N4148
0.47F*
V
BATT ON
CC
2
__________________P in Co n fig u ra t io n
V
OUT
1
VBATT
12
CE OUT
TOP VIEW
CMOS RAM
MAX691A
MAX693A
MAX800L
VBATT
RESET
RESET
WDO
CE IN
CE OUT
WDI
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
13
11
9
4
7
ADDRESS
DECODE
CE IN
PFI
V
OUT
MAX800M
V
CC
GND
A0-A15
I/O
GND
MAX691A
MAX693A
MAX800L
MAX800M
WDI
PFO
µP
OSC IN
BATT ON
LOW LINE
OSC IN
NO
10
15
NMI
CONNECTION
8
OSC SEL
PFO
RESET
RESET
LOW LINE WDO
OSC SEL
PFI
6
14
AUDIBLE
ALARM
DIP/SO
*MaxCap
SYSTEM STATUS INDICATORS
SuperCap is a registered trademark of Baknor Industries. MaxCap is a registered trademark of The Carborundum Corp.
________________________________________________________________ Maxim Integrated Products
1
For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800.
For small orders, phone 408-737-7600 ext. 3468.
Mic ro p ro c e s s o r S u p e rvis o ry Circ u it s
ABSOLUTE MAXIMUM RATINGS
Terminal Voltage (with respect to GND)
Continuous Power Dissipation (T = +70°C)
A
V
.......................................................................-0.3V to +6V
Plastic DIP (derate 10.53mW/°C above +70°C) ..........842mW
CC
VBATT...................................................................-0.3V to +6V
All Other Inputs .....................................-0.3V to (V + 0.3V)
Input Current
Narrow SO (derate 8.70mW/°C above +70°C) ...........696mW
Wide SO (derate 9.52mW/°C above +70°C)...............762mW
CERDIP (derate 10.00mW/°C above +70°C)..............800mW
Operating Temperature Ranges
MAX69_AC_ _/MAX800_C_ _ .............................0°C to +70°C
MAX69_AE_ _/MAX800_E_ _ ...........................-40°C to +85°C
MAX69_AMJE ................................................-55°C to +125°C
Storage Temperature Range .............................-65°C to +160°C
Lead Temperature (soldering, 10sec) .............................+300°C
OUT
V
Peak...........................................................................1.0A
Continuous.............................................................250mA
CC
V
CC
VBATT Peak ..................................................................250mA
VBATT Continuous ..........................................................25mA
GND, BATT ON.............................................................100mA
All Other Outputs ............................................................25mA
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(MAX691A, MAX800L: V = +4.75V to +5.5V, MAX693A, MAX800M: V = +4.5V to +5.5V, VBATT = 2.8V, T = T
to T
,
CC
CC
A
MIN
MAX
unless otherwise noted.)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Operating Voltage Range,
, VBATT (Note 1)
0
5.5
V
V
CC
I
= 25mA
V
CC
- 0.02
V
CC
- 0.05
OUT
MAX69_AC
V
- 0.2
- 0.2
V
- 0.3
CC
CC
MAX69_AE,
MAX800_C/E
I
= 250mA
V
CC
V
CC
- 0.35
- 0.40
- 0.3V
OUT
V
OUT
Output
V
CC
= 4.5V
V
MAX69_A/M
V
CC
MAX69_AC/AE,
MAX800_C/E
I
= 210mA
V
CC
- 0.17
V
CC
OUT
MAX69_AC, MAX800_C
0.8
1.2
V
CC
-to-V
On-Resistance
V = 4.5V
CC
Ω
OUT
MAX69_AE, MAX800_E
MAX69_A/M
0.8
0.8
1.4
1.6
VBATT = 4.5V, IOUT = 20mA
VBATT = 2.8V, IOUT = 10mA
VBATT = 2.0V, IOUT = 5mA
VBATT = 4.5V
VBATT - 0.3
VBATT - 0.25
VBATT - 0.15
V
Mode
in Battery-Backup
OUT
V
1693L/AX80M
15
25
30
VBATT-to-V
On-Resistance
OUT
VBATT = 2.8V
Ω
VBATT = 2.0V
Supply Current in
Normal Operating Mode
V
> VBATT - 1V
30
100
µA
µA
CC
(Excludes I
)
OUT
Supply Current in
Battery-Backup Mode
T
= +25°C
0.04
1
5
A
V
< VBATT - 1.2V
CC
VBATT = 2.8V
T
A
= T + T
MIN MIN
(Excludes I ) (Note 2)
OUT
T
= +25°C
-0.1
-1.0
0.02
0.02
VBATT Standby Current
(Note 3)
A
VBATT + 0.2V ≤ V
µA
V
CC
T
A
= T
+ T
MIN
MIN
Power-up
VBATT + 0.3
VBATT - 0.3
Battery Switchover
Threshold
Power-down
2
_______________________________________________________________________________________
Mic ro p ro c e s s o r S u p e rvis o ry Circ u it s
1693L/AX80M
ELECTRICAL CHARACTERISTICS (continued)
(MAX691A, MAX800L: V = +4.75V to +5.5V, MAX693A, MAX800M: V = +4.5V to +5.5V, VBATT = 2.8V, T = T
to T
,
CC
CC
A
MIN
MAX
unless otherwise noted.)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Battery Switchover
Hysteresis
60
mV
I
= 3.2mA
= 25mA
0.1
0.7
60
0.4
1.5
BATT ON Output
Low Voltage
SINK
V
I
SINK
Sink current
mA
µA
BATT ON Output
Short-Circuit Current
Source current
1
15
100
RESET AND WATCHDOG TIMER
MAX691A, MAX800L
MAX693A, MAX800M
MAX800L, T = +25°C, V falling
4.50
4.25
4.55
4.30
4.65
4.40
4.75
4.50
4.70
4.45
Reset Threshold Voltage
V
A
CC
MAX800M, T = +25°C, V falling
A
CC
Reset Threshold Hysteresis
15
80
mV
µs
V
to RESET Delay
Power-down
CC
800
ns
LOW LINE-to-RESET Delay
Reset Active Timeout Period,
Internal Oscillator
Power-up
Power-up
140
200
280
ms
Reset Active Timeout Period,
External Clock (Note 4)
Clock
Cycles
2048
Long period
Short period
Long period
Short period
1.0
70
1.6
100
2.25
140
sec
ms
Watchdog Timeout Period,
Internal Oscillator
4096
1024
Watchdog Timeout Period,
External Clock (Note 4)
Clock
Cycles
Minimum Watchdog Input
Pulse Width
V
= 0.8V, V = 0.75 x V
CC
100
3.5
0.1
ns
V
IL
IH
I
= 50µA, V = 1V, VBATT = 0V, V falling
0.004
0.1
0.3
0.4
SINK
CC
CC
I
= 3.2mA, V = 4.25V
CC
RESET Output Voltage
SINK
I
= 1.6mA, V = 5V
CC
SOURCE
–
RESET Output Short-Circuit
Output source current
7
20
mA
V
Current
RESET Output Voltage Low
(Note 5)
I
= 3.2mA
0.4
SINK
I
= 3.2mA, V = 4.25V
0.4
SINK
CC
V
LOW LINE Output Voltage
I
= 1µA, V = 5V
3.5
1
SOURCE
CC
LOW LINE Output
Short-Circuit Current
Output source current
= 3.2mA
15
3
100
0.4
µA
V
I
SINK
WDO Output Voltage
I
= 500µA, V = 5V
3.5
SOURCE
CC
WDO Output
Short-Circuit Current
Output source current
10
mA
V
V
0.75 x V
WDI Threshold Voltage
(Note 6)
IH
CC
V
0.8
50
IL
WDI = 0V
WDI = V
-50
-10
20
WDI Input Current
µA
OUT
_______________________________________________________________________________________
3
Mic ro p ro c e s s o r S u p e rvis o ry Circ u it s
ELECTRICAL CHARACTERISTICS (continued)
(MAX691A, MAX800L: V = +4.75V to +5.5V, MAX693A, MAX800M: V = +4.5V to +5.5V, VBATT = 2.8V, T = T
to T
,
CC
CC
A
MIN
MAX
unless otherwise noted.)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
POWER-FAIL COMPARATOR
MAX69_AC/AE/AM, V = 5V
1.2
1.25
1.25
1.3
1.275
±25
0.4
CC
PFI Input Threshold
V
nA
V
MAX800_C/E, V = 5V
1.225
CC
PFI Leakage Current
PFO Output Voltage
±0.01
I
= 3.2mA
SINK
I
= 1µA, V = 5V
3.5
1
SOURCE
CC
PFO Output Short-Circuit
Current
Output source current
= -20mV, V = 15mV
15
100
µA
µs
V
IN
25
60
OD
PFI-to-PFO Delay
V
IN
= 20mV, V = 15mV
OD
CHIP-ENABLE GATING
Disable mode
Enable mode
±0.005
75
±1
µA
CE IN Leakage Current
CE IN-to-CE OUT Resistance
(Note 7)
150
Ω
CE OUT Short-Circuit Current
(Reset Active)
–
0.1
0.75
6
2.0
10
mA
ns
Disable mode, CE OUT = 0V
CE IN-to-CE OUT Propagation
Delay (Note 8)
50Ω source impedance driver, C
= 50pF
LOAD
V
= 5V, I
= -100µA
3.5
2.7
CC
OUT
CE OUT Output Voltage High
(Reset Active)
V
V
CC
= 0V, VBATT = 2.8V, I
= 1µA
OUT
Power-down
12
µs
RESET-to-CE OUT Delay
INTERNAL OSCILLATOR
OSC IN Leakage Current
OSC IN Input Pull-Up Current
OSC SEL = 0V
0.10
10
±5
µA
µA
OSC SEL = V
or floating, OSC IN = 0V
100
100
OUT
OSC SEL Input Pull-Up Current OSC SEL = 0V
10
µA
OSC IN Frequency Range
OSC SEL = 0V
50
kHz
V
V
OUT
- 0.3
V
- 0.6
IH
OUT
OSC IN External Oscillator
Threshold Voltage
V
V
IL
3.65
100
2.00
1693L/AX80M
OSC IN Frequency with
External Capacitor
OSC SEL = 0V, COSC = 47pF
kHz
Note 1: Either V or VBATT can go to 0V, if the other is greater than 2.0V.
CC
Note 2: The supply current drawn by the MAX691A/MAX800L/MAX800M from the battery excluding I
typically goes to 10µA
OUT
when (VBATT - 1V) < V < VBATT. In most applications, this is a brief period as V falls through this region.
CC
CC
Note 3: “+” = battery-discharging current, “--” = battery-charging current.
Note 4: Although presented as typical values, the number of clock cycles for the reset and watchdog timeout periods are fixed and
do not vary with process or temperature.
Note 5: RESET is an open-drain output and sinks current only.
Note 6: WDI is internally connected to a voltage divider between V
and GND. If unconnected, WDI is driven to 1.6V (typ),
OUT
disabling the watchdog function.
Note 7: The chip-enable resistance is tested with V = +4.75V for the MAX691A/MAX800L and V = +4.5V for the
CC
CC
MAX693A/MAX800M. CE IN = CE OUT = V / 2.
CC
Note 8: The chip-enable propagation delay is measured from the 50% point at CE IN to the 50% point at CE OUT.
4
_______________________________________________________________________________________
Mic ro p ro c e s s o r S u p e rvis o ry Circ u it s
1693L/AX80M
__________________________________________Typ ic a l Op e ra t in g Ch a ra c t e ris t ic s
(T = +25°C, unless otherwise noted.)
A
V
SUPPLY CURRENT
CC
BATTERY SUPPLY CURRENT
vs. TEMPERATURE
(BATTERY-BACKUP MODE)
CHIP-ENABLE ON-RESISTANCE
vs. TEMPERATURE
vs. TEMPERATURE
(NORMAL OPERATING MODE)
120
100
36
34
32
30
28
2
1.5
1
V
= 4.75V
V
= 5V
CC
CC
V = 5V
CC
VBATT = 2.8V
NO LOAD
VBATT = 2.8V
= V /2
VBATT = 2.8V
PFI, CE IN = 0V
V
CE IN CC
80
60
0.5
0
26
40
-60 -30
0
30 60 90 120 150 180
TEMPERATURE (°C)
-60 -30
0
30
60
90 120 150
-60 -30
0
30
60
90 120 150
TEMPERATURE (°C)
TEMPERATURE (°C)
PFI THRESHOLD
vs. TEMPERATURE
VBATT to V ON-RESISTANCE
OUT
V
CC
to V ON-RESISTANCE
OUT
vs. TEMPERATURE
vs. TEMPERATURE
1.50
1.25
1.00
0.75
0.50
0.25
0
20
15
10
5
1.2
1.1
1.0
0.9
0.8
0.7
0.6
V
= 5V,
CC
VBATT = 0V
VBATT = 2.0V
VBATT = 2.8V
VBATT = 4.5V
V
= +5V,
CC
VBATT = 0V
NO LOAD ON PFO
V
= 0V
CC
-60 -30
0
30
60
90 120 150
-60 -30
0
30
60
90 120 150
-60 -30
0
30
60
90 120 150
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
RESET THRESHOLD
vs. TEMPERATURE
RESET OUTPUT RESISTANCE
vs. TEMPERATURE
RESET DELAY
vs. TEMPERATURE
230
220
210
200
190
180
170
4.75
4.70
4.65
4.60
4.55
4.50
4.45
4.40
4.35
4.30
600
500
400
300
VBATT = 2.8V
V
= 0V TO 5V STEP
CC
VBATT = 2.8V
V
= 5V, VBATT = 2.8V
CC
MAX691A
MAX800L
SOURCING CURRENT
200
100
MAX693A
MAX800M
V
= 0V, VBATT = 2.8V
CC
SINKING CURRENT
0
-60 -30
0
30
60
90 120 150
-60 -30
0
30
60
90 120 150
-60 -30
0
30
60
90 120 150
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
_______________________________________________________________________________________
5
Mic ro p ro c e s s o r S u p e rvis o ry Circ u it s
____________________________Typ ic a l Op e ra t in g Ch a ra c t e ris t ic s (c o n t in u e d )
(T = +25°C, unless otherwise noted.)
A
BATTERY CURRENT
vs. INPUT SUPPLY VOLTAGE
CHIP-ENABLE PROPAGATION DELAY
vs. CE OUT LOAD CAPACITANCE
WATCHDOG AND RESET TIMEOUT PERIOD
vs. OSC IN TIMING CAPACITOR (COSC)
20
20
100
10
1
V
= 5V
VBATT = 2.8V
CC
V
= 5V
CC
LONG WATCHDOG
TIMEOUT PERIOD
CE IN = 0V TO 5V
DRIVER SOURCE
IMPEDANCE = 50Ω
I
= 0A
OUT
VBATT = 2.8V
16
12
8
16
12
RESET ACTIVE
TIMEOUT PERIOD
8
4
0
SHORT WATCHDOG
TIMEOUT PERIOD
4
0
0.1
0
1
2
3
4
5
0
50
100
150
(pF)
200
250 300
10
100
COSC (pF)
1000
V
CC
(V)
C
LOAD
V
CC
to V vs. OUTPUT CURRENT
OUT
VBATT to V vs. OUTPUT CURRENT
OUT
V
CC
to LOW LINE
(NORMAL OPERATING MODE)
(BATTERY-BACKUP MODE)
AND CE OUT DELAY
1000
100
10
1000
100
10
V
= 4.5V
V
= 0V
CC
CC
5V
RESET
THRESHOLD
VBATT = 0V
VBATT = 4.5V
V
CC
80µs
HI
LOW LINE
LO
800ns
SLOPE = 8Ω
HI
RESET
LO
SLOPE = 0.8Ω
HI
CE OUT
LO
12µs
1
1
1
10
100
1000
1
10
(mA)
100
I
(mA)
I
OUT
OUT
1693L/AX80M
6
_______________________________________________________________________________________
Mic ro p ro c e s s o r S u p e rvis o ry Circ u it s
1693L/AX80M
______________________________________________________________P in De s c rip t io n
PIN
NAME
FUNCTION
Battery-Backup Input. Connect to external battery or capacitor and charging circuit. If backup battery is not
used, connect to GND.
1
VBATT
Output Supply Voltage. When V is greater than VBATT and above the reset threshold, V
connects to
CC
OUT
2
V
OUT
V
. When V falls below VBATT and is below the reset threshold, V connects to VBATT. Connect a 0.1µF
OUT
CC
CC
capacitor from V
to GND. Connect V to V if no backup battery is used.
OUT CC
OUT
3
4
V
CC
Input Supply Voltage, 5V input.
GND
Ground. 0V reference for all signals.
Battery On Output. When V
goes low. Connect the base of a PNP through a current-limiting resistor to BATT ON for V
ments greater than 250mA.
switches to VBATT, BATT ON goes high. When V
switches to V
BATT ON
OUT
OUT
CC,
5
6
BATT ON
current require-
OUT
LOW LINE output goes low when V falls below the reset threshold. It returns high as soon as V rises above
the reset threshold.
CC
CC
LOW LINE
External Oscillator Input. When OSC SEL is unconnected or driven high, a 10µA pull-up connects from V
to
OUT
OSC IN, the internal oscillator sets the reset and watchdog timeout periods, and OSC IN selects between fast
and slow watchdog timeout periods. When OSC SEL is driven low, the reset and watchdog timeout periods may
be set either by a capacitor from OSC IN to ground or by an external clock at OSC IN (Figure 3).
7
8
OSC IN
Oscillator Select. When OSC SEL is unconnected or driven high, the internal oscillator sets the reset delay and
watchdog timeout period. When OSC SEL is low, the external oscillator input (OSC IN) is enabled (Table 1).
OSC SEL has a 10µA internal pull-up.
OSC SEL
Power-Fail Input. This is the noninverting input to the power-fail comparator. When PFI is less than 1.25V, PFO
9
PFI
goes low. When PFI is not used, connect PFI to GND or V
.
OUT
Power-Fail Output. This is the output of the power-fail comparator. PFO goes low when PFI is less than 1.25V.
This is an uncommitted comparator, and has no effect on any other internal circuitry.
10
PFO
Watchdog Input. WDI is a three-level input. If WDI remains either high or low for longer than the watchdog time-
out period, WDO goes low and reset is asserted for the reset timeout period. WDO remains low until the next tran-
sition at WDI. Leaving WDI unconnected disables the watchdog function. WDI connects to an internal voltage
11
WDI
divider between V
and GND, which sets it to mid-supply when left unconnected.
OUT
Chip-Enable Output. CE OUT goes low only when CE IN is low and V is above the reset threshold. If CE IN is
low when reset is asserted, CE OUT will stay low for 15µs or until CE IN goes high, whichever occurs first.
CC
12
13
CE OUT
CE IN
Chip-Enable Input. The input to chip-enable gating circuit. If CE IN is not used, connect CE IN to GND or V
OUT.
Watchdog Output. If WDI remains high or low longer than the watchdog timeout period, WDO goes low and reset
is asserted for the reset timeout period. WDO returns high on the next transition at WDI. WDO remains high if
WDI is unconnected.
14
WDO
RESET Output goes low whenever V falls below the reset threshold. RESET will remain low typically for
200ms after V crosses the reset threshold on power-up.
CC
CC
15
16
RESET
RESET
RESET is an active-high output. It is open drain, and the inverse of RESET.
g ua ra nte e d to b e va lid d own to VCC = 1V, a nd a n
external 10kΩ pull-down resistor on RESET insures
that it will be valid with VCC down to GND (Figure 1).
As VCC goes below 1V, the gate drive to the RESET
outp ut s witc h re d uc e s a c c ord ing ly, inc re a s ing the
RDS(ON) and the saturation voltage. The 10kΩ pull-
down resistor insures the parallel combination of switch
plus resistor is around 10kΩ and the output saturation
voltage is below 0.4V while sinking 40µA. When using
a 10kΩ external pull-down resistor, the high state for
RESET output with VCC = 4.75V will be 4.5V typical.
For battery voltages ≥ 2V connected to VBATT, RESET
and RESET remain valid for VCC from 0V to 5.5V.
_______________De t a ile d De s c rip t io n
–————–
R E S E T a n d RES ET Ou t p u t s
The MAX691A/MAX693A/MAX800L/MAX800M’s RESET
a nd RESET outp uts e ns ure tha t the µP (with re s e t
inputs a sse rte d e ithe r hig h or low) p owe rs up in a
known state, and prevents code-execution errors dur-
ing power-down or brownout conditions.
The RESET output is active low, and typically sinks
3.2mA at 0.1V saturation voltage in its active state.
–
When deasserted, RESET sources 1.6mA at typically
VOUT - 0.5V. RESET output is open drain, active high,
and typically sinks 3.2mA with a saturation voltage of
0.1V. When no backup battery is used, RESET output is
_______________________________________________________________________________________
7
Mic ro p ro c e s s o r S u p e rvis o ry Circ u it s
WDI
15
RESET
TO µP RESET
WDO
1k
MAX691A
MAX693A
t
2
RESET
t
1
t
1
t
3
t = RESET TIMEOUT PERIOD
1
t = NORMAL WATCHDOG TIMEOUT PERIOD
2
t = WATCHDOG TIMEOUT PERIOD IMMEDIATELY AFTER RESET
3
Figure 2. Watchdog Timeout Period and Reset Active Time
Figure 1. Adding an external pull-down resistor ensures
–————–
RESET is valid with V down to GND.
CC
Watchdog Output
RESET and RESET are asserted when VCC falls below
the reset threshold (4.65V for the MAX691A/MAX800L,
4.4V for the MAX693A/MAX800M) and remain asserted
for 200ms typ after VCC rises above the reset threshold
on p owe r-up (Fig ure 5). The d e vic e s ’ b a tte ry-
switchover comparator does not affect reset assertion.
However, both reset outputs are asserted in battery-
b a c kup mod e s inc e VCC mus t b e b e low the re s e t
threshold to enter this mode.
The Watchdog Output (WDO) remains high if there is a
transition or pulse at WDI during the watchdog timeout
–
period. The watchdog function is disabled and WDO is
a logic high when VCC is below the reset threshold, bat-
tery-backup mode is enabled, or WDI is an open circuit.
In watchdog mode, if no transition occurs at WDI during
the watchdog timeout period, RESET and RESET are
asserted for the reset timeout period (200ms typical).
WDO goes low and remains low until the next transition
at WDI (Figure 2). If WDI is held high or low indefinitely,
RESET and RESET will generate 200ms pulses every
1.6sec. WDO has a 2 x TTL output characteristic.
Wa t c h d o g Fu n c t io n
The watchdog monitors µP activity via the Watchdog
Input (WDI). If the µP becomes inactive, RESET and
RESET are asserted. To use the watchdog function,
c onne c t WDI to a b us line or µP I/O line . If WDI
remains high or low for longer than the watchdog time-
out period (1.6sec nominal), WDO, RESET, and RESET
are asserted (see RESET and RESET Outputs section,
and the Watchdog Output discussion on this page).
Selecting an Alternative
Watchdog and Reset Timeout Period
The OSC SEL and OSC IN inputs control the watchdog
and reset timeout periods. Floating OSC SEL and OSC
IN or tying them both to VOUT selects the nominal 1.6sec
watchdog timeout period and 200ms reset timeout peri-
od. Connecting OSC IN to GND and floating or connect-
ing OSC SEL to VOUT s e le c ts the 100ms norma l
watchdog timeout delay and 1.6sec delay immediately
after reset. The reset timeout delay remains 200ms
(Figure 2). Select alternative timeout periods by con-
necting OSC SEL to GND and connecting a capacitor
between OSC IN and GND, or by externally driving OSC
IN (Table 1 and Figure 3). OSC IN is internally connect-
ed to a ±100nA (typ) current source that charges and
discharges the timing capacitor to create the oscillator
frequency, which sets the reset and watchdog timeout
periods (see Connecting a Timing Capacitor at OSC IN
in the Applications Information section).
1693L/AX80M
Watchdog Input
A change of state (high to low, low to high, or a mini-
mum 100ns pulse) at the WDI during the watchdog
p e riod re s e ts the wa tc hd og time r. The wa tc hd og
default timeout is 1.6sec.
To disable the watchdog function, leave WDI floating.
An internal resistor network (100kΩ equivalent imped-
a nc e a t WDI) b ia s e s WDI to a p p roxima te ly 1.6V.
Internal comparators detect this level and disable the
watchdog timer. When VCC is below the reset thresh-
old, the watchdog function is disabled and WDI is dis-
c onne c te d from its inte rna l re s is tor ne twork, thus
becoming high impedance.
8
_______________________________________________________________________________________
Mic ro p ro c e s s o r S u p e rvis o ry Circ u it s
1693L/AX80M
Table 1. Reset Pulse Width and Watchdog Timeout Selections
Watchdog Timeout Period
OSC SEL
OSC IN
Reset Timeout Period
Normal
Immediately After Reset
4096 clks
Low
Low
External Clock Input
External Capacitor
Low
1024 clks
(600/47pF x C)ms
100ms
2048 clks
(1200/47pF x C)ms
200ms
(2.4/47pF x C)sec
1.6sec
Floating
Floating
Floating
1.6sec
1.6sec
200ms
In the high-impedance mode, the leakage currents into
this terminal are ±1µA max over temperature. In the
low-impedance mode, the impedance of CE IN appears
as a 75Ω resistor in series with the load at CE OUT.
EXTERNAL
CLOCK
EXTERNAL
OSCILLATOR
–
MAX691A
MAX693A
MAX800L
MAX800M
8
7
8
7
OSC SEL
OSC SEL
The propagation delay through the CE transmission
gate depends on both the source impedance of the
OSC IN
OSC IN
–
drive to CE IN and the capacitive loading on the Chip-
50kHz
–
Enable Output (CE OUT) (see Chip-Enable Propagation
Delay vs. CE OUT Load Capacitance in the Typical
Operating Characteristics). The CE propagation delay
INTERNAL OSCILLATOR
1.6sec WATCHDOG
INTERNAL OSCILLATOR
100ms WATCHDOG
–
is production tested from the 50% point of CE IN to the
–
8
8
50% point of CE OUT using a 50Ω driver and 50pF of
OSC SEL
OSC SEL
N.C.
N.C.
load capacitance (Figure 6). For minimum propagation
delay, minimize the capacitive load at CE OUT, and
use a low output-impedance driver.
7
7
N.C.
OSC IN
OSC IN
Chip-Enable Output
Figure 3. Oscillator Circuits
In the enabled mode, the impedance of CE OUT is
equivalent to 75Ω in series with the source driving CE
IN. In the disabled mode, the 75Ω transmission gate is
off and CE OUT is actively pulled to VOUT. This source
turns off when the transmission gate is enabled.
Ch ip -En a b le S ig n a l Ga t in g
The MAX691A/MAX693A/MAX800L/MAX800M provide
internal gating of chip-enable (CE) signals to prevent
erroneous data from being written to CMOS RAM in the
event of a power failure. During normal operation, the
CE gate is enabled and passes all CE transitions. When
reset is asserted, this path becomes disabled, prevent-
ing erroneous data from corrupting the CMOS RAM. All
these parts use a series transmission gate from CE IN to
CE OUT (Figure 4).
–———————–
LOW LINE Ou t p u t
LOW LINE is the buffered output of the reset threshold
comparator. LOW LINE typically sinks 3.2mA at 0.1V.
For normal operation (VCC above the LOW LINE thresh-
–
old), LOW LINE is pulled to VOUT
.
P o w e r-Fa il Co m p a ra t o r
The power-fail comparator is an uncommitted comparator
tha t ha s no e ffe c t on the othe r func tions of the IC.
Common uses include low-battery indication (Figure 7),
and early power-fail warning (see Typical Operating
Circuit).
The 10ns max CE propagation delay from CE IN to CE
OUT enables the parts to be used with most µPs.
Chip-Enable Input
The Chip-Enable Input (CE IN) is high impedance (dis-
abled mode) while RESET and RESET are asserted.
–————–
Power-Fail Input
During a power-down sequence where V falls below
CC
–
the reset threshold or a watchdog fault, CE IN assumes
–
Power Fail Input (PFI) is the input to the power-fail com-
parator. It has a guaranteed input leakage of ±25nA
max over temperature. The typical comparator delay is
a high-impedance state when the voltage at CE IN
goes high or 15µs after reset is asserted, whichever
occurs first (Figure 5).
25µs from V to V (power failing), and 60µs from V
IL
OL
IH
to VOH (power being restored). If PFI is not used, con-
nect it to ground.
During a p owe r-up s e q ue nc e , CE IN re ma ins hig h
impedance, regardless of CE IN activity, until reset is
deasserted following the reset timeout period.
_______________________________________________________________________________________
9
Mic ro p ro c e s s o r S u p e rvis o ry Circ u it s
5
BATT ON
4.65V*
6
LOW LINE
3
V
CC
2
V
OUT
CHIP-ENABLE
OUTPUT
CONTROL
1
VBATT
CE IN
13
12
16
CE OUT
RESET
MAX691A
MAX693A
MAX800L
MAX800M
RESET
GENERATOR
15
RESET
7
8
TIMEBASE FOR
RESET AND
OSC IN
OSC SEL
WATCHDOG
WATCHDOG
TRANSITION
DETECTOR
11
9
WATCHDOG
TIMER
14
10
WDI
PFI
WDO
PFO
1.25V
4
GND
* 4.4V FOR THE MAX693A/MAX800M
Figure 4. MAX691A/MAX693A/MAX800L/MAX800M Block Diagram
5.0V
V
CC
RESET
THRESHOLD
4.0V
5.0V
CE IN
1693L/AX80M
0V
5V
CE OUT
0V
15µs
100µs
100µs
5V
RESET
RESET
0V
5V
0V
LOGIC LEVELS SHOWN ARE FROM 0V TO 5V.
Figure 5. Reset and Chip-Enable Timing
10 ______________________________________________________________________________________
Mic ro p ro c e s s o r S u p e rvis o ry Circ u it s
1693L/AX80M
+5V
+5V
V
CC
V
CC
VBATT
VBATT
2.8V
MAX691A
MAX693A
MAX800L
MAX800M
MAX691A
MAX693A
MAX800L
MAX800M
2.0V to 5.5V
PFI
LOW BATT
PFO
CE OUT
CE IN
50Ω
OUTPUT
GND
GND
C
LOAD
IMPEDANCE
Figure 6. CE Propagation Delay Test Circuit
Figure 7. Low-Battery Indicator
Power-Fail Output
Table 2. Input and Output Status in Battery-Backup
Mode
The Power-Fail Output (PFO) goes low when PFI goes
below 1.25V. It typically sinks 3.2mA with a saturation
voltage of 0.1V. With PFI above 1.25V, PFO is actively
PIN
NAME
STATUS
1
VBATT
Supply current is 1µA max.
pulled to VOUT
.
V
is connected to VBATT through an
OUT
2
V
OUT
Ba t t e ry-Ba c k u p Mo d e
internal PMOS switch.
Two conditions are required to switch to battery-back-
up mode: 1) VCC must be below the reset threshold,
and 2) VCC must be below VBATT. Table 2 lists the sta-
tus of the inputs and outputs in battery-backup mode.
Battery switchover comparator monitors
3
4
5
V
CC
V
CC
for active switchover.
GND
GND 0V, 0V reference for all signals.
Logic high. The open-circuit output is
Ba t t e ry On Ou t p u t
The Battery On (BATT ON) output indicates the status
of the inte rna l VCC/b a tte ry-s witc hove r c omp a ra tor,
which controls the internal VCC and VBATT switches.
For VCC greater than VBATT (ignoring the small hys-
teresis effect), BATT ON typically sinks 3.2mA at 0.1V
saturation voltage. In battery-backup mode, this termi-
nal sources approximately 10µA from VOUT. Use BATT
ON to indicate battery-switchover status or to supply
base drive to an external pass transistor for higher-cur-
rent applications (see Typical Operating Circuit).
BATT ON
equal to V
.
OUT
6
7
8
Logic low*
OSC IN is ignored.
LOWLINE
OSC IN
OSC SEL OSC SEL is ignored.
The power-fail comparator remains
9
PFI
active in the battery-backup mode for
≥ VBATT - 1.2V typ.
V
CC
The power-fail comparator remains
active in the battery-backup mode for
10
PFO
V
CC
≥ VBATT - 1.2V typ. Below this volt-
In p u t S u p p ly Vo lt a g e
The Input Supply Voltage (VCC) should be a regulated
5V. VCC connects to VOUT via a parallel diode and a
large PMOS switch. The switch carries the entire cur-
rent load for currents less than 250mA. The parallel
diode carries any current in excess of 250mA. Both the
switch and the diode have impedances less than 1Ω
each. The maximum continuous current is 250mA, but
power-on transients may reach a maximum of 1A.
age, PFO is forced low.
11
12
13
14
WDI
CE OUT
CE IN
Watchdog is ignored.
Logic high. The open-circuit voltage is
equal to V
.
OUT
High impedance
Logic high. The open-circuit voltage is
WDO
equal to V
.
OUT
15
16
Logic low*
High impedance*
RESET
RESET
* V must be below the reset threshold to enter battery-backup
CC
mode.
______________________________________________________________________________________ 11
Mic ro p ro c e s s o r S u p e rvis o ry Circ u it s
1) Normal operating mode with all circuitry powered
Ba t t e ry-Ba c k u p In p u t
The Battery-Backup Input (VBATT) is similar to the VCC
input except the PMOS switch and parallel diode are
much smaller. Accordingly, the on-resistances of the
diode and the switch are each approximately 10Ω.
Continuous current should be limited to 25mA and
peak currents (only during power-up) limited to 250mA.
The reverse leakage of this input is less than 1µA over
temperature and supply voltage (Figure 8).
up. Typical supply current from VCC is 35µA while
only leakage currents flow from the battery.
2) Battery-backup mode where VCC is typically within
0.7V below VBATT. All circuitry is powered up
and the supply current from the battery is typically
less than 60µA.
3) Ba tte ry-b a c kup mod e whe re VCC is le s s tha n
VBATT by at least 0.7V. VBATT supply current is
1µA max.
Ou t p u t S u p p ly Vo lt a g e
The Output Supply Voltage (VOUT) pin is internally con-
nected to the substrate of the IC and supplies current
to the external system and internal circuitry. All open-
circuit outputs will, for example, assume the VOUT volt-
age in their high states rather than the VCC voltage. At
the maximum source current of 250mA, VOUT will typi-
cally be 200mV below VCC. Decouple this terminal with
a 0.1µF capacitor.
Us in g S u p e rCa p ™ o r Ma x Ca p ™ w it h t h e
MAX6 9 1 A/MAX6 9 3 A/MAX8 0 0 L/MAX8 0 0 M
VBATT has the same operating voltage range as VCC
,
and the battery switchover threshold voltages are typi-
c a lly ±30mV c e nte re d a t VBATT, a llowing use of a
SuperCap and a simple charging circuit as a backup
source (Figure 9).
If VCC is above the reset threshold and VBATT is 0.5V
above VCC, current flows to VOUT and VCC from VBATT
until the voltage at VBATT is less than 0.5V above VCC.
__________Ap p lic a t io n s In fo rm a t io n
The MAX691A/MAX693A/MAX800L/MAX800M are not
short-circuit protected. Shorting VOUT to ground, other
than power-up transients such as charging a decou-
pling capacitor, destroys the device.
For example, with a SuperCap connected to VBATT and
through a diode to VCC, if VCC quickly changes from 5.4V
to 4.9V, the capacitor discharges through VOUT and VCC
until VBATT reaches 5.1V typ. Leakage current through
the SuperCap charging diode and the internal power
diode eventually discharges the SuperCap to VCC. Also, if
VCC and VBATT start from 0.1V above the reset threshold
and power is lost at VCC, the SuperCap on VBATT dis-
charges through VCC until VBATT reaches the reset
threshold; then the battery-backup mode is initiated and
the current through VCC goes to zero.
All open-circuit outputs swing between VOUT and GND
rather than VCC and GND.
If long leads connect to the chip inputs, insure that
these leads are free from ringing and other conditions
that would forward bias the chip’s protection diodes.
There are three distinct modes of operation:
+5V
3
V
CC
1N4148
0.47F*
1693L/AX80M
VBATT
1
2
VBATT
V
OUT
MAX691A
MAX693A
MAX800L
MAX800M
V
OUT
MAX691A
MAX693A
MAX800L
MAX800M
0.1µF
V
CC
GND
4
* MaxCap
Figure 8. V and VBATT to V
Switch
Figure 9. SuperCap or MaxCap on VBATT
CC
OUT
12 ______________________________________________________________________________________
Mic ro p ro c e s s o r S u p e rvis o ry Circ u it s
1693L/AX80M
V
IN
Rp*
+5V
CE
CE
R1
RAM 1
RAM 2
V
CC
V
OUT
C1*
R3
PFI
CE IN
CE OUT
CE
CE
MAX691A
MAX693A
MAX800L
MAX800M
MAX691A
MAX693A
MAX800L
MAX800M
R2
CE
CE
PFO
RAM 3
RAM 4
GND
GND
TO µP
*OPTIONAL
CE
CE
5V
PFO
0V
0V
V
L
V
V
TRIP H
V
IN
R1 + R2
R2
V
= 1.25
TRIP
*MAXIMUM Rp VALUE DEPENDS ON
THE NUMBER OF RAMS.
MINIMUM Rp VALUE IS 1kΩ.
ACTIVE-HIGH
CE LINES
FROM LOGIC
R2 I I R3
R1 + R2 I I R3
V - 1.25 5 - 1.25 1.25
L
V = 1.25/
H
+
=
R1
R3
R2
Figure 10. Alternate CE Gating
Figure 11. Adding Hysteresis to the Power-Fail Comparator
Us in g S e p a ra t e P o w e r S u p p lie s
fo r VBATT a n d V
CC
+5V
If using separate power supplies for VCC and VBATT,
VBATT must be less than 0.3V above VCC when VCC is
above the reset threshold. As described in the previ-
ous section, if VBATT exceeds this limit and power is
lost at VCC, current flows continuously from VBATT to
VCC via the VBATT-to-VOUT diode and the VOUT-to-VCC
switch until the circuit is broken (Figure 8).
R1
V
CC
PFO
PFI
MAX691A
MAX693A
MAX800L
MAX800M
Alt e rn a t e Ch ip -En a b le Ga t in g
Using memory devices with both CE and CE inputs
allows the CE loop to be bypassed. To do this, con-
R2
GND
nect CE IN to ground, pull up CE OUT to VOUT, and
–
c onne c t CE OUT to the CE inp ut of e a c h me mory
V-
5V
PFO
0V
device (Figure 10). The CE input of each part then
connects directly to the chip-select logic, which does
not have to be gated.
V
TRIP
V-
0V
Ad d in g Hys t e re s is t o t h e
P o w e r-Fa il Co m p a ra t o r
5 - 1.25 1.25 - V
TRIP
=
R1
R2
Hysteresis adds a noise margin to the power-fail com-
parator and prevents repeated triggering of PFO when
NOTE: V IS NEGATIVE
TRIP
V
is near the power-fail comparator trip point. Figure
IN
11 shows how to add hysteresis to the power-fail com-
Figure 12. Monitoring a Negative Voltage
______________________________________________________________________________________ 13
Mic ro p ro c e s s o r S u p e rvis o ry Circ u it s
Ba c k u p -Ba t t e ry Re p la c e m e n t
The backup battery may be disconnected while VCC is
above the reset threshold. No precautions are neces-
sary to avoid spurious reset pulses.
100
80
V
= 5V
CC
T = +25°C
A
0.1µF CAPACITOR
FROM V TO GND
Ne g a t ive -Go in g V
Tra n s ie n t s
CC
OUT
While issuing resets to the µP during power-up, power-
down, and brownout conditions, these supervisors are
relatively immune to short-duration, negative-going VCC
transients (glitches). It is usually undesirable to reset
the µP when VCC experiences only small glitches.
60
40
Figure 13 shows maximum transient duration vs. reset-
comparator overdrive, for which reset pulses are not
generated. The graph was produced using negative-
going VCC pulses, starting at 5V and ending below the
reset threshold by the magnitude indicated (reset com-
parator overdrive). The graph shows the maximum
pulse width a negative-going VCC transient may typical-
ly have without causing a reset pulse to be issued. As
the amplitude of the transient increases (i.e., goes far-
ther below the reset threshold), the maximum allowable
pulse width decreases. Typically, a VCC transient that
goes 100mV below the reset threshold and lasts for
40µs or less will not cause a reset pulse to be issued.
20
0
10
100
RESET COMPARATOR OVERDRIVE,
(Reset Threshold Voltage - V ) (mV)
1000
10000
CC
Figure 13. Maximum Transient Duration without Causing a
Reset Pulse vs. Reset Comparator Overdrive
parator. Select the ratio of R1 and R2 such that PFI sees
1.25V when V falls to the desired trip point (VTRIP).
Resistor R3 adIdNs hysteresis. It will typically be an order
of ma g nitud e g re a te r tha n R1 or R2. The c urre nt
through R1 and R2 should be at least 1µA to ensure that
the 25nA (max) PFI input current does not shift the trip
point. R3 should be larger than 10kΩ to prevent it from
loading down the PFO pin. Capacitor C1 adds noise
rejection.
A 100nF bypass capacitor mounted close to the VCC
pin provides additional transient immunity.
Co n n e c t in g a Tim in g Ca p a c it o r a t OS C IN
When OSC SEL is connected to ground, OSC IN dis-
connects from its internal 10µA (typ) pull-up and is
inte rna lly c onne c te d to a ± 100nA c urre nt s ourc e .
When a capacitor is connected from OSC IN to ground
(to select alternative reset and watchdog timeout peri-
ods), the current source charges and discharges the
timing capacitor to create the oscillator that controls the
reset and watchdog timeout period. To prevent timing
errors or oscillator start-up problems, minimize external
current leakage sources at this pin, and locate the
capacitor as close to OSC IN as possible. The sum of
PC-board leakage plus OSC capacitor leakage must be
small compared to ±100nA.
Mo n it o rin g a Ne g a t ive Vo lt a g e
The power-fail comparator can be used to monitor a
negative supply voltage using Figure 12’s circuit. When
the negative supply is valid, PFO is low. When the neg-
ative supply voltage drops, PFO goes high. This cir-
c uit’s a c c ura c y is a ffe c te d b y the PFI thre s hold
tolerance, the VCC voltage, and resistors R1 and R2.
1693L/AX80M
14 ______________________________________________________________________________________
Mic ro p ro c e s s o r S u p e rvis o ry Circ u it s
1693L/AX80M
Ma x im u m V
Fa ll Tim e
CC
The VCC fall time is limited by the propagation delay of
the b a tte ry s witc hove r c omp a ra tor a nd s hould not
exceed 0.03V/µs. A standard rule of thumb for filter
capacitance on most regulators is on the order of 100µF
per amp of current. When the power supply is shut off or
the main battery is disconnected, the associated initial
VCC fall rate is just the inverse or 1A/100µF = 0.01V/µs.
The VCC fall rate decreases with time as VCC falls expo-
nentially, which more than satisfies the maximum fall-time
requirement.
START
SET
WDI
LOW
Wa t c h d o g S o ft w a re Co n s id e ra t io n s
A way to help the watchdog timer keep a closer watch
on software execution involves setting and resetting the
wa tc hd og inp ut a t d iffe re nt p oints in the p rog ra m,
rather than “pulsing” the watchdog input high-low-high
or low-high-low. This technique avoids a “stuck” loop
where the watchdog timer continues to be reset within
the loop, keeping the watchdog from timing out. Figure
14 shows an example flow diagram where the I/O dri-
ving the watchdog input is set high at the beginning of
the program, set low at the beginning of every subrou-
tine or loop, then set high again when the program
returns to the beginning. If the program should “hang”
in any subroutine, the I/O is continually set low and the
watchdog timer is allowed to time out, causing a reset
or interrupt to be issued.
SUBROUTINE
OR PROGRAM LOOP
SET WDI
HIGH
RETURN
END
Figure 14. Watchdog Flow Diagram
______________________________________________________________________________________ 15
Mic ro p ro c e s s o r S u p e rvis o ry Circ u it s
_Ord e rin g In fo rm a t io n (c o n t in u e d )
___________________Ch ip To p o g ra p h y
V
VBATT RESET RESET
OUT
PART
TEMP. RANGE
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-55°C to +125°C
0°C to +70°C
0°C to +70°C
-40°C to +85°C
-40°C to +85°C
0°C to +70°C
0°C to +70°C
-40°C to +85°C
-40°C to +85°C
PIN-PACKAGE
16 Plastic DIP
16 Narrow SO
16 Wide SO
MAX693ACPE
MAX693ACSE
MAX693ACWE
MAX693AC/D
MAX693AEPE
MAX693AESE
MAX693AEWE
MAX693AEJE
MAX693AMJE
MAX800LCPE
MAX800LCSE
MAX800LEPE
MAX800LESE
MAX800MCPE
MAX800MCSE
MAX800MEPE
MAX800MESE
V
Dice*
CC
WDO
16 Plastic SO
16 Narrow SO
16 Wide SO
CE IN
GND
CE OUT
0. 11"
(2. 794mm)
16 CERDIP
16 CERDIP
16 Plastic DIP
16 Narrow SO
16 Plastic DIP
16 Narrow SO
16 Plastic DIP
16 Narrow SO
16 Plastic DIP
16 Narrow SO
BATT ON
LOW LINE
WDI
PFI PFO
OSC SEL
OSC IN
0. 07"
(1. 778mm)
* Dice are specified at T = +25°C, DC parameters only.
A
TRANSISTOR COUNT: 729
SUBSTRATE CONNECTED TO V
OUT
________________________________________________________P a c k a g e In fo rm a t io n
1693L/AX80M
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
16 ____________________Ma x im In t e g ra t e d P ro d u c t s , 1 2 0 S a n Ga b rie l Drive , S u n n yva le , CA 9 4 0 8 6 4 0 8 -7 3 7 -7 6 0 0
© 1996 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
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