MAX66300ETN+T [MAXIM]
Consumer Circuit, ROHS COMPLIANT, TQFN-56;
| 型号： | MAX66300ETN+T |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Consumer Circuit, ROHS COMPLIANT, TQFN-56 商用集成电路 |
| 文件： | 总20页 (文件大小：516K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ABRIDGED DATA SHEET
MAX66300
DeepCover Secure Authenticator
with SHA-256 and RFID Reader
● Scalable 13.56MHz Analog Front-End Provides
Support for Multiple Antenna Configurations
• Single- or Double-Antenna Driver Using On-Off
Keying (OOK) Modulation
General Description
DeepCover embedded security solutions cloak sensitive
data under multiple layers of advanced physical security
to provide the most secure key storage possible.
®
• User-Selectable ASK Uplink Modulations Index
Adjustable from 7% Up to 30%
• High-Output RF Power of Up to 200mW
• Multiple Receiver Inputs for High-Communication
Reliability
• Built-In Receiver Lowpass-Filter Cutoff Frequen-
cies Selectable Between 400kHz and 1MHz
• Built-In Receiver Highpass-Filter Cutoff Frequency
Selectable Among 100kHz, 200kHz, and 300kHz
• Selectable Receive Gain from 0dB up to 40dB
• Multiple Subcarrier Receiving Compatibility
• (212kHz and 424kHz)
The DeepCover Secure Authenticator (MAX66300)
combines a highly integrated RFID reader for contactless
communication at 13.56MHz and a SHA-256 secure
authenticator coprocessor. The RFID IC reader covers
the ISO 15693 standard. The authenticator coprocessor’s
engine is based on the FIPS 180-4 standard and supports
secure challenge-and-response authentication when
paired with peripherals such as the Maxim MAX66240/
MAX66242 family of tag solutions. An embedded host
processor can easily interface with the MAX66300 using
its UART or SPI interface.
● Antenna Short-Circuit Protection Enhances System
Applications
● Secure Access Control
Ruggedness
● Asset-Tracking Readers
● Authentication of Consumables
•
•
Readers in Printers (Ink Cartridge)
Blood Glucose Meters/Monitors
Ordering Information appears at end of data sheet.
● Handheld Reader Modules
Typical Application Circuit
Features and Benefits
● Secure, Contactless Host Authenticator
• ISO/IEC 15693 Standard Compliant
• SHA-256 Engine to Run a Symmetric Key-Based
Bidirectional Secure Authentication
MAX66300
ANALOG
FRONT-END
COPROCESSOR
UART
SPI
SHA-256 CORE
MEMORY PAGES
M-SECRET KEYS
• Four 32-Byte Pages of User Memory
• Four Master Secrets with Multiple Programmable
Protection Options
• 76-Byte Scratchpad in SRAM
• True Hardware Random-Number Generator
• Unique 64-Bit Serial Number
MAX66242
(TAG)
ANTENNA
DRIVE
CONTROL
RFID READER
PROTOCOL
ARBITRATION
MODULATOR
DEMODULATOR
● Design Flexibility Supports Diverse Applications
• UART and SPI Interface Ports
• Power-Down Mode by an Input Pin
(Low, Standby Power)
• Antenna Short-Circuit Protection
• Compatible with 3.3V or 5V Supply Voltages
• ±2kV HBM ESD Protection
DeepCover is a registered trademark of Maxim Integrated
Products, Inc.
219-0045; Rev 0; 9/14
ABRIDGED DATA SHEET
MAX66300
DeepCover Secure Authenticator
with SHA-256 and RFID Reader
Absolute Maximum Ratings
Continuous Power Dissipation (T = +70°C)
(Applies to pins 33 to 51)
Voltage Range on V , V
A
TQFN (multilayer board)
,
DDA1 DDA2
(derate 47.6mW/°C above +70°C) ..................................1.9W
Operating Temperature Range........................... -40°C to +85°C
Maximum Junction Temperature ..................................... +110°C
Lead Temperature (soldering, 10s) .................................+300°C
ESD Protection per Method 3015 .......................................±2kV
(Applies to pins 1 to 32 and 52 to 56)
and V
...............................................-0.3V to +6V
DD_AFE_DIG
Maximum Voltage Range on Any Input
or Bidirectional Pin.................................V
Minimum Voltage Range on
Any input or Bidirectional Pin .................................V - 0.3V
Maximum Output Current on
+ 0.3V
DD_AFE_DIG
SS
Voltage Range on V
, V
..................-0.3V to +3.6V
Any Single I/O pin except ANT1 and ANT2....................10mA
Maximum AC Peak Current on ANT1 and ANT2 .............100mA
Storage Temperature Range (Note 1).............. -55°C to +120°C
ESD Protection per Method 3015 on ANT1 and ANT2.......±4kV
DD_CORE DDQ
Voltage Range on Any Input
or Bidirectional Pin................................. -0.3V to the lesser of
((V +3.6V),5.5V) for the max
DD_CORE
Voltage Range on HFXIN.............. -0.3V to (V
+ 0.5V)
DD_CORE
Continuous Output Current on Any Single I/O Pin.............25mA
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Note 1: Storage temperature is defined as the temperature of the device when all supply voltage is 0V.
(Note 2)
Package Thermal Characteristics
TQFN
Junction-to-Ambient Thermal Resistance (θ ) ..........21°C/W
Junction-to-Case Thermal Resistance (θ )....................1°C/W
JC
JA
Note 2: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer
board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.
Electrical Characteristics
(V
= V
, limits are 100% tested at T = +25°C and T = +85°C. Limits over the operating temperature range and relevant
DDQ
DD_CORE A A
supply voltage range are guaranteed by design and characterization. Specifications marked GBD are guaranteed by design and not
production tested.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DIGITAL (APPLIES TO PINS 1 TO 32 AND 52 TO 56)
Operating Supply Voltage
Power-Fail Warning Voltage
V
V
3.3
3.6
3.0
V
V
DD_CORE
RST
V
Brownout detection
2.8
RST
External 24MHz clock source
generates system clock; device in
reset
Reset Mode Current
(RESET)
I
I
12
14.4
2.3
20
mA
mA
mA
DD1
External 24MHz clock source
generates system clock; code
running from data memory; CSAM
subcommand loop
Supply Current, External
Clock Source
DD2
T
= +25°C, V = 3.6V,
DD_CORE
A
Sleep Mode Current
(SLEEP)
I
SLEEP = GND, all other pins
disconnected
SLEEP
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ABRIDGED DATA SHEET
MAX66300
DeepCover Secure Authenticator
with SHA-256 and RFID Reader
Electrical Characteristics (continued)
(V
= V
, limits are 100% tested at T = +25°C and T = +85°C. Limits over the operating temperature range and relevant
DDQ
DD_CORE A A
supply voltage range are guaranteed by design and characterization. Specifications marked GBD are guaranteed by design and not
production tested.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
V
current is the sum of V
DDIOH
DDIO
I/O Supply Output High
Voltage
V
DD_CORE
-0.4
V
current and I
of all I/O,
V
V
DDIOH
OH1
DD_CORE
I
= 20mA
OH1
Input Low Voltage (HFXIN)
Input Low Voltage (Any I/O)
V
V
V
V
0.4
V
V
IL1
GND
GND
0.2 x
IL2
V
DD_CORE
Input High Voltage (HFXIN)
Input High Voltage (Any I/O)
Input Hysteresis (Schmitt)
Output Low Voltage
V
V
0.7 x V
0.7 x V
V
V
V
IH1
DDIO
DD_CORE
5.5
IH2
DDIO
V
0.5
6
V
IHYS
V
I
I
= 4mA, V
= 3.0V
V
0.4
V
OL1
OH1
OL1
OH1
DDIO
GND
Output High Voltage
V
= -4mA, V
= 3.0V
V
- 0.6
V
DDIO
V
DDIO
DDIO
Input Crystal Capacitance
Input Leakage Current
Input Pullup Current (Any I/O)
Pullup Resistor (RESET)
VOLTAGE SENSOR
C
Not production tested
5.5V (Note 3)
pF
µA
µA
kΩ
IN
I
V
V
-10
20
+10
55
LEAK
GND ≤ IN ≤
I
-85
40
PU
R
PU
V
High Reset
VDD_CORE
V
4.0
4.6
V
V
DD_CORE_OV
Overvoltage Threshold
REG18 Overvoltage Reset
Threshold
V
2.6
REG18_OV
CLOCK SOURCE
External-Crystal Frequency
Between HFXIN and
HFXOUT
f
f
23.95
24
24
24.05
24.05
MHz
MHz
HFXIN
HFXIN
External-Clock Oscillator
Frequency on HFXIN
23.95
45
External-Clock Period Duty
Cycle
t
55
3
%
CLDC
Clock Rise Time
t
ns
CR
MEMORY CHARACTERISTICS
t
27
20,000
100
ms
PROG
Write/Erase Cycles
Data Retention
Cycles
Years
T = +25°C
A
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ABRIDGED DATA SHEET
MAX66300
DeepCover Secure Authenticator
with SHA-256 and RFID Reader
Electrical Characteristics (continued)
(V
= V
, limits are 100% tested at T = +25°C and T = +85°C. Limits over the operating temperature range and relevant
DDQ
DD_CORE A A
supply voltage range are guaranteed by design and characterization. Specifications marked GBD are guaranteed by design and not
production tested.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
SPI ELECTRICAL CHARACTERISTICS (Figure 6)
SPI Slave Operating
Frequency
1/t
f
= f
f /4
CK
MHz
ns
SCK
SPI_RF
CK
HFXIN
SPI I/O Rise/Fall Time
t
CL = 15pF, pullup = 560Ω
8.3
23.6
SCLK Input Pulse-Width
High/Low
t
t
t
/2
SCK
ns
SCH, SCL
SSEL Active to First Shift
Edge
t
t
t
ns
ns
SSE
SPI_RF
SPI_RF
MOSI Input to SCLK Sample
Edge Rise Setup
t
SIS
MOSI Input from SCLK
Sample Edge Transition Hold
t
t
ns
SIH
SPI_RF
MISO Output Valid After
SCLK Shift Edge Transition
t
2t
ns
ns
ns
SOV
SPI_RF
SSEL Inactive
t
f
f
= 1/f
= 1/f
t
+ t
CK SPI_RF
SSH
CK
CK
HFXIN
SCLK Inactive to SSEL
Rising
t
t
SPI_RF
SD
MISO Output Disabled After
SSEL Edge Rise
2t
2t
+
CK
t
ns
SLH
HFXIN
SPI_RF
SSEL Rising to Active BUSY
SCLK Delay Between Bytes
SHA-256 ENGINE
t
2
µs
µs
SAB
t
3
SDLY
Computation Time
t
t
ms
ms
CSHA
See Full data sheet
Authentication Time
AUTH
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ABRIDGED DATA SHEET
MAX66300
DeepCover Secure Authenticator
with SHA-256 and RFID Reader
Electrical Characteristics
(Limits are 100% tested at T = +25°C. Limits over the operating temperature range and relevant supply voltage range are guaranteed
A
by design and characterization. Specifications marked GBD are guaranteed by design and not production tested. V
= V
=
DD
DDA1
V
= V
; V = V
= V
= 0V.)
DDA2
DD_AFE_DIG SS
SSA1
SSA2
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
ANALOG FRONT-END (APPLIES TO PINS 33 TO 51)
3.3V
3.3
4.5
3.45
5.0
3.6
5.5
Supply Voltage
V
V
DD
PD
ON
5.0V (Note 4)
Sleep Mode Current
(SLEEP)
I
1
5
µA
mA
3.3V (Note 5)
5.0V
8.5
12
12
20
Supply Current Excluding
Antenna Driver Current
I
3.3V (Note 5)
5.0V
0.7
2.3
1.3
2.5
2.1
2.1
1.6
2.7
AGD Level
V
V
V
V
AGD
POR
3.3V
Power-On Reset Level
5.0V
1.4
3.6
ANTENNA DRIVERS
3.3V, I
modulation index
= 100mA, 100%
ANT
4
5
3
5
9.3
11
7
15
20
12
15
3.3V, I
index
= 30mA, 10% modulation
ANT
Driver Output Impedance
(ANT1 or ANT2)
R
Ω
AD
5.0V, I
= 100mA, 100%
ANT
modulation index
5.0V, I
index
= 100mA, 10% modulation
ANT
10
SPECIAL-PURPOSE PINS (SYSAOUT, SYSBOUT, SYSCOUT, SYSDOUT, SYSEOUT)
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
V
0.2 x V
0.1 x V
V
V
V
V
IL
DD
V
0.8 x V
IH
DD
DD
V
I
I
= 1mA
= 1mA
OL
OL
DD
V
0.9 x V
OH
OH
Interface Clock Rate
Frequency (SYSCOUT)
f
1
MHz
MAX
AM DEMODULATION
RF Amplitude of RFIN Inputs
RFIN Input Resistance
3.3V
1.65
2.5
V
R
V
PP
RFIN
RFIN
SENS
5.0V
3.3V, 5.0V
3.3V
5
15.5
0.75
1.5
20
kΩ
mV
Receiver Sensitivity at
212kHz
V
PP
5.0V
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ABRIDGED DATA SHEET
MAX66300
DeepCover Secure Authenticator
with SHA-256 and RFID Reader
Electrical Characteristics (continued)
(Limits are 100% tested at T = +25°C. Limits over the operating temperature range and relevant supply voltage range are guaranteed
A
by design and characterization. Specifications marked GBD are guaranteed by design and not production tested. V
= V
=
DD
DDA1
V
= V
; V = V
= V = 0V.)
SSA2
DDA2
DD_AFE_DIG SS
SSA1
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
0.8
MAX
UNITS
3.3V
5.0V
3.3V
5.0V
Receiver Sensitivity at 24kHz
V
mV
mV
SENS
SENS
P-P
P-P
2.2
1.95
3.5
Receiver Sensitivity at
848kHz
V
Recovery Time of Reception
after Antenna Modulation
t
100
µs
REC
XTAL OSCILLATOR (OSCIN, OSCOUT)
3.3V, normal mode
0.45
2
3.3V, high-oscillator mode
Transconductance
g
mS
M
5.0V, normal mode (Notes 6 and 7)
5.0V, high-oscillator mode (Note 7)
0.9
2.7
Set-Up Time after Power
Down
t
5
15
ms
pF
SET
Input Crystal Capacitance
C
Not production tested
22
INPUT
Note 3: Any tolerant I/O pin, when an input with no internal weak pullup, can reach a peak static current of 45µA (typ) at V
+ 0.4V.
DD_CORE
Note 4: Due to the 10kΩ ±5% resistor pullups on pins SYSBIN, SYSCIN, and SYSEIN in 5V operation, V
needs to be
DD_CORE
present at or before V
.
DD_AFE_DIG
Note 5: Includes external 1.8kΩ ±5% resistor connected on AGD output to fix a voltage on the pin of 1.3V.
Note 6: Recommended to use the high g transconductance (i.e., high oscillator mode).
M
Note 7: Recommended to use the following crystal electrical parameters: quality factor min of 26,000, series resistance typical of
20Ω, and a static capacitance typical of 2.8pF.
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ABRIDGED DATA SHEET
MAX66300
DeepCover Secure Authenticator
with SHA-256 and RFID Reader
Pin Configuration
TOP VIEW
42 41 40 39 38 37 36 35 34 33 32 31 30 29
43
44
45
46
47
48
49
50
51
52
53
54
55
56
28
27
26
25
24
23
22
21
20
19
18
17
16
15
N.C.
RFIN2
N.C.
N.C.
RFIN1
REG18
N.C.
SYSBOUT
SYSCOUT
SYSAOUT
SYSDOUT
N.C.
GND
V
DDQ
MAX66300
HFXOUT
HFXIN
V
SS
AGD
SYSEIN
TP
N.C.
RESET
PORTSLCT
BUSY
SYSDIN
N.C.
EP
+
SYSAIN_1
SLEEP
1
2
3
4
5
6
7
8
9
10 11 12 13 14
TQFN
Pin Description
PIN
NAME
SYSAIN_2
FUNCTION
1
Special-Purpose Pin. Must be connected to SYSAOUT. This pin is 5V tolerant.
2, 4, 19, 24,
25, 27, 28, 30,
43, 55
N.C.
No Connection
3
5
6
SYSAIN_3
RXD
Special-Purpose Pin. Must be connected to SYSAOUT. This pin is 5V tolerant.
UART Receive. Data input from host. This pin is 5V tolerant.
TXD
UART Transmit. Data output to host. This pin is 5V tolerant.
Special-Purpose Pin. This pin must be connected to SYSCOUT. Also, this pin must be
7
SYSCIN
pulled up with a 10kΩ ±5% resistor to the same voltage potential as V
.
DD_AFE_DIG
Special-Purpose Pin. This pin must be connected to SYSBOUT. Also, this pin must be
8
9
SYSBIN
GND
pulled up with a 10kΩ ±5% resistor to the same voltage potential as V
.
DD_AFE_DIG
Digital Ground
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MAX66300
DeepCover Secure Authenticator
with SHA-256 and RFID Reader
Pin Description (continued)
PIN
NAME
FUNCTION
Master In-Slave Out. The MISO pin is used to transfer data out of the MAX66300. During
a read cycle, data bytes are shifted out on this pin after the falling edge of the serial
clock. This pin is 5V tolerant.
10
MISO
Master Out-Slave In. The MOSI pin is used to transfer data into the device. It receives
instructions, addresses, and data. Data is latched on the rising edge of the serial clock.
This pin is 5V tolerant.
11
12
MOSI
SCLK
Serial Clock. The SCLK pin is used to synchronize the communication between host
processor (master) and the MAX66300. Data bytes present on the MOSI pin are latched
on the rising edge of the clock input, and data bytes on the MISO pin are updated after
the falling edge of the clock input. This pin is 5V tolerant.
Slave Select. A low level on the SSEL pin selects the device; a high level deselects the
device. When the MAX66300 is deselected, MISO goes to the high-impedance state,
allowing multiple parts to share the same SPI bus. This pin is 5V tolerant.
13
14
15
SSEL
IRQ
Interrupt Out. This pin drives low when an interrupt has occurred. Otherwise, the pin is in
high impedance. This pin is 5V tolerant.
Sleep Mode In. This pin is used to put the device into low-power mode when set low.
This device comes out of low-power mode and into normal operation within 20ms of
transition from low to high logic state. This pin is 5V tolerant.
SLEEP
Busy Out. This pin indicates a transaction is in progress when driving high and that no
messages should be sent to the device. When driving low, the device is ready to accept
new messages. Note in UART mode, BUSY in not required since communication is
asynchronous.
16
17
BUSY
Port Select In. After a reset, this pin is sampled within 20ms. If the sample detects logic-
low, the UART port is enabled and the SPI port is disabled. If the sample detects logic-
high, the SPI port is enabled and the UART port is disabled. This pin is 5V tolerant.
PORTSLCT
Active-Low Reset. This bidirectional pin recognizes external active-low reset inputs and
uses an internal pullup resistor to allow for a combination of wired-OR external reset
sources. An RC is not required for power-up, as this function is provided internally. This
pin also acts as an output when the source of the reset is internal to the device (e.g.,
exception handling of an incorrect message, etc.). In this case, the pin is low while the
processor is in a reset state, and returns high as the processor exits this state. This pin
is 5V tolerant.
18
RESET
High-Frequency Crystal Input/Output. Connect an external 24MHz crystal or resonator
between HFXIN and HFXOUT as the high-frequency system clock. Alternatively, if a
more accurate external system clock is available, HFXIN can be the input for a 24MHz
clock source when HFXOUT is unconnected.
20
21
HFXIN
HFXOUT
22
23
V
Digital Supply. Connect to V
through a 50Ω 1µF capacitor filter.
DDIO
DDQ
GND
Digital Ground
Regulator Capacitor. This pin must be connected to ground through a 1.0µF external
ceramic chip capacitor. The capacitor must be placed as close as possible to this pin. No
devices other than the capacitor should be connected to this pin.
26
29
REG18
V
Digital Core Supply Voltage. +3.3V nominal supply voltage.
DD_CORE
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MAX66300
DeepCover Secure Authenticator
with SHA-256 and RFID Reader
Pin Description (continued)
PIN
NAME
FUNCTION
Switched I/O Power Supply (Internally Connected to V
). This output pin must
DD_CORE
be connected to ground through a 1.0µF external ceramic chip capacitor. The capacitor
must be placed as close as possible to this pin. No devices or power rail other than the
31
V
DDIO
capacitor and V
Digital Ground
through a filter should be connected to this pin.
DDQ
32
33
GND
SYSEOUT
Special-Purpose Pin. This pin must be connected to SYSEIN.
Digital Supply Voltage for the Analog Front-End. This pin can operate at 3.3V or 5V.
This pin has to be the same voltage potential as V
and V
. This pin must be
DDA1
DDA2
34
V
connected to ground through a 0.1µF external ceramic chip capacitor. The capacitor
must be placed as close as possible to this pin. No devices other than the capacitor
should be connected to this pin.
DD_AFE_DIG
35
36
OSCIN
Quartz Oscillator Input/Output. These pins are driven by an external crystal oscillator
to generate the needed RF frequencies for the analog front-end. These pins require a
standard 13.56MHz ±7kHz quartz crystal. A CoG-rated capacitor should be used for
loading with a typical value of 22pF for each pin.
OSCOUT
Positive Supply for Antenna Driver. This pin is to be separately filtered from any of the
digital supplies and lumped together with V
. Variations in this supply voltage directly
DDA2
modulate the antenna driver and effect the receiver’s input. The power-supply sensitivity
range, for frequency components that are in the receiving bandwidth, is the same as the
37
V
DDA1
RFIN sensitivity. The ground pins used for V
and V
of the antenna driver are
DDA2
DDA1
V
and V
(see note).
SSA2
SSA1
RF Output (10Ω Output Impedance). This pin is the output of the antenna driver.
Connect to external antenna components.
38
39
ANT1
Negative Supply for Antenna Driver (0V). This pin is the ground pin for the antenna
driver. This pin is to be separately filtered from any of the digital supplies and lumped
V
SSA1
together with V
.
SSA2
40
41
V
Negative Supply for Antenna Driver (0V). See the V
pin description.
SSA2
SSA2
RF Output (10Ω Output Impedance). This pin is the output of the antenna driver.
Connect to external antenna circuit.
ANT2
42
44
V
Positive Supply for Antenna Driver. See the V
pin description (see note).
DDA2
DDA1
RFIN2
RF Input PM (maximum 5V , DC-coupled to AGD). These two input pins are to be
P-P
connected with external components to detect the amplitude or phase modulated
signals.
45
RFIN1
46
47
SYSBOUT
SYSCOUT
Special-Purpose Pin. This pin must be connected to SYSBIN.
Special-Purpose Pin. This pin must be connected to SYSCIN.
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MAX66300
DeepCover Secure Authenticator
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Pin Description (continued)
PIN
48
NAME
FUNCTION
SYSAOUT
SYSDOUT
Special-Purpose Pin. Must be connected to SYSAIN_1, SYSAIN_2, and SYSAIN_3.
Special-Purpose Pin. Must be connected to SYSDIN.
49
50
V
Ground (Analog Ground of RF AFE)
SS
Reference Voltage Output 2.5V. This pin is to be connected to a 0.1µF X7R capacitor to
51
52
AGD
ground when V
ground to fix the voltage at 1.3V when V
is 5V. This pin is to be connected to an external resistor to
DD_AFE_DIG
is 3.3V.
DD_AFE_DIG
Special-Purpose Pin. This pin must be connected to SYSEOUT. Also, this pin must be
pulled up with a 10kΩ ±5% resistor to the same voltage potential as V
SYSEIN
.
DD_AFE_DIG
53
54
56
—
TP
SYSDIN
SYSAIN_1
EP
Test Pin. This pin is to be pulled up for standard operation to V
.
DD_CORE
Special-Purpose Pin. Must be connected to SYSDOUT. This pin is 5V tolerant.
Special-Purpose Pin. This pin must be connected to SYSAOUT. This pin is 5V tolerant.
Exposed Pad
Note: Decouple V
to V
with the following types of capacitors; use C0D ceramic technology (±5%) for the 10nF
DDA1/2
SS1/2
capacitors, use X7R ceramic technology (±10%) for the 100nF capacitors, and use tantalum electrolytic technology for the
3.3µF capacitors.
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ABRIDGED DATA SHEET
MAX66300
DeepCover Secure Authenticator
with SHA-256 and RFID Reader
VDD_CORE
HFXOUT
HFXIN
VDD_AFE_DIG
EXTERNAL
CRYSTAL
OSCILLATOR
EXTERNAL
13.56MHz
OSCILLATOR
VDDQ
PORTSLCT
INTERFACE
OPTION BITS
UART
SPI
PROTOCOL
ARBITRATION OF
MESSAGES AND
RESPONSES
SPI/UART
INTERFACE
CONTROLLER
VSSA2
EN
AND
ANT2
VDDA2
ANTENNA
DRIVER
I/O MULTIPLEX
BUSY
SLEEP
POWER-ON
RESET
STATUS
MAX66300
MODULATOR
RESET
POWER-FAIL
WARNING
FACTORY DETAILS
BPCK
DECODER
SCRATCHPAD
M-SECRETS 0 – 3
OR
VSSA2
ANT2
VDDA2
S-SECRET
ANTENNA
DRIVER
RANDOM
NUMBER
GENERATOR
SHA-256
ENGINE
AGD
BANDGAP
REFERENCE
64-BIT SERIAL
NUMBER
MAC READOUT
REGISTER
RFIN2
GND
USER MEMORY
PAGES 0 – 3
FILTER AND
GAIN
COMPARATOR
DEMODULATOR
RFIN1
VSS
COPROCESSOR
ANALOG FRONT END
Figure 1. Block Diagram
at 3.3V with 5V tolerant I/O. The device’s coprocessor
computes a unique slave secret (S-Secret) from any one of
four master secrets (M-Secrets) and additional data. Once
the S-Secret is computed, the coprocessor computes slave
authentication MACs (to verify a tag’s authenticity). The
same S-Secret in the coprocessor generates slave write
MACs. For example, a slave-write MAC permits writing to
the memory and protection registers of a secure memory in
a tag. If the memory is not write-protected, a new M-Secret
can be loaded directly and additional data. In addition,
the coprocessor can perform a slave authentication from
knowing the MAX66240/42’s tag UID with a single message
and response, greatly relieving the host’s burden. This only
requires that both the MAX66300 and MAX66240/42 have
been properly set up with secrets. This can be achieved by
using Maxim’s preprogramming service.
Detailed Description
The RFID reader’s analog front-end (AFE) function is
highly integrated into the MAX66300 to support contactless
communication at 13.56MHz for compliancy with the ISO/
IEC 15693 standard. The host configures this reader with
ease and flexibility. This is accomplished through single
configuration byte writes to the AFE. The AFE operates at
3.3V or 5V. The reader’s push-pull transmitter generates
up to 200mW output RF power depending on the antenna
configuration design selected. The output stage drivers are
capable of on-off keying (OOK) and amplitude shift keying
(ASK) modulation from 7% up to 30% of AM modulation.
See Figure 1 for a block diagram.
The MAX66300 has a built-in SHA-256 engine and user
memory space divided into four pages. Its core operates
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ABRIDGED DATA SHEET
MAX66300
DeepCover Secure Authenticator
with SHA-256 and RFID Reader
Switch Coil On
UART:
STX ICK SCOF 02h CHK ETX
STX ICK SCOF ACK CHK ETX
SPI (assume MOSI = FFh during MISO output):
SSEL STX ICK SCOF 02h CHK ETX DSEL
SSEL STX ICK SCOF ACK CHK ETX DSEL
02h = On – standard operation
Xxh = All other values are invalid
Power Management
There are two available power modes. The selection of
these two modes is done by setting the PUF bit to logic-
low. Here are the two modes:
Functional Description
Coprocessor
● Reset the power-up flag in the configuration word
(option bit 0), which turns off the AFE only. The copro-
cessor and UART/SPI interface continues to run.
The MAX66300 coprocessor analyzes command IDs and
payload received from the host. Next, the coprocessor
communicates with theAFE to send and capture data from
a tag. The coprocessor then returns the proper responses
and payload to the host after it has analyzed the received
data bytes. The ISO 15693 uplink encoding supported in
the MAX66300 is the “1 out of 4” pulse position encoding
scheme. The other encoding scheme supported on the
ISO 15693 standard, “1 out of 256,” is not supported in the
MAX66300. Additionally, the coprocessor also performs
all the SHA-256 computations necessary for all secure
transactions. Doing so helps to reduce host processing
time during a tag authentication session. The coprocessor
operates a 3.3V and requires a clock running at 24MHz
with an external crystal for greater accuracy.
● Apply a low level on the SLEEP pin input. In this case,
the AFE goes to sleep and the coprocessor, including
the UART/SPI, goes to sleep mode.
When the SLEEP pin input is changed to high (i.e., PUF
is high), the MAX66300 goes immediately to the mode in
which it was before the SLEEP pin went to a low level.
Bandgap Reference
A reference voltage (2.5V) is generated internally by a
bandgap reference and uses an external capacitor for
blocking.
Antenna Drivers
The antenna driver produces the RF signal from the
oscillator output. The pMOS and nMOS driver sides are
fed by nonoverlapping signals (3ns) to minimize the power
consumption. The output resistance of each antenna
driver is typically 7Ω. The two integrated antenna drivers
can be used in three possible configurations, depending
on the output power level desired. When a single driver
configuration is selected, the output power level on the
50Ω load is 100mW. For a 200mW output power, both
drivers must be used in a parallel configuration fashion
to double the output power (option bit 5). The drivers can
operate in a push-pull configuration (option bit 6). This
mode can used in case of a direct antenna connection
configuration. In that configuration, the reader's antenna
AFE Power-Supply Considerations
The MAX66300AFE can operate at 3.3V or 5V. The supply
voltages to power the AFE must be the same on both the
analog and digital input lines (V
, V
,
DD_AFE_DIG
DDA1
V
DDA2
). It is strongly recommended to use a regulated
supply. Power-supply ripples and noise inside the receiver
frequency range degrade the overall performance of the
system. An external resistor must be added to the AGD
output to use the AFE at 3.3V. Doing so fixes the voltage
level on AGD to 1.3V. For power efficiency reasons, the
external resistor can be switched off (using for example a
microcontroller I/O) when the MAX66300 is not used or is
in the sleep mode.
Maxim Integrated
│ 12
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ABRIDGED DATA SHEET
MAX66300
DeepCover Secure Authenticator
with SHA-256 and RFID Reader
is connected to the output drivers through a resonant
capacitor (LC tank adjusted to 13.56MHz). In the direct
antenna configuration, the user can achieve an RF output
power above 200mW. To be compliant with emissions
regulation in certain countries (e.g., FCC in the U.S.), it
could be necessary to add a filtering structure between
the device output state drivers and the antenna. The short
protection circuit (option bit 4) prevents damage to the
output driver when the ANT pin is shorted to ground or to
the AFE’s power supply.
RF frequency components still present in the envelope
signal are removed by a second-order lowpass filter.
The received signal DC component is removed by the
highpass filter, which has selectable corner frequency
(option bits 7 and 8). The signal is amplified and further
processed by the lowpass filtering stage, which corner
frequency is selectable (option bit 9). The gain selection
(option bits 10, 11, and 12) should be chosen according
to the reader system parameters. Modifying the signal
bandwidth changes noise level and results in different
input sensitivity.
Modulator
AGC System
The modulator enables OOK or ASK modulation of the
RF signal on the antenna outputs (ANT1 and ANT2). The
reader can cause a low field (ASK modulation index as in
Figure 5) or a field-stop (OOK modulation as in Figure 4).
The selection between OOK and ASK modulation depth
is done using configuration word (option bits 1, 2, and 3).
The field modulation index can be adjusted from 7%
up to 30% covering all the ISO standard air interface
requirements. Before and after a modulation phase, the
receiver input is disconnected from the antenna circuitry
to preserve DC operating point setting. For high-quality
factor systems, it may be necessary to prolong (option bit
24) the hold time after modulation to allow settling of the
resonant circuit.
The integrated AGC system can be activated by the
configuration word (option bit 14). The AGC amplifier has a
40dB gain correction depth. The AGC system is adapted to
all RFID communication protocols. Before the tag starts to
emit the data, the receiver gain is set to maximum (option
bits 10, 11, 12). When the reader detects a tag signal that
is above the attack threshold the receiver gain is rapidly
reduced (option bits 17 and 18) to fit the signal into a linear
range of the receiver. The gain remains unchanged as long
as the signal level is above the decay threshold. When
the received signal falls below the decay threshold for a
period of time set by option bits 19 and 20, the reader logic
establishes that the communication with one tag is finished
and makes a fast decay to return to the maximum gain.
The receiver is ready to demodulate the emission of the
next tag, which can be far away from the reader antenna.
This feature is necessary for anti-collision purposes. With
tags that have a modulation DC level shift significantly
higher than modulation sub-carrier AC level the AGC can
Receiver
The receiver senses the envelope of the signal present
on the inputs RFIN1 or RFIN2 (option bit 13). These
two inputs, used with external components, permit the
detection of amplitude or phase modulated signals. Any
CARRIER AMPLITUDE
100%
CARRIER AMPLITUDE
100%
84%
t
t
Figure 4. Transmitter Field on ANT1 for Modulation Set to OOK
(100% AM)
Figure 5. Transmitter Field for ANT1 for Modulation Set to ASK
(16% AM)
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ABRIDGED DATA SHEET
MAX66300
DeepCover Secure Authenticator
with SHA-256 and RFID Reader
react on DC shift and decrease the system gain too much.
It is possible not to attack the first pulse (option bit 15) in a
burst (for OOK modulation) to allow the DC level to settle
before AGC action. The time after which the first pulse in
a burst is not attacked (shortest sub-carrier stop in OOK
modulation is 1/10 of the time) is set by option bits 19, 20
as decay wait time. It is also possible to use slow decay
mode (option bit 16). The slow decay is started when the
received signal falls below the decay threshold. The decay
rate is one gain step per time defined by option bits 19
and 20. When AGC system is disabled the receiver gain is
directly controlled by option bits 10, 11, 12.
SPI Interface
The MAX66300 is a slave device that communicates with
its master—a microcontroller—through the serial SPI
interface. This interface uses the signals SSEL, SCLK,
MOSI, and MISO.
The SPI protocol defines communication in full bytes
with the most significant bit being transmitted first. Every
SPI communication sequence begins with at least 1 byte
written to the slave device. The first byte that the slave
receives from the master is understood as the beginning
of the message. Depending on the first few message bytes
the slave may need more bytes, e.g., more message data
to complete the message; for a read function, after having
received the beginning response message bytes, the
slave starts sending data to the master.
True Random-Number Generator
A true hardware random-number generator is included for
key generation and challenge generation. As an example,
during a SHA-256 authentication of a tag, it is required to
have a challenge. If a system only has a pseudo random-
number generator, hackers who know how the random
number is generated can compromise a system. By using
true hardware to generate a random number, a higher
level of security is achieved.
The SPI protocol knows four communication modes,
which differ in the polarity and phase of the SCLK signal.
The MAX66300 supports MODE (0/0). See the timing
specification in Figure 6.
The read timing of these graphics begins with the first
bit that the MAX66300 transmits to the master and ends
when the master ends the communication by deactivating
SSEL (low to high transition). The data on the MOSI is
latched (i.e., sampled) on the SCLK's rising edge and data
on the MISO is updated (i.e., shifted out) on a falling edge
of SCLK. Also, the first bit on the MOSI is latched on the
first leading rising edge of SCLK. So data on the MOSI
UART
The
universal
asynchronous
receiver-transmitter
(UART) interface provides transmit and receive signals
to communicate with PCs, modems, and other similar
interfaces when paired with an external RS-232 line driver/
receive. This device provides asynchronous, full-duplex
communication (i.e., Baud rate: 38400, Data: 8 bit, Parity:
none, Stop: 1 bit, Flow control: none).
needs to be stable for at least a t
before the first SCLK
SIS
cycle for MAX66300. Therefore, the first bit transmitted
from the MISO is updated at least a half cycle before the
first SCLK cycle to meet the master's setup time.
SAMPLE
SAMPLE
SHIFT
SHIFT
t
SSE
SSEL
t
SSH
t
SCK
t
t
t
SD
SCH
t
SDLY
SCL
SCLK
MODE
0/0
t
t
SIH
SIS
MOSI
MSB
MSB-1
MSB-1
LSB
MSB
MSB-1
MSB-1
LSB
t
t
t
SOV
SPI_RF
SLH
MISO
BUSY
MSB
LSB
MSB
LSB
t
SAB
Figure 6. SPI Timing Specification
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ABRIDGED DATA SHEET
MAX66300
DeepCover Secure Authenticator
with SHA-256 and RFID Reader
Configuration Word (Option Bits) Selection
Applications Information
Depending on Tag IC
AFE Oscillator
The MAX66300 is compliant with almost all 13.56MHz
tag ICs by setting the AFE by the use of Table 18. The
large combinations offered by the MAX66300 option bits
permit to adapt the reader IC to the tag communication
protocol. Table 20 gives the ISO typical suggested option
bit configuration depending on the tag IC used.
The frequency range allowed by the regulations is
13.56MHz ±7kHz. The correct load capacitance has to
be chosen according to the manufacturer’s guideline. A
temperature coefficent of type C0G capacitors should be
used. It is not recommended to connect any components
except quartz crystal and load capacitors to the oscillator’s
pins since any interference or noise injected into the
oscillator corrupts the system performance. When an
external clock source is used, the phase noise of the
clock has to be kept low since it also corrupts the system
performances.
Table 20. Option Bit Configuration for ISO
15693 Standard
OPTION
BIT
SUGGESTED
VALUE
CONFIGURATION
Antenna Driver
0
1, 2, 3
4
1
1, 0, 0
1
Power up
The correct load impedance for a single output driver
(100mW) is 7Ω resistive. The correct load impedance for
a double parallel output driver (option bit 5, 200mW) is
3.5Ω resistive. The load impedance for a push-pull driver
(option bits 5 and 6) must be at least 14Ω resistive. In this
configuration, the consideration of chip power dissipation
and junction temperature is necessary. It is also possible to
use this configuration for low power systems with a direct
antenna connection if a load impedance higher than 14Ω
is used. Since the ASK modulation index is dependent on
the load, it differs from those listed in Table 18.
OOK modulation
Short circuit enabled
Two drivers in differential
300kHz
5, 6
7, 8
9
1, 1
0, 0
0
1MHz
10, 11, 12
13
1, 0, 0
0
Gain decreased for 5.7dB
RFIN1 selected
AGC activated
14
1
15 to 20
21
0, 0, 0, 0, 0, 0 Standard configuration
Receiver
0
Sub-carrier mode
BPSK not used
Systems using a 212kHz sub-carrier modulation should
use the medium filter selection and systems using a
424kHz or 848kHz sub-carrier should use the high
frequency filter selection. When a 424kHz or 848kHz
system with on/off sub-carrier coding is used, the higher
frequency zero enables very fast response of the receiver
to the pulse burst with high DC level shift. When a BPSK
system is used, lower frequency zero decreases phase
distortion of the BPSK signal. System option bits control
the receiver gain. Different receiver bandwidths result in
different noise levels therefore enabling different gain and
sensitivity levels. The combination of filter selection and
gain selection allows the system designer to choose the
best combination for the RFID reader.
22
0
23
0
Analog output disable
Hold delay set to 5µs
24
0
25
1
High g
M
26
0
Internal quartz
27 to 31
0, 0, 0, 0, 0
Normal IC mode
Tag subcarrier: 424kHz or 484kHz
Modulation index: 100%
Reception bandwidth: 300kHz to 1MHz
AGC: Nominal gain
Configuration word value: (MSB) 02h 00h 44h 73h (LSB)
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ABRIDGED DATA SHEET
MAX66300
DeepCover Secure Authenticator
with SHA-256 and RFID Reader
Antenna Configurations and Decoupling
The theoretical antenna configurations and typical decoupling are shown in Figure 7, Figure 8, and
Figure 9. Since the LC tank values needed for tuning of the antenna are subject to a larger dialogue, this information is
available in Application Note 5912: Designing an Antenna for the MAX66300.
J 1
1
VC C 5
VC C 5
VC C 3 . 3
2
U?
C O N 2
J 2
L 1
1 0 u H
2 2
2 9
3 1
3 4
3 7
4 2
5 1
5
6
R XD
T XD
VDDQ
VD D Q
VD D _ C O R E
VD D I O
VD D _ AF E _ D I G
VD D A1
VD D A2
R XD
T XD
1
2
3
4
VDDIO
1 0
1 1
1 2
1 3
M O S I
M I S O
S C LK
S S E L
VDDAFEDIG
VDDA1
VDDA2
AGD
M I S O
M O S I
S C LK
S S E L
1
AN T E N N A
C O N 4
J 3
AG D
W 1
L 2
3 8
4 1
4 5
4 4
1 4
1 5
1 6
1 7
5 3
I R Q
AN T 1
AN T 2
R F I N 1
R F I N 2
I R Q
S L E E P
B US Y
Po r t S L C T
T P
1
2
3
4
5
S L E E P
B US Y
Po r t S L C T
T P
C O AX
C 1
G N D
C 2 2
2 2 p F
2 2 p F
2 0
2 1
3 5
3 6
C O N 5
C 2
G N D
VC C 5
H F XI N
H F XO UT
O S C I N
C 3
1 0 n F 5 2
3 3
X1
S Y S E I N
S Y S E O U T
R 2 2
1 0 K
2 4 . 0 0 M H z
O S C O UT
G N D
5 6
1
3
4 8
8
4 6
7
4 7
5 4
4 9
1 8
C 4
RESET_I N
S Y S AI N _ 1
S Y S AI N _ 2
S Y S AI N _ 3
S Y S AO U T
S Y S B I N
S Y S B O UT
S Y S C I N
S Y S C O UT
S Y S D I N
R E S E T
2 6
5 0
3 9
4 0
9
2 3
3 2
E P
C 5
R E G 1 8
VS S
C 6
R 1
X2
1 3 . 5 6 M H z
2 2 p F
C 7
VS S A 1
VS S A 2
G N D
G N D
G N D
E P
1 u F
1 0 K
R 2
2 2 p F
1 0 K
S Y S D O UT
M AX 6 6 3 0 0
G N D
VC C 3 . 3
AG D
VC C 5
VC C 3 . 3
VD D AF E D I G
VD D A1 VD D A2
R 3
VD D Q
VD D I O
R 4
2 0 K
5
0
O
h
m
C 8
0 . 1 u F
C 9
0 . 1 u F
C 1 0
3 . 3 u F
C 1 1
1 0 n F
C 1 2
3 . 3 u F
C 1 3
1 0 n F
C 1 4
0 . 1 u F
C 1 5
0 . 1 u F
C 1 6
0 . 1 u F
C 1 7
0 . 1 u F
C 1 8
0 . 1 u F
C 1 9
1 0 n F
C 2 0
1 u F
S W 1
R E S E T
R ESET_IN
G N D
Figure 7. Single Output Driver (100mW)
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ABRIDGED DATA SHEET
MAX66300
DeepCover Secure Authenticator
with SHA-256 and RFID Reader
J 1
1
2
VC C 5
VC C 5
VC C 3 . 3
U?
C O N 2
L 1
1 0 u H
2 2
2 9
3 1
3 4
3 7
4 2
5 1
5
6
R XD
T XD
J 2
VDDQ
VD D Q
VD D _ C O R E
VD D I O
VD D _ AF E _ D I G
VD D A1
VD D A2
R XD
T XD
1
VDDIO
2
3
4
1 0
1 1
1 2
1 3
M O S I
M I S O
S C LK
S S E L
VDDAFEDIG
VDDA1
VDDA2
AGD
M I S O
M O S I
S C LK
S S E L
1
AN T E N N A
C O N 4
J 3
AG D
W 1
L 2
3 8
4 1
4 5
4 4
1 4
1 5
1 6
1 7
5 3
I R Q
AN T 1
AN T 2
R F I N 1
R F I N 2
I R Q
S L E E P
B US Y
Po r t S L C T
T P
1
2
3
4
5
S L E E P
B US Y
Po r t S L C T
T P
C O AX
C 1
G N D
C 2 2
2 2 p F
2 2 p F
2 0
2 1
3 5
3 6
C O N 5
C 2
G N D
VC C 5
H F XI N
H F XO UT
O S C I N
C 3
1 0 n F 5 2
3 3
X1
S Y S E I N
S Y S E O U T
R 2 2
1 0 K
2 4 . 0 0 M H z
O S C O UT
G N D
5 6
1
3
4 8
8
4 6
7
4 7
5 4
4 9
1 8
C 4
RESET_I N
S Y S AI N _ 1
S Y S AI N _ 2
S Y S AI N _ 3
S Y S AO U T
S Y S B I N
S Y S B O UT
S Y S C I N
S Y S C O UT
S Y S D I N
R E S E T
2 6
5 0
3 9
4 0
9
2 3
3 2
E P
C
5
R E G 1 8
VS S
C
6
R
1
X
2
2 2 p F
C 7
VS S A 1
VS S A 2
G N D
G N D
G N D
E P
1
u
F
1
3
.
5
6
M
H
z
1 0 K
R 2
2
2
p
F
1
0
K
S
Y
S
D
O
U
T
M
A
X
6
6
3
0
0
G
N
D
V
C
C
3
.
3
A
G
D
V
C
C
5
V
C
C
3
.
3
V
D
D
A
F
E
D
I
G
V
D
D
A
1
V
D
D
A
2
R
3
V
D
D
Q
V
D
D
I
O
R 4
2 0 K
5
0
O
h
m
C 8
0 . 1 u F
C 9
0 . 1 u F
C 1 0
3 . 3 u F
C 1 1
1 0 n F
C 1 2
3 . 3 u F
C 1 3
1 0 n F
C 1 4
0 . 1 u F
C 1 5
0 . 1 u F
C 1 6
0 . 1 u F
C 1 7
0 . 1 u F
C 1 8
0 . 1 u F
C 1 9
1 0 n F
C 2 0
1 u F
S W 1
R E S E T
R
E
S
E
T
_
I
N
G
N
D
Figure 8. Double Parallel Output Driver (Options Bit 5, 200mW)
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MAX66300
DeepCover Secure Authenticator
with SHA-256 and RFID Reader
J 1
1
2
VC C 5
VC C 5
VC C 3 . 3
U1
C O N 2
L 1
1 0 u H
2 2
2 9
3 1
3 4
3 7
4 2
5 1
5
6
R XD
T XD
J 2
VDDQ
VD D Q
VD D _ C O R E
VD D I O
VD D _ AF E _ D I G
VD D A1
VD D A2
R XD
T XD
1
VDDIO
2
3
4
1 0
1 1
1 2
1 3
M O S I
M I S O
S C LK
S S E L
VDDAFEDIG
VDDA1
VDDA2
AGD
M I S O
M O S I
S C LK
S S E L
C O N 4
J 3
AG D
L 2
AN T E N N A
C 2 1
R ser
3 8
4 1
4 5
4 4
1 4
1 5
1 6
1 7
5 3
I R Q
AN T 1
AN T 2
R F I N 1
R F I N 2
I R Q
S L E E P
B US Y
Po r t S L C T
T P
1
2
3
4
5
S L E E P
B US Y
Po r t S L C T
T P
C 1
C 2 2
2 2 p F
2 2 p F
2 0
2 1
3 5
3 6
C O N 5
C 2
G N D
VC C 5
H F XI N
H F XO UT
O S C I N
C 3
1 0 n F 5 2
3 3
X1
S Y S E I N
S Y S E O U T
R 2 2
1 0 K
2 4 . 0 0 M H z
O S C O UT
G N D
5 6
1
3
4 8
8
4 6
7
4 7
5 4
4 9
1 8
C 4
RESET_I N
S Y S AI N _ 1
S Y S AI N _ 2
S Y S AI N _ 3
S Y S AO U T
S Y S B I N
S Y S B O UT
S Y S C I N
S Y S C O UT
S Y S D I N
R E S E T
2 6
5 0
3 9
4 0
9
2 3
3 2
E P
C 5
R E G 1 8
VS S
N o t e: I n su ch a con fi gu r a tion, t he
r eso n a nt fre q u ency o f t he ext ern a l L C
t a n k h a s t o be t u ned a ccu r a t el y t o
1 3 . 5 6 M H z. T he reson a nt c a pa ci t or i s
composed by C 2 1 i n p a r a l l el wi t h t he
ca pa ci t or d i v i d er ( C 1 a nd C 3 ).
C 6
R 1
X2
2 2 p F
C 7
VS S A 1
VS S A 2
G N D
G N D
G N D
E P
1 u F
1 3 . 5 6 M H z
1 0 K
R 2
2 2 p F
1 0 K
S Y S D O UT
M AX 6 6 3 0 0
G N D
VC C 3 . 3
AG D
V
C
C
5
V
C
C
3
.
3
VD D AF E D I G
VD D A1 VD D A2
R 3
VD D Q
VD D I O
R 4
2 0 K
5 0 O h m
C 8
0 . 1 u F
C 9
0 . 1 u F
C 1 0
3 . 3 u F
C 1 1
1 0 n F
C 1 2
3 . 3 u F
C 1 3
1 0 n F
C 1 4
0 . 1 u F
C 1 5
0 . 1 u F
C 1 6
0 . 1 u F
C 1 7
0 . 1 u F
C 1 8
0 . 1 u F
C 1 9
1 0 n F
C 2 0
1 u F
S W 1
R ESET_IN
R
E
S
E
T
G
N
D
Figure 9. Configuration for Lower Power Systems with Direct Antenna Connections
Maxim Integrated
│ 18
www.maximintegrated.com
ABRIDGED DATA SHEET
MAX66300
DeepCover Secure Authenticator
with SHA-256 and RFID Reader
Ordering Information
Package Information
For the latest package outline information and land patterns
(footprints), go to www.maximintegrated.com/packages.
Note that a “+”, “#”, or “-” in the package code indicates
RoHS status only. Package drawings may show a different
suffix character, but the drawing pertains to the package
regardless of RoHS status.
PART
TEMP RANGE
-40°C to +85°C
PIN-PACKAGE
MAX66300ETN+
56 TQFN-EP*
+Denotes lead(Pb)-free/RoHS-compliant package.
*EP = Exposed pad.
PACKAGE
TYPE
PACKAGE
CODE
OUTLINE
NO.
LAND
PATTERN NO.
56 TQFN-EP
T5688M+3
21-0135
90-0047
Note to readers: This document is an abridged version of the full data sheet.Additional device information is available
only in the full version of the data sheet. To request the full data sheet, go to www.maximintegrated.com/MAX66300
and click on Request Full Data Sheet.
Maxim Integrated
│ 19
www.maximintegrated.com
ABRIDGED DATA SHEET
MAX66300
DeepCover Secure Authenticator
with SHA-256 and RFID Reader
Revision History
REVISION
NUMBER
REVISION
DATE
PAGES
CHANGED
DESCRIPTION
0
9/14
Initial release
—
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim Integrated’s website at www.maximintegrated.com.
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses
are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits)
shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
©
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.
2014 Maxim Integrated Products, Inc.
│ 20
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