MAX6447 [MAXIM]
µ.P Reset Circuits with Long Manual Reset Setup Period ; ＆＃ 181.P复位电路，带有长手动复位初始化期间\n
| 型号： | MAX6447 |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | µ.P Reset Circuits with Long Manual Reset Setup Period
|
| 文件： | 总13页 (文件大小：260K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-2656; Rev 1; 1/03
µP Reset Circuits with Long Manual Reset
Setup Period
General Description
Features
The MAX6443–MAX6452 low-current microprocessor
reset circuits feature single or dual manual reset inputs
with an extended 6.72s setup period. Because of the
extended setup period, short switch closures (nuisance
resets) are ignored.
o Single- or Dual-Supply Voltage Monitors
o Precision Factory-Set Reset Thresholds from
1.6V to 4.6V
o Adjustable Threshold to Monitor Voltages Down
On all devices, the reset output asserts when any of the
monitored supply voltages drops below its specified
threshold. The reset output remains asserted for the
reset timeout period (210ms typ) after all monitored
supplies exceed their reset thresholds. The reset output
is one-shot pulse asserted for the reset timeout period
(140ms min) when selected manual reset input(s) are
held low for an extended setup timeout period of 6.72s.
These devices ignore manual reset transitions of less
than 6.72s (typ).
to 0.63V (MAX6449–MAX6452)
o Single or Dual Manual Reset Inputs with Extended
6.72s Setup Period
o Optional Short Setup Time Manual Reset Input
(MAX6447/MAX6448 and MAX6451/MAX6452)
o Immune to Short Voltage Transients
o Low 6µA Supply Current
o Guaranteed Valid Reset Down to V
= 1.0V
CC
The MAX6443–MAX6448 are single fixed-voltage µP
supervisors. The MAX6443/MAX6444 have a single
extended manual reset input. The MAX6445/MAX6446
have two extended manual reset inputs. The MAX6447/
MAX6448 have one extended and one immediate manual
reset input.
o Active-Low RESET (Push-Pull or Open-Drain)
Outputs
o 140ms (min) Reset Timeout Period
o Small SOT143 and SOT23 Packages
The MAX6449–MAX6452 have one fixed-threshold µP
supervisor and one adjustable-threshold µP supervisor.
The MAX6449/MAX6450 have two delayed manual
reset inputs. The MAX6451/MAX6452 have one delayed
and one immediate manual reset input.
Ordering Information
PART
TEMP RANGE
-40°C to +85°C
-40°C to +85°C
PIN-PACKAGE
4 SOT143-4
MAX6443US_ _L -T
MAX6444US_ _L -T
The MAX6443–MAX6452 have an active-low RESET
with push-pull or open-drain output logic options. These
devices, offered in small SOT packages, are fully guar-
anteed over the extended temperature range (-40°C to
+85°C).
4 SOT143-4
Note: The “_ _ ” is a placeholder for the threshold voltage level
of the devices. A desired threshold level is set by the two-num-
ber suffix found in Table 1. All devices are available in tape-
and-reel only. There is a 2500-piece minimum order increment
for standard versions (Table 2). Sample stock is typically held
on standard versions only. Nonstandard versions require a
minimum order increment of 10,000 pieces. Contact factory for
availability.
Applications
Set-Top Boxes
Consumer Electronics
DVD Players
Modems
Pin Configurations
MP3 Players
Industrial Equipment
Automotive
TOP VIEW
4
3
1
2
GND
V
CC
Medical Devices
MAX6443
MAX6444
RESET
MR1
SOT143
Pin Configurations continued at end of data sheet.
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
µP Reset Circuits with Long Manual Reset
Setup Period
ABSOLUTE MAXIMUM RATINGS
All Voltages Referenced to GND
Continuous Power Dissipation (T = +70°C)
A
V
..........................................................................-0.3V to +6V
4-Pin SOT143-4 (derate 4.0ꢀW/°C above +70°C) .....320ꢀW
5-Pin SOT23-5 (derate 7.1ꢀW/°C above +70°C) .......571ꢀW
6-Pin SOT23-6 (derate 8.7ꢀW/°C above +70°C) .......696ꢀW
Operating Teꢀperature Range .......................... -40°C to +85°C
Junction Teꢀperature......................................................+150°C
Storage Teꢀperature Range.............................-65°C to +150°C
Lead Teꢀperature (soldering, 10s) .................................+300°C
CC
Open-Drain RESET ..................................................-0.3V to +6V
Push-Pull RESET ........................................-0.3V to (V + 0.3V)
MR1, MR2, MR2, RSTIN ..........................................-0.3V to +6V
CC
Input Current, All Pins....................................................... 20ꢀA
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V
CC
= 1.0V to 5.5V, T = -40°C to +85°C, unless otherwise specified. Typical values are at T = +25°C.) (Note 1)
A
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
5.5
UNITS
Operating Voltage Range
V
1.0
V
CC
V
V
= 5.5V, no load
7
20
CC
CC
V
V
Supply Current
I
µA
CC
CC
= 3.6V, no load
6
16
46
44
31
29
26
23
22
17
16
4.50
4.25
3.00
2.85
2.55
2.25
2.12
1.62
1.52
4.63
4.38
3.08
2.93
2.63
2.32
2.19
1.67
1.58
60
4.75
4.50
3.15
3.00
2.70
2.38
2.25
1.71
1.62
Reset Threshold
V
V
CC
TH
Reset Threshold Teꢀpco
Reset Threshold Hysteresis
ppꢀ/°C
2 × V
ꢀV
TH
T
T
= 0°C to +85°C
0.615
0.610
0.630
0.645
0.650
A
A
RSTIN Threshold
V
MAX6449–MAX6452
V
TH-RSTIN
= -40°C to +85°C
RSTIN Threshold Hysteresis
RSTIN Input Current
V
MAX6449–MAX6452
MAX6449–MAX6452
2.5
ꢀV
nA
HYST
I
-25
+25
280
RSTIN
MAX6449–MAX6452, V
1ꢀV/µs
falling at
RSTIN
RSTIN to Reset Output Delay
Reset Tiꢀeout Period
15
µs
t
RP
140
210
20
ꢀs
µs
V
to RESET Output Delay
t
V
falling at 1ꢀV/µs
CC
CC
RD
MR1 Miniꢀuꢀ Setup Period
Pulse Width
t
4.48
4.48
6.72
6.72
8.96
8.96
s
s
MR
MR1 + MR2 Miniꢀuꢀ Setup
Period Pulse Width
MAX6445/MAX6446/MAX6449/MAX6450
2
_______________________________________________________________________________________
µP Reset Circuits with Long Manual Reset
Setup Period
ELECTRICAL CHARACTERISTICS (continued)
(V
CC
= 1.0V to 5.5V, T = -40°C to +85°C, unless otherwise specified. Typical values are at T = +25°C.) (Note 1)
A
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
MR2 Miniꢀuꢀ Setup Period
Pulse Width
MAX6447/MAX6448/MAX6451/MAX6452
1
µs
MR2 Glitch Rejection
MAX6447/MAX6448/MAX6451/MAX6452
MAX6447/MAX6448/MAX6451/MAX6452
100
200
210
50
ns
ns
MR2 to RESET Delay
Manual Reset Tiꢀeout Period
t
140
25
280
75
ꢀs
kΩ
kΩ
MRP
MR1 to V
MR2 to V
Pullup Iꢀpedance
Pullup Iꢀpedance
CC
CC
MAX6445/MAX6446/MAX6449/MAX6450
25
50
75
V
≥ 1.00V, I
= 50µA, RESET asserted
0.3
0.3
0.3
0.4
CC
SINK
V
≥ 1.20V, I
= 100µA, RESET
= 1.2ꢀA, RESET
= 3.2ꢀA, RESET
CC
SINK
asserted
≥ 2.55V, I
RESET Output Low
(Open Drain or Push-Pull)
V
V
OL
V
CC
SINK
asserted
V
≥ 4.25V, I
CC
SINK
asserted
V
≥ 1.80V, I
= 200µA, RESET
= 500µA, RESET
= 800µA, RESET
CC
SOURCE
SOURCE
SOURCE
0.8 × V
0.8 × V
0.8 × V
CC
CC
CC
deasserted
V ≥ 3.15V, I
CC
RESET Output High
(Push-Pull)
V
V
OH
deasserted
V
≥ 4.75V, I
CC
deasserted
RESET Open-Drain Leakage
Current
I
RESET deasserted
1
µA
V
LKG
MR1, MR2, MR2
Input Low Voltage
V
0.3 × V
CC
IL
MR1, MR2, MR2
Input High Voltage
V
0.7 × V
V
IH
CC
Note 1: Devices production tested at +25°C. Overteꢀperature liꢀits are guaranteed by design.
_______________________________________________________________________________________
3
µP Reset Circuits with Long Manual Reset
Setup Period
Typical Operating Characteristics
(V
CC
= 3.3V, T = +25°C, unless otherwise noted.)
A
SUPPLY CURRENT
vs. SUPPLY VOLTAGE
NORMALIZED RESET TIMEOUT PERIOD
vs. TEMPERATURE
MAXIMUM TRANSIENT DURATION
vs. RESET THRESHOLD OVERDRIVE
9
8
7
6
5
4
3
2
1
0
1.05
1.04
1.03
1.02
1.01
1.00
0.99
0.98
0.97
0.96
0.95
250
200
150
100
50
T
= +85°C
A
T
= +25°C
A
RESET OCCURS
ABOVE THE CURVE
T
= -40°C
A
V
= 4.4V
800
TH
0
1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
SUPPLY VOLTAGE (V)
-40
-15
10
35
60
85
0
200
400
600
1000
TEMPERATURE (°C)
RESET THRESHOLD OVERDRIVE (mV)
NORMALIZED V RESET THRESHOLD
CC
V
TO RESET DELAY
vs. TEMPERATURE
RSTIN TO RESET DELAY
vs. TEMPERATURE (RSTIN FALLING)
CC
vs. TEMPERATURE
1.03
1.02
1.01
1.00
0.99
0.98
0.97
24.0
23.6
23.2
22.8
22.4
22.0
21.6
21.2
20.8
20.4
20.0
24.0
23.6
23.2
22.8
22.4
22.0
21.6
21.2
20.8
20.4
20.0
V
= FALLING AT 1mV/µs
RSTIN FALLING AT 1mV/µs
CC
-40
-15
10
35
60
85
-40
-15
10
35
60
85
-40
-15
10
35
60
85
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
MANUAL RESET TO RESET DELAY
(MAX6445/MAX6446/MAX6449/MAX6450)
V
TO RESET DELAY
MAX6443/52 toc08
CC
MAX6443/52 toc07
V
= 5V
CC
MR1
V
= 4.5V
CC
(5V/div)
V
= 4.392V
TH
V
(100mV/div)
CC
V
= 4.3V
CC
MR2
(5V/div)
RESET
(5V/div)
RESET
(2V/div)
TIME (1s/div)
TIME (100µs/div)
4
_______________________________________________________________________________________
µP Reset Circuits with Long Manual Reset
Setup Period
Pin Description
PIN
NAME
FUNCTION
MAX6443 MAX6445 MAX6447 MAX6449 MAX6451
MAX6444 MAX6446 MAX6448 MAX6450 MAX6452
1
2
2
1
2
2
GND
Ground
Active-Low Push-Pull or Open-Drain Output. RES ET
changes froꢀ high to low when V or RSTIN drops below
CC
its selected reset threshold and reꢀains low for the 210ꢀs
reset tiꢀeout period after all ꢀonitored power-supply inputs
2
1
1
1
RESET exceed their selected reset thresholds. RES ET is one-shot
pulsed low for the reset tiꢀeout period (140ꢀs ꢀin) after
selected ꢀanual reset inputs are asserted longer than the
specified setup period. For the open-drain output, use a
ꢀiniꢀuꢀ 20kΩ pullup resistor to V
.
CC
Manual Reset Input, Active Low. Internal 50kΩ pullup to
Pull MR1 low for the typical input pulse width
(6.72s) to one-shot pulse RESET for the reset tiꢀeout
V
CC.
3
—
3
—
3
period.
MR1
Manual Reset Input, Active Low. Pull both MR1 and
MR2 low for the typical input pulse width (6.72s) to one-
shot pulse RESET for the reset tiꢀeout period.
—
3
4
—
3
4
—
V
Voltage Input. Power supply and input for the
CC
4
4
4
V
CC
priꢀary ꢀicroprocessor voltage reset ꢀonitor.
Manual Reset Input, Active Low. Internal 50kΩ pullup to
V
. Pull both MR1 and MR2 low for the typical input
CC
—
5
—
6
—
MR2
pulse width (6.72s) to one-shot pulse RESET for the
reset tiꢀeout period.
Manual Reset Input. Pull the MR2 high to iꢀꢀediately
one-shot pulse RESET for the reset tiꢀeout period.
—
—
—
—
5
—
6
5
MR2
Reset Input. High-iꢀpedance input to the adjustable
reset coꢀparator. Connect RSTIN to the center point of
an external resistor-divider to set the threshold of the
externally ꢀonitored voltage.
—
5
RSTIN
threshold voltages. Once V
and V
exceed their
CC
RSTIN
Detailed Description
respective reset threshold voltages, RESET reꢀains low
for the reset tiꢀeout period and then goes high. RESET
is one-shot pulsed whenever selected ꢀanual reset
inputs are asserted. RESET stays asserted for the nor-
ꢀal reset tiꢀeout period (140ꢀs ꢀin).
Reset Output
The reset output is typically connected to the reset
input of a ꢀicroprocessor (µP). A µP’s reset input starts
or restarts the µP in a known state. The MAX6443–
MAX6452 µP supervisory circuits provide the reset
logic to prevent code-execution errors during power-
up, power-down and brownout conditions (see the
Typical Operating Circuit).
RESET is guaranteed to be in the proper output logic
state for V
inputs ≥ 1V. For applications requiring valid
CC
reset logic when V
is less than 1V, see the Ensuring a
CC
Valid RESET Output Down to V
= 0V section.
CC
RESET changes froꢀ high to low whenever the ꢀoni-
tored voltages (RSTIN or V ) drop below the reset
CC
_______________________________________________________________________________________
5
µP Reset Circuits with Long Manual Reset
Setup Period
Manual Reset Input Options
RESET TIMEOUT PERIOD
210ms
Unlike typical ꢀanual reset functions associated with
supervisors, each device in the MAX6443–MAX6452
faꢀily includes at least one ꢀanual reset input, which
ꢀust be held logic-low for an extended setup period
(6.72s typ) before the RESET output asserts. When
valid ꢀanual reset input conditions/setup periods are
ꢀet, the RESET output is one-shot pulse asserted low
for a fixed reset tiꢀeout period (140ꢀs ꢀin). Existing
front-panel pushbutton switches (i.e., power on/off,
channel up/down, or ꢀode select) can be used to drive
the ꢀanual reset inputs. The extended ꢀanual reset
setup period prevents nuisance systeꢀ resets during
norꢀal front-panel usage or resulting froꢀ inadvertent
short-terꢀ pushbutton closure.
MR1 SETUP PERIOD
6.72s
MR1
RESET
Figure 1. MAX6443/MAX6444 Manual Reset Timing Diagram
The MAX6443/MAX6444, MAX6447/MAX6448, and
MAX6451/MAX6452 include a single ꢀanual reset input
with extended setup period (MR1). The MAX6445/
MAX6446 and MAX6449/MAX6450 include two ꢀanual
reset inputs (MR1 and MR2) with extended setup peri-
ods. For dual MR1, MR2 devices, both inputs ꢀust be
held low siꢀultaneously for the extended setup period
(6.72s typ) before the reset output is pulse asserted.
The dual extended setup provides greater protection
froꢀ nuisance resets. (For exaꢀple, the user or service
technician is inforꢀed to siꢀultaneously push both the
on/off button and the channel-select button for 6.72s to
reset the systeꢀ.)
210ms
MR1
6.72s
MR2
RESET
Figure 2. MAX6445/MAX6446/MAX6449/MAX64450 Manual
Reset Timing Diagram
The MAX6443–MAX6452 RESET output is pulse asserted
once for the reset tiꢀeout period after each valid ꢀanual
reset input condition. At least one ꢀanual reset input
ꢀust be released (go high) and then be driven low for the
extended setup period before RESET asserts again.
Internal tiꢀing circuitry debounces low-to-high ꢀanual
reset logic transitions, so no external circuitry is required.
Figure 1 illustrates the single ꢀanual reset function of the
MAX6443/MAX6444 single-voltage ꢀonitors, and Figure
2 represents the dual ꢀanual reset function of the
MAX6445/MAX6446 and MAX6449/MAX6450.
there are no false RESET assertions when MR2 is dri-
ven froꢀ high to low (Figure 4). The MR2 input can be
used for systeꢀ test purposes or sꢀart-card-detect
applications (see the Applications Information section).
Adjustable Input Voltage (RSTIN)
The MAX6449–MAX6452 ꢀonitor the voltage on RSTIN
using an adjustable reset threshold set with an external
resistor voltage-divider (Figure 5). Use the following for-
ꢀula to calculate the externally ꢀonitored voltage
The MAX6447/MAX6448 and MAX6451/MAX6452
include both an extended setup period and iꢀꢀediate
setup period ꢀanual reset inputs. A low-to-high MR2
rising edge transition iꢀꢀediately pulse asserts the
RESET output for the reset tiꢀeout period (140ꢀs ꢀin).
If the MAX6447/MAX6448 and MAX6451/MAX6452
MR2 input senses another rising edge before the end
of the 140ꢀs tiꢀeout period (Figure 3), the internal
tiꢀer clears and begins counting again. If no rising
edges are detected within the 210ꢀs tiꢀeout period,
RESET deasserts. The high-to-low transition on MR2
input is internally debounced for 210ꢀs to ensure that
(V
):
MON-TH
V
= V
✕ (R1+ R2) / R2
MON-TH
TH-RSTIN
where V
and V
is the desired reset threshold voltage
is the reset input threshold (0.63V).
Resistors R1 and R2 can have very high values to ꢀini-
ꢀize current consuꢀption because of low leakage cur-
rents. Set R2 to soꢀe conveniently high value (250kΩ,
for exaꢀple), and calculate R1 based on the desired
reset threshold voltage, using the following forꢀula:
MON-TH
TH-RSTIN
R1 = R2 ✕ (V
MON-TH
/ V
- 1) Ω
TH-RSTIN
6
_______________________________________________________________________________________
µP Reset Circuits with Long Manual Reset
Setup Period
t < 210ms
COUNTER RESET
210ms
DEBOUNCING PERIOD
t = 210ms
POSITIVE EDGE
210ms
TIMEOUT PERIOD
MR2
MR2
NO RESET
OUTPUT
ASSERTED
RESET
RESET
Figure 3. MAX6447/MAX6448/MAX6451/MAX6452 MR2
Assertion DebouncingTiming Diagram
Figure 4. MAX6447/MAX6448/MAX6451/MAX6452 MR2
Deassertion Debouncing Timing Diagram
+3.3V
V
V
CC
MON_TH
MAX6449
MAX6451
R1
R2
V
CC
V
CC
RESET
RESET
RSTIN
GND
V
CC
µP
MAX6443
LED
RESET
GND
MR1
NMI
V
= 0.63 x (R1 + R2) / R2
MON_TH
Figure 5. Calculating the Monitored Threshold Voltages
PUSHBUTTON SWITCH:
CLOSE FOR < 4.48s
FOR SYSTEM INTERRUPT;
CLOSE FOR > 6.72s FOR
SYSTEM RESET
Applications Information
Interrupt Before Reset
To ꢀiniꢀize data loss and speed systeꢀ recovery,
ꢀany applications interrupt the processor or reset only
portions of the systeꢀ before a processor hard reset is
asserted. The extended setup tiꢀe of the MAX6443–
MAX6452 ꢀanual reset inputs allows the saꢀe push-
button (connected to both the processor interrupt and
the extended MR1 input, as shown in Figure 6) to con-
trol both the interrupt and hard reset functions. If the
pushbutton is closed for less than 6.72s, the processor
is only interrupted. If the systeꢀ still does not respond
properly, the pushbutton (or two buttons for the dual
ꢀanual reset) can be closed for the full extended setup
period to hard reset the processor. If desired, connect
an LED to the RESET output to blink off (or on) for the
reset tiꢀeout period to signify when the pushbutton is
Figure 6. Interrupt Before Reset Application Circuit
closed long enough for a hard reset (the saꢀe LED
ꢀight be used as the front-panel power-on display).
Smart Card Insertion/Removal
The MAX6447/MAX6448/MAX6451/MAX6452 dual ꢀanu-
al resets are useful in applications in which both an
extended and iꢀꢀediate setup periods are needed.
Figure 7 illustrates the insertion and reꢀoval of a sꢀart
card. MR1 ꢀonitors a front-panel pushbutton. When
closed for 6.72s, RESET one-shot pulses low for 140ꢀs
ꢀin. Because MR1 is internally pulled to V
through a
CC
50kΩ resistor, the front-panel switch can be connected to
_______________________________________________________________________________________
7
µP Reset Circuits with Long Manual Reset
Setup Period
+3.3V
3.3V
5V
+1.5V
CORE SUPPLY I/O SUPPLY
RESET
V
CC
V
CC
RESET
MAX6444
MAX6446
MAX6448
MAX6450
MAX6452
100kΩ
µP
MAX6451
µP
DIGITAL INPUT
RSTIN
MR1
MR2
RESET
RESET
GND
N
SMART CARD DETECT:
IMMEDIATE ONE-SHOT
WHEN MANUAL
GND
RESET CLOSES
FRONT-PANEL SWITCH
STANDARD µP INPUT
AND 6.72s MANUAL
RESET DELAY
Figure 8. Interfacing to Other Voltage Levels
Figure 7. MAX6451/MAX6452 Application Circuit
a ꢀicroprocessor for general-purpose I/O control. MR2
ꢀonitors a switch to detect when a sꢀart card is inserted.
When the switch is closed high (card inserted), RESET
one-shot pulses low for 140ꢀs. MR2 is internally
debounced for 210ꢀs to prevent false resets when the
sꢀart card is reꢀoved.
Ensuring a Valid RESET Down to
= 0V (Push-Pull RESET)
V
CC
When V
falls below 1V, RESET current-sinking capa-
CC
bilities decline drastically. The high-iꢀpedance CMOS-
logic inputs connected to RESET can drift to
undeterꢀined voltages. This presents no probleꢀs in
ꢀost applications, because ꢀost µPs and other circuitry
Interfacing to Other Voltages
for Logic Compatibility
do not operate with V
below 1V.
CC
In applications in which RESET ꢀust be valid down to
0V, add a pulldown resistor between RESET and GND
for the push-pull outputs. The resistor sinks any stray
leakage currents, holding RESET low (Figure 9). The
value of the pulldown resistor is not critical; 100kΩ is
large enough not to load RESET and sꢀall enough to
pull RESET to ground. The external pulldown cannot be
used with the open-drain reset outputs.
The open-drain RESET output can be used to interface
to a µP with other logic levels. As shown in Figure 8, the
open-drain output can be connected to voltages froꢀ 0
to 6V.
Generally, the pullup resistor connected to the RESET
connects to the supply voltage that is being ꢀonitored
at the IC’s V
pin. However, soꢀe systeꢀs ꢀay use
CC
the open-drain output to level-shift froꢀ the ꢀonitored
supply to reset circuitry powered by soꢀe other supply
Transient Immunity
In addition to issuing a reset to the µP during power-up,
power-down, and brownout conditions, these supervi-
sors are relatively iꢀꢀune to short-duration falling tran-
sients (glitches). The graph Maxiꢀuꢀ Transient Duration
vs. Reset Threshold Overdrive in the Typical Operating
Characteristics section shows this relationship.
(Figure 8). Keep in ꢀind that as the supervisor’s V
CC
decreases toward 1V, so does the IC’s ability to sink
current at RESET. RESET is pulled high as V decays
CC
toward 0. The voltage where this occurs depends on
the pullup resistor value and the voltage to which it is
connected.
8
_______________________________________________________________________________________
µP Reset Circuits with Long Manual Reset
Setup Period
Table 1. Reset Voltage Threshold
V
CC
V
NOMINAL
VOLTAGE
CC
PART NO. SUFFIX
( _ _ )
THRESHOLD (V)
MAX6443
MAX6445
MAX6447
MAX6449
MAX6451
V
CC
46
44
31
29
26
23
22
17
16
4.625
4.375
3.075
2.925
2.625
2.313
2.188
1.665
1.575
RESET
100kΩ
GND
Figure 9. Ensuring RESET Valid to V
= 0
CC
The area below the curves of the graph is the region in
which these devices typically do not generate a reset
pulse. This graph was generated using a falling pulse
Table 2. Standard Versions Table
TOP
MARK
TOP
MARK
PART
PART
applied to V , starting above the actual reset thresh-
CC
old (V ) and ending below it by the ꢀagnitude indicat-
TH
MAX6443US16L
MAX6443US23L
MAX6443US26L
MAX6443US29L
MAX6443US46L
MAX6444US16L
MAX6444US23L
MAX6444US26L
MAX6444US29L
MAX6444US46L
MAX6445UK16L
MAX6445UK23L
MAX6445UK26L
MAX6445UK29L
MAX6445UK46L
MAX6446UK16L
MAX6446UK23L
MAX6446UK26L
MAX6446UK29L
MAX6446UK46L
MAX6447UK16L
MAX6447UK23L
MAX6447UK26L
MAX6447UK29L
MAX6447UK46L
KAFW
KAFX
KAFY
KAFK
KAFZ
KAGA
KAGB
KAGC
KAGD
KAFL
AEEF
AEEG
AEEH
AEEI
MAX6448UK16L
MAX6448UK23L
MAX6448UK26L
MAX6448UK29L
MAX6448UK46L
MAX6449UT16L
MAX6449UT23L
MAX6449UT26L
MAX6449UT29L
MAX6449UT46L
MAX6450UT16L
MAX6450UT23L
MAX6450UT26L
MAX6450UT29L
MAX6450UT46L
MAX6451UT16L
MAX6451UT23L
MAX6451UT26L
MAX6451UT29L
MAX6451UT46L
MAX6452UT16L
MAX6452UT23L
MAX6452UT26L
MAX6452UT29L
MAX6452UT46L
AEER
AEES
AEET
ed (reset threshold overdrive). As the ꢀagnitude of the
transient increases (V
goes further below the reset
CC
threshold), the ꢀaxiꢀuꢀ allowable pulse width
decreases. Typically, a V transient that goes 100ꢀV
AEEU
AEEV
ABEL
ABNP
ABNQ
ABNR
ABNS
ABEM
ABNX
ABNY
ABNZ
ABOA
ABNT
ABEN
ABNU
ABNV
ABNW
ABOB
ABOC
ABOD
ABOE
ABOF
CC
below the reset threshold and lasts 20µs or less does
not cause a reset pulse to be asserted.
Chip Information
TRANSISTOR COUNT: 1384
PROCESS: BiCMOS
AEAO
AEEN
AEEO
AEEP
AEAP
AEEQ
AEEJ
AEEK
AEAQ
AEEL
AEEM
_______________________________________________________________________________________
9
µP Reset Circuits with Long Manual Reset
Setup Period
Pin Configurations (continued)
TOP VIEW
RESET
1
2
3
5
4
MR2
RESET
GND
1
2
3
5
4
MR2
MAX6445
MAX6446
MAX6447
MAX6448
GND
MR1
V
MR1
V
CC
CC
SOT23-5
SOT23-5
RESET
GND
1
2
3
6
5
4
MR2
RESET
GND
1
2
3
6
MR2
MAX6451
MAX6452
MAX6449
MAX6450
RSTIN
5
4
RSTIN
MR1
V
CC
MR1
V
CC
SOT23-6
SOT23-6
Typical Operating Circuit
Ordering Information (continued)
PART
TEMP RANGE
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
PIN-PACKAGE
5 SOT23-5
5 SOT23-5
5 SOT23-5
5 SOT23-5
6 SOT23-6
6 SOT23-6
6 SOT23-6
6 SOT23-6
+3.3V
MAX6445UK_ _L -T
MAX6446UK_ _L -T
MAX6447UK_ _L -T
MAX6448UK_ _L -T
MAX6449UT_ _L -T
MAX6450UT_ _L -T
MAX6451UT_ _L -T
MAX6452UT_ _L -T
V
CC
V
CC
MAX6444
µP
MR1
RESET
RESET
GND
GND
Note: The “_ _ ” is a placeholder for the threshold voltage level
of the devices. A desired threshold level is set by the two-num-
ber suffix found in Table 1. All devices are available in tape-
and-reel only. There is a 2500-piece minimum order increment
for standard versions (Table 2). Sample stock is typically held
on standard versions only. Nonstandard versions require a
minimum order increment of 10,000 pieces. Contact factory for
availability.
RESET TIMEOUT PERIOD
210ms
MR1 SETUP PERIOD
6.72s
MR1
RESET
10 ______________________________________________________________________________________
µP Reset Circuits with Long Manual Reset
Setup Period
Selector Guide
MR1
SETUP
MR2
(NO SETUP)
MR2
SETUP
PART
RSTIN
PUSH-PULL RESET OPEN-DRAIN RESET
MAX6443
MAX6444
MAX6445
MAX6446
MAX6447
MAX6448
MAX6449
MAX6450
MAX6451
MAX6452
6.72s
6.72s
6.72s
6.72s
6.72s
6.72s
6.72s
6.72s
6.72s
6.72s
—
—
—
—
✔
—
—
—
—
—
—
—
—
✔
✔
—
✔
—
✔
—
✔
—
✔
—
—
✔
—
✔
—
✔
—
✔
—
✔
6.72s
6.72s
—
✔
—
—
—
✔
6.72s
6.72s
—
✔
✔
✔
—
✔
*Other timing options may be available. Contact factory for availability.
Functional Diagram
V
CC
MAX6443–
MAX6452
RESET
TIMEOUT PERIOD
(210ms typ)
RESET
RSTIN
MAX6449–
MAX6452
MAX6447
V
MR2 ONE-SHOT
DEBOUNCE
CIRCUIT
MANUAL RESET
SETUP PERIOD
(6.72s typ)
CC
MR2
MAX6448
MAX6451
MAX6452
0.63V
1.23V
V
V
CC
CC
GND
MR1
MR2
MAX6445
MAX6446
MAX6449
MAX6450
______________________________________________________________________________________ 11
µP Reset Circuits with Long Manual Reset
Setup Period
Package Information
(The package drawing(s) in this data sheet ꢀay not reflect the ꢀost current specifications. For the latest package outline inforꢀation,
go to www.maxim-ic.com/packages.)
12 ______________________________________________________________________________________
µP Reset Circuits with Long Manual Reset
Setup Period
Package Information (continued)
(The package drawing(s) in this data sheet ꢀay not reflect the ꢀost current specifications. For the latest package outline inforꢀation,
go to www.maxim-ic.com/packages.)
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 13
© 2003 Maxiꢀ Integrated Products
Printed USA
is a registered tradeꢀark of Maxiꢀ Integrated Products.
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