MAX5942A-MAX5942B [MAXIM]
IEEE 802.3af Power-Over-Ethernet Interface/PWM Controller for Power Devices; IEEE 802.3af标准的供电的以太网供电接口/ PWM控制器，适用于用电设备
| 型号： | MAX5942A-MAX5942B |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | IEEE 802.3af Power-Over-Ethernet Interface/PWM Controller for Power Devices |
| 文件： | 总24页 (文件大小：464K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-3024; Rev 0; 10/03
IEEE 802.3af Power-Over-Ethernet
Interface/PWM Controller for Power Devices
General Description
Features
The MAX5942A/MAX5942B integrate a complete power
IC for powered devices (PD) in a power-over-ethernet
(PoE) system. The MAX5942A/MAX5942B provide a PD
interface and a compact DC-DC PWM controller suitable
for flyback and forward converters in either isolated or
nonisolated designs.
o Powered Device Interface
Fully Integrated IEEE 802.3af-Compliant PD
Interface
PD Detection and Programmable Classification
Signatures
Less than 10µA Leakage Current Offset During
Detection
Integrated MOSFET for Isolation and Inrush
Current Limiting
Gate Output Allows External Control of the
Internal Isolation FET
Programmable Inrush Current Control/ULVO
PGOOD/PGOOD Outputs Enable PWM
Controller
The MAX5942A/MAX5942B PD interface complies with
the IEEE 802.3af standard, providing the PD with a detec-
tion signature, a classification signature, and an integrat-
ed isolation switch with programmable inrush current
control. These devices also feature power-mode under-
voltage lockout (UVLO) with wide hysteresis and power-
good status outputs.
The MAX5942A/MAX5942B also integrate all the build-
ing blocks necessary for implementing DC-DC fixed-
frequency isolated power supplies. This device is a
current-mode controller with an integrated high startup
circuit suitable for isolated telecom/industrial voltage
range power supplies. A high-voltage startup circuit
allows the PWM controller to draw power directly from the
18V to 67V input supply during startup. The switching
frequency is internally trimmed to 275kHz 10ꢀ, thus
reducing magnetics and filter components. The
MAX59412A allows an 85ꢀ operating duty cycle and can
be used to implement flyback converters. The MAX5942B
limits the operating duty cycle to less than 50ꢀ and can
be used in single-ended forward converters. The
MAX5942A/MAX5942B are designed to work with or with-
out an external diode bridge in front of the PD.
o PWM Controller
Wide Input Range: 18V to 67V
Isolated (Without Optocoupler) or Nonisolated
Power Supply
Current-Mode Control
Leading-Edge Blanking
Internally Trimmed 275kHz 10ꢀ Oscillator
Soft-Start
Ordering Information
PIN-
MAX DUTY
PACKAGE CYCLE (ꢀ)
PART
TEMP RANGE
MAX5942AESE* -40°C to +85°C
MAX5942ACSE 0°C to +70°C
MAX5942BESE* -40°C to +85°C
MAX5942BCSE
*Future product—contact factory for availability.
16 SO
16 SO
16 SO
85
85
50
50
The MAX5942A/MAX5942B are available in 16-pin SO
packages.
Applications
0°C to +70°C 16 SO
IP Phones
Wireless Access Nodes
Internet Appliances
Computer Telephony
Security Cameras
Pin Configuration
TOP VIEW
V+
1
2
3
4
5
6
7
8
16 V
CC
Power Devices in Power-Over-Ethernet/
Power-Over-MDI
V
DD
15 NDRV
14 V-
FB
SS_SHDN
ULVO
MAX5942A
MAX5942B
13 CS
12 GND
11 PGOOD
10 PGOOD
RCL
Typical Operating Circuit appears at end of data sheet.
GATE
V
9
OUT
EE
SO
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
IEEE 802.3af Power-Over-Ethernet
Interface/PWM Controller for Power Devices
ABSOLUTE MAXIMUM RATINGS
(All voltages are referenced to V , unless otherwise noted.)
UVLO, PGOOD, PGOOD to V .....................................20mA
EE
EE
GND........................................................................-0.3V to +80V
OUT, PGOOD ...........................................-0.3V to (GND + 0.3V)
RCL, GATE .............................................................-0.3V to +12V
UVLO........................................................................-0.3V to +8V
PGOOD to OUT.........................................-0.3V to (GND + 0.3V)
V+ to V-...................................................................-0.3V to +80V
GATE to V ....................................................................80mA
EE
V
, V .........................................................................20mA
DD CC
NDRV Continuous ...........................................................25mA
NDRV (pulsed for less than 1µs) ....................................... 1A
Continuous Power Dissipation (T = +70°C)
A
16-Pin SO (derate 9.1mW/°C above +70°C)................727mW
Operating Temperature Ranges
MAX5942_CSE...................................................0°C to +70°C
MAX5942_ESE................................................-40°C to +85°C
Storage Temperature Range.............................-65°C to +150°C
Junction Temperature......................................................+150°C
Lead Temperature (soldering, 10s) ................................+300°C
V
V
to V-.................................................................-0.3V to +40V
to V-..............................................................-0.3V to +12.5V
DD
CC
FB, NDRV, SS_SHDN, CS to V-..................-0.3V to (V
+ 0.3V)
CC
Maximum Input/Output Current (continuous)
OUT to V ...................................................................500mA
EE
GND, RCL to V ............................................................70mA
EE
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V = (GND - V ) = 48V, GATE = PGOOD = PGOOD = OPEN, V- tied to OUT, V+ tied to GND, UVLO = V , T = T
to T
,
MAX
MIN
IN
EE
EE
A
unless otherwise noted. Typical values are at T = +25°C. All voltages are referenced to V , unless otherwise noted.) (Note 1)
A
EE
PARAMETER
PD INTERFACE
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DETECTION MODE
Input Offset Current
I
V
V
= 1.4V to 10.1V (Note 2)
10
µA
OFFSET
dR
IN
IN
Effective Differential Input
Resistance
= 1.4V up to 10.1V with 1V step,
550
kΩ
OUT = PGOOD = GND (Note 3)
CLASSIFICATION MODE
Classification Current Turn-Off
Threshold
V
V
V
rising (Note 4)
20.8
21.8
22.5
V
TH,CLSS
IN
IN
Class 0, R = 10kΩ
0
2
CL
= 12.6V
Class 1, R = 732Ω
9.17
17.29
26.45
36.6
11.83
19.71
29.55
41.4
CL
to 20V, R
= 25.5kΩ
(Notes 5, 6)
DISC
Classification Current
I
Class 2, R = 392Ω
mA
CLASS
CL
Class 3, R = 255Ω
CL
Class 4, R = 178Ω
CL
POWER MODE
Operating Supply Voltage
Operating Supply Current
Default Power Turn-On Voltage
V
V
= (GND - V )
EE
67
1
V
mA
V
IN
IN
I
IN
Measure at GND, not including R
0.4
DISC
V
V
increasing, UVLO = V
EE
37.4
30
38.6
40.1
UVLO,ON
IN
Default Power Turn-Off Voltage
V
V
decreasing, UVLO = V
V
V
UVLO,OFF
IN
EE
Default Power Turn-On/Off
Hysteresis
V
7.4
HYST,UVLO
External UVLO Programming
Range
V
Set UVLO externally (Note 7)
increasing
12
67
V
V
IN,EX
UVLO External Reference Voltage
V
V
2.400
19.2
2.460
20
2.522
20.9
REF,UVLO
HYST
UVLO
UVLO External Reference
Voltage Hysteresis
Ratio to V
%
REF,UVLO
2
_______________________________________________________________________________________
IEEE 802.3af Power-Over-Ethernet
Interface/PWM Controller for Power Devices
ELECTRICAL CHARACTERISTICS (continued)
(V = (GND - V ) = 48V, GATE = PGOOD = PGOOD = OPEN, V- tied to OUT, V+ tied to GND, UVLO = V , T = T
to T
,
MAX
MIN
IN
EE
EE
A
unless otherwise noted. Typical values are at T = +25°C. All voltages are referenced to V , unless otherwise noted.) (Note 1)
A
EE
PARAMETER
UVLO Bias Current
SYMBOL
CONDITIONS
UVLO = 2.460V
MIN
TYP
MAX
UNITS
I
-1.5
+1.5
µA
UVLO
UVLO Input Ground Sense
Threshold
V
(Note 8)
50
440
mV
µs
TH,G,UVLO
UVLO Input Ground Sense Glitch
Rejection
UVLO = V
7
EE
Power Turn-Off Voltage,
Undervoltage Lockout Deglitch
Time
t
V
, V falling (Note 9)
IN UVLO
0.32
ms
OFF_DLY
T
= +25°C
A
Output current =
300mA, V = 5.6V,
0.6
0.8
1.1
1.5
(Note 11)
Isolation Switch N-Channel
MOSFET On-Resistance
GATE
R
Ω
ON
measured between
OUT and V
T
= +85°C
A
EE
Isolation Switch N-Channel
MOSFET Off-Threshold Voltage
OUT = GND, V
< 1µA
- V output current
EE,
GATE
V
0.5
V
GSTH
GATE Pulldown Switch Resistance
GATE Charging Current
GATE High Voltage
R
Power-off mode, V = 12V, UVLO = V
EE
38
10
80
15
Ω
µA
V
G
IN
I
V
= 2V
5
G
GATE
GATE
V
I
= 1µA
5.58
5.76
5.93
GATE
V
V
- V , |V
- V | decreasing,
OUT
EE
OUT EE
1.15
4.62
1.23
1.31
4.91
V
PGOOD, PGOOD Assertion
= 5.75V
V
GATE
OUTEN
V
Threshold
OUT
Hysteresis
70
4.76
80
mV
V
(GATE - V ) increasing, OUT = V
EE
EE
PGOOD, PGOOD Assertion
Threshold
V
GSEN
V
GATE
Hysteresis
mV
V
PGOOD Output Low Voltage
PGOOD Output Low Voltage
PGOOD Leakage Current
PGOOD Leakage Current
V
I
I
= 2mA (Note 10)
0.4
0.2
1
OLDCDC
SINK
SINK
= 2mA, OUT ≤ (GND - 5V) (Note 10)
= 67V (Note 10)
V
GATE = high, GND - V
µA
µA
OUT
GATE = V , PGOOD - V = 67V (Note 10)
1
EE
EE
ELECTRICAL CHARACTERISTICS (PWM Controller)
(All voltages referenced to V-. V
= 13V, a 10µF capacitor connects V
to V-, V = V-, V+ = 48V, 0.1µF capacitor connected to
DD
CC CS
SS_SHDN, NDRV = open circuit, V = 3V, T = T
to T
, unless otherwise noted. Typical values are at T = +25°C.) (Note 1)
MAX
A
FB
MIN
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
SUPPLY CURRENT
I
V
= 0V, V+ = 67V, driver not switching
DD
0.8
1.6
14
1.6
3.2
V+(NS)
V+ Supply Current
mA
µA
V+ = 67V, V
switching
= 0V, V = 4V, driver
FB
DD
I
V+(S)
V+ Supply Current After Startup
V+ = 67V, V
= 13V, V = 4V
FB
DD
_______________________________________________________________________________________
3
IEEE 802.3af Power-Over-Ethernet
Interface/PWM Controller for Power Devices
ELECTRICAL CHARACTERISTICS (PWM Controller) (continued)
(All voltages referenced to V-. V
SS_SHDN, NDRV = open circuit, V = 3V, T = T
= 13V, a 10µF capacitor connects V
to V-, V = V-, V+ = 48V, 0.1µF capacitor connected to
DD
CC CS
to T
, unless otherwise noted. Typical values are at T = +25°C.) (Note 1)
MAX
A
FB
MIN
A
PARAMETER
Supply Current
SYMBOL
CONDITIONS
= 36V, driver not switching
MIN
TYP
0.9
1.9
180
4
MAX
1.6
UNITS
I
V
V
V
V
VDD(NS)
DD
V
mA
DD
I
= 36V, driver switching, V = 4V
OPTO
3.2
VDD(S)
DD
V+ Shutdown Current
Shutdown Current
= 0V, V+ = 67V
= 0V
290
20
µA
µA
SS_SHDN
SS_SHDN
V
DD
PREREGULATORS/STARTUP
V+ Input Voltage
18
13
67
36
V
V
V
Supply Voltage
DD
INTERNAL REGULATORS
Powered from V+, I
= 7.5mA, V
= 0V
DD
7.5
9.0
9.8
10.0
6.6
12
CC
V
Output Voltage
V
V
CC
Powered from V , I
= 7.5mA
11.0
DD CC
V
Undervoltage Lockout
V
V
falling
CC
CC
CC_UVLO
OUTPUT DRIVER
Peak Source Current
Peak Sink Current
V
V
V
= 11V (externally forced)
= 11V (externally forced)
570
mA
mA
CC
CC
1000
NDRV High-Side Driver
Resistance
= 11V, externally forced, NDRV
CC
R
4
12
4
Ω
Ω
OH
sourcing 50mA
NDRV Low-Side Driver
Resistance
V
CC
50mA
= 11V, externally forced, NDRV sinking
R
1.6
OL
ERROR AMPLIFIER
FB Input Resistance
R
50
1
kΩ
µA
V/V
kHz
V
IN
FB Input Bias Current
Error Amplifier Gain (Inverting)
Closed-Loop 3dB Bandwidth
FB Input Voltage Range
SLOPE COMPENSATION
Slope Compensation
I
V
= V
FB SS_SHDN
FB
A
-20
200
VCL
2
3
V
MAX5942A
FB = 4V
26
mV/µs
SCOMP
THERMAL SHUTDOWN
Thermal Shutdown Temperature
Thermal Hysteresis
+150
25
°C
°C
CURRENT LIMIT
CS Threshold Voltage
CS Input Bias Current
V
419
-1
465
510
+1
mV
µA
ILIM
0V ≤ V ≤ 2V, FB = 4V
CS
Current-Limit Comparator
Propagation Delay
25mV overdrive on CS, FB = V-
180
70
ns
ns
CS Blanking Time
OSCILLATOR
FB = GND, only PWM comparator is blanked
Clock Frequency Range
FB = V-
235
75
275
314
85
kHz
%
MAX5942A, FB = V-
MAX5942B, FB = V-
Max Duty Cycle
44
50
4
_______________________________________________________________________________________
IEEE 802.3af Power-Over-Ethernet
Interface/PWM Controller for Power Devices
ELECTRICAL CHARACTERISTICS (PWM Controller) (continued)
(All voltages referenced to V-. V
SS_SHDN, NDRV = open circuit, V = 3V, T = T
= 13V, a 10µF capacitor connects V
to V-, V = V-, V+ = 48V, 0.1µF capacitor connected to
DD
CC CS
to T
, unless otherwise noted. Typical values are at T = +25°C.) (Note 1)
MAX
A
FB
MIN
A
PARAMETER
SOFT-START
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
SS Source Current
I
V
= V-
SS_SHDN
2.0
1
4.5
6.5
µA
mA
V
SSO
SS Sink Current
Peak Soft-Start Voltage Clamp
No external load
2.331
0.25
0.53
2.420
0.37
0.59
2.500
0.41
0.65
V
V
falling (Note 11)
rising (Note 11)
SS_SHDN
SS_SHDN
Shutdown Threshold
V
Note 1: All min/max limits for the PD interface are production tested at +85°C (extended grade)/+70°C (commercial grade). Limits
at +25°C and -40°C are guaranteed by design. All PWM controller min/max limits are 100% production tested at +25°C
and +85°C (extended grade)/+70°C (commercial grade). Limits at -40°C are guaranteed by design, unless otherwise
noted.
Note 2: The input offset current is illustrated in Figure 1.
Note 3: Effective differential input resistance is defined as the differential resistance between GND and V without any external
EE
resistance.
Note 4: Classification current is turned off whenever the IC is in power mode.
Note 5: See Table 2 in the PD Classification Mode section. R
Note 6: See Thermal Dissipation section for details.
and R must be 100ppm or better.
DISC
CL
Note 7: When UVLO is connected to the midpoint of an external resistor-divider with a series resistance of 25.5kΩ ( 1%), the turn-
on threshold set point for the power mode is defined by the external resistor-divider. Make sure the voltage on the UVLO
pin does not exceed its maximum rating of 8V when V is at the maximum voltage.
IN
Note 8: When the V
is below V
the MAX5942_ sets the turn-on voltage threshold internally (V
).
UVLO
TH, G, UVLO,
UVLO,ON
Note 9: An input voltage or V
glitch below their respective thresholds shorter than or equal to t
will not cause the
UVLO
OFF_DLY
MAX5942A/MAX5942B to exit power-on mode (as long as the input voltage remains above an operable voltage level of 12V).
Note 10: PGOOD references to OUT while PGOOD references to V
Note 11: Guaranteed by design.
.
EE
I
IN
(V
(I
- V
)
INi
1V
INi + 1
dR ≅
i
=
- I
)
(I
- I
INi + 1 INi
)
INi + 1 INi
V
INi
I
≅ I
-
OFFSET INi
dR
i
I
+1
INi
dR
i
I
INi
I
OFFSET
V
1V
V
+1
INi
INi
Figure 1. Effective Differential Input Resistance/Offset Current
_______________________________________________________________________________________
5
IEEE 802.3af Power-Over-Ethernet
Interface/PWM Controller for Power Devices
Typical Operating Characteristics
(V = (GND - V ) = 48V, GATE = PGOOD = PGOOD = OUT = OPEN, UVLO = V , V
= 13V, NDRV floating, T = T
to T
.
MAX
IN
EE
EE DD
A
MIN
Typical values are at T = +25°C. All voltages are referenced to V (for graphs 1–11 in the Typical Operating Characteristics); all
A
EE
voltages are referenced to V- (for graphs 12–30 in the Typical Operating Characteristics), unless otherwise noted.
CLASSIFICATION CURRENT
vs. INPUT VOLTAGE
DETECTION CURRENT vs.
INPUT VOLTAGE
EFFECTIVE DIFFERENTIAL INPUT
RESISTANCE vs. INPUT VOLTAGE
40
35
30
25
20
15
10
5
0.45
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
R
= 25.5kΩ
DISC
CLASS 4
GND = V+ = V- = OUT
CLASS 3
CLASS 2
CLASS 1
CLASS 0
0
10
15
20
25
30
0
2
4
6
8
10
0
5
10
15
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
OFFSET CURRENT
vs. INPUT VOLTAGE
NORMALIZED UVLO
vs. TEMPERATURE
PGOOD OUTPUT LOW VOLTAGE
vs. CURRENT
0
-0.5
-1.0
-1.5
-2.0
-2.5
-3.0
-3.5
1.010
1.008
1.006
1.004
1.002
1.000
0.998
0.996
0.994
0.992
0.990
200
180
160
140
120
100
80
UVLO = V
EE
60
40
20
0
1
2
3
4
5
6
7
8
9
10 11
-40
-15
10
35
60
85
0
4
8
12
(mA)
16
20
INPUT VOLTAGE (V)
TEMPERATURE (°C)
I
SINK
INRUSH CURRENT CONTROL
PGOOD OUTPUT LOW VOLTAGE
vs. CURRENT
OUT LEAKAGE CURRENT
vs. TEMPERATURE
(V = 12V)
IN
MAX5942A/B toc09
400
350
300
250
200
150
100
50
20
16
12
V
= 67V
OUT
V
GATE
5V/div
I
INRUSH
100mA/div
8
4
V
OUT
10V/div
P
GOOD
10V/div
0
0
1ms/div
0
4
8
12
(mA)
16
20
-40
-15
10
35
60
85
I
SINK
INPUT VOLTAGE (V)
6
_______________________________________________________________________________________
IEEE 802.3af Power-Over-Ethernet
Interface/PWM Controller for Power Devices
Typical Operating Characteristics (continued)
(V = (GND - V ) = 48V, GATE = PGOOD = PGOOD = OUT = OPEN, UVLO = V , V
= 13V, NDRV floating, T = T
to T
.
MAX
IN
EE
EE DD
A
MIN
Typical values are at T = +25°C. All voltages are referenced to V (for graphs 1–11 in the Typical Operating Characteristics); all
A
EE
voltages are referenced to V- (for graphs 12–30 in the Typical Operating Characteristics), unless otherwise noted.
V
vs. TEMPERATURE
INRUSH CURRENT CONTROL
INRUSH CURRENT CONTROL
SS_SHDN
(AT THE END OF SOFT-START)
(V = 48V)
(V = 67V)
IN
IN
MAX5942A/B toc10
1.003
1.002
1.001
1.000
0.999
V
V
= V-
GATE
5V/div
FB
V
GATE
5V/div
I
INRUSH
100mA/div
I
INRUSH
100mA/div
V
OUT
50V/div
V
OUT
50V/div
P
P
GOOD
GOOD
50V/div
50V/div
-40
-20
0
20
40
60
80
2ms/div
2ms/div
TEMPERATURE (°C)
NDRV FREQUENCY
vs. TEMPERATURE
MAX5942A
MAXIMUM DUTY CYCLE vs. TEMPERATURE
MAX5942B
MAXIMUM DUTY CYCLE vs. TEMPERATURE
81.0
278
277
276
275
274
273
48.0
80.9
80.8
80.7
80.6
80.5
80.4
47.8
47.6
47.4
47.2
47.0
46.8
FB = V-
FB = V-
FB = V-
-40
-20
0
20
40
60
80
-40
-20
0
20
40
60
80
-40
-20
0
20
40
60
80
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
V+ INPUT CURRENT vs.
TEMPERATURE (AFTER STARTUP)
V+ SUPPLY CURRENT
vs. TEMPERATURE
SOFT-START SOURCE CURRENT
vs. TEMPERATURE
13.80
13.75
13.70
13.65
1.64
1.63
1.62
4.50
4.49
4.48
4.47
4.46
4.45
4.44
4.43
4.42
4.41
4.40
V
= FB = SS_SHDN = V-
DD
V+ = 67V, V = 13V, FB = V-
DD
FB = V = V-
V+ = 67V
DD
1.61
1.60
1.59
13.60
13.55
13.50
1.58
1.57
1.56
1.55
-40
-20
0
20
40
60
80
-40
-20
0
20
60
80
40
-40
-20
0
20
40
60
80
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
_______________________________________________________________________________________
7
IEEE 802.3af Power-Over-Ethernet
Interface/PWM Controller for Power Devices
Typical Operating Characteristics (continued)
(V = (GND - V ) = 48V, GATE = PGOOD = PGOOD = OUT = OPEN, UVLO = V , V
= 13V, NDRV floating, T = T
to T
.
MAX
IN
EE
EE DD
A
MIN
Typical values are at T = +25°C. All voltages are referenced to V (for graphs 1–11 in the Typical Operating Characteristics); all
A
EE
voltages are referenced to V- (for graphs 12–30 in the Typical Operating Characteristics), unless otherwise noted.
V+ SHUTDOWN CURRENT
vs. TEMPERATURE
CS THRESHOLD VOLTAGE
vs. TEMPERATURE
0.488
0.487
0.486
0.485
0.484
0.483
182.5
182.0
V+ = 67V, FB = SS_SHDN = V-
FB = V-
181.5
181.0
180.5
180.0
179.5
179.0
-40
-20
0
20
40
60
80
-40
-20
0
20
40
60
80
TEMPERATURE (°C)
TEMPERATURE (°C)
CURRENT-LIMIT DELAY
vs. TEMPERATURE
NDRV RESISTANCE
vs. TEMPERATURE
210
208
206
204
202
200
198
196
194
192
190
188
5.0
4.5
4.0
3.5
3.0
FB = V-, 100mV OVERDRIVE ON CS
HIGH-SIDE DRIVER
LOW-SIDE DRIVER
2.5
2.0
1.5
1.0
-40
-20
0
20
40
60
80
-40
-20
0
20
60
80
40
TEMPERATURE (°C)
TEMPERATURE (°C)
V
vs. V
DD
NDRV FREQUENCY vs. V
SS_SHDN
DD
271.0
2.410
2.408
2.406
2.404
2.402
2.400
270.5
270.0
269.5
269.0
268.5
268.0
267.5
267.0
FB = V-
0
5
10 15 20 25 30 35 40
(V)
0
5
10 15 20 25 30 35 40
(V)
V
V
DD
DD
8
_______________________________________________________________________________________
IEEE 802.3af Power-Over-Ethernet
Interface/PWM Controller for Power Devices
Typical Operating Characteristics (continued)
(V = (GND - V ) = 48V, GATE = PGOOD = PGOOD = OUT = OPEN, UVLO = V , V
= 13V, NDRV floating, T = T
to T
.
MAX
IN
EE
EE DD
A
MIN
Typical values are at T = +25°C. All voltages are referenced to V (for graphs 1–11 in the Typical Operating Characteristics); all
A
EE
voltages are referenced to V- (for graphs 12–30 in the Typical Operating Characteristics), unless otherwise noted.
MAX5942B
MAXIMUM DUTY CYCLE vs. V
DD
V
vs. V
DD
CC
48.0
47.9
47.8
47.7
47.6
47.5
47.4
47.3
47.2
47.1
47.0
10.2
10.1
10.0
9.9
V
= 4V, CS = V-
FB
DEVICE POWERED FROM V
DD
FB = V-
DEVICE POWERED
FROM V
9.8
DD
9.7
DEVICE POWERED
FROM V+
9.6
DEVICE POWERED
FROM V+
9.5
0
5
10 15 20 25 30 35 40
(V)
0
5
10 15 20 25 30 35 40
(V)
V
DD
V
DD
V+ SUPPLY CURRENT vs.
V+ VOLTAGE
V+ SUPPLY CURRENT vs. V+ VOLTAGE
(AFTER STARTUP)
1.60
1.59
1.58
1.57
1.56
1.55
1.54
1.53
1.52
1.51
16
14
12
10
8
V
= V = V-
DD
FB
V
= 13V, FB = V-
DD
6
4
2
0
0
20
40
60
80
100
0
10 20 30 40 50 60 70 80 90 100 110
V+ VOLTAGE (V)
V+ VOLTAGE (V)
V
VOLTAGE vs. V CURRENT
V
VOLTAGE vs. V CURRENT
CC
CC
CC
CC
10.0
9.9
9.8
9.7
9.6
9.5
9.4
9.3
9.2
9.1
9.0
10.4
10.2
10.0
9.8
V
= GND, V = 4V
V+ = +67V, V = 4V
DD
FB
FB
V
= 36V
V
DD
V+ = 67V
V+ = 48V
= 13V
V+ = 36V
V+ = 24V
DD
9.6
9.4
9.2
9.0
0
5
10
15
20
0
5
10
CURRENT (mA)
15
20
V
V
CURRENT (mA)
CC
CC
_______________________________________________________________________________________
9
IEEE 802.3af Power-Over-Ethernet
Interface/PWM Controller for Power Devices
Pin Description
PIN
NAME
FUNCTION
High-Voltage Startup Input. Referenced to V-. Connect directly to an input voltage range between 18V to 67V.
1
V+
Connects internally to a high-voltage linear regulator that generates V during startup.
CC
Line Regulator Input. Referenced to V-. V is the input to the linear regulator that generates V . For
DD
CC
supply voltages less than 36V, connect V
and V+ to the supply. For supply voltages greater than 36V,
DD
2
V
DD
V
receives its power from the tertiary winding of the transformer and accepts voltages from 13V to 36V.
DD
Bypass V
to V- with a 4.7µF capacitor.
DD
Fixed-Gain Inverting Amplifier Input. Referenced to V-. Connect a voltage-divider from the regulated output
to FB. The noninverting input of the amplifier is referenced to +2.4V
3
4
FB
Soft-Start Timing Capacitor Connection. Referenced to V-. Ramp time to full current limit is approximately
SS_SHDN 0.45ms/nF. Bypass with a minimum 10nF capacitor to V-. A 2.4V reference voltage appears across the
capacitor. Disable the PWM controller by pulling SS_SHDN below 0.25V.
Undervoltage Lockout Programming Input for Power Mode. Referenced to V . When UVLO is above its
EE
threshold, the device enters the power mode. Connect UVLO to V to use the default undervoltage lockout
EE
5
UVLO
threshold. Connect UVLO to an external resistor-divider to define a threshold externally. The series
resistance value of the external resistors must add to 25.5kΩ ( 1%) and replaces the detection resistor. To
keep the device in undervoltage lockout, pull UVLO between V
and V
.
TH,G,UVLO
REF,UVLO
6
7
RCL
Classification Setting. Referenced to V . Add a resistor from RCL to V to set a PD class (see Table 1).
EE EE
Gate of Internal N-Channel Power MOSFET. Referenced to V
GATE sources 10µA when the device
EE .
enters the power mode. Connect an external 100V ceramic capacitor from GATE to V
to program the
OUT
GATE
inrush current. Pull GATE to V to turn off the internal MOSFET. The detection and classification functions
EE
operate normally when GATE is pulled to V
.
EE
Negative Input Power. Source of the integrated isolation N-channel power MOSFET. Connect V to
EE
-48V.
8
9
V
EE
Output Voltage. Referenced to V . Drain of the integrated isolation N-channel power MOSFET. Connect
EE
OUT to V-.
OUT
Power-Good Indicator Output, Active High, Open Drain. PGOOD is referenced to OUT. PGOOD goes high
10
PGOOD impedance when V is within 1.2V of V and when GATE is 5V above V . Otherwise, PGOOD is pulled
OUT EE EE
to OUT (given that V
is at least 5V below GND).
OUT
Power-Good Indicator Output, Active Low, Open Drain. PGOOD is referenced to V . PGOOD is pulled to
EE
V
when V
is within 1.2V of V and when GATE is 5V above V . Otherwise, PGOOD goes high
11
12
13
PGOOD
GND
CS
EE
OUT EE EE
impedance.
Ground. Referenced to V . GND is the positive input power.
EE
Current-Sense Input. Referenced to V-. Turns power switch off if V rises above 465mV for cycle-by-cycle
CS
current limiting. CS is also the feedback for the current-mode controller. CS connects to the PWM controller
through a leading-edge blanking circuit.
14
15
V-
Ground. V- is the ground terminal of the PWM controller.
NDRV
Gate Drive. Referenced to V-. Drives a high-voltage external N-channel power MOSFET.
Regulated IC Supply. Referenced to V-. Provides power for MAX5942_. V
is regulated from V
during
DD
CC
16
V
normal operation and from V+ during startup. Bypass V with a 10µF tantalum capacitor in parallel with a
CC
CC
0.1µF ceramic capacitor to V-.
10 ______________________________________________________________________________________
IEEE 802.3af Power-Over-Ethernet
Interface/PWM Controller for Power Devices
Table 1. PD Power Classification/R Selection
CL
CLASS
USAGE
Default
R
(Ω)
MAXIMUM POWER USED BY PD (W)
0.44 to 12.95
CL
0
1
2
3
4
10k
732
392
255
178
Optional
Optional
Optional
Not allowed
0.44 to 3.84
3.84 to 6.49
6.49 to 12.95
Reserved*
*Class 4 reserved for future use.
magnetic components to minimize board space. Both the
MAX5942A and MAX5942B can be used in power sup-
plies providing multiple output voltages. A functional dia-
gram of the PWM controller is shown in Figure 4. Typical
application circuits for forward and flyback topologies are
shown in Figure 5 and Figure 6, respectively.
Detailed Description
The MAX5942A/MAX5942B integrate a complete power
IC for powered devices (PD) in a power-over-ethernet
(PoE) system. The MAX5942A/MAX5942B provide PD
Interface and a compact DC-DC PWM controller suitable
for flyback and forward converters in either isolated or
nonisolated designs.
Powered Device Interface
The MAX5942A/MAX5942B PD interface complies with
the IEEE 802.3af standard, providing the PD with a
detection signature, a classification signature, and an
integrated isolation switch with programmable inrush
current control. These devices also feature power-mode
undervoltage lockout (UVLO) with wide hysteresis, and
power-good status outputs.
Operating Modes
The PD front-end section of the MAX5942A/MAX5942B
operates in three different modes: PD detection signa-
ture, PD classification, and PD power, depending on its
input voltage (V = GND - V ). All voltage thresholds
IN
EE
are designed to operate with or without the optional
diode bridge while still complying with the IEEE 802.3af
standard (see Application Circuit 1).
An integrated MOSFET provides PD isolation during
detection and classification. The MAX5942A/MAX5942B
guarantee a leakage current offset of less than 10µA dur-
ing the detection phase. A programmable current limit
prevents high inrush current during power-on. The
devices feature power-mode UVLO with wide hysteresis
and long deglitch time to compensate for twisted-pair
cable resistive drop and to ensure glitch-free transition
between detection, classification, and power-on/off
phases. The MAX5942A/MAX5942B provide both active-
high (PGOOD) and active-low (PGOOD) outputs. Both
devices offer an adjustable UVLO threshold with a
default value compliant to the IEEE 802.3af standard.
The MAX5942A/MAX5942B are designed to work with or
without an external diode bridge in front of the PD.
Detection Mode (1.4V ≤ V ≤ 10.1V)
IN
In detection mode, the power source equipment (PSE)
applies two voltages on V in the range of 1.4V to
IN
10.1V (1V step minimum), and then records the current
measurements at the two points. The PSE then com-
putes ∆V/∆I to ensure the presence of the 25.5kΩ sig-
nature resistor. In this mode, most of the
MAX5942A/MAX5942B internal circuitry is off and the
offset current is less than 10µA.
If the voltage applied to the PD is reversed, install pro-
tection diodes on the input terminal to prevent internal
damage to the MAX5942A/MAX5942B (see Figures 8
and 9). Since the PSE uses a slope technique (∆V/∆I) to
calculate the signature resistance, the DC offset due to
the protection diodes is subtracted and does not affect
the detection process.
Use the MAX5942A/MAX5942B PWM current-mode con-
trollers to design flyback- or forward-mode power sup-
plies. Current-mode operation simplifies control-loop
design while enhancing loop stability. An internal high-
voltage startup regulator allows the device to connect
directly to the input supply without an external startup
resistor. Current from the internal regulator starts the con-
troller. Once the tertiary winding voltage is established,
the internal regulator is switched off and bias current
for running the PWM controller is derived from the
tertiary winding. The internal oscillator is set to 275kHz
and trimmed to 10%. This permits the use of small
Classification Mode (12.6V ≤ V ≤ 20V)
IN
In the classification mode, the PSE classifies the PD
based on the power consumption required by the PD.
This allows the PSE to efficiently manage power distribu-
tion. The IEEE 802.3af standard defines five different
classes as shown in Table 1. An external resistor (R
)
CL
connected from RCL to V sets the classification current.
EE
______________________________________________________________________________________ 11
IEEE 802.3af Power-Over-Ethernet
Interface/PWM Controller for Power Devices
Table 2. Setting Classification Current
IEEE 802.3af PD CLASSIFICATION
CURRENT SPECIFICATION (mA)
CLASS CURRENT SEEN AT V (mA)
IN
CLASS
R
(Ω)
V * (V)
IN
CL
MIN
0
MAX
4
MIN
0
MAX
4
0
1
2
3
4
10k
732
392
255
178
12.6 to 20
12.6 to 20
12.6 to 20
12.6 to 20
12.6 to 20
9
12
20
30
42
9
12
20
30
44
17
26
36
17
26
36
*V is measured across the MAX5942 input pins (V and GND), which does not include the diode bridge voltage drop.
IN
EE
GND
2.4V,
REF
UVLO
REF
6.8V
EN
GND
RCL
CLASSIFICATION
R1
R2
PGOOD
2.4V, 0.8
HYST
21.8V
MAX5942B
Q4
39V
R3
V
, 6V
GATE
1.2V, REF
EN
UVLO
PGOOD
5V, REF
Q3
V
OUT
Q2
200mV
GATE
Q1
V
EE
Figure 2. Powered Device Interface Block Diagram
12 ______________________________________________________________________________________
IEEE 802.3af Power-Over-Ethernet
Interface/PWM Controller for Power Devices
The PSE determines the class of a PD by applying a volt-
V
IN
= 24V TO 60V
age at the PD input and measures the current sourced
out of the PSE. When the PSE applies a voltage between
12.6V and 20V, the MAX5942A/MAX5942B exhibit a cur-
rent characteristic with values indicated in Table 2. The
PSE uses the classification current information to classify
the power requirement of the PD. The classification cur-
rent includes the current drawn by the 25.5kΩ detection
signature resistor and the supply current of the
MAX5942A/MAX5942B so that the total current drawn by
the PD is within the IEEE 802.3af standard figures. The
classification current is turned off whenever the device is
in power mode.
GND
R1
R2
MAX5942A
MAX5942B
UVLO
V
EE
Power Mode
During power mode, when V rises above the undervolt-
IN
age lockout threshold (V
), the MAX5942A/
UVLO,ON
MAX5942B gradually turn on the internal N-channel MOS-
FET Q1 (see Figure 2). The MAX5942A/MAX5942B
charge the gate of Q1 with a constant current source
(10µA, typ). The drain-to-gate capacitance of Q1 limits
the voltage rise rate at the drain of MOSFET, thereby limit-
ing the inrush current. To reduce the inrush current, add
external drain-to-gate capacitance (see the Inrush
Current section). When the drain of Q1 is within 1.2V of its
source voltage and its gate-to-source voltage is above
5V, the MAX5942A/MAX5942B assert the PGOOD/
PGOOD outputs. The MAX5942A/MAX5942B have a wide
UVLO hysteresis and turn-off deglitch time to compensate
for the high impedance of the twisted-pair cable.
Figure 3. Setting Undervoltage Lockout with an External
Resistor-Divider
1%. When using the external resistor-divider, the
MAX5942 has an external reference voltage hysteresis of
20% (typ). In other words, when UVLO is programmed
externally, the turn-off threshold will be 80% (typ) of the
new UVLO turn-on threshold.
Inrush Current Limit
The MAX5942A/MAX5942B charge the gate of the inter-
nal MOSFET with a constant current source (10µA, typ).
The drain-to-gate capacitance of the MOSFET limits the
voltage rise rate at the drain, thereby limiting the inrush
current. Add an external capacitor from GATE to OUT
to further reduce the inrush current. Use the following
equation to calculate the inrush current:
Undervoltage Lockout
The MAX5942A/MAX5942B operate up to a 67V supply
voltage with a default UVLO turn-on set at 39V and a
UVLO turn-off set at 30V. Adjust the UVLO threshold
using a resistor-divider connected to UVLO (see Figure
3). When the input voltage is above the UVLO threshold
COUT
CGATE
IINRUSH = IG
x
(V ), the IC is in power mode and the MOSFET is
UVLO,ON
on. When the input voltage goes below the UVLO thresh-
old (V ) for more than t , the MOSFET
The recommended inrush current for a PoE application
is 100mA.
UVLO,OFF
turns off.
OFF_DLY
PGOOD/PGOOD Outputs
PGOOD is an open-drain, active-high logic output.
To adjust the UVLO threshold, connect an external
resistor-divider from GND to UVLO and from UVLO to
PGOOD goes high impedance when V
is within 1.2V
OUT
V
. Use the following equations to calculate R1 and
EE
of V
and when GATE is 5V above V . Otherwise,
EE
EE
R2 for a desired UVLO threshold:
PGOOD is pulled to V
(given that V
is at least 5V
OUT
OUT
below GND). Connect PGOOD to SS_SHDN to enable
the PWM controller.
V
REF,UVLO
R2 = 25.5kΩ x
V
IN,EX
PGOOD is an open-drain, active-low logic output.
R1 = 25.5kΩ - R2
PGOOD is pulled to V when V
is within 1.2V of V
EE
EE
OUT
EE
and when GATE is 5V above V . Otherwise, PGOOD
where V
is the desired UVLO threshold. Since the
IN,EX
goes high impedance.
resistor-divider replaces the 25.5kΩ PD detection resis-
tor, ensure that the sum of R1 and R2 equals 25.5kΩ
______________________________________________________________________________________ 13
IEEE 802.3af Power-Over-Ethernet
Interface/PWM Controller for Power Devices
Thermal Dissipation
During classification mode, if the PSE applies the maxi-
mum DC voltage, the maximum voltage drop from GND
Internal Regulators
The internal regulators of the MAX5942A/MAX5942B
enable initial startup without a lossy startup resistor and
regulate the voltage at the output of a tertiary (bias)
winding to provide power for the IC. At startup, V+ is reg-
to V
will be 13V. If the maximum classification cur-
RCL
rent of 42mA flows through the MAX5942A/
MAX5942B, then the maximum DC power dissipation
will be close to 546mW, which is slightly higher than the
maximum DC power dissipation the IC can handle.
However, according to the IEEE 802.3af standard, the
duration of the classification mode is limited to 75ms
(max). The MAX5942A/MAX5942B handle the maxi-
mum classification power dissipation for the maximum
duration time without sustaining any internal damage. If
the PSE violates the IEEE 802.3af standard by exceed-
ing the 75ms maximum classification duration, it may
cause internal damage to the IC.
ulated down to V
DD
to provide bias for the device. The
CC
V
regulator then regulates from the output of the ter-
tiary winding to V . This architecture allows the tertiary
CC
winding to have only a small filter capacitor at its output,
thus eliminating the additional cost of a filter inductor.
When designing the tertiary winding, calculate the num-
ber of turns so the minimum reflected voltage is always
higher than 12.7V. The maximum reflected voltage
must be less than 36V.
To reduce power dissipation, the high-voltage regulator
is disabled when the V
voltage reaches 12.7V. This
DD
greatly reduces power dissipation and improves effi-
PWM Controller
ciency. If V
falls below the undervoltage lockout
= 6.6V), the low-voltage regulator is dis-
CC
Current-Mode Control
The MAX5942A/MAX5942B offer current-mode control
operation with added features such as leading-edge
blanking with dual internal path that only blanks the
sensed current signal applied to the input of the PWM
comparator. The current-limit comparator monitors the
CS pin at all times and provides cycle-by-cycle current
limit without being blanked. The leading-edge blanking
of the CS signal prevents the PWM comparator from
prematurely terminating the on cycle. The CS signal
contains a leading-edge spike that is the result of the
MOSFET gate charge current, capacitive and diode
reverse recovery current of the power circuit. Since this
leading-edge spike is normally lower than the current-
limit comparator threshold, current limiting is not
blanked and cycle-by-cycle current limiting is provided
under all conditions.
threshold (V
CC
abled, and soft-start is reinitiated. In undervoltage lock-
out, the MOSFET driver output (NDRV) is held low.
If the input voltage range is between 13V and 36V, V+
and V
may be connected to the line voltage, provid-
DD
ed that the maximum power dissipation is not exceed-
ed. This eliminates the need for a tertiary winding.
PWM Controller Undervoltage Lockout,
Soft-Start, and Shutdown
The soft-start feature of the MAX5942A/MAX5942B
allows the load voltage to ramp up in a controlled man-
ner, thus eliminating output voltage overshoot.
While the part is in undervoltage lockout, the capacitor
connected to the SS_SHDN pin is discharged. Upon
coming out of undervoltage lockout, an internal current
source starts charging the capacitor to initiate the soft-
start cycle. Use the following equation to calculate total
soft-start time:
Use the MAX5942A in discontinuous flyback applica-
tions where wide line voltage and load current variation
are expected. Use the MAX5942B for single-transistor
forward converters where the maximum duty cycle
must be limited to less than 50%.
ms
nF
t
= 0.45
×C
ss
startup
Under certain conditions, it may be advantageous to
use a forward converter with greater than 50% duty
cycle. For those cases, use the MAX5942A. The large
duty cycle results in much lower operating primary
RMS currents through the MOSFET switch and in most
cases a smaller output filter inductor. The major disad-
vantage to this is that the MOSFET voltage rating must
be higher and that slope compensation must be provid-
ed to stabilize the inner current loop. The MAX5942A
provides internal slope compensation.
where C is the soft-start capacitor as shown in Figure 5.
SS
Operation begins when V
ramps above 0.6V.
SS_SHDN
SS_SHDN
When soft-start has completed, V
is regulated
to 2.4V, the internal voltage reference. Pull V
below 0.25V to disable the controller.
SS_SHDN
Undervoltage lockout shuts down the controller when
is less than 6.6V. The regulators for V+ and the ref-
V
CC
erence remain on during shutdown.
14 ______________________________________________________________________________________
IEEE 802.3af Power-Over-Ethernet
Interface/PWM Controller for Power Devices
V
DD
V
DD-OK
V+
V-
IN
IN
HIGH-
VOLTAGE
REGULATOR
BIAS
WINDING
REGULATOR
EN
EN
OUT
OUT
0.7V
V
CC
MAX5942A ONLY
UVLO
6.6V
SLOPE
COMPENSATION
26mV/µs
V
CC
275kHz
R
S
OSCILLATOR
NDRV
Q
26mV/µs
1MΩ
80%/50%
DUTY CYCLE
CLAMP
∑
50kΩ
FB
ILIM
70ns
PWM
125mV
CS
ERROR
AMP
5kΩ
V
CC
BLANKING
SS_SHDN
4µA
3R
2.4V
BUF
R
0.25V
Figure 4. MAX5942A/MAX5942B PWM Controller Functional Diagram
______________________________________________________________________________________ 15
IEEE 802.3af Power-Over-Ethernet
Interface/PWM Controller for Power Devices
1N4148
N
T
N
R
L1
4.7µH
6
14
CMHD2003
V
IN
V
SBL204OCT
OUT
5V/10A
(36V TO 72V)
C
IN
3
C
OUT
✕
✕
3
0.1µF
GND
V+
V
DD
0.47µF
20Ω
N
N
S
5
P
560µF
C
DD
14
4.7µF
1nF
M1
IRF640N
NDRV
CS
RCL
R
1
V
MAX5942
CC
2kΩ
100Ω
R
C
SENSE
100mΩ
CC
10µF
R
25.5kΩ
CL
V-
UVLO
SS_SHDN
C
SS
0.1µF
PGOOD
GATE
OUT
FB
V
EE
GATE
R
2
C
FB
2kΩ
(OPTIONAL)
Figure 5. Forward Converter
Figure 5). Calculate the output voltage using the follow-
ing equation:
Current-Sense Comparator
The current-sense (CS) comparator and its associated
logic limit the peak current through the MOSFET.
Current is sensed at CS as a voltage across a sense
resistor between the source of the MOSFET and GND.
To reduce switching noise, connect CS to the external
MOSFET source through a 100Ω resistor or an RC low-
pass filter (Figures 5, 6). Select the current-sense resis-
R1
R
VOUT = 1+
× VREF
2
where V
= 2.4V.
REF
Choose R1//R2 << R , where R ≅ 50kΩ is the input
IN
IN
tor, R
according to the following equation:
SENSE
resistance of FB. The gain of the error amplifier is inter-
nally configured for -20 (see Figure 4).
RSENSE = 0.465V/ILIMPrimary
The error amplifier may also be used to regulate the out-
put of the tertiary winding for implementing a primary-
side regulated isolated power supply (see Figure 7).
Calculate the output voltage using the following equation:
where I
current.
is the maximum peak primary-side
LIMPrimary
When V
> 465mV, the power MOSFET switches off.
CS
The propagation delay from the time the switch current
reaches the trip level to the driver turn-off time is 180ns.
NS
NT
R1
R
VOUT
=
1+
× VREF
2
Internal Error Amplifier
The MAX5942A/MAX5942B include an internal error
amplifier that can be used to regulate the output volt-
age in the case of a nonisolated power supply (see
where N is the number of secondary turns and N is
S
T
the number of tertiary winding turns.
16 ______________________________________________________________________________________
IEEE 802.3af Power-Over-Ethernet
Interface/PWM Controller for Power Devices
N
T
V
OUT
V
IN
C
OUT
C
IN
V+
GND
V
DD
N
N
S
P
C
C
DD
CC
M1
NDRV
CS
RCL
V
CC
MAX5942
100Ω
R
R
CL
SENSE
25.5kΩ
R
1
V-
PGOOD
SS_SHDN
PGOOD
UVLO
C
SS
OUT
FB
V
EE
GATE
R
2
Figure 6. Flyback Converter
N
T
V
V
OUT
IN
C
OUT
C
IN
GND
V+
V
DD
N
N
S
P
C
DD
R
R
1
2
FB
M1
NDRV
PGOOD
V
CC
CS
MAX5942
100Ω
C
CC
25.5kΩ
GATE
R
SENSE
RCL
V-
OUT
SS_SHDN
PGOOD
C
SS
R
CL
UVLO
V
EE
Figure 7. Flyback Converter
______________________________________________________________________________________ 17
IEEE 802.3af Power-Over-Ethernet
Interface/PWM Controller for Power Devices
PWM Comparator and Slope Compensation
Applications Information
Design Example
The following is a general procedure for designing a
forward converter using the MAX5942B:
An internal 275kHz oscillator determines the switching
frequency of the controller. At the beginning of each
cycle, NDRV switches the N-channel MOSFET on.
NDRV switches the external MOSFET off after the maxi-
mum duty cycle has been reached, regardless of the
feedback.
1) Determine the requirements.
2) Set the output voltage.
The MAX5942B uses an internal ramp generator for
slope compensation. The internal ramp signal is reset
at the beginning of each cycle and slews at 26mV/µs.
3) Calculate the transformer primary to secondary
winding turns ratio.
4) Calculate the reset to primary winding turns ratio.
The PWM comparator uses the instantaneous current,
the error voltage, the internal reference, and the slope
compensation (MAX5942A only) to determine when to
switch the N-channel MOSFET off. In normal operation,
the N-channel MOSFET turns off when:
5) Calculate the tertiary to primary winding turns
ratio.
6) Calculate the current-sense resistor value.
7) Calculate the output inductor value.
8) Select the output capacitor.
I
× R
> V -V -V
EA REF SCOMP
PRIMARY
SENSE
The circuit in Figure 5 was designed as follows:
where I
is the current through the N-channel
PRIMARY
1) 30V ≤ V ≤ 67V, V
= 5V, I
= 10A, V
≤
IN
OUT
OUT
RIPPLE
MOSFET, V
is the 2.4V internal reference, V is the
REF
EA
SCOMP
50mV. Turn-on threshold is set at 38.6V.
output voltage of the internal amplifier, and V
is a
2) To set the output voltage, calculate the values of
resistors R1 and R2 according to the following
equation:
ramp function starting at zero and slewing at 26mV/µs
(MAX5942A only). When using the MAX5942A in a for-
ward-converter configuration, the following condition
must be met to avoid control-loop subharmonic oscilla-
tions:
R1
R2
VOUT = V
1+
REF
N
k ×R
× V
OUT
S
SENSE
L
×
= 26mV/µs
R1//R2 << 50kΩ
VREF = VSS_SHDN = 2.4V
N
P
where k = 0.75 to 1, and N and N are the number of
S
P
where V
is the reference voltage of the shunt reg-
REF
turns on the secondary and primary side of the trans-
former, respectively. L is the output filter inductor. This
makes the output inductor current downslope as refer-
ulator, and R and R are the resistors shown in
1
2
Figures 5 and 6.
enced across R
tion. The controller responds to transients within one
cycle when this condition is met.
equal to the slope compensa-
SENSE
3) The turns ratio of the transformer is calculated based
on the minimum input voltage and the lower limit of
the maximum duty cycle for the MAX5942B (44%).
To enable the use of MOSFETs with drain-source
breakdown voltages of less than 200V, use the
MAX5942B with the 50% maximum duty cycle.
Calculate the turns ratio according to the following
equation:
N-Channel MOSFET Gate Driver
NDRV drives an N-channel MOSFET. NDRV sources
and sinks large transient currents to charge and dis-
charge the MOSFET gate. To support such switching
transients, bypass V
with a ceramic capacitor. The
CC
average current as a result of switching the MOSFET is
the product of the total gate charge and the operating
frequency. It is this current plus the DC quiescent cur-
rent that determines the total operating current.
V
+ V ×D
(
)
N
OUT
D1
MAX
S
≥
N
D
× V
IN_MIN
P
MAX
where:
N /N = Turns ratio (N is the number of secondary
turns and N is the number of primary turns).
S
P
S
P
18 ______________________________________________________________________________________
IEEE 802.3af Power-Over-Ethernet
Interface/PWM Controller for Power Devices
V
V
= Output voltage (5V).
OUT
1-0.5
0.5
= Voltage drop across D1 (typically 0.5V for
power Schottky diodes).
D1
N ≤14×
=14
R
D
= Minimum value of maximum operating duty
MAX
cycle (44%).
Round N to the nearest smallest integer.
R
The turns ratio of the reset winding (N /N ) determines
R
P
V
= Minimum input voltage (30V).
IN_MIN
the peak voltage across the N-channel MOSFET.
Use the following equation to determine the maxi-
mum drain-source voltage across the N-channel
MOSFET:
In this example:
5V+ 0.5V × 0.44
(
)
N
S
≥
= 0.395
N
0.44× 30V
P
N
P
V
≥ V
× 1 +
DSMAX
IN_MAX
N
Choose N based on core losses and DC resis-
R
P
tance. Use the turns ratio to calculate N , rounding
S
V
V
= Maximum MOSFET drain-source voltage.
= Maximum input voltage:
DSMAX
up to the nearest integer. In this example, N = 14
P
and N = 6.
S
IN_MAX
For a forward converter, choose a transformer with a
magnetizing inductance in the neighborhood of
200µH. Energy stored in the magnetizing inductance
of a forward converter is not delivered to the load
and must be returned back to the input; this is
accomplished with the reset winding.
14
14
V
≥ 67V × 1 +
=134V
DSMAX
Choose MOSFETs with appropriate avalanche
power ratings to absorb any leakage energy.
The transformer primary to secondary leakage
inductance should be less than 1µH. Note that all
leakage energy is dissipated across the MOSFET.
Snubber circuits may be used to direct some or all
of the leakage energy to be dissipated across a
resistor.
5) Choose the tertiary winding turns ratio (N /N ) so that
T
P
the minimum input voltage provides the minimum
operating voltage at V
(13V). Use the following
DD
equation to calculate the tertiary winding turns ratio:
VDDMIN + 0.7
×NP ≤NT ≤
To calculate the minimum duty cycle (D
following equation:
), use the
MIN
V
IN_MIN
VDDMAX + 0.7
V
×NP
OUT
=
D
=
MIN
V
IN_MAX
N
S
V
×
-V
D1
IN_MAX
N
P
where:
V
is the minimum V supply voltage (13V).
DD
where V
is the maximum input voltage (67V).
DDMIN
IN_MAX
V
is the maximum V
supply voltage (30V).
DD
4) The reset winding turns ratio (N /N ) needs to be
DDMAX
R
P
low enough to guarantee that the entire energy in
the transformer is returned to V+ within the off cycle
at the maximum duty cycle. Use the following equa-
tion to determine the reset winding turns ratio:
V
V
is the minimum input supply voltage (30V).
is the maximum input supply voltage (67V
IN_MIN
IN_MAX
in this design example).
N is the number of turns of the primary winding.
P
1-DMAX
′
N is the number of turns of the tertiary winding:
T
NR ≤NP ×
DMAX
′
13.7
30
36.7
67
×14≤N ≤
×14
T
where:
N /N = Reset winding turns ratio.
R
P
6.39≤N ≤ 7.67
T
D
MAX
’ = Maximum value of maximum duty cycle:
Choose N = 7.
T
______________________________________________________________________________________ 19
IEEE 802.3af Power-Over-Ethernet
Interface/PWM Controller for Power Devices
Table 3. Component Suppliers
COMPONENT
SUPPLIERS
International Rectifier
Fairchild
WEBSITE
www.irf.com
Power FETS
www.fairchildsemi.com
www.vishay.com/brands/siliconix/main.html
www.vishay.com/brands/dale/main.html
www.irctt.com/pages/index.cfm
www.onsemi.com
Vishay-Siliconix
Dale-Vishay
Current-Sense Resistors
Diodes
IRC
ON Semi
General Semiconductor
Central Semiconductor
Sanyo
www.gensemi.com
www.centralsemi.com
www.sanyo.com
Capacitors
Magnetics
Taiyo Yuden
AVX
www.t-yuden.com
www.avxcorp.com
Coiltronics
www.cooperet.com
Coilcraft
www.coilcraft.com
Pulse Engineering
www.pulseeng.com
6) Choose R
according to the following equation:
8) The size and ESR of the output filter capacitor deter-
mine the output ripple. Choose a capacitor with a
low ESR to yield the required ripple voltage.
SENSE
V
ILIM
R
≤
SENSE
N
Use the following equations to calculate the peak-to-
peak output ripple:
S
×1.2×I
OUTMAX
N
P
2
2
where:
V
= V
+ V
RIPPLE
RIPPLE,ESR RIPPLE,C
V
ILIM
is the current-sense comparator trip threshold
voltage (0.465V).
where:
N /N is the secondary-side turns ratio (5/14 in this
V
is the combined RMS output ripple due to
S
P
RIPPLE
VRIPPLE,ESR, the ESR ripple, and V
example).
, the
RIPPLE,C
capacitive ripple. Calculate the ESR ripple and
capacitive ripple as follows:
I
is the maximum DC output current (10A in
OUTMAX
this example):
V
= I
x ESR
RIPPLE,ESR
RIPPLE
0.465V
R
≤
= 90.4mΩ
SENSE
V
= I /(2 x π x 275kHz x C
RIPPLE
)
OUT
RIPPLE,C
6
×1.2×10
14
Layout Recommendations
7) Choose the inductor value so that the peak ripple
current (LIR) in the inductor is between 10% and
20% of the maximum output current:
All connections carrying pulsed currents must be very
short, be as wide as possible, and have a ground plane
as a return path. The inductance of these connections
must be kept to a minimum due to the high di/dt of the
currents in high-frequency switching power converters.
V
+ V × 1-D
(
) (
)
OUT
D
MIN
L ≥
2×LIR×275kHz×I
OUTMAX
Current loops must be analyzed in any layout pro-
posed, and the internal area kept to a minimum to
reduce radiated EMI. Ground planes must be kept as
intact as possible.
where V is the output Schottky diode forward-volt-
D
age drop (0.5V) and LIR is the ratio of inductor rip-
ple current to DC output current:
5.5 × 1-0.198
0.4×275kHz×10A
(
) (
)
L ≥
= 4.01µH
20 ______________________________________________________________________________________
IEEE 802.3af Power-Over-Ethernet
Interface/PWM Controller for Power Devices
POWER-OVER
SIGNAL PAIRS
VREG
PHY
RX
3
6
1
2
GND
DF025A
DF025A
+
-
+
-
RJ-45
4
5
7
8
TX
-48V
POWER-OVER
SPARE PAIRS
VREG
V+
V
GND
NDRV
CS
DD
MAX5942
V
V-
CC
*D1
GND
SS_SHDN
**R1
**R2
SMBJ58CA
60V
R
=
DISC
25.5kΩ
UVLO
RCL
PGOOD
PGOOD
68nF
GATE
FB
*D2
OUT
V
EE
-48V
C
*
GATE
* OPTIONAL.
** R1 AND R2 ARE OPTIONAL AND WHEN USED, THEY MUST TOTAL TO 25.5kΩ AND REPLACE THE 25.5kΩ RESISTOR.
Figure 8. PD with Power-Over-Ethernet (Power is Provided by Either the Signal Pairs or the Spare Pairs)
______________________________________________________________________________________ 21
IEEE 802.3af Power-Over-Ethernet
Interface/PWM Controller for Power Devices
POWER-SUPPLY CIRCUIT 1
VREG1
V+
V
GND
NDRV
CS
DD
MAX5942
V
V-
CC
*D1
GND
SS_SHDN
**R1
**R2
R
=
DISC
25.5kΩ
UVLO
RCL
PGOOD
PGOOD
68nF
60V
GATE
FB
R
CL
*D2
OUT
V
EE
-48V
POWER-SUPPLY CIRCUIT 2
C
GATE
*
V+
VREG2
V+
V
NDRV
CS
DD
MAX5019
V
GND
CC
SS_SHDN
FB
*OPTIONAL.
**R1 AND R2 ARE OPTIONAL AND WHEN USED, THEY MUST TOTAL TO 25.5kΩ AND REPLACE THE 25.5kΩ RESISTOR.
Figure 9. Power-Supply Circuit 1 Enabling PWM Controller of a Second Power Circuit
22 ______________________________________________________________________________________
IEEE 802.3af Power-Over-Ethernet
Interface/PWM Controller for Power Devices
Typical Operating Circuit
VREG
V+
V
GND
NDRV
CS
DD
MAX5942
V
V-
CC
GND
SS_SHDN
PGOOD
UVLO
RCL
R
=
DISC
25.5kΩ
PGOOD
60V
GATE
FB
OUT
V
EE
-48V
C
GATE
Chip Information
TRANSISTOR COUNT: 4232
PROCESS: BiCMOS
______________________________________________________________________________________ 23
IEEE 802.3af Power-Over-Ethernet
Interface/PWM Controller for Power Devices
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
24 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2003 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
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