MAX5935 [MAXIM]
Quad Network Power Controller for Power-Over-LAN;
| 型号： | MAX5935 |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Quad Network Power Controller for Power-Over-LAN 局域网 |
| 文件： | 总44页 (文件大小：706K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-3412; Rev 3; 5/07
Quad Network Power Controller
for Power-Over-LAN
General Description
Features
♦ IEEE 802.3af Compliant
The MAX5935 quad network power controller is designed
for use in IEEE 802.3af-compliant power sourcing equip-
ment (PSE). The device provides power devices (PD) dis-
covery, classification, current limit, and both DC and AC
load disconnect detections. The MAX5935 can be used
in either endpoint PSE (LAN switches/routers) or midspan
PSE (power injector) applications.
♦ Controls Four Independent, -48V-Powered
Ethernet Ports in Either Endpoint or Midspan PSE
Applications
♦ Wide Digital Power Input, V
, Common-Mode
DIG
Range: V to (AGND + 7.7V)
EE
♦ PD Violation of Class Current Protection
♦ PD Detection and Classification
The MAX5935 can operate autonomously or be con-
trolled by software through an I2C-compatible interface.
Separate input and output data lines (SDAIN and
SDAOUT) allow usage with optocouplers. The
MAX5935 is a slave device. Its four address inputs
allow 16 unique MAX5935 addresses. A separate INT
output and four independent shutdown inputs (SHD_)
allow fast response from a fault to port shutdown. A
RESET input allows hardware reset of the device. A
special Watchdog feature allows the hardware to
gracefully take over control if the software crashes. A
cadence timing feature allows the MAX5935 to be used
in midspan systems.
♦ Provides Both DC and AC Load Removal
Detections
♦ I2C-Compatible, 3-Wire Serial Interface
♦ Fully Programmable and Configurable Operation
Through I2C Interface
♦ Current Foldback and Duty-Cycle-
Controlled/Programmable Current Limit
♦ Short-Circuit Protection with Fast Gate Pulldown
♦ Direct Fast Shutdown Control Capability
♦ Programmable Direct Interrupt Output
The MAX5935 is fully software configurable and program-
mable. A class-over-current detection function enables
system power management to detect if a PD draws more
current than the allowable amount for its class. Other fea-
tures are input under/overvoltage lockout, overtempera-
ture protection, output voltage slew-rate limit during
startup, power-good, and fault status. The MAX5935’s
programmability includes gate charging current, current-
limit threshold, startup timeout, overcurrent timeout,
autorestart duty cycle, PD disconnect AC detection
threshold, and PD disconnect detection timeout.
♦ Watchdog Mode Enable Hardware Graceful
Takeover
Ordering Information
PKG
CODE
PART
TEMP RANGE PIN-PACKAGE
36 SSOP
36 SSOP
36 SSOP
36 SSOP
MAX5935CAX
0°C to +70°C
A36-2
A36-2
A36-2
A36-2
MAX5935CAX+ 0°C to +70°C
MAX5935EAX -40°C to +85°C
MAX5935EAX+ -40°C to +85°C
The MAX5935 is available in a 36-pin SSOP package
and is rated for both extended (-40°C to +85°C) and
commercial (0°C to +70°C) temperature ranges.
Pin Configuration
TOP VIEW
RESET
MIDSPAN
INT
1
2
3
4
5
6
7
8
9
36 OSC_IN
35 AUTO
Applications
34 OUT1
SCL
33 GATE1
32 SENSE1
Power-Sourcing Equipment (PSE)
Power-Over-LAN/Power-Over-Ethernet
Switches/Routers
SDAOUT
SDAIN
A3
MAX5935
31 OUT2
30 GATE2
29 SENSE2
A2
A1
28 V
EE
Midspan Power Injectors
A0 10
DET1 11
DET2 12
DET3 13
DET4 14
DGND 15
27 OUT3
26 GATE3
25 SENSE3
24 OUT4
23 GATE4
22 SENSE4
21 AGND
20 SHD4
19 SHD3
V
DD
16
SHD1 17
SHD2 18
Typical Operating Circuits appear at end of data sheet.
SSOP
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
Quad Network Power Controller
for Power-Over-LAN
ABSOLUTE MAXIMUM RATINGS
(Voltages referenced to V , unless otherwise noted.)
Maximum Power Dissipation
36-Pin SSOP (derate 11.4mW/°C above +70°C) .........941mW
Operating Temperature Ranges:
MAX5935EAX ..................................................-40°C to +85°C
MAX5935CAX .....................................................0°C to +70°C
Storage Temperature Range.............................-65°C to +150°C
Junction Temperature......................................................+150°C
Lead Temperature (soldering, 10s) .................................+300°C
EE
AGND, DGND, DET_, V , RESET, A3, A2, A1, A0, SHD_,
DD
OSC_IN, SCL, SDAIN, OUT_ and AUTO............-0.3V to +80V
GATE_ (Internally Clamped, Note 1)...................-0.3V to +11.4V
SENSE_ ..................................................................-0.3V to +24V
V
, RESET, A3, A2, A1, A0, SHD_, OSC_IN, SCL, SDAIN and
AUTO to DGND ....................................................-0.3V to +7V
DD
INT and SDAOUT to DGND....................................-0.3V to +12V
Maximum Current into INT, SDAOUT, DET_.......................80mA
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(AGND = +48V. V
values are at AGND = +48V, DGND = +48V, V
negative otherwise.)
= 0V, V
to DGND = +3.3V. All voltages are referenced to V , unless otherwise noted. Typical
EE
DD EE
= (DGND + 3.3V), T = +25°C. Currents are positive when entering the pin and
A
DD
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX UNITS
POWER SUPPLIES
V
V
V
- V
EE
32
0
60
AGND
AGND
60
V
DGND
Operating Voltage Range
Supply Currents
V
V
to V
, V
= V
= V
1.71
3.0
5.50
DD
DD
DGND DGND
AGND
EE
V
DD
to V
, V
5.5
DGND DGND
OUT_= V , SENSE_ = V , DET_ = AGND,
all logic inputs open, SCL = SDAIN = V
INT and SDAOUT open; measured at AGND
in power mode after GATE_ pullup
EE
EE
,
DD
I
EE
4.2
2.7
6.8
mA
I
All logic inputs high, measured at V
5.6
DIG
DD
GATE DRIVER AND CLAMPING
GATE_ Pullup Current
I
Power mode, gate drive-on, V
= V (Note 2)
-35
25
-50
40
-65
55
µA
µA
mA
V
PU
GATE
EE
Weak GATE_ Pulldown Current
Maximum Pulldown Current
External Gate Drive
I
SHD_ = DGND, V = V + 5V
GATE_ EE
PDW
I
V
V
= 1V, V
= V + 2V
100
10
PDS
SENSE
GATE_
EE
V
- V , power mode, gate drive-on
EE
9
11
GS
GATE
CURRENT LIMIT
Maximum V
allowed during current limit,
SENSE_
Current-Limit Clamp Voltage
V
202
177
212
222
196
mV
mV
SU_LIM
FLT_LIM
FLBK_ST
V
= V (Note 3)
EE
OUT_
Default, Class 0,
Class 3, Class 4
Overcurrent V
threshold allowed for
SENSE_
Overcurrent Threshold After
Startup
V
t ≤ t
after startup;
= V
EE
Class 1
Class 2
48
89
61
FAULT
V
OUT_
105
V
- V , above which the current-limit trip
OUT_
EE
Foldback Initial OUT_ Voltage
V
30
50
V
V
voltage starts folding back
V
- V , above which the current-limit trip
OUT_
EE
Foldback Final OUT_ Voltage
V
FLBK_END
voltage reaches V
TH_FB
2
_______________________________________________________________________________________
Quad Network Power Controller
for Power-Over-LAN
ELECTRICAL CHARACTERISTICS (continued)
(AGND = +48V. V
values are at AGND = +48V, DGND = +48V, V
negative otherwise.)
= 0V, V
to DGND = +3.3V. All voltages are referenced to V , unless otherwise noted. Typical
EE
DD EE
= (DGND + 3.3V), T = +25°C. Currents are positive when entering the pin and
A
DD
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX UNITS
Minimum Foldback Current-
Limit Threshold
V
V
V
= V
AGND
64
mV
TH_FB
OUT_
SENSE_ Input Bias Current
= V
-2
µA
SENSE_
EE
SUPPLY MONITORS
V
Undervoltage Lockout
V
V
- V , (V
– V ) increasing
28.5
3
V
V
EE
EEUVLO
AGND
EE
AGND
EE
V
Undervoltage-Lockout
EE
V
EEUVLOH
Hysteresis
V
V
V
Overvoltage
V
(V
- V ) > V , V
EE_OV AGND
increasing
decreasing
62.5
1
V
V
V
EE
EE
EE
EE_OV
AGND
EE
Overvoltage Hysteresis
Undervoltage
V
OVH
V
(V
(V
(V
- V ) < V , V
EE_UV AGND
40
EE_UV
AGND
EE
V
V
Overvoltage
V
V
- V
- V
) > V
, V
DD_OV DD
increasing
decreasing
3.71
2.82
1.3
V
V
DD
DD
DD_OV
DD_UV
DD
DD
DGND
DGND
Undervoltage
) < V
, V
DD_UV DD
Device operates when (V
- V
) >
DD
DGND
V
V
Undervoltage Lockout
Undervoltage-Lockout
V
V
DD
DD
DDUVLO
V
, V
increasing
DDUVLO DD
V
120
mV
DDHYS
Hysteresis
Ports shut down and device resets if its junction
temperature exceeds this limit, temperature
increasing
Thermal-Shutdown Threshold
T
+150
20
°C
°C
µA
µA
SHD
Thermal-Shutdown Hysteresis
OUTPUT MONITOR
T
SHDH
BOUT
OUT_ Input Current
I
V
= V , all modes
AGND
2
OUT
OUT_ discharge current, detection and
classification off, port shutdown,
Idle Pullup Current at OUT_
I
200
1.5
260
2.5
DIS
V
= V
- 2.8V
AGND
OUT_
PGOOD High Threshold
PGOOD Hysteresis
PG
V
- V , OUT_ decreasing
2.0
V
TH
OUT_
EE
PG
220
mV
HYS
PGOOD Low-to-High Glitch
Filter
Minimum time PGOOD has to be high to set bit in
register 10h
t
3
4
ms
mV
PGOOD
LOAD DISCONNECT
DC Load Disconnect
Threshold
Minimum V
allowed before disconnect (DC
SENSE
V
2.5
5
DCTH
disconnect active), V
= V
EE
OUT_
_______________________________________________________________________________________
3
Quad Network Power Controller
for Power-Over-LAN
ELECTRICAL CHARACTERISTICS (continued)
(AGND = +48V. V
values are at AGND = +48V, DGND = +48V, V
negative otherwise.)
= 0V, V
to DGND = +3.3V. All voltages are referenced to V , unless otherwise noted. Typical
EE
DD EE
= (DGND + 3.3V), T = +25°C. Currents are positive when entering the pin and
A
DD
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX UNITS
AC Load Disconnect
Threshold (Note 4)
Current into DET_, ACD_EN_ bit = high,
OSC_IN = 2.2V
I
300
325
350
3.1
2.2
µA
V/ V
V
ACTH
V
/V
, ACD_EN_ bit = high,
DET_ OSC_IN
Oscillator Buffer Gain
A
2.90
1.8
2.93
1.9
OSC
C
= 400nF
DET
OSC_IN Fail Threshold
(Note 5)
Port will not power on if V
ACD_EN_ bit = high
< V
and
OSC_FAIL
OSC_IN
V
OSC_FAIL
OSC_IN input impedance when all the ACD_EN_
are active
OSC_IN Input Resistance
OSC_IN Input Capacitance
Load Disconnect Timer
DETECTION
Z
100
kΩ
pF
ms
OSC
C
5
OSC_IN
Time from V
< V
or current into DET_
DCTH
SENSE
t
300
400
DISC
< I
to gate shutdown (Note 6)
ACTH
Detection Probe Voltage
(First Phase)
V
V
V
V
- V
during the first detection phase
3.8
9.0
1.5
4
4.2
9.6
2.0
V
V
DPH1
DPH2
DLIM
AGND
DET_
Detection Probe Voltage
(Second Phase)
- V
during the second detection
AGND
DET_
9.3
phase
V
= V
AGND
, during detection, measure
DET_
Current-Limit Protection
Short-Circuit Threshold
I
1.75
1.62
12.5
mA
V
current through DET_
If V - V < V after the first detection
DCP
AGND
OUT
V
DCP
phase a short circuit to AGND is detected
First point measurement current threshold for
open condition
Open-Circuit Threshold
Resistor Detection Window
Resistor Rejection Window
I
µA
kΩ
kΩ
D_OPEN
R
(Note 7)
19.0
32
26.5
15.2
DOK
Detection rejects lower values
Detection rejects higher values
R
DBAD
CLASSIFICATION
Classification Probe Voltage
V
V
V
- V
during classification
, during classification,
16
50
20
75
V
CL
AGND
DET_
= V
DET_
AGND
Current-Limit Protection
I
mA
ClLIM
measure current through DET_
Class 0, Class 1
5.5
13.0
21
6.5
14.5
23
7.5
16.0
25
Class 1, Class 2
Class 2, Class 3
Class 3, Class 4
>Class 4
Classification current
thresholds between
classes
Classification Current
Thresholds
I
CL
mA
31
33
35
45
48
51
DIGITAL INPUTS/OUTPUTS (REFERRED to DGND)
Digital Input Low
Digital Input High
V
0.9
V
V
IL
V
2.4
IH
4
_______________________________________________________________________________________
Quad Network Power Controller
for Power-Over-LAN
ELECTRICAL CHARACTERISTICS (continued)
(AGND = +48V. V
values are at AGND = +48V, DGND = +48V, V
negative otherwise.)
= 0V, V
to DGND = +3.3V. All voltages are referenced to V , unless otherwise noted. Typical
EE
DD EE
= (DGND + 3.3V), T = +25°C. Currents are positive when entering the pin and
A
DD
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX UNITS
Internal Input Pullup/Pulldown
Resistor
Pullup (pulldown) resistor to V
default level
(DGND) to set
DD
R
DIN
25
50
75
kΩ
Open-Drain Output Low
Voltage
V
I
= 15mA
0.4
2
V
OL
SINK
Open-Drain Leakage
I
Open-drain high impedance, V = 3.3V
O
µA
OL
TIMING
Time during which a current limit set by V
SU_LIM
is allowed, starts when the GATE_ is turned on
(Note 8)
Startup Time
t
t
50
60
70
ms
START
FAULT
Maximum allowed time for an overcurrent
Fault Time
50
60
70
1
ms
ms
ms
condition set by V
after startup (Note 8)
FLT_LIM
Minimum delay between any port turning off,
does not apply in the case of a reset
Port Turn-Off Time
Detection Time
t
t
0.5
0.75
OFF
DET
Maximum time allowed before detection
is completed
320
Midspan Mode Detection
Delay
t
2.0
2
2.4
40
s
DMID
Classification Time
t
Time allowed for classification
ms
CLASS
Time V
must be above the V
EEUVLO
AGND
V
Turn-On Delay
t
4
ms
EEUVLO
DLY
thresholds before the device operates
16 x
FAULT
RSTR bits = 00
t
t
t
Time a port has to wait
before turning on after an
overcurrent fault,
32 x
FAULT
RSTR bits = 01
Restart Timer
t
ms
ms
RESTART
64 x
FAULT
RSTR_EN bit = high
RSTR bits = 10
RSTR bits = 11
0
Watchdog Clock Period
t
Rate of decrement of the watchdog timer
164
WD
TIMING CHARACTERISTICS for 2-WIRE FAST MODE (Figures 5 and 6)
Serial Clock Frequency
f
(Note 9)
400
kHz
µs
SCL
Bus Free Time Between a
STOP and a START Condition
t
(Note 9)
1.2
BUF
Hold Time for Start Condition
Low Period of the SCL Clock
High Period of the SCL Clock
t
(Note 9)
(Note 9)
(Note 9)
0.6
1.2
0.6
µs
µs
µs
HD, STA
t
LOW
t
HIGH
_______________________________________________________________________________________
5
Quad Network Power Controller
for Power-Over-LAN
ELECTRICAL CHARACTERISTICS (continued)
(AGND = +48V. V
values are at AGND = +48V, DGND = +48V, V
negative otherwise.)
= 0V, V
to DGND = +3.3V. All voltages are referenced to V , unless otherwise noted. Typical
EE
DD EE
= (DGND + 3.3V), T = +25°C. Currents are positive when entering the pin and
A
DD
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX UNITS
Setup Time for a Repeated
START Condition (Sr)
t
(Note 9)
0.6
µs
SU, STA
Data Hold Time
Data Setup Time
t
(Note 9)
(Note 9)
0
150
ns
ns
HD, DAT
t
100
SU, DAT
Rise Time of Both SDA and
SCL Signals, Receiving
t
(Note 9)
20+0.1C
300
300
ns
R
B
Fall Time of SDA Transmitting
Setup Time for STOP Condition
t
(Note 9)
(Note 9)
20+0.1C
0.6
ns
µs
F
B
t
SU, STO
Capacitive Load for Each Bus
Line
C
(Note 9)
(Note 9)
400
50
pF
ns
B
Pulse Width of Spike
Suppressed
t
SP
Note 1: GATE_ is internally clamped to 11.4V above V . Driving GATE_ higher than 11.4V above V may damage the device.
EE
EE
Note 2: Default values. The charge/discharge currents are programmable through the serial interface (see the Register Map and
Description section).
2
Note 3: Default values. The current-limit thresholds are programmed through the I C-compatible serial interface (see the Register
Map and Description section).
Note 4: This is the default value. Threshold can be programmed through serial interface R23h[2:0].
Note 5: AC disconnect works only if V
- V
≥ 3V.
DD
DGND
Note 6: t
can also be programmed through the serial interface (R29h) (see the Register Map and Description section).
DISC
Note 7: R = (V
- V
) / (I
- I
). V
, V
, I
and I represent the voltage at OUT_ and the current
D
OUT_2
OUT_1
DET_2 DET_1
OUT_1 OUT_2 DET_2
DET_1
at DET_ during phase 1 and 2 of the detection.
2
Note 8: Default values. The startup and fault times can be also programmed through the I C serial interface (see the Register Map
and Description section).
Note 9: Guaranteed by design. Not subject to production testing.
Typical Operating Characteristics
(V
= -48V, V
= +3.3V, AUTO = AGND = DGND = 0, RESET = SHD_ = unconnected, R
= 0.5Ω, T = +25°C,
SENSE A
EE
DD
all registers = default setting, unless otherwise noted.)
ANALOG SUPPLY CURRENT
vs. TEMPERATURE
DIGITAL SUPPLY CURRENT
vs. TEMPERATURE
ANALOG SUPPLY CURRENT
vs. INPUT VOLTAGE
5.0
4.8
4.6
4.4
4.2
4.0
3.8
3.6
3.4
3.2
3.0
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
4.5
4.4
4.3
4.2
4.1
4.0
3.9
3.8
3.7
3.6
3.5
MEASURED AT AGND
-40
-15
10
35
60
85
-40
-15
10
35
60
85
32
37
42
47
52
57
62
TEMPERATURE (°C)
TEMPERATURE (°C)
INPUT VOLTAGE (V)
6
_______________________________________________________________________________________
Quad Network Power Controller
for Power-Over-LAN
Typical Operating Characteristics (continued)
(V
= -48V, V
= +3.3V, AUTO = AGND = DGND = 0, RESET = SHD_ = unconnected, R
= 0.5Ω, T = +25°C,
SENSE A
EE
DD
all registers = default setting, unless otherwise noted.)
DIGITAL SUPPLY CURRENT
vs. INPUT VOLTAGE
V
EE
UNDERVOLTAGE LOCKOUT
vs. TEMPERATURE
GATE OVERDRIVE
vs. INPUT VOLTAGE
6
5
4
3
2
1
0
30.0
29.5
29.0
28.5
28.0
27.5
27.0
9.98
9.96
9.94
9.92
9.90
9.88
9.86
9.84
9.82
9.80
9.78
MEASURED AT V
DD
1.8 2.2 2.6 3.0 3.4 3.8 4.2 4.6 5.0
INPUT VOLTAGE (V)
-40
-15
10
35
60
85
32
37
42
47
52
57
62
TEMPERATURE (°C)
INPUT VOLTAGE (V)
SENSE TRIP VOLTAGE
vs. INPUT VOLTAGE
GATE OVERDRIVE
vs. TEMPERATURE
SENSE TRIP VOLTAGE
vs. TEMPERATURE
190
188
186
184
182
180
10.5
10.4
10.3
10.2
10.1
10.0
9.9
200
195
190
185
180
175
170
9.8
9.7
9.6
9.5
32
37
42
47
52
57
62
-40
-15
10
35
60
85
-40
-15
10
35
60
85
INPUT VOLTAGE (V)
TEMPERATURE (°C)
TEMPERATURE (°C)
ZERO-CURRENT DETECTION
THRESHOLD vs. TEMPERATURE
FOLDBACK CURRENT-LIMIT
THRESHOLD vs. OUTPUT VOLTAGE
300
250
200
150
100
50
5
4
3
2
1
0
0
0
10
20
30
- V (V)
40
50
-40
-15
10
35
60
85
V
TEMPERATURE (°C)
OUT
EE
_______________________________________________________________________________________
7
Quad Network Power Controller
for Power-Over-LAN
Typical Operating Characteristics (continued)
(V
= -48V, V
= +3.3V, AUTO = AGND = DGND = 0, RESET = SHD_ = unconnected, R
= 0.5Ω, T = +25°C,
SENSE A
EE
DD
all registers = default setting, unless otherwise noted.)
OVERCURRENT TIMEOUT
OVERCURRENT RESPONSE WAVEFORM
(R = 240Ω TO 57Ω)
(R
LOAD
= 240Ω TO 57Ω)
LOAD
MAX5935 toc12
MAX5935 toc13
(AGND - OUT)
20V/div
(AGND - OUT)
20V/div
I
OUT
200mA/div
0V
0V
I
OUT
0A
200mA/div
GATE
10V/div
0A
GATE 10V/div
V
EE
V
EE
INT
INT
2V/div
2V/div
0V
0V
20ms/div
400µs/div
SHORT-CIRCUIT RESPONSE TIME
SHORT-CIRCUIT RESPONSE TIME
MAX5935 toc15
MAX5935 toc14
(AGND - OUT)
20V/div
(AGND - OUT)
20V/div
0V
0V
I
OUT
I
OUT
5A/div
250mA/div
0A
0A
GATE
10V/div
GATE
10V/div
V
V
EE
EE
20ms/div
4µs/div
RESET TO OUTPUT TURN-OFF DELAY
ZERO-CURRENT DETECTION WAVEFORM
MAX5935 toc16
MAX5935 toc17
RESET
0V
(AGND - OUT)
20V/div
I
OUT
0V
200mA/div
0A
I
OUT
200mA/div
(AGND - OUT)
20V/div
GATE
10V/div
GATE
INT
5V/div
10V/div
V
EE
100µs/div
100ms/div
8
_______________________________________________________________________________________
Quad Network Power Controller
for Power-Over-LAN
Typical Operating Characteristics (continued)
(V
= -48V, V
= +3.3V, AUTO = AGND = DGND = 0, RESET = SHD_ = unconnected, R
= 0.5Ω, T = +25°C,
EE
DD
SENSE
A
all registers = default setting, unless otherwise noted.)
STARTUP WITH VALID PD
(25kΩ AND 0.1µF)
OVERCURRENT RESTART DELAY
MAX5935 toc19
MAX5935 toc18
(AGND - OUT)
20V/div
(AGND - OUT)
20V/div
0V
0V
I
OUT
100mA/div
I
OUT
200mA/div
0A
GATE
GATE_
10V/div
V
V
EE
EE
100ms/div
400ms/div
DETECTION WITH INVALID PD
DETECTION WITH INVALID PD (15kΩ)
(25kΩ AND 10µF)
MAX5935 toc21
MAX5935 toc20
(AGND - OUT)
5V/div
0V
(AGND - OUT)
2V/div
0V
I
OUT
I
1mA/div
0A
OUT
1mA/div
100ms/div
40ms/div
STARTUP IN MIDSPAN MODE
WITH VALID PD (25kΩ AND 0.1µF)
DETECTION WITH INVALID PD (33kΩ)
MAX5935 toc23
MAX5935 toc22
(AGND - OUT)
20V/div
(AGND - OUT)
5V/div
0V
0V
I
OUT
100mA/div
I
OUT
1mA/div
0A
0A
GATE_
10V/div
V
EE
100ms/div
100ms/div
_______________________________________________________________________________________
9
Quad Network Power Controller
for Power-Over-LAN
Typical Operating Characteristics (continued)
(V
= -48V, V
= +3.3V, AUTO = AGND = DGND = 0, RESET = SHD_ = unconnected, R
= 0.5Ω, T = +25°C,
EE
DD
SENSE
A
all registers = default setting, unless otherwise noted.)
DETECTION WITH MIDSPAN MODE
DETECTION WITH MIDSPAN MODE
WITH INVALID PD (33kΩ)
WITH INVALID PD (15kΩ)
MAX5935 toc24
MAX5935 toc25
(AGND - OUT)
5V/div
(AGND - OUT)
5V/div
0V
0V
I
OUT
I
OUT
1mA/div
0A
1mA/div
0A
GATE_
10V/div
GATE_
10V/div
V
EE
V
EE
400ms/div
400ms/div
DETECTION WITH INVALID PD (OPEN CIRCUIT,
USING TYPICAL OPERATING CIRCUIT 1)
DETECTION WITH OUTPUT SHORTED
MAX5935 toc27
MAX5935 toc26
(AGND - OUT)
5V/div
(AGND - OUT)
5V/div
0V
0V
I
OUT
1mA/div
I
OUT
1mA/div
0A
0A
GATE_
GATE_
10V/div
10V/div
V
V
EE
EE
100ms/div
40ms/div
DETECTION WITH INVALID PD (OPEN CIRCUIT,
USING TYPICAL OPERATING CIRCUIT 2)
STARTUP WITH DIFFERENT PD CLASSES
MAX5935 toc28
MAX5935 toc29
(AGND-OUT)
5V/div
(AGND - OUT)
5V/div
CLASS4
I
OUT
CLASS3
CLASS2
2mA/div
GATE_
10V/div
0V
CLASS1
CLASS0
I
OUT
10mA/div
100ms/div
40ms/div
10 ______________________________________________________________________________________
Quad Network Power Controller
for Power-Over-LAN
Pin Description
PIN
NAME
FUNCTION
Hardware Reset. Pull RESET low for at least 300µs to reset the device. All internal registers reset to
1
RESET
their default value. The address (A0–A3), and AUTO and MIDSPAN input logic levels latch on during
low-to-high transition of RESET. Internally pulled up to V
with a 50kΩ resistor.
DD
MIDSPAN Mode Input. An internal 50kΩ pulldown resistor to DGND sets the default mode to endpoint
PSE operation (power-over-signal pairs). Pull MIDSPAN TO VDIG to set MIDSPAN operation. The
MIDSPAN value latches after the IC is powered up or reset (see the PD Detection section).
2
3
MIDSPAN
Open-Drain Interrupt Output. INT goes low whenever a fault condition exists. Reset the fault condition
using software or by pulling RESET low (see the Interrupt section of the Detailed Description for more
information about interrupt management).
INT
4
5
SCL
Serial Interface Clock Line
Serial Output Data Line. Connect the data line optocoupler input to SDAOUT (see the Typical
Application Circuit). Connect SDAOUT to SDAIN if using a 2-wire I2C-compatible system.
SDAOUT
Serial Interface Input Data Line. Connect the data line optocoupler output SDAIN (see the Typical
Application Circuit). Connect SDAIN to SDAOUT if using a 2-wire wire I2C-compatible system.
6
SDAIN
Address Bit. A3, A2, A1, and A0 form the lower part of the device’s address. Address inputs default
7–10
A3, A2, A1, A0
high with an internal 50kΩ pullup resistor to V . The address values latch when V
or V ramps
EE
DD
DD
up and exceeds its UVLO threshold or after a reset. The 3 MSB bits of the address are set to 010.
Detection and Classification Voltage Output. Use DET1 to set the detection and classification probe
voltages on port 1. Use DET1 for the AC voltage sensing of port 1 when using the AC disconnect
scheme (see the Typical Application Circuit).
DET1, DET2,
DET3, DET4
11–14
15
16
DGND
Connect to Digital Ground
V
Positive Digital Supply. Connect to digital supply (referenced to DGND).
DD
SHD1, SHD2,
SHD3, SHD4
Port Shutdown Input. Pull SHD_ low to turn-off the external FET on port_. Internally pulled up to V
with a 50kΩ resistor.
DD
17–20
21
AGND
Analog Ground. Connect to the high-side analog supply.
22, 25, SENSE4, SENSE3, MOSFET Source Current-Sense Negative Input. Connect to the source of the power MOSFET and
29, 32 SENSE2, SENSE1 connect a current-sense resistor between SENSE_ and V (see the Typical Application Circuit).
EE
23, 26,
30, 33
GATE4, GATE3, Port_ MOSFET Gate Driver. Connect GATE_ to the gate of the external FET (see the Typical
GATE2, GATE1
Application Circuit).
MOSFET Drain-Output Voltage Sense. Connect OUT_ to the power MOSFET drain through a resistor
(100Ω to 100kΩ). The low leakage at OUT_ limits the drop across the resistor to less than 100mV
(see the Typical Application Circuit).
24, 27,
31, 34
OUT4, OUT3,
OUT2, OUT1
Low-Side Analog Supply Input. Connect the low-side analog supply to V (-48V). Bypass with a 1µF
EE
28
V
EE
capacitor between AGND and V
.
EE
AUTO or SHUTDOWN Mode Input. Force high to enter AUTO mode after a reset or power-up. Drive
low to put the MAX5935 into SHUTDOWN mode. In SHUTDOWN mode, software controls the
operational modes of the MAX5935. A 50kΩ internal pulldown resistor defaults AUTO low. AUTO
35
AUTO
latches when V
or V ramps up and exceeds its UVLO threshold or when the device resets.
DD
EE
Software commands can take the MAX5935 out of AUTO while AUTO is high.
Oscillator Input. AC-disconnect detection function uses OSC_IN. Connect a 100Hz 10ꢀ, 2V
5ꢀ, +1.2V offset sine wave to OSC_IN. If the oscillator positive peak falls below OSC_FAIL
threshold of 2V, the ports that have the AC function enabled shut down and are not allowed to power
up. When not using the AC-disconnect detection function, leave OSC_IN unconnected.
P-P
36
OSC_IN
______________________________________________________________________________________ 11
Quad Network Power Controller
for Power-Over-LAN
V
DD
SCL SDAIN SDAOUT
SHD_
OSC_IN DGND
CURRENT SENSING
VOLTAGE PROBING
AND
DET_
OUT_
OSCILLATOR
MONITOR
SERIAL
PORT
INTERFACE
(SPI)
CURRENT-LIMIT
CONTROL
A0
A1
DETECTION/
CLASSIFICATION
SM
9-BIT ADC
CONVERTER
VOLTAGE
SENSING
10V
ACD_ENABLE
PORT
STATE
MACHINE
(SM)
A2
REGISTER FILE
50µA
A = 3
A3
GATE_
AUTO
MIDSPAN
RESET
PWR_EN
13V CLAMP
AC DISCONNECT
SIGNAL
CENTRAL LOGIC UNIT
(CLU)
AC
DETECTION
(ACD)
FAST
DISCHARGE
CONTROL
100mA
MAX
90µA
ACD
INT
REFERENCE
CURRENT
SENSE_
AGND
ANALOG
BIAS/
SUPPLY
MONITOR
+10V ANALOG
+5V DIG
CURRENT
LIMIT (ILIM)
CURRENT-LIMIT
DETECTOR
V
EE
VOLTAGE
REFERENCES
CURRENT
REFERENCES
OPEN CIRCUIT
(OC)
OVERCURRENT
(OVC)
FOLDBACK
CONTROL
4mV
182mV
212mV
MAX5935
Figure 1. MAX5935 Functional Diagram
other necessary functions for an IEEE 802.3af-compli-
ant PSE. The MAX5935 can be used in either endpoint
PSE (LAN Switch/Router) or midspan PSE (Power
Injector) applications.
Detailed Description
The MAX5935 four-port network power controller con-
trols -32V to -60V negative supply rail systems. Use the
MAX5935, which is compliant with the IEEE 802.3af
standard for power-sourcing equipment (PSE) in
power-over-LAN applications. The MAX5935 provides
Power Device (PD) discovery, classification, current
limit, both DC and AC load disconnect detections, and
The MAX5935 is fully software-configurable and pro-
grammable with more than 25 internal registers. The
device features an I2C-compatible, 3-wire serial inter-
face and a class-over-current detection. The class-
12 ______________________________________________________________________________________
Quad Network Power Controller
for Power-Over-LAN
over-current detection function enables system power
Port Reset (R1Ah[3:0])
Set high anytime during normal operation to turn off
power and clear the events and status registers of the
corresponding port. Port reset only resets the events
and status registers.
management where it detects a PD that draws more
current than the allowable amount for its class. The
MAX5935’s extensive programmability enhances sys-
tem flexibility and allows for uses in other applications.
The MAX5935 has four different operating modes: auto
mode, semi-auto mode, manual mode, and shutdown
mode (see the Operation Modes section). A special
Watchdog feature allows the hardware to gracefully
take over control if the software/firmware crashes. A
cadence timing feature allows the MAX5935 to be used
in midspan systems.
Operation Modes
The MAX5935 contains four independent but identical
state machines to provide reliable and real-time control
of the four network ports. Each state machine has four
different operating modes: auto, semi-auto, manual,
and shutdown. Auto mode allows the device to operate
automatically without any software supervision. Semi-
auto mode, upon request, continuously detects and
classifies a device connected to a port but does not
power up that port until instructed by software. Manual
mode allows total software control of the device and is
useful in system diagnostic. Shutdown mode terminates
all activities and securely turns off power to the ports.
Switching between AUTO, SEMI, or MANUAL mode
does not take effect until the part finishes its current
task. When the port is set into SHUTDOWN mode, all
the port operations are immediately stopped and the
port remains idle until SHUTDOWN is exited.
The MAX5935 provides input undervoltage lockout,
input undervoltage detection, input overvoltage lockout,
overtemperature protection, output voltage slew-rate
limit during startup, power-good status, and fault sta-
tus. The MAX5935’s programmability includes gate-
charging current, current-limit threshold, startup
timeout, overcurrent timeout, autorestart duty cycle,
PD-disconnect AC-detection threshold, and PD-discon-
nect detection timeout.
The MAX5935 communicates with the system micro-
controller through an I2C-compatible interface. The
MAX5935 features separate input and output data lines
(SDAIN and SDAOUT) for use with optocoupler isola-
tion. The MAX5935 is a slave device. Its four address
inputs allow 16 unique MAX5935 addresses. A sepa-
rate INT output and four independent shutdown inputs
(SHD_) allow fast interrupt signals between the
MAX5935 and the microcontroller. A RESET input
allows hardware reset of the device.
Automatic (AUTO) Mode
Enter automatic (AUTO) mode by forcing the AUTO
input high prior to a reset, or by setting R12h[P_
M1,P_M0] to [1,1] during normal operation (see Tables
15 and 15a). In AUTO mode, the MAX5935 performs
detection and classification, and powers up the port
automatically once a valid power device (PD) is detect-
ed at the port. If a valid PD is not connected at the port,
the MAX5935 repeats the detection routine continuous-
ly until a valid PD is connected.
Reset
Reset is a condition the MAX5935 enters following any
of the following conditions:
Going into AUTO mode, the DET_EN and CLASS_EN
bits are set to high and stay high unless changed by
software. Using software to set DET_EN and/or
CLASS_EN low causes the MAX5935 to skip detection
and/or classification. As a protection, disabling the
Detection routine in AUTO mode will not allow the cor-
responding port to power up, unless the DET_BYP
(R23H[4]) is set to 1.
•
•
•
•
After power-up (V and V
EE
rise above their UVLO
DD
thresholds)
Hardware reset. The RESET input is driven low and
up high again any time after power-up.
Software reset. Writing a 1 into R1Ah[4] any time
after power-up.
Thermal shutdown
The AUTO status is latched into the register only during
a reset. Any changes to the AUTO input after reset is
ignored.
During a reset, the MAX5935 resets its register map to
the Reset state as shown in Table 30 and latches in the
state of AUTO (pin 35) and MIDSPAN (pin 2). During
normal operation, changes at the AUTO and MIDSPAN
inputs are ignored. While the condition that caused the
reset persists (i.e., high temperature, RESET input low
or UVLO conditions), the MAX5935 will not acknowl-
edge any addressing from the serial interface.
Semi-Automatic (SEMI) Mode
Enter semi-automatic (SEMI) mode by setting
R12h[P_M1,P_M0] to [1,0] during normal operation
(see Tables 15 and 15a). In SEMI mode, the MAX5935,
upon request, performs detection and/or classification
repeatedly but does not power up the port(s), regard-
less of the status of the port connection.
______________________________________________________________________________________ 13
Quad Network Power Controller
for Power-Over-LAN
Setting R19h[PWR_ON_] (Table 21) high immediately
terminates detection/classification routines and turns on
power to the port(s).
PD Detection
When PD detection is activated, the MAX5935 probes
the output for a valid PD. After each detection cycle,
the device sets the DET_END_ bit R04h/05h[3:0] high
and reports the detection results in the status registers
R0Ch[2:0], R0Dh[2:0], R0Eh[2:0], and R0Fh[2:0]. The
DET_END_ bit is reset to low when read through R05h
or after a port reset. Both DET_END_bit status registers
are cleared after the port powers down.
R14h[DET_EN_, CLASS_EN_] default to low in SEMI
mode. Use software to set R14h[DET_EN_,
CLASS_EN_] to high to start the detection and/or classi-
fication routines. R14h[DET_EN_, CLASS_EN_] are
reset every time the software commands a power-off of
the port (either through reset or PWR_OFF). In any other
cases, the status of the bits is left unchanged (including
when the state machine turns off the power because a
load disconnect or a fault condition is encountered).
A valid PD has a 25kΩ discovery signature characteris-
tic as specified in the IEEE 802.3af standard. Table 1
shows the IEEE 802.3af specification for a PSE detect-
ing a valid PD signature (see the Typical Application
Circuit and Figure 2). The MAX5935 can probe and cat-
egorize different types of devices connected to the port
such as a valid PD, an open circuit, a low resistive load,
a high resistive load, a high capacitive load, a positive
DC supply, or a negative DC supply.
MANUAL Mode
Enter MANUAL mode by setting R12h[P_M1,P_M0] to
[0,1] during normal operation (see Tables 15 and 15a).
MANUAL mode allows the software to dictate any
sequence of operation. Write a 1 to both R14h[DET_
EN_] and R14h[CLASS_EN_] start detection and classi-
fication operations, respectively and in that priority
order. After execution, the command is cleared from
the register(s). PWR_ON_ has highest priority. Setting
PWR_ON_ high at any time causes the device to enter
the powered mode immediately. Setting DET_EN and
CLASS_EN high at the same time causes detection to
be performed first. Once in the powered state, the
device ignores DET_EN_ or CLASS_EN_ commands.
During detection, the MAX5935 turns off the external
MOSFET and forces two probe voltages through the
DET_ input. The current through the DET_ input is mea-
sured as well as the voltage at OUT_. A two-point slope
measurement is used as specified by the IEEE 802.3af
standard to verify the device connected to the port. The
MAX5935 implements appropriate settling times and a
100ms digital integration to reject 50Hz/60Hz power-
line noise coupling.
When switching to MANUAL mode from another mode,
DET_EN_, CLASS_EN_ default to low. These bits
become “pushbutton” rather than configuration bits
(i.e., writing ones to these bits while in MANUAL mode
commands the device to execute one cycle of detec-
tion and/or classification. The bits are reset back to
zeros at the end of the execution). Putting the MAX5935
into shutdown mode immediately turns off power and
halts all operations to the corresponding port. The
event and status bits of the affected port(s) are also
cleared. In SHUTDOWN mode, the DET_EN,
CLASS_EN, and PWR_ON commands are ignored.
An external diode, in series with the DET_ input,
restricts PD detection to the 1st quadrant as specified
by the IEEE 802.3af standard. To prevent damage to
non-PD devices and to protect itself from an output
short circuit, the MAX5935 limits the current into DET_
to less than 2mA maximum during PD detection.
In midspan mode, the MAX5935 waits 2.2s before
attempting another detection cycle after every failed
detection. The first detection, however, happens imme-
diately after issuing the detection command.
Power Device Classification
(PD Classification)
During the PD classification mode, the MAX5935 forces
a probe voltage (-18V) at DET_ and measures the cur-
rent into DET_. The measured current determines the
class of the PD.
In SHUTDOWN mode, the serial interface operates
normally.
Watchdog
R1Dh, R1Eh, and R1Fh registers control Watchdog oper-
ation. The Watchdog function, when enabled, allows the
MAX5935 to gracefully take over control or securely shut
down the power to the ports in case of software/firmware
crashes. Contact the factory for more details.
After each classification cycle, the device sets the
CL_END_ bit (R04h/05h[7:4]) high and reports the clas-
sification results in the status registers R0Ch[6:4],
R0Dh[6:4], R0Eh[6:4], and R0Fh[6:4]. The CL_END_ bit
is reset to low when read through register R05h or after
a port reset. Both Class_END_bit status registers are
cleared after the port powers down.
14 ______________________________________________________________________________________
Quad Network Power Controller
for Power-Over-LAN
Table 1. PSE PI Detection Modes Electrical Requirement
(Table 33-2 of the IEEE 802.3af Standard)
PARAMETER
Open-Circuit Voltage
Short-Circuit Current
Valid Test Voltage
SYMBOL
MIN
—
MAX
30
UNITS
ADDITIONAL INFORMATION
In detection mode only.
V
V
mA
V
OC
SC
I
—
5
In detection mode only.
V
2.8
10
VALID
Voltage Difference Between
Test Points
∆V
1
2
—
—
V
TEST
Time Between Any Two Test
Points
t
ms
This timing implies a 500Hz maximum probing frequency.
BP
Slew Rate
V
—
19
0.1
26.5
> 33
—
V/µs
kΩ
SLEW
Accept Signature Resistance
Reject Signature Resistance
Open-Circuit Resistance
R
GOOD
R
< 15
500
kΩ
BAD
R
kΩ
OPEN
Accept Signature
Capacitance
C
—
10
0
150
—
nF
µF
V
GOOD
Reject Signature
Capacitance
C
BAD
Signature Offset Voltage
Tolerance
V
2.0
12
OS
Signature Offset Current
Tolerance
I
0
µA
OS
checks if any other port is not turning on and if the
timer is zero. Another check is performed if the
ACD_EN bit is set; in this case, the OSC_FAIL bit must
be low (oscillator is okay) for the port to be powered.
Table 2. PSE Classification of a PD
(Table 33.4 of the IEEE 802.3af Standard)
t
FAULT
MEASURED I
(mA)
CLASSIFICATION
Class 0
CLASS
If these conditions are met, then the part enters startup
where it turns on power to the port. An internal signal,
0 to 5
> 5 and < 8
8 to 13
May be Class 0 and 1
Class 1
POK_, is asserted high when V
is within 2V from
OUT
V
. PGOOD_ status bits are set high if POK_ stays
EE
> 13 and < 16
16 to 21
May be Class 0, 1, or 2
Class 2
high longer than t
. PGOOD immediately resets
PGOOD
when POK goes low.
The PWR_CHG bit sets when a port powers up or down.
PWR_EN sets when a port powers up and resets when a
port shuts down. The port shutdown timer lasts 0.5ms
and prevents other ports from turning off during that peri-
od, except in the case of emergency shutdowns (RESET
> 21 and < 25
25 to 31
May be Class 0, 2, or 3
Class 3
> 31 and <35
35 to 45
May be Class 0, 3, or 4
Class 4
= L, RESET_IC = H, V
, V
, and TSHD).
> 45 and < 51
May be Class 0 or 4
EEUVLO DDUVLO
The MAX5935 always checks the status of all ports before
turning off. A priority logic system determines the order to
prevent the simultaneous turn-on or turn-off of the ports.
The port with the lesser ordinal number gets priority over
the others (i.e., Port 1 turns on first, Port 2 second, Port 3
third and Port 4 fourth). Setting PWR_OFF_ high turns off
power to the corresponding port.
Table 2 shows the IEEE 802.3af requirement for a PSE
classifying a PD at the Power Interface (PI).
Powered State
When the part enters PWR MODE, the t
and t
DISC
START
timers are reset. Before turning on the power, the part
______________________________________________________________________________________ 15
Quad Network Power Controller
for Power-Over-LAN
Overcurrent Protection
A sense resistor (R ), connected between SENSE_ and
EE
150ms
150ms
21.3ms
80ms
S
0V
V
, monitors the load current. Under all circum-
t
t
t
CLASS
DETI
DETII
t
stances, the voltage across R never exceeds the
S
threshold V
. If SENSE_ exceeds V
, an
SU_LIM
SU_LIM
0V
internal current-limiting circuit regulates the GATE volt-
age, limiting the current to I = V / R . During
LIM
SU_LIM
S
transient conditions, if the SENSE_ voltage exceeds
, a fast pulldown circuit activates in order to
-4V
-9V
V
SU_LIM
quickly recover from the current overshoot. During
startup, if the current-limit condition persists, when the
startup timer, t
, times out, the port shuts off and
START
the STRT_FLT_ bit is set. In the normal powered state,
the MAX5935 checks for overcurrent conditions as
determined by V
FAULT
overcurrent period. The t
= ~88ꢀ of V
. The
SU_LIM
FLT_LIM
OUT_
t
counter sets the maximum-allowed continuous
counter increases when
FAULT
V
exceeds V
and decreases at a slower
SENSE
pace when V
FLT_LIM
-18V
drops below V
. A slower
FLT_LIM
SENSE
decrement for the t
counter allows for detecting
FAULT
repeated short-duration overcurrents. When the counter
reaches the t limit, the MAX5935 powers off the
FAULT
port and asserts the IMAX_FLT_ bit. For a continuous
overstress, a fault latches exactly after a period of
-48V
t
t
. V
, is programmable using R27h[4-7].
SU_LIM
FAULT
FAULT
is programmable using R16h[2-3] and R28[4-7].
Figure 2. Detection, Classification, and Power-Up Port
Sequence
After power-off due to an overcurrent fault, and if the
RSTR_EN bit is set, the t timer is not immediately
FAULT
reset but starts decrementing at the same slower pace.
The MAX5935 allows the port to be powered on only
when the t
counter is at zero. This feature sets an
FAULT
automatic duty-cycle protection to the external MOSFET
to avoid overheating. The duty cycle is programmable
using R16h[6-7].
t
PGOOD
POK
The MAX5935 continuously flags when the current
exceeds the maximum current allowed for the class as
indicated in the CLASS status register. When class
overcurrent occurs, the MAX5935 sets the IVC bit in
register R09h.
Foldback Current
During startup and normal operation, an internal circuit
senses the voltage at OUT_ and reduces the current-
PGOOD
limit value when (V
_ - V ) > 30V. The foldback
EE
OUT
function helps to reduce the power dissipation on the
FET. The current limit eventually reduces to 1/3 of I
LIM
when (V
_ - V ) > 50V (see Figure 4).
EE
OUT
Figure 3. PGOOD Timing
16 ______________________________________________________________________________________
Quad Network Power Controller
for Power-Over-LAN
digital supply for compatibility with the internal logic.
(V
- V )
EE
SENSE_
The MAX5935 also features a V
undervoltage lockout
condition keeps the
DD
DDUVLO
(V
) of +1.35V. A V
DDUVLO
V
SU_LIM
MAX5935 in reset and the ports shut off. Bit 0 in the
supply event register shows the status of V
DDUVLO
(Table 11) after V
has recovered. All logic inputs and
DD
outputs reference to DGND. DGND and AGND are
completely isolated internally to the MAX5935. In a
completely isolated system, the digital signal can be
referenced indifferently to V
or V or at voltages
EE
AGND
V
/ 3
SU_LIM
even higher than AGND (up to 60V). V
- V
must
DGND
DD
be greater than 3.0V when V
≤ (V + 3.0V)
DGND
EE
When using the AC disconnect-detection feature,
AGND must be connected directly to DGND and V
30V
50V
(V
- V )
EE
OUT_
DD
must be greater than +3V. In this configuration, con-
nect DGND to AGND at a single point in the system as
close to MAX5935 as possible.
Figure 4. Foldback Current Characteristics
MOSFET Gate Driver
Connect the gate of the external n-channel MOSFET to
GATE_. An internal 50µA current source pulls GATE_ to
Hardware Shutdown
SHD_ shuts down the respective ports without using
the serial interface. Hardware shutdown offers an emer-
gency turn-off feature that allows a fast disconnect of
the power supply from the port. Pull SHD_ low to
remove power.
(V + 10V) to turn on the MOSFET. An internal 40µA
EE
current source pulls down GATE_ to V to turn off the
EE
MOSFET.
The pullup and pulldown current controls the maximum
slew rate at the output during turn-on or turn-off. The
pullup current (gate-charging current) is programmable
using R23h[5-7]. Use the following equation to set the
maximum slew rate:
Interrupt
The MAX5935 contains an open-drain logic output (INT)
that goes low when an interrupt condition exists. R00h
and R01h (Tables 5 and 6) contain the definitions of the
interrupt registers. The mask register R01h determines
events that trigger an interrupt. As a response to an
interrupt, the controller reads the status of the event reg-
ister to determine the cause of the interrupt and takes
subsequent actions. Each interrupt event register also
contains a clear-on-read (CoR) register. Reading
through the CoR register address clears the interrupt.
INT remains low when reading the interrupt through the
read-only addresses. For example, to clear a startup
fault on port 4 read address 09h (see Table 10). Use the
global pushbutton bit on register 1Ah (bit 7, Table 22) to
clear interrupts, or use a software or hardware reset.
∆V
I
GATE
OUT
=
∆t
C
GD
where C
is the total capacitance between GATE and
GD
DRAIN of the external FET. Current limit and the capac-
itive load at the drain control the slew rate during start-
up. During current-limit regulation, the MAX5935
manipulates the GATE_ voltage to control the voltage at
SENSE_. A fast pulldown activates if SENSE_ over-
shoots the limit threshold. The fast pulldown current
increases with the amount of overshoot. The maximum
fast pulldown current is 100mA.
Undervoltage and Overvoltage Protection
The MAX5935 contains several undervoltage and over-
voltage protection features. Table 11 in the Register Map
and Description section shows a detailed list of the
undervoltage and overvoltage protection features. An
During turn-off when the GATE voltage reaches a value
lower than 1.2V, a strong pulldown switch is activated
to keep the FET securely off.
internal V
undervoltage-lockout (V
) circuit
EEUVLO
EE
Digital Logic
supplies power for the internal logic circuitry. V
DD
keeps the MOSFET off and the MAX5935 in reset until
V
DD
V
V
- V exceeds 29V for more than 3ms. An internal
EE
AGND
ranges from +1.71V to +3.7V and determines the logic
thresholds for the CMOS connections (SDAIN,
SDAOUT, SCL, AUTO, SHD_, A_). This voltage range
enables the MAX5935 to interface with a nonisolated
low-voltage microcontroller. The MAX5935 checks the
overvoltage (V
) circuit shuts down the ports
EE_OV
- V ) exceeds 60V. The digital supply also
EE
EE
when (V
AGND
contains an undervoltage lockout (V
).
DDUVLO
______________________________________________________________________________________ 17
Quad Network Power Controller
for Power-Over-LAN
The MAX5935 also features three other undervoltage
Table 3. MAX5935 Address
and overvoltage interrupts: V undervoltage interrupt
EE
0
1
0
A3
A2
A1
A0
R/W
(V
), V
undervoltage interrupt (V
), and V
DDUV DD
EEUV
DD
overvoltage interrupt (V
). A fault latches into the
DDOV
supply events register (Table 11), but the MAX5935
does not shut down the ports with a V , V , or
DDOV
Thermal Shutdown
EEUV DDUV
If the MAX5935 die temperature reaches +150°C, an
overtemperature fault generates and the MAX5935
shuts down and the MOSFETs turn off. The die temper-
ature of the MAX5935 must cool down below +130°C to
remove the overtemperature fault condition. After a
thermal shutdown, the part is reset.
V
.
DC Disconnect Monitoring
Setting R13h[DCD_EN_] bits high enables DC load
monitoring during normal powered state. If SENSE_
falls below the DC load disconnect threshold, V
,
DCTH
for more than t
, the device turns off power and
DISC
Address Inputs
A3, A2, A1, and A0 represent the four LSBs of the chip
address, the complete seven bits chip address (see
Table 3).
asserts the LD_DISC_ bit of the corresponding port.
t
is programmable using R16h[0-1] and R27h[0-3].
DISC
AC Disconnect Monitoring
The MAX5935 features AC load disconnect monitoring.
Connect an external sine wave to OSC_IN. The oscilla-
tor requirements are:
The four LSBs latch on the low-to-high transition of
RESET or after a power-supply start (either on V
or
DD
V
). Address inputs default high through an internal
EE
•
•
•
•
Frequency x V
= 200V
x Hz 15ꢀ
P-P
P-P
50kΩ pullup resistor to V . The MAX5935 also
DD
responds to the call through a global address 60h (see
the Global Addressing and Alert Response Protocol
section).
Positive peak voltage > +2V
Frequency > 60Hz
A 100Hz 10ꢀ, 2V
5ꢀ, with +1.2V offset
P-P
2
I C-Compatible Serial Interface
(V
= +2.2V, typ) is recommended.
PEAK
The MAX5935 operates as a slave that sends and
receives data through an I2C-compatible, 2-wire or 3-
wire interface. The interface uses a serial data input line
(SDAIN), a serial data output line (SDAOUT) and a seri-
al clock line (SCL) to achieve bidirectional communica-
tion between master(s) and slave(s). A master (typically
a microcontroller) initiates all data transfers to and from
the MAX5935, and generates the SCL clock that syn-
chronizes the data transfer. In most applications, con-
nect the SDAIN and the SDAOUT lines together to form
the serial data line (SDA).
The MAX5935 buffers and amplifies 3x the external
oscillator signal and sends the signal to DET_, where
the sine wave is AC-coupled to the output. The
MAX5935 senses the presence of the load by monitor-
ing the amplitude of the AC current returned to DET_
(see the Functional Diagram).
Setting R13h[ACD_EN_] bits high enable AC load dis-
connect monitoring during the normal powered state. If
the AC current peak at the DET_ pin falls below I
ACTH
for more than t
, the device turns off power and
DISC
asserts the LD_DISC_ bit of the corresponding port.
is programmable using R23h[0-3].
Using the separate input and output data lines allows
optocoupling with the controller bus when an isolated
supply powers the microcontroller.
I
ACTH
An internal comparator checks for a proper amplitude
of the oscillator input. If the positive peak of the input
sinusoid falls below a safety value of 2V, OSC_FAIL
sets and the port shuts down. Power cannot be applied
to the ports when ACD_EN is set high and OSC_FAIL is
set high. Leave OSC_IN unconnected or connect it to
DGND when not using AC disconnect detection.
The MAX5935 SDAIN line operates as input. The
MAX5935 SDAOUT operates as an open-drain output.
A pullup resistor, typically 4.7kΩ, is required on
SDAOUT. The MAX5935 SCL line operates only as an
input. A pullup resistor, typically 4.7kΩ, is required on
SCL if there are multiple masters, or if the master in a
single-master system has an open-drain SCL output.
When using the AC disconnect detection feature, con-
nect AGND directly to DNGD as close as possible to
Serial Addressing
Each transmission consists of a START condition (Figure
7) sent by a master, followed by the MAX5935 7-bit slave
address plus R/W bit, a register address byte, one or
more data bytes, and finally a STOP condition.
the IC. The MAX5935 also requires a V
of greater
DD
than +3V for this function. See the Typical Application
Circuit with AC disconnect for other external compo-
nent requirements.
18 ______________________________________________________________________________________
Quad Network Power Controller
for Power-Over-LAN
SDAIN
t
BUF
t
t
SU, DAT
SU, STA
t
HD, STA
t
LOW
t
t
SU, STO
HD, DAT
SCL
t
HIGH
t
HD, STA
t
t
F
R
START CONDITION
REPEATED START CONDITION
STOP
START
CONDITION
CONDITION
Figure 5. 2-Wire Serial Interface Timing Details
SDAIN/SDA
t
BUF
t
t
SU, DAT
SU, STA
t
HD, STA
t
LOW
t
t
SU, STO
HD, DAT
SCL
t
HIGH
t
HD, STA
t
t
F
R
START CONDITION
REPEATED START CONDITION
STOP
START
CONDITION
CONDITION
Figure 6. 3-Wire Serial Interface Timing Details
SDA
SCL
SDA/
SDAIN
SCL
S
P
.
START
STOP
DATA LINE STABLE; CHANGE OF
DATA VALID
DATA ALLOWED
Figure 7. Start and Stop Conditions
Figure 8. Bit Transfer
Start and Stop Conditions
Both SCL and SDA remain high when the interface is
not busy. A master signals the beginning of a transmis-
sion with a START (S) condition by transitioning SDA
from high to low while SCL is high. When the master fin-
ishes communicating with the slave, the master issues
a STOP (P) condition by transitioning SDA from low to
high while SCL is high. The stop condition frees the bus
for another transmission.
______________________________________________________________________________________ 19
Quad Network Power Controller
for Power-Over-LAN
CLOCK PULSE FOR ACKNOWLEDGEMENT
START CONDITION
1
2
8
9
SCL
SDA
BY TRANSMITTER
S
SDA
BY RECEIVER
Figure 9. Acknowledge
MSB
LSB
A0
0
SDA
SCL
1
0
A3
A2
A1
R/W
ACK
Figure 10. Slave Address
Bit Transfer
and A0 latch in upon the reset of the MAX5935 into reg-
ister R11h. The MAX5935 monitors the bus continuous-
ly, waiting for a START condition followed by the
MAX5935’s slave address. When the MAX5935 recog-
nizes its slave address, it acknowledges and is then
ready for continued communication.
Each clock pulse transfers one data bit (Figure 8). The
data on SDA must remain stable while SCL is high.
Acknowledge
The acknowledge bit is a clocked 9th bit (Figure 9),
which the recipient uses as a handshake receipt of each
byte of data. Thus, each byte effectively transferred
requires 9 bits. The master generates the 9th clock
pulse, and the recipient pulls down SDA (or the SDAOUT
in the 3-wire interface) during the acknowledge clock
pulse, such that the SDA line is stable low during the
high period of the clock pulse. When the master trans-
mits to the MAX5935, the MAX5935 generates the
acknowledge bit. When the MAX5935 transmits to the
master, the master generates the acknowledge bit.
Global Addressing and Alert Response Protocol
The global address call is used in writing mode to write
the same register to multiple devices (address 0x60). In
read mode (address 0x61), the global address call is
used as the Alert Response address. When responding
to a global call, the MAX5935 puts out on the data line its
own address whenever its interrupt is active and so does
every other device connected to the SDAOUT line that
has an active interrupt. After every bit is transmitted, the
MAX5935 checks that the data line effectively corre-
sponds to the data it is delivering. If it is not, it then backs
off and frees the data line. This litigation protocol always
allows the part with the lowest address to complete the
transmission. The microcontroller can then respond to
the interrupt and take proper actions. The MAX5935
does not reset its own interrupt at the end of the Alert
Response protocol. The microcontroller has to do it by
clearing the event register through their CoR addresses
or activating the CLR_INT pushbutton.
Slave Address
The MAX5935 has a 7-bit long slave address (Figure
10). The bit following the 7-bit slave address (bit eight)
is the R/W bit, which is low for a write command and
high for a read command.
010 always represent the first three bits (MSBs) of the
MAX5935 slave address. Slave address bits A3, A2,
A1, and A0 represent the states of the MAX5935’s A3,
A2, A1, and A0 inputs, allowing up to sixteen MAX5935
devices to share the bus. The states of the A3, A2, A1,
20 ______________________________________________________________________________________
Quad Network Power Controller
for Power-Over-LAN
CONTROL BYTE IS STORED ON RECEIPT OF STOP CONDITION
ACKNOWLEDGE FROM MAX5935
D15 D14 D13 D12 D11 D10 D9
D8
S
SLAVE ADDRESS
0
A
CONTROL BYTE
ACKNOWLEDGE FROM MAX5935
A
P
R/W
Figure 11. Control Byte Received
ACKNOWLEDGE FROM MAX5935
D15 D14 D13 D12 D11 D10 D9 D8
ACKNOWLEDGE FROM MAX5935
HOW CONTROL BYTE AND DATA BYTE MAP
D7 D6 D5 D4 D3 D2 D1 D0
INTO THE REGISTER
ACKNOWLEDGE FROM MAX5935
S
SLAVE ADDRESS
0
A
CONTROL BYTE
A
DATA BYTE
1 BYTE
A
P
R/W
AUTO-INCREMENT
MEMORY WORD ADDRESS
Figure 12. Control and Single Data Byte Received
ACKNOWLEDGE FROM MAX5935
ACKNOWLEDGE FROM MAX5935
HOW CONTROL BYTE AND DATA BYTE MAP
INTO THE REGISTER
D15 D14 D13 D12 D11 D10 D9 D8
D7 D6 D5 D4 D3 D2 D1 D0
ACKNOWLEDGE FROM MAX5935
S
SLAVE ADDRESS
0
A
CONTROL BYTE
A
DATA BYTE
n BYTES
A
P
R/W
AUTO-INCREMENT
MEMORY WORD ADDRESS
Figure 13. ‘n’ Data Bytes Received
Message Format for Writing the MAX5935
A write to the MAX5935 comprises of the MAX5935’s
slave address transmission with the R/W bit set to 0, fol-
lowed by at least one byte of information. The first byte
of information is the command byte (Figure 11). The
command byte determines which register of the
MAX5935 is written to by the next byte, if received. If
the MAX5935 detects a STOP condition after receiving
the command byte, then the MAX5935 takes no further
action beyond storing the command byte. Any bytes
received after the command byte are data bytes. The
first data byte goes into the internal register of the
MAX5935 selected by the command byte. If the
MAX5935 transmits multiple data bytes before the
MAX5935 detects a STOP condition, these bytes store
in subsequent MAX5935 internal registers because the
control byte address auto-increments.
Any bytes received after the control byte are data
bytes. The first data byte goes into the internal register
of the MAX5935 selected by the control byte (Figure 8).
If multiple data bytes are transmitted before a STOP
condition is detected, these bytes are stored in subse-
quent MAX5935 internal registers because the control
byte address auto-increments.
______________________________________________________________________________________ 21
Quad Network Power Controller
for Power-Over-LAN
INT_EN (R17h[7]) is a global interrupt mask (Table 6).
Table 4. Auto-Increment Rules
The MASK_ bits activate the corresponding interrupt
bits in register R00h. Writing a 0 to INT_EN (R17h[7])
disables the INT output.
COMMAND BYTE
AUTO-INCREMENT BEHAVIOR
ADDRESS RANGE
A Reset sets R01h to AAA00A00b, where A is the state
of the AUTO input prior to the reset.
Command address will auto-
increment after byte read or written
0x00 to 0x26
The power event register (Table 7) records changes in
the power status of the four ports. Any change in
PGOOD_ (R10h[7:4]) sets PG_CHG_ to 1. Any change
in the PWR_EN_ (R10h[3:0]) sets PWEN_CHG_ to 1.
PG_CHG_ and PWEN_CHG_ trigger on the edges of
PGOOD_ and PWR_EN_ and do not depend on the
actual level of the bits. The power event register has
two addresses. When read through the R02h address,
the content of the register is left unchanged. When read
through the CoR R03h address, the register content will
be cleared. A Reset sets R02h/R03h = 00h.
Command address remains at 0x26
after byte written or read
0x26
Message Format for Reading
The MAX5935 reads using the MAX5935’s internally
stored command byte as an address pointer, the same
way the stored command byte is used as an address
pointer for a write. The pointer auto-increments after
reading each data byte using the same rules as for a
write. Thus, a read is initiated by first configuring the
MAX5935’s command byte by performing a write
(Figure 12). The master now reads “n” consecutive
bytes from the MAX5935, with the first data byte read
from the register addressed by the initialized command
byte (Figure 13). When performing read-after-write veri-
fication, remember to reset the command byte’s
address because the stored control byte address auto-
increments after the write.
DET_END_/CL_END_ is set high whenever detection/
classification is completed on the corresponding port.
A 1 in any of the CL_END_ bits forces R00h[4] to 1. A 1
in any of the DET_END_ bits forces R00h[3] to 1. As
with any of the other events register, the detect event
register (Table 8) has two addresses. When read
through the R04h address, the content of the register is
left unchanged. When read through the CoR R05h
address, the register content will be cleared. A Reset
sets R04h/R05h = 00h.
Operation with Multiple Masters
When the MAX5935 operates on a 2-wire interface with
multiple masters, a master reading the MAX5935
should use repeated starts between the write that sets
the MAX5935’s address pointer, and the read(s) that
takes the data from the location(s). It is possible for
master 2 to take over the bus after master 1 has set up
the MAX5935’s address pointer but before master 1
has read the data. If master 2 subsequently resets the
MAX5935’s address pointer, then master 1’s read may
be from an unexpected location.
LD_DISC_ is set high whenever the corresponding port
shuts down due to detection of load removal.
IMAX_FLT_ is set high when the port shuts down due to
an extended overcurrent event after a successful start-
up. A 1 in any of the LD_DISC_ bits forces R00h[2] to 1.
A 1 in any of the IMAX_FLT_ bits forces R00h[5] to 1.
As with any of the other events registers, the fault event
register (Table 9) has two addresses. When read
through the R06h address, the content of the register is
left unchanged. When read through the CoR R07h
address, the register content will be cleared. A reset
sets R06h/R07h = 00h.
Command Address Auto-Incrementing
Address auto-incrementing allows the MAX5935 to be
configured with fewer transmissions by minimizing the
number of times the command address needs to be
sent. The command address stored in the MAX5935
generally increments after each data byte is written or
read (Table 4). The MAX5935 is designed to prevent
overwrites on unavailable register addresses and unin-
tentional wraparound of addresses.
If the port remains in current limit or the PGOOD condi-
tion is not met at the end of the startup period, the port
shuts down and the corresponding STRT_FLT_ is set to
1. A 1 in any of the STRT_FLT_ bits forces R00h[6] to 1.
IVC_ is set to 1 whenever the port current exceeds the
maximum allowed limit for the class (determined during
the classification process). A 1 in any of IVC_ forces
R00h[6] to 1. When the CL_DISC (R17h[2]) is set to 1,
the port will also limit the load current according to its
class as specified in the Electrical Characteristics table.
As with any of the other events registers, the startup
event register (Table 10) has two addresses. When
Register Map And Description
The interrupt register (Table 5) summarizes the event
register status and is used to send an interrupt signal
(INT goes low) to the controller. Writing a 1 to R1Ah[7]
clears all interrupt and events registers. A Reset sets
R00h to 00h.
22 ______________________________________________________________________________________
Quad Network Power Controller
for Power-Over-LAN
Table 5. Interrupt Register
ADDRESS = 00h
DESCRIPTION
SYMBOL
BIT
R/W
Interrupt signal for supply faults. SUP_FLT is the logic OR of all the bits [7:0] in register R0Ah/R0Bh
(Table 8).
SUP_FLT
7
R
Interrupt signal for startup failures. TSRT_FLT is the logic OR of bits [7:0] in register R08h/R09h
(Table 7).
TSTR_FLT
IMAX_FLT
CL_END
DET_END
LD_DISC
PG_INT
6
5
4
3
2
1
0
R
R
R
R
R
R
R
Interrupt signal for current-limit violations. IMAX_FLT is the logic OR of bits [3:0] in register
R06h/R07h (Table 6).
Interrupt signal for completion of classification. CL_END is the logic OR of bits [7:4] in register
R04h/R05h (Table 5).
Interrupt signal for completion of detection. DET_END is the logic OR of bits [3:0] in register
R04h/R05h (Table 5).
Interrupt signal for load disconnection. LD_DISC is the logic OR of bits [7:4] in register R06h/R07h
(Table 6).
Interrupt signal for PGOOD status change. PG_INT is the logic OR of bits [7:4] in register R02h/R03h
(Table 4).
Interrupt signal for power-enable status change. PEN_INT is the logic OR of bits [3:0] in register
R02h/R03h (Table 4).
PE_INT
Table 6. Interrupt Mask Register
ADDRESS = 01h
DESCRIPTION
SYMBOL
BIT
R/W
Interrupt mask bit 7. A logic high enables the SUP_FLT interrupts. A logic low disables the SUP_FLT
interrupts.
MASK7
7
R/W
Interrupt mask bit 6. A logic high enables the TSTR_FLT interrupts. A low disables the TSTR_FLT
interrupts.
MASK6
MASK5
MASK4
MASK3
MASK2
MASK1
MASK0
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Interrupt mask bit 5. A logic high enables the IMAX_FLT interrupts. A logic low disables the
IMAX_FLT interrupts.
Interrupt mask bit 4. A logic high enables the CL_END interrupts. A logic low disables the CL_END
interrupts.
Interrupt mask bit 3. A logic high enables the DET_END interrupts. A logic low disables the
DET_END interrupts.
Interrupt mask bit 2. A logic high enables the LD_DISC interrupts. A logic low disables the LD_DISC
interrupts.
Interrupt mask bit 1. A logic high enables the PG_INT interrupts. A logic low disables the PG_INT
interrupts.
Interrupt mask bit 0. A logic high enables the PEN_INT interrupts. A logic low disables the PEN_INT
interrupts.
______________________________________________________________________________________ 23
Quad Network Power Controller
for Power-Over-LAN
Table 7. Power Event Register
ADDRESS =
SYMBOL
02h
R/W
R
03h
R/W
CoR
CoR
CoR
CoR
CoR
CoR
CoR
CoR
DESCRIPTION
BIT
7
PG_CHG4
PG_CHG3
PGOOD change event for port 4
PGOOD change event for port 3
PGOOD change event for port 2
PGOOD change event for port 1
6
R
PG_CHG2
5
R
PG_CHG1
4
R
PWEN_CHG4
PWEN_CHG3
PWEN_CHG2
PWEN_CHG1
3
R
Power enable change event for port 4
Power enable change event for port 3
Power enable change event for port 2
Power enable change event for port 1
2
R
1
R
0
R
Table 8. Detect Event Register
ADDRESS =
SYMBOL
04h
R/W
R
05h
R/W
CoR
CoR
CoR
CoR
CoR
CoR
CoR
CoR
DESCRIPTION
BIT
7
CL_END4
CL_END3
CL_END2
CL_END1
DET_END4
DET_END3
DET_END2
DET_END1
Classification completed on port 4
Classification completed on port 3
Classification completed on port 2
Classification completed on port 1
Detection completed on port 4
Detection completed on port 3
Detection completed on port 2
Detection completed on port 1
6
R
5
R
4
R
3
R
2
R
1
R
0
R
Table 9. Fault Event Register
ADDRESS =
SYMBOL
06h
R/W
R
07h
R/W
CoR
CoR
CoR
CoR
CoR
CoR
CoR
CoR
DESCRIPTION
BIT
7
LD_DISC4
LD_DISC3
LD_DISC2
LD_DISC1
IMAX_FLT4
IMAX_FLT3
IMAX_FLT2
IMAX_FLT1
Disconnect on port 4
Disconnect on port 3
Disconnect on port 2
Disconnect on port 1
Overcurrent on port 4
Overcurrent on port 3
Overcurrent on port 2
Overcurrent on port 1
6
R
5
R
4
R
3
R
2
R
1
R
0
R
24 ______________________________________________________________________________________
Quad Network Power Controller
for Power-Over-LAN
Table 10. Startup Event Register
ADDRESS =
SYMBOL
08h
R/W
R
09h
R/W
CoR
CoR
CoR
CoR
CoR
CoR
CoR
CoR
DESCRIPTION
BIT
7
IVC4
IVC3
Class overcurrent flag for port 4
Class overcurrent flag for port 3
Class overcurrent flag for port 2
Class overcurrent flag for port 1
Startup failed on port 4
6
R
IVC2
5
R
IVC1
4
R
STRT_FLT4
STRT_FLT3
STRT_FLT2
STRT_FLT1
3
R
2
R
Startup failed on port 3
1
R
Startup failed on port 2
0
R
Startup failed on port 1
Table 11. Supply Event Register
ADDRESS =
SYMBOL
0Ah
R/W
R
0Bh
R/W
CoR
CoR
CoR
CoR
CoR
CoR
CoR
CoR
DESCRIPTION
BIT
7
TSD
Overtemperature shutdown
V
V
6
R
V
V
V
V
V
overvoltage condition
undervoltage condition
undervoltage-lockout condition
overvoltage condition
DD_OV
DD_UV
DD
DD
EE
EE
EE
5
R
V
4
R
EE_UVLO
V
V
3
R
EE_OV
EE_UV
2
R
undervoltage condition
OSC_FAIL
1
R
Oscillator amplitude is below limit
V undervoltage-lockout condition
DD
V
0
R
DD_UVLO
The MAX5935 continuously monitors the power supplies
and sets the appropriate bits in the supply event register
Table 12. Port Status Registers
(Table 11). V
/V
is set to 1 whenever
ADDRESS = 0Ch, 0Dh, 0Eh, 0Fh
DD_OV EE_OV
DESCRIPTION
V
V
/V
exceeds its overvoltage threshold.
is set to 1 whenever V /V falls below
DD EE
SYMBOL
BIT
7
R/W
R
/V
DD_UV EE_UV
DD EE
Reserved
Reserved
its undervoltage threshold.
6
R
CLASS_[2]
CLASS_[1]
CLASS_[0]
Reserved
DET_[2]
OSC_FAIL is set to 1 whenever the amplitude of the
oscillator signal at the OSC_input falls below a level
that might compromise the AC disconnect detection
function. OSC_FAIL generates an interrupt only if at
least one of the ACD_EN (R13h[7:4]) bit is set high.
CLASS_
Reserved
DET_ST_
5
R
4
R
3
R
2
R
A thermal shutdown circuit monitors the temperature of
the die and resets the MAX5935 if the temperature
exceeds +150°C. TSD is set to 1 after the MAX5935
returns to normal operation. TSD is also set to 1 after
every UVLO reset.
1
R
DET_[1]
0
R
DET_[0]
read through the R08h address, the content of the reg-
ister is left unchanged. When read through the CoR
R09h address, the register content will be cleared. A
reset sets R08h/R09h = 00h.
When V
and/or |V | is below its undervoltage-lock-
EE
DD
out (UVLO) threshold, the MAX5935 is in Reset mode
and securely holds all ports off. When V and |V
|
EE
DD
rise to above their respective UVLO thresholds, the
device comes out of reset as soon as the last supply
______________________________________________________________________________________ 25
Quad Network Power Controller
for Power-Over-LAN
Table 12a. Detection Result Decoding Chart
DET_ST_[2:0]
DETECTED
None
DESCRIPTION
000
001
010
011
100
101
110
111
Detection status unknown.
DCP
Positive DC supply connected at the port (AGND - V < 1.65V).
OUT_
HIGH CAP
RLOW
High capacitance at the port (>5µF).
Low resistance at the port. R < 17kΩ.
PD
Detection pass. 17kΩ > R > 28kΩ.
DET_OK
RHIGH
OPEN0
DCN
PD
High resistance at the port. R > 28kΩ.
PD
Open port (I < 12.5µA).
Negative DC supply connected to the port (V
- V < 2V).
EE
OUT
PGOOD_ is set to 1 (Table 13) at the end of the power-up
startup period if the power-good condition is met (0 <
Table 12b. Classification Result
Decoding Chart
(V
- V
< PG ). The power-good condition must
OUT
EE) TH
remain valid for more than t to assert PGOOD_.
CLASS_[2:0]
000
CLASS RESULT
PGOOD
PGOOD_ is reset to 0 whenever the output falls out of the
power-good condition. A fault condition immediately
forces PGOOD_ low.
Unknown
001
1
010
2
PWR_EN_ is set to 1 when the port power is turned on.
PWR_EN resets to 0 as soon as the port turns off. Any
transition of PGOOD_ and PWR_EN_ bits set the corre-
sponding bit in the power event registers R02h/R03h
(Table 7). A reset sets R10h = 00h.
011
3
100
4
101
Undefined (treated as CLASS 0)
0
110
A3, A2, A1, and A0 (Table 14) represent the four LSBs
of the MAX5935 address (Table 3). During a reset, the
devices latch into R11h. These four bits address from
the corresponding inputs as well as the state of the
MIDSPAN and AUTO inputs. Changes to those inputs
during normal operation are ignored.
111
Current limit (>I
)
CILIM
crosses the UVLO threshold. The last supply corre-
sponding UV and UVLO bits in the supply event regis-
ter will be set to 1.
The MAX5935 uses two bits for each port to set the mode
of operation (Table 15). Set the modes according to
Table 15a.
A 1 in any supply event register’s bits forces R00h[7] to
1. As with any of the other events register, the supply
event register has two addresses. When read through
the R0Ah address, the content of the register is left
unchanged. When read through the CoR R0Bh
address, the register content will be cleared. A reset
A reset sets R12h = AAAAAAAA where A represents
the latched-in state of the AUTO input prior to the reset.
Use software to change the mode of operation.
Software resets of ports (RESET_P_ bit, Table 22) do
not affect the mode register.
sets R0Ah/R0Bh to 00100001 if V
comes up after
DD
V
or to 00010100 if V comes up after V
.
DD
EE
EE
The port status register (Table 12) records the results of
the detection and classification at the end of each phase
in three encoding bits each. R0Ch contains detection
and classification status of port 1. R0Dh corresponds to
port 2, R0Eh corresponds to port 3, and R0Fh corre-
sponds to port 4. Tables 12a and 12b show the detec-
tion/classification result decoding charts, respectively.
Setting DCD_EN_ to 1 enables the DC load disconnect
detection feature (Table 16). Setting ACD_EN_ to 1
enables the AC load disconnect feature. If enabled, the
load disconnect detection starts during power mode
and after startup when the corresponding PGOOD_ bit
in register R10h (Table 13) goes high. A reset sets
R13h = 0000AAAA, where A represents the latched-in
state of the AUTO input prior to the reset.
As a protection, when POFF_CL (R17h[3], Table 20) is
set to 1, the MAX5935 prohibits turning on power to the
port that returns a status 111 after classification. A reset
sets 0Ch, 0Dh, 0Eh, and 0Fh = 00h.
26 ______________________________________________________________________________________
Quad Network Power Controller
for Power-Over-LAN
Table 13. Power Status Register
ADDRESS = 10h
DESCRIPTION
DESCRIPTION
DESCRIPTION
SYMBOL
BIT
7
R/W
R
PGOOD4
PGOOD3
PGOOD2
PGOOD1
PWR_EN4
PWR_EN3
PWR_EN2
PWR_EN1
Power-good condition on Port 4
Power-good condition on Port 3
Power-good condition on Port 2
Power-good condition on Port 1
Power is enabled on Port 4
Power is enabled on Port 3
Power is enabled on Port 2
Power is enabled on Port 1
6
R
5
R
4
R
3
R
2
R
1
R
0
R
Table 14. Address Input Status Register
ADDRESS = 11h
SYMBOL
Reserved
Reserved
A3
BIT
7
R/W
R
Reserved
6
R
Reserved
5
R
Device address, A3 pin latched in status
Device address, A2 pin latched in status
Device address, A1 pin latched in status
Device address, A0 pin latched in status
MIDSPAN inputs latched in status
AUTO input’s latched-in status
A2
4
R
A1
3
R
A0
2
R
MIDSPAN
AUTO
1
R
0
R
Table 15. Mode Register
ADDRESS = 12h
SYMBOL
P4_M1
P4_M0
P3_M1
P3_M0
P2_M1
P2_M0
P1_M1
P1_M0
BIT
7
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
M0DE[1] for port 4
M0DE[0] for port 4
M0DE[1] for port 3
M0DE[0] for port 3
M0DE[1] for port 2
M0DE[0] for port 2
M0DE[1] for port 1
M0DE[0] for port 1
6
5
4
3
2
1
0
Setting DET_EN_/CLASS_EN_ to 1 (Table 17) enables
load detection/classification, respectively. Detection
always has priority over classification. To perform clas-
sification without detection, set the DET_EN_ bit low
and CLASS_EN_ bit high.
When entering AUTO mode, R14h defaults to FFh.
When entering MANUAL mode, R14h defaults to 00h.
When entering SEMI mode, R1h is left unchanged but
is reset every time the software commands power off the
port. A reset or power-up sets R14h = AAAAAAAAb,
where A represents the latched-in state of the AUTO
input prior to the reset.
In MANUAL mode, R14h works like a pushbutton. Set
the bits high to begin the corresponding routine. The bit
clears after the routine finishes.
______________________________________________________________________________________ 27
Quad Network Power Controller
for Power-Over-LAN
Setting BCKOFF_ to 1 (Table 18) enables cadence
timing on each port, where the port backs off and waits
2.2s after each failed load discovery detection. The IEEE
802.3af standard requires a PSE that delivers power
through the spare pairs (midspan PSE) to have cadence
timing. A reset sets R14h = 0000XXXX, where X is the
logic AND of the MIDSPAN and AUTO input state prior to
a reset. BCKOFF_ can be changed by software at any
time while changes to the MIDSPAN and AUTO input
state during normal operation are ignored.
TSTART[1,0] (Table 19) programs the startup timers.
Startup time is the time the port is allowed to be in current
limit during startup. TFAULT_[1,0] programs the fault
time. Fault time is the time allowable for the port to be in
current limit during normal operation. RSTR[1,0] pro-
grams the discharge rate of the TFAULT_ counter and
effectively sets the time the port remains off after an over-
current fault. TDISC[1,0] programs the load disconnect
detection time. The device turns off power to the port if it
fails to provide a minimum power maintenance signal for
longer than the load disconnect detection time (TDISC).
Set the bits in R16h to scale the TSTART, TFAULT, and
TDISC to a multiple of their nominal value specified in
the Electrical Characteristics table. R27h and R28h fur-
ther extend the programming range of these timers and
also increase the programming resolution.
Table 15a. Mode Status
MODE
00
DESCRIPTION
Shutdown
MANUAL
When the MAX5935 shuts down a port due to an
extended overcurrent condition (either during startup or
normal operation), if RSRT_EN is set high, then the part
does not allow the port to power back on before the
restart timer (Table 19a) returns to zero. This effectively
01
10
Semi AUTO
AUTO
11
Table 16. Load Disconnect Detection Enable Register
ADDRESS = 13h
DESCRIPTION
SYMBOL
ACD_EN4
ACD_EN3
ACD_EN2
ACD_EN1
DCD_EN4
DCD_EN3
DCD_EN2
DCD_EN1
BIT
7
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Enable AC disconnect detection on port 4
6
Enable AC disconnect detection on port 3
Enable AC disconnect detection on port 2
Enable AC disconnect detection on port 1
Enable DC disconnect detection on port 4
Enable DC disconnect detection on port 3
Enable DC disconnect detection on port 2
Enable DC disconnect detection on port 1
5
4
3
2
1
0
Table 17. Detection and Classification Enable Register
ADDRESS = 14h
DESCRIPTION
SYMBOL
CLASS_EN4
CLASS_EN3
CLASS_EN4
CLASS_EN3
DET_EN4
BIT
7
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Enable classification on port 4
Enable classification on port 3
Enable classification on port 2
Enable classification on port 1
Enable detection on port 4
Enable detection on port 3
Enable detection on port 2
Enable detection on port 1
6
5
4
3
DET_EN3
2
DET_EN2
1
DET_EN1
0
28 ______________________________________________________________________________________
Quad Network Power Controller
for Power-Over-LAN
Table 18. Backoff Enable Register
ADDRESS = 15h
DESCRIPTION
SYMBOL
BIT
7
R/W
R
Reserved
Reserved
Reserved
Reserved
BCKOFF4
BCKOFF3
BCKOFF2
BCKOFF1
Reserved
6
R
Reserved
5
R
Reserved
4
R
Reserved
3
R/W
R/W
R/W
R/W
Enable Cadence timing on Port 4
Enable Cadence timing on Port 3
Enable Cadence timing on Port 2
Enable Cadence timing on Port 1
2
1
0
Table 19. Timing Register
ADDRESS = 16h
DESCRIPTION
SYMBOL
RSTR[1]
BIT
7
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Restart timer programming bit 1
Restart timer programming bit 0
Startup timer programming bit 1
Startup timer programming bit 0
Overcurrent timer programming bit 1
Overcurrent timer programming bit 0
RSTR[0]
6
TSTART[1]
TSTART[0]
TFAULT[1]
TFAULT[0]
TDISC[1]
TDISC[0]
5
4
3
2
1
Load disconnect timer programming bit 1
Load disconnect timer programming bit 0
0
Table 19a. Startup, Fault, and Load Disconnect Timers with Default Values in the
Register 27h and 28h
Bit[1:0]
RSTR
t
t
t
FAULT
DISC
START
t
nominal
t
nominal
(60ms, typ)
t
nominal
(60ms, typ)
DISC
START
FAULT
00
16 x t
FAULT
(350ms, typ)
1/4 x t
nominal
1/2 x t
nominal
nominal
nominal
1/2 x t
nominal
nominal
nominal
01
10
11
32 x t
64 x t
DISC
DISC
START
START
START
FAULT
FAULT
FAULT
FAULT
FAULT
FAULT
1/2 x t
2 x t
nominal
nominal
2 x t
4 x t
2 x t
4 x t
0 x t
DISC
sets a minimum duty cycle that protects the external
MOSFET from overheating during prolonged output
overcurrent conditions.
Power-enable “pushbutton” (Table 21) for SEMI and
MANUAL modes. Setting PWR_ON_ to 1 turns on
power to the corresponding port. Setting PWR_OFF_ to
1 turns off power to the port. PWR_ON is ignored when
the port is already powered and during shutdown.
PWR_OFF is ignored when the port is already off and
during shutdown. After execution, the bits reset to 0.
During detection or classification if PWR_ON_ goes
high, the MAX5935 gracefully terminates the current
operation and turn-on power to the port. The MAX5935
ignores the PWR_ON_ in AUTO mode. A reset sets
R19h = 00h.
A reset sets R16h = 00h.
Setting CL_DISC to 1 (Table 20) enables port-over-
class current protection, where the MAX5935 scales
down the overcurrent limit (V
) according to the
FLT_LIM
port classification status. This feature provides protec-
tion to the system against PDs that violate their maxi-
mum class current allowance.
A reset sets R17h = 0xC0.
______________________________________________________________________________________ 29
Quad Network Power Controller
for Power-Over-LAN
Table 20. Miscellaneous Configurations
ADDRESS = 17h
DESCRIPTION
SYMBOL
INT_EN
BIT
7
R/W
R/W
R
A logic high enables INT functionality
RSTR_EN
Reserved
Reserved
POFF_CL
6
A logic high enables the auto-restart protection time off (as set by the RSRT[1:0] bits)
5
R
Reserved
4
R
Reserved
3
R
A logic high prevents power-up after a classification failure (I > 50mA, valid only in AUTO mode)
A logic high enables reduced current-limit voltage threshold (V ) according to port
FLT_LIM
classification result
CL_DISC
2
R/W
Reserved
Reserved
1
0
R/W
R/W
Reserved
Reserved
Table 21. Power Enable Pushbuttons
ADDRESS = 19h
DESCRIPTION
SYMBOL
PWR_OFF4
PWR_OFF3
PWR_OFF2
PWR_OFF1
PWR_ON4
PWR_ON3
PWR_ON2
PWR_ON1
BIT
7
R/W
W
A logic high powers off port 4
A logic high powers off port 3
A logic high powers off port 2
A logic high powers off port 1
A logic high powers on port 4
A logic high powers on port 3
A logic high powers on port 2
A logic high powers on port 1
6
W
5
W
4
W
3
W
2
W
1
W
0
W
Table 22. Global Pushbuttons
ADDRESS = 1Ah
DESCRIPTION
SYMBOL
CLR_INT
BIT
7
R/W
W
A logic high clears all interrupts
Reserved
Reserved
Reserved
RESET_IC
RESET_P4
RESET_P3
RESET_P2
RESET_P1
6
5
Reserved
4
W
W
W
W
W
A logic high resets the MAX5935
A logic high softly resets port 4
A logic high softly resets port 3
A logic high softly resets port 2
A logic high softly resets port 1
3
2
1
0
Writing a 1 to CLR_INT (Table 22) clears all the event
registers and the corresponding interrupt bits in register
R00h. Writing a 1 to RESET_P_ turns off power to the cor-
responding port and resets only the status and event
registers of that port. After execution, the bits reset to 0.
Writing a 1 to RESET_IC causes a global software reset,
after which the register map is set back to its reset state.
A reset sets R1Ah = 00h.
30 ______________________________________________________________________________________
Quad Network Power Controller
for Power-Over-LAN
Table 23. ID Register
ADDRESS = 1Bh
DESCRIPTION
SYMBOL
BIT
7
R/W
R
ID_CODE[4]
6
R
ID_CODE[3]
ID_CODE[2]
ID_CODE[1]
ID_CODE[0]
REV [2]
ID_CODE
5
R
4
R
3
R
2
R
REV
1
R
REV [1]
0
R
REV [0]
ID register keeps track of the device ID number and revision. The MAX5935’s ID_CODE[4:0] = 11000b. Contact the factory for
REV[2:0] value.
Table 24. SMODE Register
ADDRESS = 1Ch
DESCRIPTION
SYMBOL
Reserved
Reserved
Reserved
Reserved
SMODE4
SMODE3
SMODE2
SMODE1
BIT
7
CoR
—
Reserved
6
—
Reserved
5
—
Reserved
4
—
Reserved
3
CoR
CoR
CoR
CoR
Hardware control flag for port 4
Hardware control flag for port 3
Hardware control flag for port 2
Hardware control flag for port 1
2
1
0
Enable SMODE function (Table 24) by setting
EN_WHDOG (R1Fh[7]) to 1. SMODE_ bit goes high when
the watchdog counter reaches zero and the port(s)
switch over to hardware-controlled mode. SMODE_ also
goes high each and every time the software tries to
power on a port but is denied since the port is in hard-
ware mode. A reset sets R1Ch = 00h.
While in hardware-controlled mode, the MAX5935
ignores all requests to turn the power on and the flag
SMODE_ indicates that the hardware took control of the
MAX5935 operation. In addition, the software is not
allowed to change the mode of operation in hardware-
controlled mode. A reset sets R1Eh = 00h.
Setting EN_WHDOG (Table 26) high activates the
watchdog counter. When the counter reaches zero, the
port switches to the hardware-controlled mode deter-
mined by the corresponding HWMODE_ bit. A low in
HWMODE_ switches the port into shutdown by setting
the bits in register R12h to 00. A high in HWMODE_
switches the port into auto mode by setting the bits in
register R12h to 11. If WD_INT_EN is set, an interrupt is
sent if any of the SMODE bits are set.
Set EN_WHDOG (R1Fh[7]) to 1 (Table 25) to enable the
watchdog function. When activated, the watchdog timer
counter, WDTIME[7:0], continuously decrements toward
zero once every 164ms. Once the counter reaches zero
(also called watchdog expiry), the MAX5935 enters hard-
ware-controlled mode and each port shifts to a mode set
by the HWMODE_ bit in register R1Fh (Table 24). Use
software to set WDTIME and continuously set this register
to some nonzero value before the register reaches zero to
prevent a watchdog expiry. In this way, the software
gracefully manages the power to ports upon a system
crash or switchover.
______________________________________________________________________________________ 31
Quad Network Power Controller
for Power-Over-LAN
Table 25. Watchdog Timer Register
ADDRESS = 1Eh
DESCRIPTION
SYMBOL
BIT
7
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
WDTIME[7]
WDTIME[6]
WDTIME[5]
WDTIME[4]
WDTIME[3]
WDTIME[2]
WDTIME[1]
WDTIME[0]
6
5
4
WDTIME
3
2
1
0
Table 26. Switch Mode Register
ADDRESS = 1Fh
DESCRIPTION
SYMBOL
EN_WHDOG
WD_INT_EN
Reserved
BIT
7
R/W
R/W
—
A logic high enables the watchdog function
6
Enables interrupt on SMODE_ bits
5
—
ACTESTM
4
R/W
R/W
R/W
R/W
R/W
AC test mode
HWMODE4
HWMODE3
HWMODE2
HWMODE1
3
Port 4 switches to AUTO if logic high and SHUTDOWN if logic low when watchdog timer expires
Port 3 switches to AUTO if logic high and SHUTDOWN if logic low when watchdog timer expires
Port 2 switches to AUTO if logic high and SHUTDOWN if logic low when watchdog timer expires
Port 1 switches to AUTO if logic high and SHUTDOWN if logic low when watchdog timer expires
2
1
0
Writing a 1 to ACTESTM brings the MAX5935 to an AC
test mode. In this mode, the MAX5935 forces all GATE_
pins low and all PGOOD_ status bits high, thus allowing
AC disconnect detection without powering on the ports.
A reset sets R1Fh = 00h.
When set low, DET_BYP inhibits port power-on if the
discovery detection was bypassed in AUTO mode.
When set high, it allows the part to turn on power to a
non-IEEE 802.3af load without doing detection. If
OSCF_RS is set high, the OSC_FAIL bit is ignored.
Use IGATE[2:0] (Table 27) to set the gate pin pullup
A reset sets R23h = 04h, which sets I
= 50µA and
PU
current, I , according to the following formula:
I
= 325µA as shown in the Electrical
AC_TH
PU
Characteristics.
Use R27h (Table 28) to program the current-limit
threshold, V , and the nominal load disconnect
I
= 50µA - 6.25 x N
PU
where N is the decimal value of IGATE[2:0].
SU_LIM
detection time, t
Use AC_TH[2:0] to program the current threshold of the
AC disconnect comparator according to the following
formula:
nominal.
DISC
Use IMAX[3:0] to program the current-limit trip voltage
according to the following formula:
IAC_TH = 213.68µA + 28.33µA x N
V
= 135mV + 19.25mV x N
SU_LIM
where N is the decimal value of AC_TH[2:0]
Where N is the decimal value of IMAX[3:0]. The
Note: The programmed value has the same percent-
age tolerance as the value specified in the Electrical
Characteristics.
V
limit scales proportionally to the V
SU_LIM
FAULT_LIM
value (I
= 88ꢀ of V
).
FAULT
SU_LIM
A reset sets R27h = 47h, which sets V
= 212mV
SU_LIM
(typ) as shown in the Electrical Characteristics. The
default threshold is set to meet the IEEE 802.3af stan-
dard when using an R
= 0.5Ω, 1ꢀ, 100ppm.
SENSE
32 ______________________________________________________________________________________
Quad Network Power Controller
for Power-Over-LAN
Table 27. Program Register 1
ADDRESS = 23h
DESCRIPTION
SYMBOL
BIT
7
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
IGATE[2]
IGATE
6
IGATE[1]
5
IGATE[0]
DET_BYP
OSCF_RS
4
Detect bypass protection in AUTO mode
3
OSC_FAIL Reset Bit
AC_TH[2]
2
AC_TH
1
AC_TH[1]
0
AC_TH[0]
Table 28. Program Register 2
ADDRESS = 27h
DESCRIPTION
SYMBOL
BIT
7
R/W
R
IMAX[3]. V
IMAX[2]. V
IMAX[1]. V
IMAX[0]. V
programming bit 3
programming bit 2
programming bit 1
programming bit 0
SU_LIM
SU_LIM
SU_LIM
SU_LIM
6
R
IMAX
5
R
4
R
3
R
TD_PR[3]. t
nominal programming bit 3
nominal programming bit 2
nominal programming bit 1
nominal programming bit 0
DISC
2
R
TD_PR [2]. t
TD_PR [1]. t
TD_PR [0]. t
DISC
DISC
DISC
TD_PR
1
R
0
R
Use TF_PR[3:0] to set the nominal value for t
according to the following formula:
Example: Set TD_PR[3:0] = 1111b, TDISC[1:0] = 11b
Then:
DISC
t
nominal = 238ms + 16ms x N
DISC
t
= 2 x t
nominal
DISC
DISC
where N is the decimal value of the binary words
TF_PR[3:0].
= 2 x (238ms + 16ms x 15)
= 956ms
A reset sets R27h = 47h, which sets t
nominal =
DISC
Note: The programmed value has the same percent-
age tolerance as the value specified in the Electrical
Characteristics.
350ms as shown in the Electrical Characteristics. Use
R27h in conjunction with the two TDISC[1:0] bits in reg-
ister R16h to program the values of t
from 60ms to
DISC
almost 340ms with a 16ms resolution.
______________________________________________________________________________________ 33
Quad Network Power Controller
for Power-Over-LAN
Table 29. Program Register 3
ADDRESS = 28h
DESCRIPTION
SYMBOL
BIT
7
R/W
R
TF_PR[3]. t
TF_PR[2]. t
TF_PR[1]. t
TF_PR[0]. t
TS_PR[3]. t
TS_PR[2]. t
TS_PR[1]. t
TS_PR[0]. t
nominal programming bit 3
nominal programming bit 2
nominal programming bit 1
nominal programming bit 0
nominal programming bit 3
nominal programming bit 2
nominal programming bit 1
nominal programming bit 0
FAULT
FAULT
FAULT
FAULT
START
START
START
START
6
R
TF_PR
5
R
4
R
3
R
2
R
TS_PR
1
R
0
R
Use the program registers (Table 29) to set the nominal
value for t and t for all ports according to
Example: Set TF_PR[3:0] = 1111b, TFAULT[1:0] = 11b
Then:
FAULT
the following formula:
START
t
= 4 x t
nominal
FAULT
FAULT
t
t
nominal = 40.96ms + 2.72ms x N
nominal = 40.96ms + 2.72ms x N
FAULT
START
= 4 x (40.96ms + 2.72ms x 15)
= 327ms
where N is the decimal value of TF_PR[3:0] or
TS_PR[3:0], respectively.
Note: The programmed value has the same percent-
age tolerance as the value specified in the Electrical
Characteristics.
A reset sets R28h = 77h, which sets t
= t
=
START
FAULT
60ms as shown in the Electrical Characteristics. Use
R28h in conjunction with the two TSTART and TFAULT
bits in register R16h to program the values of t
FAULT
and t
from about 20ms to almost 330ms with a
START
2.72ms resolution.
34 ______________________________________________________________________________________
Quad Network Power Controller
for Power-Over-LAN
______________________________________________________________________________________ 35
Quad Network Power Controller
for Power-Over-LAN
36 ______________________________________________________________________________________
Quad Network Power Controller
for Power-Over-LAN
Applications Information
PSE (SWITCHES/ROUTER, ETC.)
PD (IP PHONE, WIRELESS ACCESS POINT, SECURITY CAMERAS, ETC.)
DATA
DATA
PHY
RJ–45
RJ–45
PHY
LOAD
POWER AND DATA
OVER TWISTED-PAIR
ETHERNET CABLE
POWER
POWER
3.3V
-48V
OR
MAX5020
MAX5935
MAX5940B
MAX5014
VOUT
-48V TO +3.3V
DC-DC
QUAD PoE
CONTROLLER
PD INTERFACE
CONTROLLER
DC-DC
CONVERTER
GND
-48V
MAX5941/MAX5942
PD INTERFACE AND
DC-DC CONVERTER
Figure 14. PoE System Block Diagram
______________________________________________________________________________________ 37
Quad Network Power Controller
for Power-Over-LAN
RJ–45
CONNECTOR
1
3
4
5
24
22
21
19
RD1+
RD1-
TD1+
TD1-
RX1+
RX1-
TX1+
TX1-
1
2
3
6
1/2 OF
H2005A
PHY
-48VOUT
4
5
7
8
0.1µF
0.1µF
0.1µF
0.1µF
75Ω
75Ω
75Ω
23
20
RXT1
1000pF
250VAC
75Ω
TXCT1
-48VRTN
V
DD
ISOLATION
V
CC
(3.3V)
1.8V TO 5V,
(REF TO DGND)
AGND
A0
A1
A2
A3
V
DD
1kΩ
180Ω
3kΩ
RESET
INTERNAL
4.7kΩ
3kΩ
50kΩ PULLUP
HPCL063L
VCCRTN
INT
SDAOUT
SDAIN
INTERNAL PULLDOWN
(MANUAL MODE)
OPTIONAL BUFFER
AUTO
3kΩ
180Ω
INTERNAL PULLDOWN
(SIGNAL MODE)
MIDSPAN
OSC_IN
MAX5935
HPCL063L
SDA
SCL
SINE WAVE
100Hz ±10%
PEAK AMPLITUDE 2.2V ±0.1V
VALLEY AMPLITUDE 0.2V ±0.1V
OPTIONAL BUFFER
3kΩ
180Ω
SCL
ON
HPCL063L
SHD_
DET_
OFF
OPTIONAL BUFFER
DGND
V
EE
SENSE_ GATE_
OUT_
1kΩ
SMBJ
58CA
0.1µF
2.2MΩ
0.47µF
100V
0.5Ω
1%
1kΩ
1N4448
-48VOUT
-48V
1N4002
FDT3612
100V, 120mΩ
SOT-223
1 OF 4 CHANNELS
Figure 15. PoE System Diagram of One Complete Port, Endpoint PSE
38 ______________________________________________________________________________________
Quad Network Power Controller
for Power-Over-LAN
RJ–45
CONNECTOR
1
2
DATA
3
6
4
5
7
-48VOUT
8
-48VRTN
V
DD
ISOLATION
V
CC
(3.3V)
1.8V TO 5V
(REF TO DGND)
AGND
A0
A1
A2
A3
V
DD
1kΩ
180Ω
3kΩ
RESET
INTERNAL
50kΩ PULLUP
4.7kΩ
3kΩ
HPCL063L
VCCRTN
INT
SDAOUT
SDAIN
INTERNAL PULLDOWN
(MANUAL MODE)
OPTIONAL BUFFER
AUTO
3kΩ
180Ω
INTERNAL PULLDOWN
(SIGNAL MODE)
MIDSPAN
OSC_IN
MAX5935
HPCL063L
SDA
SCL
SINE WAVE
100Hz ±10%
PEAK AMPLITUDE 2.2V ±0.1V
VALLEY AMPLITUDE 0.2V ±0.1V
OPTIONAL BUFFER
3kΩ
180Ω
SCL
ON
HPCL063L
SHD_
DET_
OFF
OPTIONAL BUFFER
DGND
V
EE
SENSE_ GATE_
OUT_
1kΩ
SMBJ
58CA
0.1µF
2.2MΩ
0.47µF
100V
0.5Ω
1%
1kΩ
1N4448
-48VOUT
-48V
1N4002
FDT3612
100V, 120mΩ
SOT-223
1 OF 4 CHANNELS
Figure 16. PoE System Diagram of One Complete Port, Midspan PSE
______________________________________________________________________________________ 39
Quad Network Power Controller
for Power-Over-LAN
R10
2Ω
L1
R6
1Ω
D1
68µH, DO3308P-683
DIODES INC.: B1100
+3.3V
+3.3V
C3
15nF
R1
2.6kΩ
300mA
C4
220µF
Sanyo 6SPS220M
R5
1kΩ
C5
4.7µF
Q4
MMBTA56
Q2
MMBTA56
GND
GND
GND
DRAIN
1
8
7
6
5
MAX5020
R8
30Ω
V+
V
Q3
MMBTA56
CC
Q1
Si2328 DS
2
3
4
GATE
SOURCE
V
NDRV
GND
CS
DD
C9
4.7µH
C6
0.47µF
100V
FB
SS_SHDN
C7
0.22µF
R2
6.81kΩ
R3
2.61kΩ
R4
1Ω
R9
1Ω
C1
0.1µF
C8
2.2µF
C2
0.022µF
R7
1.02kΩ
-48V
-48V
Figure 17. -48V to +3.3V (300mA) Boost Converter Solution for VDIG
1700 (mil)
1700 (mil)
1700 (mil)
Figure 18. Layout Example for Boost Converter Solution for VDIG
40 ______________________________________________________________________________________
Quad Network Power Controller
for Power-Over-LAN
Component List
Chip Information
TRANSISTOR COUNT: 148,768
DESIGNATION
DESCRIPTION
0.1µF, 25V ceramic capacitor
0.022µF, 25V ceramic capacitor
15nF, 25V ceramic capacitor
PROCESS: BiCMOS
C1
C2
C3
220µF capacitor
Sanyo 6SVPA220MAA
C4
C5
C6
C7
C8
C9
D1
4.7µF, 16V ceramic capacitor
0.1µF, 100V ceramic capacitor
0.22µF, 16V ceramic capacitor
0.22µF, 16V ceramic capacitor
4.7nF, 16V ceramic capacitor
B1100 100V Schottky diode
68µH inductor
Coilcraft DO3308P-683 or equivalent
L1
Si2328DS
Vishay n-Channel MOSFET, SOT-23
Q1
Q2
Q3
Q4
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
MMBTA56 small-signal pnp
MMBTA56 small-signal pnp
MMBTA56 small-signal pnp
2.61kΩ 1ꢀ resistor
6.81kΩ 1ꢀ resistor
2.61kΩ 1ꢀ resistor
1Ω 1ꢀ resistor
1kΩ 1ꢀ resistor
1Ω 1ꢀ resistor
1.02kΩ 1ꢀ resistor
30Ω 1ꢀ resistor
1Ω 1ꢀ resistor
2Ω 1ꢀ resistor
High-voltage PWM IC
MAX5020ESA (8-pin SO)
U1
______________________________________________________________________________________ 41
Quad Network Power Controller
for Power-Over-LAN
Typical Operating Circuits
-48V RTN
OUTPUT TO PORT
-48VRTN
ISOLATION
V
DD
V
(3.3V)
CC
1.8V TO 3.7V,
(REF TO DGND)
AGND
A0
A1
A2
A3
V
DD
180Ω
3kΩ
1kΩ
RESET
3kΩ
INTERNAL
4.7kΩ
50kΩ PULLUP
VCCRTN
SDAOUT
SDAIN
INT
AUTO
HPCL063L
OPTIONAL BUFFER
3kΩ
INTERNAL PULLDOWN
(MANUAL MODE)
180Ω
INTERNAL PULLDOWN
(SIGNAL MODE)
MAX5935
MIDSPAN
OSC_IN
HPCL063L
SDA
SCL
N.C.
OPTIONAL BUFFER
3kΩ
180Ω
SCL
ON
HPCL063L
SHD_
OFF
OPTIONAL BUFFER
DGND
V
EE
SENSE_ GATE_
OUT_
DET_
-48V
OUTPUT TO
PORT
1N4448
0.5Ω
1%
1kΩ
-48V
FDT3612
100V, 120mΩ
SOT-223
NOTE: ALL SIGNAL PINS ARE REFERENCED TO DGND.
DGND RANGE IS BETWEEN V AND (AGND + 4V).
EE
CAN BE UP TO 100kΩ
1 OF 4 CHANNELS
Typical Operating Circuit 1 (without AC Load Removal Detection)
42 ______________________________________________________________________________________
Quad Network Power Controller
for Power-Over-LAN
Typical Operating Circuits (continued)
-48V RTN
OUTPUT TO PORT
-48VRTN
V
DD
ISOLATION
V
(3.3V)
CC
1.8V TO 3.7V,
(REF TO DGND)
AGND
A0
A1
A2
A3
V
DD
1kΩ
180Ω
3kΩ
RESET
INTERNAL
50kΩ PULLUP
4.7kΩ
3kΩ
HPCL063L
VCCRTN
INT
SDAOUT
SDAIN
INTERNAL PULLDOWN
(MANUAL MODE)
OPTIONAL BUFFER
AUTO
3kΩ
180Ω
INTERNAL PULLDOWN
(SIGNAL MODE)
MIDSPAN
OSC_IN
MAX5935
HPCL063L
SDA
SCL
SINE WAVE
100Hz ±10%
PEAK AMPLITUDE 2.2V ±0.1V
VALLEY AMPLITUDE 0.2V ±0.1V
OPTIONAL BUFFER
3kΩ
180Ω
SCL
ON
HPCL063L
SHD_
DET_
OFF
OPTIONAL BUFFER
DGND
V
EE
SENSE_ GATE_
OUT_
1kΩ
-48V
0.47µF
0.5Ω
1%
1kΩ
1N4448
OUTPUT TO
100V
PORT
-48V
1N4002
FDT3612
100V, 120mΩ
SOT-223
NOTE: ALL SIGNAL PINS ARE REFERENCED TO DGND.
DGND MUST BE CONNECTED DIRECTLY TO AGND
FOR AC DISCONNECT DETECTION CIRCUIT TO OPERATE.
CAN BE UP TO 100kΩ
1 OF 4 CHANNELS
Typical Operating Circuit 2 (with AC Load Removal Detection)
______________________________________________________________________________________ 43
Quad Network Power Controller
for Power-Over-LAN
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
36
INCHES
MILLIMETERS
DIM
A
MIN
MAX
0.104
0.011
0.017
0.013
MIN
2.44
0.10
0.30
0.23
MAX
2.65
0.29
0.44
0.32
0.096
0.004
0.012
0.009
A1
B
C
e
0.0315 BSC
0.80 BSC
E
H
E
0.291
0.398
0.020
0.598
0.299
7.40
10.11
0.51
7.60
10.51
1.02
H
0.414
0.040
0.612
L
D
15.20
15.55
1
TOP VIEW
D
A1
A
C
e
0∞-8∞
B
L
FRONT VIEW
SIDE VIEW
PROPRIETARY INFORMATION
TITLE:
PACKAGE OUTLINE, 36L SSOP, 0.80 MM PITCH
APPROVAL
DOCUMENT CONTROL NO.
REV.
1
21-0040
E
1
Revision History
Pages changed at Rev 1: 1–6, 44
Pages changed at Rev 2: 1, 44
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
44 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2007 Maxim Integrated Products
is a registered trademark of Maxim Integrated Products, Inc.
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