MAX5700AUB+ [MAXIM]
Ultra-Small, Dual-Channel, 8-/10-/12-Bit Buffered Output DACs with Internal Reference and SPI Interface;
| 型号： | MAX5700AUB+ |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Ultra-Small, Dual-Channel, 8-/10-/12-Bit Buffered Output DACs with Internal Reference and SPI Interface |
| 文件： | 总26页 (文件大小：2250K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MAX5700/MAX5701/
MAX5702
Ultra-Small, Dual-Channel, 8-/10-/12-Bit Buffered
Output DACs with Internal Reference
and SPI Interface
General Description
Benefits and Features
The MAX5700/MAX5701/MAX5702 2-channel, low-power,
8-/10-/12-bit, voltage-output digital-to-analog converters
(DACs) include output buffers and an internal reference
that is selectable to be 2.048V, 2.500V, or 4.096V. The
MAX5700/MAX5701/MAX5702 accept a wide supply
voltage range of 2.7V to 5.5V with extremely low power
(1.5mW) consumption to accommodate most low-voltage
applications. A precision external reference input allows
rail-to-rail operation and presents a 100kI (typ) load to
an external reference.
● Two High-Accuracy DAC Channels
• 12-Bit Accuracy Without Adjustment
• ±1 LSB INL Buffered Voltage Output
• Monotonic Over All Operating Conditions
•
Independent Mode Settings for Each DAC
● Three Precision Selectable Internal References
• 2.048V, 2.500V, or 4.096V
● Internal Output Buffer
• Rail-to-Rail Operation with External Reference
•ꢀ 4.5μsꢀSettlingꢀTime
The MAX5700/MAX5701/MAX5702 have an a 50MHz
3-wire SPI/QSPI™/MICROWIRE®/DSP-compatible serial
interface. The DAC output is buffered and has a low sup-
ply current of less than 250FA per channel and a low
offset error of Q0.5mV (typ). On power-up, the MAX5700/
MAX5701/MAX5702 reset the DAC outputs to zero, pro-
viding additional safety for applications that drive valves
or other transducers which need to be off on power-up.
The internal reference is initially powered down to allow
use of an external reference. The MAX5700/MAX5701/
MAX5702 allow simultaneous output updates using soft-
ware LOAD commands.
•ꢀ OutputsꢀDirectlyꢀDriveꢀ2kΩꢀLoads
●
Smallꢀ5mmꢀxꢀ3mmꢀ10-PinꢀμMAXꢀorꢀUltra-Smallꢀ
3mm x 3mm 10-Pin TDFN Package
● Wide 2.7V to 5.5V Supply Range
● Separate 1.8V to 5.5V V Power-Supply Input
DDIO
● 50MHz 3-Wire SPI/QSPI/MICROWIRE/DSP
Compatible Serial Interface
● Power-On-Reset to Zero-Scale DAC Output
● CLR For Asynchronous Control
● Three Software-Selectable Power-Down Output
Impedances
A clear logic input (CLR) allows the contents of the CODE
and the DAC registers to be cleared asynchronously and
sets the DAC outputs to zero. The MAX5700/MAX5701/
MAX5702 are available in a 10-pin µMAXM and an ultra-
small, 10-pin TDFN package and are specified over the
-40NC to +125NC temperature range.
• 1kΩ,ꢀ100kΩ,ꢀorꢀHighꢀImpedance
●
Lowꢀ350μAꢀSupplyꢀCurrentꢀatꢀ3VꢀV
DD
Functional Diagram
Applications
V
DDIO
V
REF
Programmable Voltage and Current Sources
DD
MAX5700
MAX5701
MAX5702
Gain and Offset Adjustment
INTERNAL REFERENCE/
EXTERNAL BUFFER
Automatic Tuning and Optical Control
Power Amplifier Control and Biasing
Process Control and Servo Loops
Portable Instrumentation
CSB
1 OF 2 DAC CHANNELS
BUFFER
SCLK
CODE
REGISTER
DAC
LATCH
8-/10-/12-BIT
DAC
DIN
OUTA
OUTB
SPI SERIAL
INTERFACE
CLR
CLEAR/
CODE RESET
CLEAR/
LOAD RESET
Data Acquisition
100kI
1kI
POWER-DOWN
DAC CONTROL LOGIC
Ordering Information appears at end of data sheet.
POR
QSPI is a trademark of Motorola, Inc.
MICROWIRE is a registered trademark of National
Semiconductor Corporation.
GND
µMAX is a registered trademark of Maxim Integrated Products, Inc.
19-6455; Rev 2; 8/13
MAX5700/MAX5701/
MAX5702
Ultra-Small, Dual-Channel, 8-/10-/12-Bit Buffered
Output DACs with Internal Reference
and SPI Interface
Absolute Maximum Ratings
V
V
to GND ................................................ -0.3V to +6V
Maximum Continuous Current into Any Pin .................... Q50mA
Operating Temperature Range........................ -40NC to +125NC
Storage Temperature Range............................ -65NC to +150NC
Lead Temperature (soldering, 10s) ................................+300NC
Soldering Temperature (reflow) .................................... +260NC
DD, DDIO
OUT_, REF to GND....-0.3V to the lower of (V
+ 0.3V) and +6V
DD
CSB, SCLK, CLR to GND........................................ -0.3V to +6V
DIN to GND .................................................-0.3V to the lower of
(V
+ 0.3V) and +6V
DDIO
Continuous Power Dissipation (T = +70NC)
A
µMAX (derate at 8.8mW/NC above 70NC)....................707mW
TDFN (derate at 24.4mW/NC above 70NC)................1951mW
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional opera-
tion of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Package Thermal Characteristics (Note 1)
µMAX
Junction-to-Ambient Thermal Resistance (θ ) ........113NC/W
TDFN
Junction-to-Ambient Thermal Resistance (θ ) ..........41NC/W
JA
JA
Junction-to-Case Thermal Resistance (θ )...............42NC/W
Junction-to-Case Thermal Resistance (θ ).................9NC/W
JC
JC
Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer
board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.
Electrical Characteristics
(V
= 2.7V to 5.5V, V
= 1.8V to 5.5V, V
= 0V, C = 200pF, R = 2kI, T = -40NC to +125NC, unless otherwise noted. Typical
DD
DDIO
GND
L
L
A
values are at T = +25NC.) (Note 2)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Bits
DC PERFORMANCE (Note 3)
MAX5700
MAX5701
MAX5702
MAX5700
MAX5701
MAX5702
MAX5700
MAX5701
MAX5702
8
10
Resolution and Monotonicity
Integral Nonlinearity (Note 4)
Differential Nonlinearity (Note 4)
N
12
-0.25
-0.5
-1
Q0.05
Q0.25
Q0. 5
Q0.05
Q0.1
Q0.2
Q0.5
Q10
+0.25
+0.5
+1
INL
LSB
-0.25
-0.5
-1
+0.25
+0.5
+1
DNL
OE
LSB
Offset Error (Note 5)
Offset Error Drift
-5
+5
mV
FV/NC
%FS
Gain Error (Note 5)
GE
-1.0
Q0.1
+1.0
ppm of
FS/NC
Gain Temperature Coefficient
With respect to V
With respect to V
Q3.0
REF
Zero-Scale Error
Full-Scale Error
0
10
mV
-0.5
+0.5
%FS
REF
Maxim Integrated
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MAX5700/MAX5701/
MAX5702
Ultra-Small, Dual-Channel, 8-/10-/12-Bit Buffered
Output DACs with Internal Reference
and SPI Interface
Electrical Characteristics (continued)
(V
= 2.7V to 5.5V, V
= 1.8V to 5.5V, V
= 0V, C = 200pF, R = 2kI, T = -40NC to +125NC, unless otherwise noted. Typical
DD
DDIO
GND
L
L
A
values are at T = +25NC.) (Note 2)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DAC OUTPUT CHARACTERISTICS
No load
0
0
V
DD
V
-
DD
Output Voltage Range (Note 6)
2kIload to GND
V
0.2
2kIload to V
0.2
V
DD
DD
V
= 3V Q10%,
| P5mA
DD
300
300
0.3
|I
OUT
Load Regulation
V
= V /2
FV/mA
OUT
OUT
FS
V
= 5V Q10%,
| P10mA
DD
|I
OUT
V
= 3V Q10%,
| P5mA
DD
|I
OUT
I
DC Output Impedance
V
= V /2
FS
V
= 5V Q10%,
| P10mA
DD
0.3
|I
OUT
Maximum Capacitive Load
Handling
C
500
pF
L
Resistive Load Handling
R
2
kI
L
Sourcing (output
shorted to GND)
30
Short-Circuit Output Current
V
V
= 5.5V
mA
DD
Sinking (output
50
shorted to V
)
DD
DC Power-Supply Rejection
DYNAMIC PERFORMANCE
Voltage-Output Slew Rate
= 3V Q10% or 5V Q10%
100
FV/V
V/Fs
Fs
DD
SR
Positive and negative
1.0
2.2
2.6
4.5
7
¼ scale to ¾ scale, to P 1 LSB, MAX5700
¼ scale to ¾ scale, to P 1 LSB, MAX5701
¼ scale to ¾ scale, to P 1 LSB, MAX5702
Major code transition
Voltage-Output Settling Time
DAC Glitch Impulse
nV*s
nV*s
External reference
3.5
3.3
Channel-to-Channel
Feedthrough (Note 7)
Internal reference
Code = 0, all digital inputs from 0V to
Digital Feedthrough
Power-Up Time
0.2
nV*s
V
DDIO
Startup calibration time (Note 8)
From power-down
200
50
Fs
Fs
Maxim Integrated
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MAX5700/MAX5701/
MAX5702
Ultra-Small, Dual-Channel, 8-/10-/12-Bit Buffered
Output DACs with Internal Reference
and SPI Interface
Electrical Characteristics (continued)
(V
= 2.7V to 5.5V, V
= 1.8V to 5.5V, V
= 0V, C = 200pF, R = 2kI, T = -40NC to +125NC, unless otherwise noted. Typical
DD
DDIO
GND
L
L
A
values are at T = +25NC.) (Note 2)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
90
MAX
UNITS
f = 1kHz
External reference
f = 10kHz
82
f = 1kHz
112
102
125
110
160
145
12
2.048V internal
reference
f = 10kHz
Output Voltage-Noise Density
(DAC Output at Midscale)
nV/√Hz
f = 1kHz
2.5V internal
reference
f = 10kHz
f = 1kHz
4.096V internal
reference
f = 10kHz
f = 0.1Hz to 10Hz
f = 0.1Hz to 10kHz
f = 0.1Hz to 300kHz
f = 0.1Hz to 10Hz
f = 0.1Hz to 10kHz
f = 0.1Hz to 300kHz
f = 0.1Hz to 10Hz
f = 0.1Hz to 10kHz
f = 0.1Hz to 300kHz
f = 0.1Hz to 10Hz
f = 0.1Hz to 10kHz
f = 0.1Hz to 300kHz
f = 1kHz
External reference
76
385
14
2.048V internal
reference
91
450
15
Integrated Output Noise
(DAC Output at Midscale)
FV
P-P
2.5V internal
reference
99
470
16
4.096V internal
reference
124
490
114
99
External reference
f = 10kHz
f = 1kHz
175
153
200
174
295
255
13
2.048V internal
reference
f = 10kHz
Output Voltage-Noise Density
(DAC Output at Full Scale)
nV/√Hz
f = 1kHz
2.5V internal
reference
f = 10kHz
f = 1kHz
4.096V internal
reference
f = 10kHz
f = 0.1Hz to 10Hz
f = 0.1Hz to 10kHz
f = 0.1Hz to 300kHz
f = 0.1Hz to 10Hz
f = 0.1Hz to 10kHz
f = 0.1Hz to 300kHz
f = 0.1Hz to 10Hz
f = 0.1Hz to 10kHz
f = 0.1Hz to 300kHz
f = 0.1Hz to 10Hz
f = 0.1Hz to 10kHz
f = 0.1Hz to 300kHz
External reference
94
540
19
2.048V internal
reference
143
685
21
Integrated Output Noise
(DAC Output at Full Scale)
FV
P-P
2.5V internal
reference
159
705
26
4.096V internal
reference
213
750
Maxim Integrated
│ 4
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MAX5700/MAX5701/
MAX5702
Ultra-Small, Dual-Channel, 8-/10-/12-Bit Buffered
Output DACs with Internal Reference
and SPI Interface
Electrical Characteristics (continued)
(V
= 2.7V to 5.5V, V
= 1.8V to 5.5V, V
= 0V, C = 200pF, R = 2kI, T = -40NC to +125NC, unless otherwise noted. Typical
DD
DDIO
GND
L
L
A
values are at T = +25NC.) (Note 2)
A
PARAMETER
REFERENCE INPUT
SYMBOL
CONDITIONS
MIN
1.24
75
TYP
MAX
UNITS
Reference Input Range
Reference Input Current
Reference Input Impedance
REFERENCE OUPUT
V
V
V
REF
DD
I
V
= V
= 5.5V
55
74
FA
kI
REF
REF
DD
R
100
REF
REF
V
V
V
= 2.048V, T = +25NC
2.043
2.494
4.086
2.048
2.500
2.053
2.506
4.106
REF
REF
REF
A
Reference Output Voltage
V
= 2.5V, T = +25NC
V
A
= 4.096V, T = +25NC
4.096
129
A
f = 1kHz
V
V
V
= 2.048V
= 2.500V
= 4.096V
REF
REF
REF
122
158
151
254
237
12
f = 10kHz
f = 1kHz
Reference Output Noise Density
nV/√Hz
f = 10kHz
f = 1kHz
f = 10kHz
f = 0.1Hz to 10Hz
f = 0.1Hz to 10kHz
f = 0.1Hz to 300kHz
f = 0.1Hz to 10Hz
f = 0.1Hz to 10kHz
f = 0.1Hz to 300kHz
f = 0.1Hz to 10Hz
f = 0.1Hz to 10kHz
f = 0.1Hz to 300kHz
110
390
15
V
V
V
= 2.048V
= 2.500V
= 4.096V
REF
REF
REF
Integrated Reference Output
Noise
129
430
20
µV
P-P
205
525
MAX5702A
Q3
Q10
25
Q10
Q25
Reference Temperature
Coefficient (Note 9)
ppm/NC
MAX5700/MAX5701/MAX5702B
External load
Reference Drive Capacity
Reference Capacitive Load
Reference Load Regulation
Reference Line Regulation
POWER REQUIREMENTS
kI
pF
200
2
I
= 0 to 500FA
mV/mA
mV/V
SOURCE
0.05
V
= 4.096V
4.5
2.7
1.8
5.5
5.5
5.5
REF
Supply Voltage
V
V
V
DD
All other options
I/O Supply Voltage
V
DDIO
Maxim Integrated
│ 5
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MAX5700/MAX5701/
MAX5702
Ultra-Small, Dual-Channel, 8-/10-/12-Bit Buffered
Output DACs with Internal Reference
and SPI Interface
Electrical Characteristics (continued)
(V
= 2.7V to 5.5V, V
= 1.8V to 5.5V, V
= 0V, C = 200pF, R = 2kI, T = -40NC to +125NC, unless otherwise noted. Typical
DD
DDIO
GND
L
L
A
values are at T = +25NC.) (Note 2)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
0.55
0.60
0.65
0.40
0.55
MAX
0.75
0.80
0.90
0.60
0.75
UNITS
V
V
V
V
V
= 2.048V
= 2.5V
= 4.096V
= 3V
REF
REF
REF
REF
REF
Internal reference
External reference
Supply Current (Note 10)
I
mA
DD
= 5V
Interface Supply Current
(Note 10)
I
1
FA
FA
DDIO
All DACs off, internal reference ON
All DACs off, internal reference OFF,
140
0.5
1
Power-Down Mode Supply
Current
T
= -40NC to +85NC
I
A
PD
All DACs off, internal reference OFF,
= +125NC
1.2
2.5
T
A
DIGITAL INPUT CHRACTERISTICS (CSB, SCLK, DIN, CLR)
Hysteresis Voltage
V
0.15
V
V
H
0.7x
2.2V < V
1.8V < V
2.2V < V
1.8V < V
< 5.5V
< 2.2V
< 5.5V
< 2.2V
DDIO
DDIO
DDIO
DDIO
V
DDIO
Input High Voltage
V
IH
0.8x
V
DDIO
0.3 x
V
DDIO
Input Low Voltage
V
V
IL
0.2 x
V
DDIO
Input Leakage Current
I
V
= 0V or V (Note 10)
DDIO
Q0.1
Q1
FA
IN
IN
Input Capacitance (Note 10)
C
3
pF
IN
SPI TIMING CHARACTERISTICS (CSB, SCLK, DIN, CLR) (Note 11)
2.7V < V
1.8V < V
2.7V < V
1.8V < V
< 5.5V
< 2.7V
< 5.5V
< 2.7V
50
33
DDIO
DDIO
DDIO
DDIO
SCLK Frequency
SCLK Period
f
MHz
ns
SCLK
SCLK
20
30
8
t
SCLK Pulse Width High
t
ns
ns
ns
CH
SCLK Pulse Width Low
t
8
CL
CSB Fall to SCLK Fall Setup Time
t
To first SCLK falling edge
8
CSS0
CSH0
CSH1
Applies to inactive SCLK falling edge
preceding the first SCLK falling edge
CSB Fall to SCLK Fall Hold Time
CSB Rise to SCLK Fall Hold Time
t
t
0
0
ns
ns
Applies to the 24th SCLK falling edge
Maxim Integrated
│ 6
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MAX5700/MAX5701/
MAX5702
Ultra-Small, Dual-Channel, 8-/10-/12-Bit Buffered
Output DACs with Internal Reference
and SPI Interface
Electrical Characteristics (continued)
(V
= 2.7V to 5.5V, V
= 1.8V to 5.5V, V
= 0V, C = 200pF, R = 2kI, T = -40NC to +125NC, unless otherwise noted. Typical
DD
DDIO
GND
L
L
A
values are at T = +25NC.) (Note 2)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Applies to the 24th SCLK falling edge,
aborted sequence
CSB Rise to SCLK Fall
t
12
ns
CSA
SCLK Fall to CSB Fall
t
Applies to 24th SCLK falling edge
100
20
5
ns
ns
ns
ns
ns
ns
CSF
CSB Pulse Width High
DIN to SCLK Fall Setup Time
DIN to SCLK Fall Hold Time
CLR Pulse Width Low
t
t
CSPW
t
DS
t
4.5
20
20
DH
CLPW
CLR Rise to CSB Fall
t
Required for command to be executed
CSC
Note 2: Electrical specifications are production tested at T = +25NC. Specifications over the entire operating temperature range
A
are guaranteed by design and characterization. Typical specifications are at T = +25NC.
A
Note 3: DC Performance is tested without load.
Note 4: Linearity is tested with unloaded outputs to within 20mV of GND and V
.
DD
Note 5: Offset and gain calculated from measurements made with V
= V
at code 30 and 4065 for MAX5702, code 8 and
REF
DD
1016 for MAX5701, and code 2 and 254 for MAX5700.
Note 6: Subject to zero and full-scale error limits and V
settings.
REF
Note 7: Measured with all other DAC outputs at midscale with one channel transitioning 0 to full scale.
Note 8: On power-up, the device initiates an internal 200µs (typ) calibration sequence. All commands issued during this time
will be ignored.
Note 9: Guaranteed by design.
Note 10: All channels active at V , unloaded. Static logic inputs with V = V
and V = V
.
FS
IL
GND
IH
DDIO
Note 11: All timing tested with V = V
and V = V
.
IL
GND
IH
DDIO
Maxim Integrated
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MAX5700/MAX5701/
MAX5702
Ultra-Small, Dual-Channel, 8-/10-/12-Bit Buffered
Output DACs with Internal Reference
and SPI Interface
DIN
SCLK
CSB
D
1
23
D
2
22
D
3
21
D
20
D
5
19
D
18
D
7
17
IN
D
16
IN
D
2
IN
D
1
D
0
IN
D
1
23
IN
IN
IN
IN
IN
IN
IN
IN
t
t
DS
SCLK
t
DH
4
6
8
22
23
24
t
CSH0
t
t
CSH1
t
CSA
CH
t
t
CL
CSS0
t
t
CSF
CSPW
CLR
t
t
CSC
CLPW
Figure 1. SPI Serial Interface Timing Diagram
Typical Operating Characteristics
(MAX5702, 12-bit performance, T = +25°C, unless otherwise noted.)
A
INL vs. CODE
INL vs. CODE
DNL vs. CODE
1.0
0.8
1.0
0.8
1.0
0.8
0.6
0.4
0.2
0
V
= V = 3V
V
= V = 5V
V
= V = 3V
DD REF
DD
REF
DD
REF
NO LOAD
NO LOAD
NO LOAD
0.6
0.6
0.4
0.4
0.2
0.2
0
0
-0.2
-0.4
-0.6
-0.8
-1.0
-0.2
-0.4
-0.6
-0.8
-1.0
-0.2
-0.4
-0.6
-0.8
-1.0
0
512 1024 1536 2048 2560 3072 3584 4096
CODE (LSB)
0
512 1024 1536 2048 2560 3072 3584 4096
CODE (LSB)
0
512 1024 1536 2048 2560 3072 3584 4096
CODE (LSB)
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MAX5700/MAX5701/
MAX5702
Ultra-Small, Dual-Channel, 8-/10-/12-Bit Buffered
Output DACs with Internal Reference
and SPI Interface
Typical Operating Characteristics (continued)
(MAX5702, 12-bit performance, T = +25°C, unless otherwise noted.)
A
DNL vs. CODE
INL AND DNL vs. SUPPLY VOLTAGE
INL AND DNL vs. TEMPERATURE
1.0
0.8
1.0
0.8
1.0
0.8
V
= 3V
V
= V = 3V
DD REF
REF
V
= V = 5V
REF
DD
NO LOAD
0.6
0.6
0.6
MAX INL
MAX INL
0.4
0.4
0.4
MAX DNL
MIN DNL
MAX DNL
MIN DNL
0.2
0.2
0.2
0
0
0
-0.2
-0.4
-0.6
-0.8
-1.0
-0.2
-0.4
-0.6
-0.8
-1.0
-0.2
-0.4
-0.6
-0.8
-1.0
MIN INL
MIN INL
0
512 1024 1536 2048 2560 3072 3584 4096
CODE (LSB)
2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5
SUPPLY VOLTAGE (V)
-40 -25 -10
5
20 35 50 65 80 95 110 125
TEMPERATURE (°C)
OFFSET AND ZERO-SCALE ERROR
vs. SUPPLY VOLTAGE
OFFSET AND ZERO-SCALE ERROR
vs. TEMPERATURE
FULL-SCALE ERROR AND GAIN ERROR
vs. SUPPLY VOLTAGE
1.0
0.8
1.0
0.8
0.020
0.016
0.012
0.008
0.004
0
V
= 2.5V (EXTERNAL)
REF
NO LOAD
V
= 2.5V (EXTERNAL)
REF
NO LOAD
ZERO-SCALE ERROR
0.6
0.6
ZERO-SCALE ERROR
GAIN ERROR
0.4
0.4
OFFSET ERROR (V = 5V)
DD
0.2
0.2
0
0
-0.2
-0.4
-0.6
-0.8
-1.0
-0.2
-0.4
-0.6
-0.8
-1.0
-0.004
-0.008
-0.012
-0.016
-0.020
FULL-SCALE ERROR
OFFSET ERROR (V = 3V)
DD
OFFSET ERROR
V
= 2.5V (EXTERNAL)
REF
NO LOAD
2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5
SUPPLY VOLTAGE (V)
-40 -25 -10
5
20 35 50 65 80 95 110 125
TEMPERATURE (°C)
2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5
SUPPLY VOLTAGE (V)
FULL-SCALE ERROR AND GAIN ERROR
vs. TEMPERATURE
SUPPLY CURRENT
vs. SUPPLY VOLTAGE
SUPPLY CURRENT vs. TEMPERATURE
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.10
0.05
0
0.70
0.65
0.60
0.55
0.50
0.45
0.40
0.35
0.30
V
V
(INTERNAL) = 4.096V,
REF
= 5V
DD
OUT_ = FULL SCALE
NO LOAD
V
= 2.5V (EXTERNAL)
REF
NO LOAD
V
= 4.096V
REF
(INTERNAL)
V
(INTERNAL) = 2.048V,
REF
V
= 5V
DD
GAIN ERROR (V = 5V)
DD
V
= 2.500V
REF
V
V
(INTERNAL) = 2.5V,
REF
= 5V
DD
(INTERNAL)
FULL-SCALE ERROR
GAIN ERROR (V = 3V)
DD
V
= 2.048V
REF
-0.05
-0.10
(INTERNAL)
V
(EXTERNAL) = V = 5V
DD
REF
V
= 2.5V
REF
(EXTERNAL)
V
(EXTERNAL) = V = 3V
DD
REF
-40 -25 -10
5
20 35 50 65 80 95 110 125
TEMPERATURE (°C)
-40 -25 -10
5
20 35 50 65 80 95 110 125
TEMPERATURE (°C)
2.7
3.2
3.7
4.2
(V)
4.7 5.2
V
DD
Maxim Integrated
│ 9
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MAX5700/MAX5701/
MAX5702
Ultra-Small, Dual-Channel, 8-/10-/12-Bit Buffered
Output DACs with Internal Reference
and SPI Interface
Typical Operating Characteristics (continued)
(MAX5702, 12-bit performance, T = +25°C, unless otherwise noted.)
A
POWER-DOWN MODE SUPPLY CURRENT
vs. TEMPERATURE
SUPPLY CURRENT vs. CODE
1.6
0.80
0.70
0.60
0.50
0.40
0.30
0.20
0.10
POWER-DOWN MODE
ALL DACs
V
REF
= 5V
= 2.048V
DD
V
= 5V
= 4.096V
DD
REF
V
REF
= 5V
= 2.500V
DD
V
V
1.2
V
T
= +125°C
= +25°C
A
0.8
0.4
0
T
A
T
A
= +85°C
V
= 3V
= 3.0V
DD
V
= 5V
= 5.0V
DD
V
REF
(EXTERNAL)
V
REF
(EXTERNAL)
T
A
= -40°C
0
512 1024 1536 2048 2560 3072 3584 4096
CODE (LSB)
2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5
SUPPLY VOLTAGE (V)
SETTLING TO ±± LSꢀ
I
(EXTERNAL) vs. CODE
REF
(V = V
DD
= 5V, R = 2kI, C = 200pF)
REF
L L
60
V
= V
REF
DD
NO LOAD
V
OUT
50
40
30
20
10
0
0.5V/div
1/4 SCALE TO 3/4 SCALE
V
= 5V
REF
ZOOMED V
1 LSB/div
OUT
V
= 3V
REF
3.75µs
TRIGGER PULSE
5V/div
0
512 1024 1536 2048 2560 3072 3584 4096
CODE (LSB)
4µs/div
MAJOR CODE TRANSITION GLITCH ENERGY
SETTLING TO ±± LSꢀ
(V = V
= 5V, R = 2kI, C = 200pF)
DD
REF
L
L
(V = V
DD
= 5V, R = 2kI, C = 200pF)
REF
L L
MAX5700 toc18
V
OUT
3.3mV/div
3/4 SCALE TO 1/4 SCALE
4.3µs
ZOOMED V
1 LSB/div
OUT
V
OUT
1 LSB CHANGE
0.5V/div
(MIDCODE TRANSITION
FROM 0x7FF TO 0x800)
GLITCH ENERGY = 6.7nV*s
TRIGGER PULSE
5V/div
TRIGGER PULSE
5V/div
4µs/div
Maxim Integrated
│ 10
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MAX5700/MAX5701/
MAX5702
Ultra-Small, Dual-Channel, 8-/10-/12-Bit Buffered
Output DACs with Internal Reference
and SPI Interface
Typical Operating Characteristics (continued)
(MAX5702, 12-bit performance, T = +25°C, unless otherwise noted.)
A
MAJOR CODE TRANSITION GLITCH ENERGY
V
vs. TIME TRANSIENT
OUT
(V = V
= 5V, R = 2kI, C = 200pF)
DD
REF
L
EXITING POWER-DOWN
L
MAX5700 toc19
MAX5700 toc20
1 LSB CHANGE
(MIDCODE TRANSITION
FROM 0x800 TO 0x7FF)
GLITCH ENERGY = 6nV*s
V
SCLK
0V
0V
5V/div
24TH EDGE
DAC OUTPUT
500mV/div
V
OUT
3.3mV/div
TRIGGER PULSE
5V/div
V
= 5V, V = 2.5V
REF
DD
EXTERNAL
2µs/div
10µs/div
CHANNEL-TO-CHANNEL FEEDTHROUGH
(V = V = 5V, T = +25NC,
DD
REF
A
R = 2kI, C = 200pF)
POWER-ON RESET TO 0V
L
L
MAX5700 toc22
MAX5700 toc21
V
DD
TRANSITIONING
DAC
1V/div
V
= V = 5V
REF
DD
2V/div
R
L
= 2kI
10kI LOAD TO V
DD
0V
0V
STATIC DAC
1.25mV/div
NO LOAD
V
OUT
TRANSITIONING DAC: 0 TO FULL SCALE
STATIC DAC: MIDSCALE
ANALOG CROSSTALK = 3.5nV*s
2V/div
TRIGGER PULSE
10V/div
4µs/div
20µs/div
CHANNEL-TO-CHANNEL FEEDTHROUGH
CHANNEL-TO-CHANNEL FEEDTHROUGH
(V = V = 5V, T = +25NC, NO LOAD)
(V = 5V, V
DD
= 4.096V (INTERNAL),
REF
T
A
= +25NC, R = 2kI, C = 200pF)
L L
MAX5700 toc24
DD
REF
A
MAX5700 toc23
TRANSITIONING
DAC
1V/div
TRANSITIONING
DAC
1V/div
R
= 2kI
L
NO LOAD
NO LOAD
STATIC DAC
1.25mV/div
NO LOAD
STATIC DAC
1.25mV/div
TRANSITIONING DAC: 0 TO FULL SCALE
STATIC DAC: MIDSCALE
ANALOG CROSSTALK = 3.3nV*s
TRANSITIONING DAC: 0 TO FULL SCALE
STATIC DAC: MIDSCALE
ANALOG CROSSTALK = 1.8nV*s
TRIGGER PULSE
10V/div
TRIGGER PULSE
10V/div
5µs/div
5µs/div
Maxim Integrated
│ 11
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MAX5700/MAX5701/
MAX5702
Ultra-Small, Dual-Channel, 8-/10-/12-Bit Buffered
Output DACs with Internal Reference
and SPI Interface
Typical Operating Characteristics (continued)
(MAX5702, 12-bit performance, T = +25°C, unless otherwise noted.)
A
CHANNEL-TO-CHANNEL FEEDTHROUGH
(V = 5V, V
= 4.096V (INTERNAL),
DD
REF
DIGITAL FEEDTHROUGH
T = +25NC, NO LOAD)
A
MAX5700 toc26
MAX5700 toc25
TRANSITIONING DAC
1V/div
NO LOAD
NO LOAD
STATIC DAC
1.25mV/div
0.7mV/div
TRANSITIONING DAC: 0 TO FULL SCALE
STATIC DAC: MIDSCALE
ANALOG CROSSTALK = 1.1nV*S
V
= V = 5V
REF
DD
R = 10kΩ
L
TRIGGER PULSE
10V/div
DIGITAL FEEDTHROUGH -0.1nVs
·
4µs/div
400ns/div
OUTPUT LOAD REGULATION
OUTPUT CURRENT LIMITING
10
8
500
V
= V
REF
V
= V
DD REF
DD
400
300
200
100
0
6
V
DD
= 5V
4
V
= 5V
DD
2
0
V
= 3V
DD
-2
-4
-6
-8
-10
-100
-200
-300
-400
-500
V
= 3V
DD
-30 -20 -10
0
10 20 30 40 50 60
(mA)
-30 -20 -10
0
10 20 30 40 50 60 70
(mA)
I
I
OUT
OUT
HEADROOM AT RAILS
vs. OUTPUT CURRENT
NOISE-VOLTAGE DENSITY
VS. FREQUENCY (DAC AT MIDSCALE)
5.00
4.50
4.00
3.50
3.00
2.50
2.00
1.50
1.00
0.50
0
350
300
250
200
150
100
50
V
= 5V, V = 4.096V
REF
(INTERNAL)
DD
V
= 5V, SOURCING
DD
V
= V
REF
DAC = FULL SCALE
DD
V
= 5V, V = 2.5V
REF
DD
(INTERNAL)
V
= 5V, V = 2.048V
DD
REF
(INTERNAL)
V
= 3V, SOURCING
DD
V
= 3V AND 5V
SINKING
DD
V
= V
V
= 5V, V = 4.5V
DD REF
(EXTERNAL)
DD
REF
DAC = ZERO SCALE
0
0
1
2
3
4
I
5
6
7
8
9
10
100
1k
10k
100k
(mA)
FREQUENCY (Hz)
OUT
Maxim Integrated
│ 12
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MAX5700/MAX5701/
MAX5702
Ultra-Small, Dual-Channel, 8-/10-/12-Bit Buffered
Output DACs with Internal Reference
and SPI Interface
Typical Operating Characteristics (continued)
(MAX5702, 12-bit performance, T = +25°C, unless otherwise noted.)
A
0.1Hz TO 10Hz OUTPUT NOISE, EXTERNAL
0.1Hz TO 10Hz OUTPUT NOISE, INTERNAL
REFERENCE (V = 5V, V = 2.048V)
REFERENCE (V = 5V, V
= 4.5V)
DD
REF
DD
REF
MAX5700 toc31
MAX5700 toc32
MIDSCALE UNLOADED
= 12µV
MIDSCALE UNLOADED
= 13µV
V
V
P-P
P-P
2µV/div
2µV/div
4s/div
4s/div
0.1Hz TO 10Hz OUTPUT NOISE, INTERNAL
REFERENCE (V = 5V, V = 2.5V)
0.1Hz TO 10Hz OUTPUT NOISE, INTERNAL
REFERENCE (V = 5V, V = 4.096V)
DD
REF
DD
REF
MAX5700 toc33
MAX5700 toc34
MIDSCALE UNLOADED
= 16µV
MIDSCALE UNLOADED
= 15µV
V
V
P-P
P-P
2µV/div
2µV/div
4s/div
4s/div
REFERENCE LOAD REGULATION
SUPPLY CURRENT vs. LOGIC VOLTAGE
V
DRIFT vs. TEMPERATURE
REF
0
3000
2700
2400
2100
1800
1500
1200
900
25
20
15
10
5
V
= 5V
DD
INTERNAL REFERENCE
-0.2
-0.4
-0.6
-0.8
-1.0
V
DDIO
= 5V
V
= 2.048V, 2.5V, AND 4.096V
REF
V
= 3V
DDIO
DDIO
600
300
V
2
= 1.8V
3
0
0
0
50 100 150 200 250 300 350 400 450 500
REFERENCE OUTPUT CURRENT (µA)
0
1
4
5
0.2 2.9 3.0 3.2 3.3 3.4 3.6 3.7 3.9 4.0 4.1 4.3 4.4
TEMPERATURE DRIFT (ppm/°C)
INPUT LOGIC VOLTAGE (V)
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│ 13
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MAX5700/MAX5701/
MAX5702
Ultra-Small, Dual-Channel, 8-/10-/12-Bit Buffered
Output DACs with Internal Reference
and SPI Interface
Pin Configurations
TOP VIEW
REF
OUTA
OUTB
GND
1
2
3
4
5
10
9
CLR
1
2
3
10
9
REF
OUTA
OUTB
GND
CLR
V
DDIO
MAX5700
MAX5701
MAX5702
V
DDIO
MAX5700
MAX5701
MAX5702
8
CSB
SCLK
DIN
8
CSB
SCLK
DIN
7
7
4
5
V
6
DD
EP
6
V
DD
µMAX
TDFN
Pin Description
PIN
1
NAME
REF
FUNCTION
Reference Voltage Input/Output
Buffered Channel A DAC Output
Buffered Channel B DAC Output
Ground
2
OUTA
OUTB
GND
3
4
5
V
Supply Voltage Input. Bypass V
SPI Interface Data Input
SPI Interface Clock Input
SPI Chip-Select Input
with at least a 0.1FF capacitor to GND.
DD
DD
6
DIN
SCLK
CSB
7
8
9
V
Digital Interface Power-Supply Input
Active-Low Clear Input
DDIO
10
—
CLR
EP
Exposed Pad (TDFN Only). Connect to ground.
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│ 14
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MAX5700/MAX5701/
MAX5702
Ultra-Small, Dual-Channel, 8-/10-/12-Bit Buffered
Output DACs with Internal Reference
and SPI Interface
Detailed Description
Functional Diagram). The contents of the CODE register
hold pending DAC output settings which can later be
loaded into the DAC registers. The CODE register can be
updated using both CODE and CODE_LOAD user com-
mands. The contents of the DAC register hold the current
DAC output settings. The DAC register can be updated
directly from the serial interface using the CODE_LOAD
commands or can upload the current contents of the
CODE register using LOAD commands.
The MAX5700/MAX5701/MAX5702 are 2-channel, low-
power, 8-/10-/12-bit buffered voltage-output DACs. The
2.7V to 5.5V wide supply voltage range and low-power
consumption accommodates most low-power and low-
voltage applications. The devices present a 100kI load
to the external reference. The internal output buffers
allow rail-to-rail operation. An internal voltage reference
is available with software selectable options of 2.048V,
2.5V, or 4.096V. The devices feature a 50MHz, 3-wire
SPI/QSPI/MICROWIRE/DSP-compatible serial interface to
save board space and reduce the complexity in isolated
applications. The MAX5700/MAX5701/MAX5702 include
a serial-in/parallel-out shift register, internal CODE and
DAC registers, a power-on-reset (POR) circuit to initialize
the DAC outputs to code zero, and control logic. CLR is
available to asynchronously clear the device indepen-
dent of the serial interface.
The contents of both CODE and DAC registers are main-
tained during power-down states, so that when the DACs
are powered on, they return to their previously stored
output settings. Any CODE or LOAD commands issued
during power-down states continue to update the register
contents. SW_CLEAR and SW_RESET commands reset
the contents of all CODE and DAC registers to their zero-
scale defaults.
Internal Reference
DAC Outputs (OUT_)
The MAX5700/MAX5701/MAX5702 include an internal
precision voltage reference that is software selectable
to be 2.048V, 2.500V, or 4.096V. When an internal refer-
ence is selected, that voltage is available on the REF
pin for other external circuitry (see the Typical Operating
Circuits) and can drive a 25kI load.
The MAX5700/MAX5701/MAX5702 include internal buf-
fers on all DAC outputs. The internal output buffers
provide improved load regulation for the DAC outputs.
The output buffers slew at 1V/Fs (typ) and drive resistive
loads as low as 2kI in parallel with as much as 500pF
of capacitance.. The analog supply voltage (V ) deter-
mines the maximum output voltage range of the devices
DD
External Reference
The external reference input has a typical input
impedance of 100kI and accepts an input voltage
as V
powers the output buffer. Under no-load condi-
DD
tions, the output buffers drive from GND to V , subject
to offset and gain errors. With a 2kω load to GND, the
DD
from +1.24V to V . Connect an external voltage
DD
supply between REF and GND to apply an exter-
nal reference. The MAX5700/MAX5701/MAX5702
power up and reset to external reference mode. Visit
www.maximintegrated.com/products/references for a
list of available external voltage-reference devices.
output buffers drive from GND to within 200mV of V
.
DD
With a 2kω load to V , the output buffers drive from V
DD
DD
to within 200mV of GND.
The DAC ideal output voltage is defined by:
D
V
= V
×
OUT
REF
N
Clear Input (CLR)
2
The MAX5700/MAX5701/MAX5702 feature an asynchro-
nous active-low CLR logic input that simultaneously sets
both DAC outputs to zero. Driving CLR low clears the
contents of both the CODE and DAC registers and also
aborts the on-going SPI command. To allow a new SPI
where D = code loaded into the DAC register, V
reference voltage, N = resolution.
=
REF
Internal Register Structure
The user interface is separated from the DAC logic to
minimize digital feedthrough. Within the serial interface
is an input shift register, the contents of which can be
routed to control registers, individual, or multiple DACs
as determined by the user command.
command, drive CLR high, satisfying the t
requirement.
timing
CSC
Interface Power Supply (VDDIO
)
The MAX5700/MAX5701/MAX5702 feature a separate
supply pin (V ) for the digital interface (1.8V to 5.5V).
Within each DAC channel there is a CODE register
followed by a DAC latch register (see the Detailed
DDIO
DDIO
Connect V
to the I/O supply of the host processor.
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│ 15
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MAX5700/MAX5701/
MAX5702
Ultra-Small, Dual-Channel, 8-/10-/12-Bit Buffered
Output DACs with Internal Reference
and SPI Interface
SPI Serial Interface
The MAX5700/MAX5701/MAX5702 3-wire serial interface
is compatible with MICROWIRE, SPI, QSPI, and DSPs.
The interface provides three inputs, SCLK, CSB, and
DIN. The chip-select input (CSB, active low) frames the
data loaded through the serial data input (DIN). Following
a CSB input high-to-low transition, the data is shifted
in synchronously and latched into the input register on
each falling edge of the serial clock input (SCLK). Each
serial operation word is 24-bits long. The DAC data is
left justified as shown in Table 1. The serial input register
transfers its contents to the destination registers after
loading 24 bits of data on the 24th SCLK falling edge.
To initiate a new SPI operation, drive CSB high and then
low to begin the next operation sequence, being sure to
meet all relevant timing requirements. During CSB high
periods, SCLK is ignored, allowing communication to
other devices on the same bus. SPI operations consist-
ing of more than 24 SCLK cycles are executed on the
24th SCLK falling edge, using the first three bytes of
data available. SPI operations consisting of less than 24
SCLK cycles will not be executed. The content of the SPI
operation consists of a command byte followed by a two
byte data word.
µC
CSB1
SCLK
MOSI
CSB
SCLK
DIN
MAX5700
MAX5701
MAX5702
CSB2
CSB
*
*
SCLK
DIN
MISO
CSB3
DOUT
CSB
SCLK
DIN
*ADDITIONAL SPI DEVICE
Figure 2. Typical SPI Application Circuit
Figure 1 shows the timing diagram for the complete
3-wire serial interface transmission. The DAC code
settings (D) for the MAX5700/MAX5701/MAX5702 are
accepted in an offset binary format (see Table 1).
Otherwise, the expected data format for each command
is listed in Table 2. See Figure 2 for an example of a typi-
cal SPI circuit application.
SPI User-Command Register Map
This section lists the user accessible commands and
registers for the MAX5700/MAX5701/MAX5702.
Table 2 provides detailed information about the Command
Registers.
Table 1. Format DAC Data Bit Positions
PART
B15 B14 B13 B12 B11 B10
B9
D1
D3
D5
B8
D0
D2
D4
B7
x
B6
x
B5
x
B4
x
B3
x
B2
x
B1
x
B0
x
MAX5700
MAX5701
MAX5702
D7
D9
D6
D8
D5
D7
D9
D4
D6
D8
D3
D5
D7
D2
D4
D6
D1
D3
D0
D2
x
x
x
x
x
x
D11 D10
D1
D0
x
x
x
x
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MAX5700/MAX5701/
MAX5702
Ultra-Small, Dual-Channel, 8-/10-/12-Bit Buffered
Output DACs with Internal Reference
and SPI Interface
D A C A
D A C B
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│ 17
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MAX5700/MAX5701/
MAX5702
Ultra-Small, Dual-Channel, 8-/10-/12-Bit Buffered
Output DACs with Internal Reference
and SPI Interface
D A C A
D A C B
L D _ E N
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│ 18
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MAX5700/MAX5701/
MAX5702
Ultra-Small, Dual-Channel, 8-/10-/12-Bit Buffered
Output DACs with Internal Reference
and SPI Interface
CODEn Command
will modify at least one CODE register. To avoid this, use
the LOADn command with DAC SELECTION = ALL DACs
The CODEn command (B[23:20] = 0000) updates the
CODE register contents for the selected DAC(s). Changes
to the CODE register content based on this command will
not affect DAC outputs directly unless the DAC latch has
been configured to be transparent. Issuing the CODEn
command with DAC SELECTION = ALL DACs is equiva-
lent to CODE_ALL (B[23:16] = 10000000). See Table 2
and Table 3.
or use the LOAD_ALL command. See Table 2 and Table 3
.
CODEn_LOADn Command
The CODEn_LOADn command (B[23:20] = 0011)
updates the CODE register contents for the selected
DAC(s) as well as the DAC register content of the
selected DAC(s). Channels for which the CODE register
content has not been modified since the last load to DAC
register operation will not be updated to reduce digital
crosstalk. Issuing this command with DAC SELECTION
= ALL DACs is equivalent to the CODE_ALL_LOAD_ALL
command. See Table 2 and Table 3.
LOADn Command
The LOADn command (B[23:20] = 0001) updates the
DAC register content for the selected DAC(s) by upload-
ing the current contents of the CODE register. The
LOADn command can be used with DAC SELECTION =
ALL DACs to issue a software load for all DACs, which
is equivalent to the LOAD_ALL (B[23:16] = 10000001)
command. See Table 2 and Table 3.
CODE_ALL Command
The CODE_ALL command (B[23:16] = 10000000)
updates the CODE register contents for all DACs. See
Table 2.
CODEn_LOAD_ALL Command
LOAD_ALL Command
The CODEn_LOAD_ALL command (B[23:20] = 0010)
updates the CODE register contents for the selected
DAC(s) as well as the DAC register content of all DACs.
Channels for which the CODE register content has not
been modified since the last load to DAC register opera-
tion will not be updated to reduce digital crosstalk. Issuing
this command with DAC_ADDRESS = ALL is equivalent to
the CODE_ALL_LOAD_ALL (B[23:16] = 1000001x) com-
mand. The CODEn_LOAD_ALL command by definition
The LOAD_ALL command (B[23:16] = 10000001) updates
the DAC register content for all DACs by uploading the
current contents of the CODE registers. See Table 2.
CODE_ALL_LOAD_ALL Command
The CODE_ALL_LOAD_ALL command (B[23:16] =
1000001x) updates the CODE register contents for all
DACs as well as the DAC register content of all DACs.
See Table 2.
Table 3. DAC Selection
B19
0
B18
0
B17
0
B16
0
DAC SELECTED
DAC A
0
0
0
1
DAC B
0
0
1
X
No effect
ALL DACs
ALL DACs
X
1
X
X
1
X
X
X
Maxim Integrated
│ 19
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MAX5700/MAX5701/
MAX5702
Ultra-Small, Dual-Channel, 8-/10-/12-Bit Buffered
Output DACs with Internal Reference
and SPI Interface
POWER Command
In STANDBY mode, the internal reference can be pow-
ered down or it can be set to remain powered-on for
external use. Also, in STANDBY mode, devices using the
external reference do not load the REF pin. See Table 4.
The MAX5700/MAX5701/MAX5702 feature a software-
controlled power-mode (POWER) command (B[23:18]
= 010000). The POWER command updates the power-
mode settings of the selected DACs while the power set-
tings of the rest of the DACs remain unchanged. The new
power setting is determined by bits B[17:16] while the
affected DAC(s) are selected by bits B[9:8]. If all DACs
are powered down, the device enters a STANDBY mode.
SW_RESET and SW_CLEAR Command
The SW_RESET (B[23:16] = 01010001) and SW_CLEAR
(B[23:16] = 01010000) commands provide a means of
issuing a software reset or software clear operation. Use
SW_CLEAR to issue a software clear operation to return
all CODE and DAC registers to the zero-scale value. Use
SW_RESET to reset all CODE, DAC, and configuration
registers to their default values.
In power-down, the DAC output is disconnected from
the buffer and is grounded with either one of the two
selectable internal resistors or set to high impedance.
See Table 5 for the selectable internal resistor values in
power-down mode. In power-down mode, the DAC regis-
ter retains its value so that the output is restored when the
device powers up. The serial interface remains active in
power-down mode.
Table 4. POWER Command Format
B23 B22 B21 B20 B19 B18 B17 B16 B15 B14 B13 B12 B11 B10 B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
0
1
0
0
0
0
PD1 PD0
X
X
X
X
X
X
B
A
X
X
X
X
X
X
X
X
Power
Mode:
00 =
Normal
01 = 1kI
10 =
Multiple
DAC
Selection:
1 = DAC
Selected
0 = DAC
Not
POWER Command
Don’t Care
Don’t Care
100kI
11 = Hi-Z
Selected
Default Values (all DACs) →
0
0
X
X
X
X
X
X
1
1
X
X
X
X
X
X
X
X
Table 5. Selectable DAC Output Impedance in Power-Down Mode
PD1 (B17)
PD0 (B16)
OPERATING MODE
0
0
1
1
0
1
0
1
Normal operation
Power-down with internal 1kI pulldown resistor to GND.
Power-down with internal 100kI pulldown resistor to GND.
Power-down with high-impedance output.
Maxim Integrated
│ 20
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MAX5700/MAX5701/
MAX5702
Ultra-Small, Dual-Channel, 8-/10-/12-Bit Buffered
Output DACs with Internal Reference
and SPI Interface
CONFIG Command
REF Command
The CONFIG command (B[23:17] = 0110000) updates
the LOAD functions of selected DACs. Issue the com-
mand with B16 = 0 to allow the DAC latches to operate
normally or with B16 = 1 to disable the DAC latches,
making them perpetually transparent. Mode settings of
the selected DACs are updated while the mode settings
of the rest of the DACs remain unchanged; DAC(s) are
selected by bits B[9:8]. See Table 6.
The REF command updates the global reference setting
used for all DAC channels. Set B[17:16] = 00 to use an
external reference for the DACs or set B[17:16] to 01, 10,
or 11 to select either the 2.5V, 2.048V, or 4.096V internal
reference, respectively.
If RF2 (B18) is set to zero (default) in the REF command,
the reference will be powered down any time all DAC
channels are powered down (in STANDBY mode). If RF2
(B18 = 1) is set to one, the reference will remain powered
even if all DAC channels are powered down, allowing
continued operation of external circuitry. In this mode,
the 1FA shutdown state is not available. See Table 7.
Table 6. CONFIG Command Format
B23 B22 B21 B20 B19 B18 B17 B16 B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
0
1
1
0
0
0
0
LDB
X
X
X
X
X
X
B
A
X
X
X
X
X
X
X
X
Multiple
DAC
Selection:
1 = DAC
Selected
0 = DAC Not
Selected
CONFIG Command
Don’t Care
Don’t Care
Default Values (all DACs) →
0
X
X
X
X
X
X
1
1
X
X
X
X
X
X
X
X
Table 7. REF Command Format
B23 B22 B21 B20 B19 B18 B17 B16 B15 B14 B13 B12 B11 B10 B9 B8
B7 B6 B5 B4 B3 B2 B1 B0
X X X X X X
0
1
1
1
0
RF2 RF1 RF0
X
X
X
X
X
X
X
X
X
X
REF Mode:
00 = EXT
01 = 2.5V
10 = 2.0V
11 = 4.0V
REF Command
Don’t Care
Don’t Care
Default Values →
0
0
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Maxim Integrated
│ 21
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MAX5700/MAX5701/
MAX5702
Ultra-Small, Dual-Channel, 8-/10-/12-Bit Buffered
Output DACs with Internal Reference
and SPI Interface
Offset Error
Applications Information
Offset error indicates how well the actual transfer function
matches the ideal transfer function. The offset error is
calculated from two measurements near zero code and
near maximum code.
Power-On Reset (POR)
When power is applied to V
and V
, the DAC out-
DD
DDIO
put is set to zero scale. To optimize DAC linearity, wait
until the supplies have settled and the internal setup and
calibration sequence completes (200Fs, typ).
Gain Error
Gain error is the difference between the ideal and the
actual full-scale output voltage on the transfer curve,
after nullifying the offset error. This error alters the slope
of the transfer function and corresponds to the same
percentage error in each step.
Power Supplies and
Bypassing Considerations
Bypass V
and V
with high-quality ceramic capac-
DD
DDIO
itors to a low-impedance ground as close as possible to
the device. Minimize lead lengths to reduce lead induc-
tance. Connect the GND to the analog ground plane.
Zero-Scale Error
Zero-scale error is the difference between the DAC
output voltage when set to code zero and ground. This
includes offset and other die level nonidealities.
Layout Considerations
Digital and AC transient signals on GND can create noise
at the output. Connect GND to form the star ground for
the DAC system. Refer remote DAC loads to this system
ground for the best possible performance. Use proper
grounding techniques, such as a multilayer board with a
low-inductance ground plane, or star connect all ground
return paths back to the MAX5700/MAX5701/MAX5702
GND. Carefully layout the traces between channels to
reduce AC cross-coupling. Do not use wire-wrapped
boards and sockets. Use shielding to minimize noise immu-
nity. Do not run analog and digital signals parallel to one
another, especially clock signals. Avoid routing digital lines
underneath the MAX5700/MAX5701/MAX5702 package.
Full-Scale Error
Full-scale error is the difference between the DAC output
voltage when set to full scale and the reference volt-
age. This includes offset, gain error, and other die level
nonidealities.
Settling Time
The settling time is the amount of time required from the
start of a transition, until the DAC output settles to the new
output value within the converter’s specified accuracy.
Digital Feedthrough
Digital feedthrough is the amount of noise that appears
on the DAC output when the DAC digital control lines are
toggled.
Definitions
Integral Nonlinearity (INL)
INL is the deviation of the measured transfer function
from a straight line drawn between two codes once offset
and gain errors have been nullified.
Digital-to-Analog Glitch Impulse
A major carry transition occurs at the midscale point
where the MSB changes from low to high and all other
bits change from high to low, or where the MSB changes
from high to low and all other bits change from low to
high. The duration of the magnitude of the switching
glitch during a major carry transition is referred to as the
digital-to-analog glitch impulse.
Differential Nonlinearity (DNL)
DNL is the difference between an actual step height and
the ideal value of 1 LSB. If the magnitude of the DNL P
1 LSB, the DAC guarantees no missing codes and is
monotonic. If the magnitude of the DNL R1 LSB, the DAC
output may still be monotonic.
The digital-to-analog power-up glitch is the duration of
the magnitude of the switching glitch that occurs as the
device exits power-down mode.
Maxim Integrated
│ 22
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MAX5700/MAX5701/
MAX5702
Ultra-Small, Dual-Channel, 8-/10-/12-Bit Buffered
Output DACs with Internal Reference
and SPI Interface
Detailed Functional Diagram
V
REF
DD
100kI R
IN
MAX5700
MAX5701
MAX5702
INTERNAL /EXTERNAL REFERENCE (USER OPTION)
CODE
REGISTER
A
DAC
LATCH
A
8-/10-/12-BIT
DAC A
OUTA
BUFFER A
V
DDIO
CSB
CLEAR/
RESET
CLEAR/
RESET
CODE
LOAD
100kI
1kI
POWER-DOWN
DAC CONTROL LOGIC
SCLK
DIN
SPI SERIAL
INTERFACE
CODE
REGISTER
B
DAC
LATCH
B
8-/10-/12-BIT
DAC B
OUTB
BUFFER B
CLR
CLEAR/
RESET
CLEAR/
RESET
CODE
LOAD
100kI
1kI
POR
POWER-DOWN
DAC CONTROL LOGIC
GND
Maxim Integrated
│ 23
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MAX5700/MAX5701/
MAX5702
Ultra-Small, Dual-Channel, 8-/10-/12-Bit Buffered
Output DACs with Internal Reference
and SPI Interface
Typical Operating Circuits
100nF
100nF
4.7µF
V
V
DDIO
DD
OUT
V
OUT
= -V TO +V
REF
REF
DAC
CSB
SCLK
DIN
MAX5700
MAX5701
MAX5702
µC
R1
R2
REF
CLR
R1 = R2
GND
NOTE: BIPOLAR OPERATING CIRCUIT, ONE CHANNEL SHOWN
100nF
100nF
4.7µF
V
V
DDIO
DD
V
= 0V TO V
REF
OUT
OUT
DAC
CSB
MAX5700
MAX5701
MAX5702
SCLK
DIN
µC
REF
CLR
GND
NOTE: UNIPOLAR OPERATING CIRCUIT, ONE CHANNEL SHOWN
Maxim Integrated
│ 24
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MAX5700/MAX5701/
MAX5702
Ultra-Small, Dual-Channel, 8-/10-/12-Bit Buffered
Output DACs with Internal Reference
and SPI Interface
Ordering Information
PART
MAX5700ATB+T
MAX5700AUB+
MAX5701ATB+T
MAX5701AUB+
MAX5702AAUB+
MAX5702BATB+T
MAX5702BAUB+
PIN-PACKAGE
10 TDFN-EP*
10 µMAX
RESOLUTION (BIT)
INTERNAL REFERENCE TEMPCO (ppm/NC)
10 (typ), 25 (max)
8
8
10 (typ), 25 (max)
10 TDFN-EP*
10 µMAX
10
10
12
12
12
10 (typ), 25 (max)
10 (typ), 25 (max)
10 µMAX
3 (typ), 10 (max)
10 TDFN-EP*
10 µMAX
10 (typ), 25 (max)
10 (typ), 25 (max)
Note: All devices are specified over the -40°C to +125°C temperature range.
+Denotes a lead(Pb)-free/RoHS-compliant package.
T = Tape and reel.
*EP = Exposed pad.
Chip Information
PROCESS: BiCMOS
Package Information
For the latest package outline information and land patterns
(footprints), go to www.maximintegrated.com/packages. Note
that a “+”, “#”, or “-” in the package code indicates RoHS status
only. Package drawings may show a different suffix character, but
the drawing pertains to the package regardless of RoHS status.
PACKAGE
TYPE
PACKAGE
CODE
OUTLINE
NO.
LAND
PATTERN NO.
10 µMAX
U10+2
21-0061
21-0137
90-0330
90-0003
10 TDFN-EP
T1033+1
Maxim Integrated
│ 25
www.maximintegrated.com
MAX5700/MAX5701/
MAX5702
Ultra-Small, Dual-Channel, 8-/10-/12-Bit Buffered
Output DACs with Internal Reference
and SPI Interface
Revision History
REVISION REVISION
PAGES
DESCRIPTION
CHANGED
NUMBER
DATE
0
1
9/12
Initial release
—
12/12
Updated Electrical Characteristics and Ordering Information
7, 25
Removed future product asterisks for µMAX and TDFN products in the Ordering
Information. Updated Input Capacitance in the Electrical Characteristics.
2
8/13
6, 25
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses
are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits)
shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
©
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.
2014 Maxim Integrated Products, Inc.
│ 26
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