MAX5522 [MAXIM]
Dual, Ultra-Low-Power, 10-Bit, Voltage-Output DACs;
| 型号： | MAX5522 |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Dual, Ultra-Low-Power, 10-Bit, Voltage-Output DACs |
| 文件： | 总23页 (文件大小：1157K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-3064; Rev 1; 12/04
Dual, Ultra-Low-Power,
10-Bit, Voltage-Output DACs
General Description
Features
The MAX5522–MAX5525 are dual, 10-bit, ultra-low-
power, voltage-output, digital-to-analog converters
(DACs) offering rail-to-rail buffered voltage outputs. The
DACs operate from a 1.8V to 5.5V supply and consume
less than 5µA, making the devices suitable for low-
power and low-voltage applications. A shutdown mode
reduces overall current, including the reference input
current, to just 0.18µA. The MAX5522–MAX5525 use a
3-wire serial interface that is compatible with SPI™,
QSPI™, and MICROWIRE™.
♦ Ultra-Low 5µA Supply Current
♦ Shutdown Mode Reduces Supply Current to
0.18µA (max)
♦ Single +1.8V to +5.5V Supply
♦ Small 4mm x 4mm x 0.8mm Thin QFN Package
♦ Internal Reference Sources 8mA of Current
(MAX5523/MAX5525)
♦ Flexible Force-Sense-Configured Rail-to-Rail
Output Buffers
Upon power-up, the MAX5522–MAX5525 outputs are
driven to zero scale, providing additional safety for
applications that drive valves or for other transducers
that need to be off during power-up. The zero-scale
outputs enable glitch-free power-up.
♦ Fast 16MHz, 3-Wire, SPI-/QSPI-/MICROWIRE-
Compatible Serial Interface
♦ TTL- and CMOS-Compatible Digital Inputs with
Hysteresis
The MAX5522 accepts an external reference input and
provides unity-gain outputs. The MAX5523 contains a
precision internal reference and provides a buffered
external reference output with unity-gain DAC outputs.
The MAX5524 accepts an external reference input and
provides force-sense outputs. The MAX5525 contains a
precision internal reference and provides a buffered
external reference output with force-sense DAC outputs.
♦ Glitch-Free Outputs During Power-Up
Ordering Information
PART
TEMP RANGE
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
PIN-PACKAGE
8 µMAX
MAX5522EUA
MAX5523EUA
MAX5524ETC
MAX5525ETC
8 µMAX
12 Thin QFN-EP*
12 Thin QFN-EP*
The MAX5524/MAX5525 are available in a 4mm x 4mm
x 0.8mm, 12-pin, thin QFN package. The MAX5522/
MAX5523 are available in an 8-pin µMAX package. All
devices are guaranteed over the extended -40°C to
+85°C temperature range.
*EP = Exposed paddle (internally connected to GND).
Selector Guide
For 12-bit compatible devices, refer to the MAX5532–
MAX5535 data sheet. For 8-bit compatible devices,
refer to the MAX5512–MAX5515 data sheet.
PART
OUTPUTS
Unity gain
Unity gain
REFERENCE TOP MARK
MAX5522EUA
MAX5523EUA
External
Internal
External
Internal
—
—
Applications
Portable Battery-Powered Devices
Instrumentation
MAX5524ETC Force sense
MAX5525ETC Force sense
AACK
AACL
Automatic Trimming and Calibration in Factory
or Field
Pin Configurations
Programmable Voltage and Current Sources
TOP VIEW
Industrial Process Control and Remote
Industrial Devices
CS
SCLK
DIN
1
2
3
4
8
7
6
5
OUTA
GND
Remote Data Conversion and Monitoring
Chemical Sensor Cell Bias for Gas Monitors
Programmable LCD Bias
MAX5522
MAX5523
V
DD
REFIN(MAX5522)
OUTB
REFOUT(MAX5523)
µMAX
SPI and QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corp.
Pin Configurations continued at end of data sheet.
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
Dual, Ultra-Low-Power,
10-Bit, Voltage-Output DACs
ABSOLUTE MAXIMUM RATINGS
DD
OUTA, OUTB to GND.................................-0.3V to (V
FBA, FBB to GND.......................................-0.3V to (V
SCLK, DIN, CS to GND ..............................-0.3V to (V
V
to GND..............................................................-0.3V to +6V
Operating Temperature Range ...........................-40°C to +85°C
Storage Temperature Range.............................-65°C to +150°C
Junction Temperature......................................................+150°C
Lead Temperature (soldering, 10s) .................................+300°C
+ 0.3V)
+ 0.3V)
+ 0.3V)
DD
DD
DD
REFIN, REFOUT to GND ............................-0.3V to (V + 0.3V)
DD
Continuous Power Dissipation (T = +70°C)
A
12-Pin Thin QFN (derate 16.9mW/°C above +70°C).....1349mW
8-Pin µMAX (derate 5.9mW/°C above +70°C).............471mW
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V = +1.8V to +5.5V, OUT_ unloaded, T = T
to T
, unless otherwise noted. Typical values are at T = +25°C.)
MAX A
DD
A
MIN
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
STATIC ACCURACY (MAX5522/MAX5524 EXTERNAL REFERENCE)
Resolution
N
10
Bits
V
V
= 5V, V
= 4.096V
REF
1
1
4
4
DD
DD
Integral Nonlinearity (Note 1)
INL
LSB
= 1.8V, V
= 1.024V
REF
Guaranteed monotonic, V
= 5V,
DD
0.2
0.2
1
1
V
= 4.096V
REF
Differential Nonlinearity (Note 1)
DNL
LSB
Guaranteed monotonic, V
= 1.8V,
DD
V
V
V
= 1.024V
REF
DD
DD
= 5V, V
= 4.096V
1
1
20
20
REF
Offset Error (Note 2)
V
mV
µV/°C
LSB
OS
= 1.8V, V
= 1.024V
REF
Offset-Error Temperature Drift
Gain Error (Note 3)
2
V
V
= 5V, V
= 4.096V
REF
0.5
0.5
2
2
DD
DD
GE
= 1.8V, V
= 1.024V
REF
Gain-Error Temperature
Coefficient
4
ppm/°C
Power-Supply Rejection Ratio
PSRR
1.8V ≤ V
≤ 5.5V
85
dB
DD
STATIC ACCURACY (MAX5523/MAX5525 INTERNAL REFERENCE)
Resolution
N
10
Bits
V
V
= 5V, V
= 3.9V
REF
1
1
4
4
DD
DD
Integral Nonlinearity (Note 1)
INL
LSB
= 1.8V, V
= 1.2V
REF
Guaranteed monotonic, V
= 5V,
DD
DD
0.2
0.2
1
1
V
= 3.9V
REF
Differential Nonlinearity (Note 1)
DNL
LSB
Guaranteed monotonic, V
= 1.8V,
V
V
V
= 1.2V
REF
DD
DD
= 5V, V
= 3.9V
1
1
20
20
REF
Offset Error (Note 2)
V
mV
µV/°C
LSB
OS
= 1.8V, V
= 1.2V
REF
Offset-Error Temperature Drift
Gain Error (Note 3)
2
V
V
= 5V, V
= 3.9V
REF
0.5
0.5
2
2
DD
DD
GE
= 1.8V, V
= 1.2V
REF
Gain-Error Temperature
Coefficient
4
ppm/°C
2
_______________________________________________________________________________________
Dual, Ultra-Low-Power,
10-Bit, Voltage-Output DACs
ELECTRICAL CHARACTERISTICS (continued)
(V = +1.8V to +5.5V, OUT_ unloaded, T = T
to T
, unless otherwise noted. Typical values are at T = +25°C.)
MAX A
DD
A
MIN
PARAMETER
Power-Supply Rejection Ratio
SYMBOL
CONDITIONS
≤ 5.5V
MIN
TYP
MAX
UNITS
PSRR
1.8V ≤ V
85
dB
DD
REFERENCE INPUT (MAX5522/MAX5524)
Reference-Input Voltage Range
V
0
V
V
REFIN
DD
Normal operation
In shutdown
4.1
MΩ
GΩ
Reference-Input Impedance
R
REFIN
2.5
REFERENCE OUTPUT (MAX5523/MAX5525)
No external load, V
No external load, V
No external load, V
No external load, V
= 1.8V
= 2.5V
= 3V
1.197
1.913
2.391
3.828
1.214
1.940
2.425
3.885
1.231
1.967
2.459
3.941
DD
DD
DD
DD
Initial Accuracy
V
V
REFOUT
= 5V
Output-Voltage Temperature
Coefficient
V
T
= -40°C to +85°C (Note 4)
12
2
30
200
2
ppm/°C
TEMPCO
A
Line Regulation
V
< V
- 200mV (Note 5)
µV/V
REFOUT
DD
0 ≤ I
V
≤ 1mA, sourcing, V = 1.8V,
DD
REFOUT
0.3
= 1.2V
REF
Load Regulation
µV/µA
0 ≤ I
≤ 8mA, sourcing, V = 5V,
DD
REFOUT
= 3.9V
0.3
2
V
REF
-150µA ≤ I
≤ 0, sinking
0.2
150
600
50
REFOUT
0.1Hz to 10Hz, V
= 3.9V
= 3.9V
= 1.2V
= 1.2V
REF
10Hz to 10kHz, V
REF
REF
Output Noise Voltage
µV
P-P
0.1Hz to 10Hz, V
10Hz to 10kHz, V
450
30
REF
V
V
= 5V
DD
DD
Short-Circuit Current (Note 6)
mA
= 1.8V
14
Capacitive Load Stability Range
Thermal Hysteresis
(Note 7)
(Note 8)
0 to 10
200
5.4
nF
ppm
REFOUT unloaded, V
REFOUT unloaded, V
= 5V
DD
DD
Reference Power-Up Time
(from Shutdown)
ms
= 1.8V
4.4
ppm/
1khrs
Long-Term Stability
200
DAC OUTPUTS (OUTA, OUTB)
Capacitive Driving Capability
C
1000
pF
L
V
= 5V, V
set to full scale, OUT
OUT
DD
65
65
14
14
shorted to GND, source current
V
V
= 5V V
set to 0V, OUT shorted to
OUT
DD
DD
, sink current
Short-Circuit Current (Note 6)
mA
V
= 1.8V, V
set to full scale OUT
OUT
DD
shorted to GND, source current
V
V
= 1.8V, V
, sink current
set to 0V, OUT shorted to
OUT
DD
DD
_______________________________________________________________________________________
3
Dual, Ultra-Low-Power,
10-Bit, Voltage-Output DACs
ELECTRICAL CHARACTERISTICS (continued)
(V = +1.8V to +5.5V, OUT_ unloaded, T = T
to T
, unless otherwise noted. Typical values are at T = +25°C.)
MAX A
DD
A
MIN
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
3
MAX
UNITS
V
= 5V
DD
DD
Coming out of shutdown
(MAX5522/MAX5524)
V
= 1.8V
= 1.8V to
3.8
DAC Power-Up Time
µs
Coming out of standby
(MAX5523/MAX5525)
V
5.5V
DD
0.4
Output Power-Up Glitch
FB_ Input Current
C = 100pF
L
10
10
mV
pA
DIGITAL INPUTS (SCLK, DIN, CS)
4.5V ≤ V
2.7V < V
1.8V ≤ V
4.5V ≤ V
2.7V < V
1.8V ≤ V
(Note 9)
≤ 5.5V
≤ 3.6V
≤ 2.7V
≤ 5.5V
≤ 3.6V
≤ 2.7V
2.4
2.0
DD
DD
DD
DD
DD
DD
Input High Voltage
Input Low Voltage
V
V
V
IH
0.7 x V
DD
0.8
0.6
V
IL
0.3 x V
DD
Input Leakage Current
Input Capacitance
I
0.05
10
0.5
µA
pF
IN
C
IN
DYNAMIC PERFORMANCE
Voltage-Output Slew Rate
SR
Positive and negative (Note 10)
10
V/ms
µs
0.1 to 0.9 of full scale to within 0.5 LSB
(Note 10)
Voltage-Output Settling Time
660
V
V
V
V
= 5V
80
55
DD
DD
DD
DD
0.1Hz to 10Hz
10Hz to 10kHz
= 1.8V
= 5V
Output Noise Voltage
µV
P-P
620
476
= 1.8V
POWER REQUIREMENTS
Supply Voltage Range
V
1.8
5.5
8.0
8.0
8.0
5.0
5.0
6.0
4.5
4.0
3.5
0.25
V
DD
V
V
V
V
V
V
V
V
V
= 5V
7.0
6.4
7.0
3.8
3.8
4.7
3.3
2.8
2.4
0.05
DD
DD
DD
DD
DD
DD
DD
DD
DD
MAX5523/MAX5525
MAX5522/MAX5524
= 3V
= 1.8V
= 5V
Supply Current (Note 9)
I
µA
DD
= 3V
= 1.8V
= 5V
MAX5523/MAX5525
(Note 9)
Standby Supply Current
Shutdown Supply Current
I
I
µA
µA
= 3V
DDSD
DDPD
= 1.8V
(Note 9)
4
_______________________________________________________________________________________
Dual, Ultra-Low-Power,
10-Bit, Voltage-Output DACs
TIMING CHARACTERISTICS
(V
= +4.5V to +5.5V, T = T
A
to T
, unless otherwise noted. Typical values are at T = +25°C.)
MAX A
DD
MIN
PARAMETER
SYMBOL
= 4.5V to 5.5V )
CONDITIONS
MIN
TYP
MAX
UNITS
TIMING CHARACTERISTICS (V
Serial Clock Frequency
DD
f
0
15
0
16.7
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
SCLK
DIN to SCLK Rise Setup Time
DIN to SCLK Rise Hold Time
SCLK Pulse-Width High
t
DS
DH
CH
t
t
24
24
100
0
SCLK Pulse-Width Low
t
CL
CS Pulse-Width High
t
CSW
SCLK Rise to CS Rise Hold Time
CS Fall to SCLK Rise Setup Time
SCLK Fall to CS Fall Setup
CS Rise to SCK Rise Hold Time
t
CSH
t
20
0
CSS
CSO
t
t
20
CS1
TIMING CHARACTERISTICS
(V
= +1.8V to +5.5V, T = T
A
to T
, unless otherwise noted. Typical values are at T = +25°C.)
A
DD
MIN
MAX
SYMBOL
= 1.8V to 5.5V )
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
TIMING CHARACTERISTICS (V
Serial Clock Frequency
DD
f
0
24
0
10
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
SCLK
DIN to SCLK Rise Setup Time
DIN to SCLK Rise Hold Time
SCLK Pulse-Width High
t
DS
DH
CH
t
t
40
40
150
0
SCLK Pulse-Width Low
t
CL
CS Pulse-Width High
t
CSW
SCLK Rise to CS Rise Hold Time
CS Fall to SCLK Rise Setup Time
SCLK Fall to CS Fall Setup
CS Rise to SCK Rise Hold Time
t
CSH
t
30
0
CSS
CSO
t
t
30
CS1
Note 1: Linearity is tested within codes 24 to 1020.
Note 2: Offset is tested at code 24.
Note 3: Gain is tested at code 1023. For the MAX5524/MAX5525, FB_ is connected to its respective OUT_.
Note 4: Guaranteed by design. Not production testsed
Note 5:
V
DD
must be a minimum of 1.8V.
Note 6: Outputs can be shorted to V
or GND indefinitely, provided that package power dissipation is not exceeded.
DD
Note 7: Optimal noise performance is at 2nF load capacitance.
Note 8: Thermal hysteresis is defined as the change in the initial +25°C output voltage after cycling the device from T
to T
.
MIN
MAX
Note 9: All digital inputs at V
or GND.
DD
Note 10: Load = 10kΩ in parallel with 100pF, V
= 5V, V
= 4.096V (MAX5522/MAX5524) or V
= 3.9V (MAX5523/MAX5525).
DD
REF
REF
_______________________________________________________________________________________
5
Dual, Ultra-Low-Power,
10-Bit, Voltage-Output DACs
Typical Operating Characteristics
(V
= 5.0V, V
= 4.096V (MAX5522/MAX5524), VREF = 3.9V (MAX5523/MAX54525), T = +25°C, unless otherwise noted.)
REF
A
DD
SUPPLY CURRENT vs. SUPPLY VOLTAGE
(MAX5522/MAX5524)
SUPPLY CURRENT vs. TEMPERATURE
(MAX5522/MAX5524)
SUPPLY CURRENT vs. SUPPLY VOLTAGE
(MAX5523/MAX5525)
5.0
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
10
9
8
7
6
5
4
3
2
1
0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
SUPPLY VOLTAGE (V)
-40
-15
10
35
60
85
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
SUPPLY VOLTAGE (V)
TEMPERATURE (°C)
SUPPLY CURRENT vs. TEMPERATURE
(MAX5523/MAX5525)
SHUTDOWN SUPPLY CURRENT
vs. TEMPERATURE (MAX5522/MAX5524)
SHUTDOWN SUPPLY CURRENT
vs. TEMPERATURE (MAX5523/MAX5525)
10
9
8
7
6
5
4
3
2
1
0
1000
100
10
1000
100
10
1
1
0.1
0.1
-40
-15
10
35
60
85
-40
-15
10
35
60
85
-40
-15
10
35
60
85
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
SUPPLY CURRENT
vs. CLOCK FREQUENCY
SUPPLY CURRENT
vs. LOGIC INPUT VOLTAGE
STANDBY SUPPLY CURRENT
vs. TEMPERATURE (MAX5523/MAX5525)
1000
100
10
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
V
= 5V
DD
CS = LOGIC LOW
CODE = 0
ALL DIGITAL INPUTS
SHORTED TOGETHER
V
= 5V
V
= 3.9V
DD
REF
V
= 2.4V
REF
V
= 1.9V
REF
V
= 1.2V
REF
V
= 1.8V
DD
1
0.01 0.1
1
10 100 1000 10000100000
FREQUENCY (kHz)
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
LOGIC INPUT VOLTAGE (V)
-40
-15
10
35
60
85
TEMPERATURE (°C)
6
_______________________________________________________________________________________
Dual, Ultra-Low-Power,
10-Bit, Voltage-Output DACs
Typical Operating Characteristics (continued)
(V
= 5.0V, V
= 4.096V (MAX5522/MAX5524), VREF = 3.9V (MAX5523/MAX54525), T = +25°C, unless otherwise noted.)
REF
A
DD
INL vs. INPUT CODE
DNL vs. INPUT CODE
INL vs. INPUT CODE
(V = V = 5V)
(V = V
= 1.8V)
(V = V
= 1.8V)
DD
REF
DD
REF
DD
REF
0.4
0.06
0.05
0.04
0.03
0.02
0.01
0
0.4
0.2
0.2
0
0
-0.2
-0.4
-0.6
-0.8
-1.0
-1.2
-0.2
-0.4
-0.6
-0.8
-1.0
-1.2
-0.01
-0.02
-0.03
0
200
400
600
800 1000 1200
0
200
400
600
800 1000 1200
0
200
400
600
800 1000 1200
DIGITAL INPUT CODE
DIGITAL INPUT CODE
DIGITAL INPUT CODE
OFFSET VOLTAGE
vs. TEMPERATURE
DNL vs. INPUT CODE
GAIN ERROR CHANGE
vs. TEMPERATURE
(V = V
= 5V)
DD
REF
1.0
0.8
0.6
0.4
0.2
0
0.04
0.03
0.02
0.01
0
0.10
0.08
0.06
0.04
0.02
0
V
V
= 5V
DD
V
V
= 5V
DD
= 3.9V
REF
= 3.9V
REF
-0.2
-0.02
-0.04
-0.06
-0.08
-0.10
-0.4
-0.6
-0.8
-1.0
-0.01
-0.02
-0.03
-40
-15
10
35
60
85
0
200
400
600
800 1000 1200
-40
-15
10
35
60
85
TEMPERATURE (°C)
DIGITAL INPUT CODE
TEMPERATURE (°C)
DAC OUTPUT LOAD REGULATION
vs. OUTPUT CURRENT
DAC OUTPUT LOAD REGULATION
vs. OUTPUT CURRENT
DIGITAL FEEDTHROUGH RESPONSE
MAX5522 toc16
1.9440
1.9435
1.9430
1.9425
1.9420
1.9415
1.9410
1.9405
1.9400
0.6050
0.6048
0.6046
0.6044
0.6042
0.6040
ZERO SCALE
V
= 5.0V
DD
V
= 1.8V
DD
DAC CODE = MIDSCALE
= 3.9V
CS
5V/div
DAC CODE = MIDSCALE
= 1.2V
V
REF
V
REF
SCLK
5V/div
DIN
5V/div
OUT
50mV/div
-10 -8 -6 -4 -2
0
2
4
6
8
10
-1000-800 -600-400 -200
0
200 400 600 800 1000
20µs/div
DAC OUTPUT CURRENT (mA)
DAC OUTPUT CURRENT (µA)
_______________________________________________________________________________________
7
Dual, Ultra-Low-Power,
10-Bit, Voltage-Output DACs
Typical Operating Characteristics (continued)
(V
= 5.0V, V
= 4.096V (MAX5522/MAX5524), VREF = 3.9V (MAX5523/MAX54525), T = +25°C, unless otherwise noted.)
DD
REF
A
OUTPUT LARGE-SIGNAL STEP RESPONSE
(V = 1.8V, V = 1.2V)
DAC OUTPUT VOLTAGE
vs. OUTPUT SOURCE CURRENT
DAC OUTPUT VOLTAGE
vs. OUTPUT SINK CURRENT
DD
REF
MAX5522 toc21
5
4
3
2
1
0
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
V
= V
V
= V
REF
DD
REF
DD
CODE = MIDSCALE
CODE = MIDSCALE
V
= 5V
DD
V
V
= 5V
= 3V
DD
DD
V
OUT
200mV/div
V
= 3V
DD
V
= 1.8V
DD
V
= 1.8V
DD
0.001
0.010
0.100
1
10
100
0.001
0.01
0.1
1
10
100
100µs/div
OUTPUT SOURCE CURRENT (mA)
OUTPUT SINK CURRENT (mA)
OUTPUT MINIMUM SERIES RESISTANCE
vs. LOAD CAPACITANCE
OUTPUT LARGE-SIGNAL STEP RESPONSE
(V = 5V, V = 3.9V)
POWER-UP OUTPUT VOLTAGE GLITCH
DD
REF
MAX5522 toc22
MAX5522 toc24
600
500
400
300
200
100
0
FOR NO OVERSHOOT
V
DD
2V/div
V
OUT
500mV/div
V
OUT
10mV/div
0.0001 0.001 0.01
0.1
1
10
100
200µs/div
20ms/div
CAPACITANCE (µF)
MAJOR CARRY OUTPUT VOLTAGE GLITCH
(CODE 7FFh TO 800h)
REFERENCE OUTPUT VOLTAGE
vs. TEMPERATURE
REFERENCE OUTPUT VOLTAGE
vs. REFERENCE OUTPUT CURRENT
(V = 5V, V
= 3.9V)
DD
REF
MAX5522 toc25
3.940
3.935
3.930
3.925
3.920
3.915
3.910
3.905
3.900
1.220
1.219
1.218
1.217
1.216
1.215
1.214
V
= 5V
DD
V
= 1.8V
DD
V
OUT
AC-COUPLED
5mV/div
-40
-15
10
35
60
85
-500
1500
3500
5500
7500
100µs/div
TEMPERATURE (°C)
REFERENCE OUTPUT CURRENT (µA)
8
_______________________________________________________________________________________
Dual, Ultra-Low-Power,
10-Bit, Voltage-Output DACs
Typical Operating Characteristics (continued)
(V
= 5.0V, V
= 4.096V (MAX5522/MAX5524), VREF = 3.9V (MAX5523/MAX54525), T = +25°C, unless otherwise noted.)
REF
A
DD
REFERENCE OUTPUT VOLTAGE
vs. REFERENCE OUTPUT CURRENT
REFERENCE LINE-TRANSIENT RESPONSE
(V = 1.2V)
REFERENCE OUTPUT VOLTAGE
vs. SUPPLY VOLTAGE
REF
MAX5522 toc30
3.92
3.91
3.90
3.89
3.88
1.21750
1.21748
1.21746
1.21744
1.21742
1.21740
1.21738
1.21736
1.21734
1.21732
1.21730
V
= 5V
DD
2.8V
V
DD
1.8V
V
REF
500mV/div
-500 2000 4500 7000 9500 12,000 14,500
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
SUPPLY VOLTAGE (V)
100µs/div
REFERENCE OUTPUT CURRENT (µA)
REFERENCE LOAD TRANSIENT
REFERENCE LINE-TRANSIENT RESPONSE
(V = 3.9V)
(V = 1.8V)
DD
REF
MAX5522 toc32
MAX5522 toc31
5.5V
V
DD
REFOUT
SOURCE
CURRENT
0.5mA/div
4.5V
V
REF
500mV/div
V
REF
3.9V
500mV/div
200µs/div
100µs/div
REFERENCE LOAD TRANSIENT
REFERENCE LOAD TRANSIENT
(V = 1.8V)
DD
(V = 5V)
DD
MAX5522 toc34
MAX5522 toc33
REFOUT
REFOUT
SINK
CURRENT
50µA/div
SOURCE
CURRENT
0.5mA/div
V
REF
V
REF
500mV/div
500mV/div
3.9V
200µs/div
200µs/div
_______________________________________________________________________________________
9
Dual, Ultra-Low-Power,
10-Bit, Voltage-Output DACs
Typical Operating Characteristics (continued)
(V
= 5.0V, V
= 4.096V (MAX5522/MAX5524), VREF = 3.9V (MAX5523/MAX54525), T = +25°C, unless otherwise noted.)
DD
REF
A
REFERENCE LOAD TRANSIENT
(V = 5V)
DD
REFERENCE PSRR vs. FREQUENCY
MAX5522 toc35
80
70
60
50
40
30
20
10
0
V
DD
= 1.8V
REFOUT
SINK
CURRENT
100µA/div
V
REF
500mV/div
3.9V
0.01
0.1
1
10
100
1000
200µs/div
FREQUENCY (kHz)
REFERENCE OUTPUT NOISE
(0.1Hz TO 10Hz) (V = 1.8V, V
= 1.2V)
REFERENCE PSRR vs. FREQUENCY
= 5V
DD
REF
MAX5522 toc38
80
70
60
50
40
30
20
10
0
V
DD
100µV/div
0.01
0.1
1
10
100
1000
1s/div
FREQUENCY (kHz)
REFERENCE OUTPUT NOISE
(0.1Hz TO 10Hz) (V = 5V, V
= 3.9V)
DAC-TO-DAC CROSSTALK
DD
REF
MAX5522 toc39
MAX5522 toc40
OUTA
1V/div
100µV/div
OUTB
AC-COUPLED
10mV/div
OUTB AT FULL SCALE
1s/div
400µs/div
10 ______________________________________________________________________________________
Dual, Ultra-Low-Power,
10-Bit, Voltage-Output DACs
Pin Description
PIN
NAME
FUNCTION
MAX5522
MAX5523
MAX5524
MAX5525
1
2
1
2
1
2
1
2
CS
SCLK
DIN
Active-Low Digital Chip-Select Input
Serial-Interface Clock Input
Serial-Interface Data Input
Reference Input
3
3
3
3
4
—
4
4
—
4
REFIN
REFOUT
—
—
Reference Output
No Connection. Leave N.C. inputs unconnected
(floating) or connected to GND.
—
—
5, 11
5, 11
N.C.
—
5
—
5
6
7
6
7
FBB
Channel B Feedback Input
OUTB
Channel B Analog Voltage Output
Power Input. Connect V
to a 1.8V to 5.5V power
DD
6
6
8
8
V
DD
supply. Bypass V
to GND with a 0.1µF capacitor.
DD
7
8
7
8
9
9
GND
OUTA
FBA
Ground
10
12
EP
10
12
EP
Channel A Analog Voltage Output
Channel A Feedback Input
—
—
—
—
Exposed Paddle Exposed Paddle. Connect EP to GND.
Functional Diagrams
V
REFIN
DD
POWER-
DOWN
CONTROL
MAX5522
INPUT
REGISTER
DAC
REGISTER
10-BIT DAC
10-BIT DAC
CONTROL
LOGIC
AND
SHIFT
REGISTER
SCLK
DIN
CS
OUTA
OUTB
INPUT
REGISTER
DAC
REGISTER
GND
______________________________________________________________________________________ 11
Dual, Ultra-Low-Power,
10-Bit, Voltage-Output DACs
Functional Diagrams (continued)
V
DD
POWER-
DOWN
CONTROL
2-BIT
PROGRAMMABLE
REFERENCE
REF
BUF
REFOUT
OUTA
MAX5523
INPUT
REGISTER
DAC
REGISTER
10-BIT DAC
10-BIT DAC
CONTROL
LOGIC
AND
SHIFT
REGISTER
SCLK
DIN
CS
INPUT
REGISTER
DAC
REGISTER
OUTB
GND
V
DD
REFIN
POWER-
DOWN
CONTROL
MAX5524
INPUT
REGISTER
DAC
REGISTER
10-BIT DAC
10-BIT DAC
CONTROL
LOGIC
AND
SHIFT
REGISTER
SCLK
DIN
CS
OUTA
FBA
INPUT
REGISTER
DAC
REGISTER
OUTB
FBB
GND
12 ______________________________________________________________________________________
Dual, Ultra-Low-Power,
10-Bit, Voltage-Output DACs
Functional Diagrams (continued)
V
DD
POWER-
DOWN
CONTROL
2-BIT
PROGRAMMABLE
REFERENCE
REF
BUF
REFOUT
MAX5525
INPUT
REGISTER
DAC
REGISTER
10-BIT DAC
10-BIT DAC
CONTROL
LOGIC
AND
SHIFT
REGISTER
SCLK
DIN
CS
OUTA
FBA
INPUT
REGISTER
DAC
REGISTER
OUTB
FBB
GND
Digital Interface
Detailed Description
The MAX5522–MAX5525 use a 3-wire serial interface
that is compatible with SPI/QSPI/MICROWIRE protocols
(Figures 1 and 2).
The MAX5522–MAX5525 dual, 10-bit, ultra-low-power,
voltage-output DACs offer rail-to-rail buffered voltage
outputs. The DACs operate from a 1.8V to 5.5V supply
and require only 5µA (max) supply current. These
devices feature a shutdown mode that reduces overall
current, including the reference input current, to just
0.18µA (max) The MAX5523/MAX5525 include an inter-
nal reference that saves additional board space and
can source up to 8mA, making it functional as a system
reference. The 16MHz, 3-wire serial interface is com-
patible with SPI, QSPI, and MICROWIRE protocols.
The MAX5522–MAX5525 include a single, 16-bit, input
shift register. Data loads into the shift register through
the serial interface. CS must remain low until all 16 bits
are clocked in. The 16 bits consist of 4 control bits
(C3–C0), 10 data bits (D9–D0) (Table 1), and 2 sub-bits
(S1 and S0). D9–D0 are the DAC data bits and S1 and
S0 are the sub-bits. The sub-bits must be set to zero for
proper operation. Following the control bits, data loads
MSB first, D9–D0. The control bits C3–C0 control the
MAX5522–MAX5525, as outlined in Table 2.
When V
is applied, all DAC outputs are driven to
DD
zero scale with virtually no output glitch. The MAX5522/
MAX5523 output buffers are configured in unity gain
and come in µMAX packages. The MAX5524/MAX5525
output buffers are configured in force sense allowing
users to externally set voltage gains on the output (an
output-amplifier inverting input is available). The
MAX5524/MAX5525 come in 4mm x 4mm thin QFN
packages.
Each DAC channel includes two registers: an input reg-
ister and a DAC register. The input register holds input
data. The DAC register contains the data updated to
the DAC output.
The double-buffered register configuration allows any
of the following:
• Loading the input registers without updating the DAC
registers
• Updating the DAC registers from the input registers
• Updating all the input and DAC registers simultaneously
______________________________________________________________________________________ 13
Dual, Ultra-Low-Power,
10-Bit, Voltage-Output DACs
Table 1. Serial Write Data Format
CONTROL
DATA BITS
MSB
LSB
C3
C2
C1
C0
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
S1
S0
Sub-bits S1 to S0 must be set to zero for proper operation.
t
CH
SCLK
t
CL
t
DS
C3
C2
C1
S0
DIN
CS
t
CS0
t
t
DH
CSH
t
CSS
t
CSW
t
CS1
Figure 1. Timing Diagram
SCLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
DIN
CS
C3
C2
C1
C0
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
S1
S0
CONTROL BITS
DATA BITS
SUB-BITS
COMMAND
EXECUTED
Figure 2. Register Loading Diagram
14 ______________________________________________________________________________________
Dual, Ultra-Low-Power,
10-Bit, Voltage-Output DACs
Table 2. Serial-Interface Programming Commands
CONTROL BITS
INPUT DATA
D9–D0
SUB-BITS
FUNCTION
No operation; command is ignored.
C3
C2
C1
C0
S1 AND S0
0
0
0
0
XXXXXXXXXX
00
Load input register A from shift register; DAC registers unchanged;
DAC outputs unchanged.
0
0
0
0
0
1
1
0
10-bit data
10-bit data
00
00
Load input register B from shift register; DAC registers unchanged;
DAC outputs unchanged.
0
0
0
0
0
0
1
1
1
1
1
0
0
1
1
1
0
1
0
1
—
—
—
—
—
—
—
—
—
—
Command reserved. Do not use.
Command reserved. Do not use.
Command reserved. Do not use.
Command reserved. Do not use.
Command reserved. Do not use.
Load DAC registers A and B from respective input registers; DAC
outputs A and B updated; MAX5523/MAX5525 enter normal
operation if in standby or shutdown; MAX5522/MAX5524 enter
normal operation if in shutdown.
1
0
0
0
10-bit data
00
Load input register A and DAC register A from shift register; DAC
output A updated; Load DAC register B from input register B; DAC
output B updated; MAX5523/MAX5525 enter normal operation if in
standby or shutdown; MAX5522/MAX5524 enter normal operation
if in shutdown.
1
0
0
1
10-bit data
00
Load input register B and DAC register B from shift register; DAC
output B updated; Load DAC register A from input register A; DAC
output A updated; MAX5523/MAX5525 enter normal operation if in
standby or shutdown; MAX5522/MAX5524 enter normal operation
if in shutdown.
1
0
1
0
10-bit data
—
00
1
1
0
1
1
0
1
0
—
Command reserved. Do not use.
MAX5523/MAX5525 enter standby*, MAX5522/MAX5524 enter
shutdown. For the MAX5523/MAX5525, D9 and D8 configure the
internal reference voltage (Table 3).
D9, D8,
XXXXXXXX
00
MAX5522–MAX5525 enter normal operation; DAC outputs reflect
existing contents of DAC registers. For the MAX5523/MAX5525,
D9 and D8 configure the internal reference voltage (Table 3).
D9, D8,
XXXXXXXX
1
1
1
1
0
1
1
0
00
00
MAX5522–MAX5525 enter shutdown; DAC outputs set to high
impedance. For the MAX5523/MAX5525, D9 and D8 configure the
internal reference voltage (Table 3).
D9, D8,
XXXXXXXX
Load input registers A and B and DAC registers A and B from shift
register; DAC outputs A and B updated; MAX5523/MAX5525 enter
normal operation if in standby or shutdown; MAX5522/MAX5524
enter normal operation if in shutdown.
1
1
1
1
10-bit data
00
X = Don’t care.
*Standby mode can be entered from normal operation only. It is not possible to enter standby mode from shutdown.
______________________________________________________________________________________ 15
Dual, Ultra-Low-Power,
10-Bit, Voltage-Output DACs
For the MAX5523/MAX5525, standby mode cannot be
Power Modes
The MAX5522–MAX5525 feature two power modes to
conserve power during idle periods. In normal opera-
tion, the device is fully operational. In shutdown mode,
the device is completely powered down, including the
internal voltage reference in the MAX5523/MAX5525.
The MAX5523/MAX5525 also offer a standby mode in
which all circuitry is powered down except the internal
voltage reference. Standby mode keeps the reference
powered up while the remaining circuitry is shut down,
allowing it to be used as a system reference. It also
helps reduce the wake-up delay by not requiring the ref-
erence to power up when returning to normal operation.
entered directly from shutdown mode. The device must
be brought into normal operation first before entering
standby mode. To enter standby from shutdown, issue
the command to return to normal operation followed
immediately by the command to go into standby.
Table 2 shows several commands that bring the
MAX5523/MAX5525 back to normal operation. When
transitioning from standby mode to normal operation,
only the DAC power-up time is required before the DAC
outputs are valid.
Reference Input
The MAX5522/MAX5524 accept a reference with a volt-
Shutdown Mode
The MAX5522–MAX5525 feature a software-program-
mable shutdown mode that reduces the supply current
and the interface input-current to 0.18µA (max). Writing
an input control word with control bits C[3:0] = 1110
(Table 2) places the device in shutdown mode. In shut-
down, the MAX5522/MAX5524 reference input and DAC
output buffers go high impedance. Placing the MAX5523/
MAX5525 into shutdown turns off the internal reference
and the DAC output buffers go high impedance. The seri-
al interface still remains active for all devices.
age range extending from 0 to V . The output voltage
DD
(V
) is represented by a digitally programmable volt-
OUT
age source as:
V
OUT
= (V
x N / 256) x gain
REF
where N is the numeric value of the DAC’s binary input
code (0 to 1023), V is the reference voltage, gain is
REF
the externally set voltage gain for the MAX5524, and
gain is one for the MAX5522.
In shutdown mode, the reference input enters a high-
impedance state with an input impedance of 2.5GΩ (typ).
Table 2 shows several commands that bring the
MAX5522–MAX5525 back to normal operation. The
power-up time from shutdown is required before the
DAC outputs are valid.
Reference Output
The MAX5523/MAX5525 internal voltage reference is
software configurable to one of four voltages. Upon
power-up, the default reference voltage is 1.214V.
Configure the reference voltage using D8 and D9 data
bits (Table 3) when the control bits are as follows C[3:0]
Note: For the MAX5523/MAX5525, standby mode can-
not be entered directly from shutdown mode. The
device must be brought into normal operation first
before entering standby mode.
= 1100, 1101, or 1110 (Table 2). V
must be kept at a
DD
minimum of 200mV above V
for proper operation.
REF
Standby Mode (MAX5523/MAX5525 Only)
The MAX5523/MAX5525 feature a software-program-
mable standby mode that reduces the typical supply
current to 3µA (max). Standby mode powers down all
circuitry except the internal voltage reference. Place
the device in standby mode by writing an input control
word with control bits C[3:0] = 1100 (Table 2). The
internal reference and serial interface remain active
while the DAC output buffers go high impedance.
Table 3. Reference Output Voltage
Programming
D9
0
D8
0
REFERENCE VOLTAGE (V)
1.214
1.940
2.425
3.885
0
1
1
0
1
1
16 ______________________________________________________________________________________
Dual, Ultra-Low-Power,
10-Bit, Voltage-Output DACs
Programmable Current Source
Applications Information
See the circuit in Figure 4 for an illustration of how to
configure the MAX5524/MAX5525 as a programmable
current source for driving an LED. The MAX5524/
MAX5525 drive a standard NPN transistor to program
1-Cell and 2-Cell Circuits
See Figure 3 for an illustration of how to power the
MAX5522–MAX5525 with either one lithium-ion battery
or two alkaline batteries. The low current consumption
of the devices make the MAX5522–MAX5525 ideal for
battery-powered applications.
the current source. The current source (I
in the equation in Figure 4.
) is defined
LED
V
DD
536kΩ
+1.25V
1.8V ≤ V
2.2V ≤ V
≤ 3.3V
ALKALINE
≤ 3.3V
LITHIUM
REFIN
DAC
VOUT
V (1.22mV / LSB)
OUT
0.1µF
0.01µF
MAX6006
(1µA, 1.25V
SHUNT
V
× N
1024
REFIN
DAC
V
=
OUT
MAX5524
N
IS THE NUMERIC VALUE
OF THE DAC INPUT CODE.
DAC
REFERENCE)
GND
Figure 3. Portable Application Using Two Alkaline Cells or One Lithium Coin Cell
V+
LED
DAC
REFIN
VOUT
V
OUT
I
LED
V
OUT
= V + (I × R)
BIAS T
DAC
REFIN
VOUT
1/2 MAX5524
2N3904
R
FB
FB
1/2 MAX5524
I
TRANSDUCER
T
V
× N
DAC
1024
REFIN
R
V
BIAS
=
V
BIAS
V
× N
DAC
1024 × R
REFIN
I
=
LED
N
IS THE NUMERIC VALUE
DAC
N
DAC
IS THE NUMERIC VALUE
OF THE DAC INPUT CODE.
OF THE DAC INPUT CODE.
Figure 4. Programmable Current Source Driving an LED
Figure 5. Transimpedance Configuration for a Voltage-Biased
Current-Output Transducer
______________________________________________________________________________________ 17
Dual, Ultra-Low-Power,
10-Bit, Voltage-Output DACs
An example of a custom fixed gain using the MAX5524/
MAX5525 force-sense output is shown in Figure 8. In
this example, R1 and R2 set the gain for V
Voltage Biasing a
Current-Output Transducer
.
See the circuit in Figure 5 for an illustration of how to
configure the MAX5524/MAX5525 to bias a current-out-
put transducer. In Figure 5, the output voltage of the
MAX5524/MAX5525 is a function of the voltage drop
across the transducer added to the voltage drop
across the feedback resistor R.
OUTA
V
OUTA
= [(V x N ) / 1024] x [1 + (R2 / R1)]
REFIN A
where N represents the numeric value of the DAC
A
input code.
Self-Biased Two-Electrode
Potentiostat Application
See the circuit in Figure 10 for an illustration of how to
use the MAX5525 to bias a two-electrode potentiostat
on the input of an ADC.
Unipolar Output
Figure 6 shows the MAX5524 in a unipolar output con-
figuration with unity gain. Table 4 lists the unipolar out-
put codes.
Power Supply and
Bypassing Considerations
Bypass the power supply with a 4.7µF capacitor in parallel
with a 0.1µF capacitor to GND. Minimize lengths to reduce
lead inductance. If noise becomes an issue, use shielding
and/or ferrite beads to increase isolation. For the thin QFN
package, connect the exposed pad to ground.
Bipolar Output
The MAX5524 output can be configured for bipolar
operation as shown in Figure 7. The output voltage is
given by the following equation:
V
OUT_
= V x [(N - 512) / 512]
REFIN A
where N represents the decimal value of the DAC’s
A
binary input code. Table 5 shows the digital codes (off-
set binary) and the corresponding output voltage for
the circuit in Figure 7.
Configurable Output Gain
The MAX5524/MAX5525 have force-sense outputs,
which provide a connection directly to the inverting ter-
minal of the output op amp, yielding the most flexibility.
The advantage of the force-sense output is that specific
gains can be set externally for a given application. The
gain error for the MAX5524/MAX5525 is specified in a
unity-gain configuration (op-amp output and inverting ter-
minals connected), and additional gain error results from
external resistor tolerances. Another advantage of the
force-sense DAC is that it allows many useful circuits to
be created with only a few simple external components.
Table 4. Unipolar Code Table (Gain = +1)
DAC CONTENTS
ANALOG OUTPUT
MSB
1111
1000
1000
0111
0000
0000
LSB
1100
0100
0000
1100
0100
0000
1111
0000
0000
1111
0000
0000
+V
(1023/1024)
(513/1024)
REF
+V
REF
+V
(512/1024) = +V
/2
REF
REF
+V
(511/1024)
REF
+V
(1/1024)
REF
0V
Table 5. Bipolar Code Table (Gain = +1)
REFIN
DAC
DAC CONTENTS
ANALOG OUTPUT
OUT_
MSB
1111
1000
1000
0111
0000
0000
LSB
1100
0100
0000
1100
0100
0000
1111
0000
0000
1111
0000
0000
+V
(511/512)
REF
MAX5524
FB_
+V
(1/512)
REF
V
× N
A
1024
REFIN
0V
V
=
OUT
-V
-V
(1/512)
REF
N IS THE DAC INPUT CODE
A
(0 TO 1023 DECIMAL).
(511/512)
REF
-V
(512/512) = -V
REF
REF
Figure 6. Unipolar Output Circuit
18 ______________________________________________________________________________________
Dual, Ultra-Low-Power,
10-Bit, Voltage-Output DACs
Layout Considerations
V
× N
1024
255 - N
255
REFIN
DAC
POT
Digital and AC transient signals coupling to GND can
create noise at the output. Use proper grounding tech-
niques, such as a multilayer board with a low-inductance
ground plane. Wire-wrapped boards and sockets are not
recommended. For optimum system performance, use
printed circuit (PC) boards. Good PC board ground lay-
out minimizes crosstalk between DAC outputs, reference
inputs, and digital inputs. Reduce crosstalk by keeping
analog lines away from digital lines.
V
=
1 +
OUT
(
)
N
N
IS THE NUMERIC VALUE OF THE DAC INPUT CODE.
IS THE NUMERIC VALUE OF THE POT INPUT CODE.
DAC
POT
1.8V ≤ V ≤ 5.5V
DD
REFIN
DAC
VOUT
V
OUT
H
CS1
1/2 MAX5524
MAX5401
SOT-POT
100kΩ
FB
W
SCLK
DIN
5PPM/°C
RATIOMETRIC
TEMPCO
10kΩ
10kΩ
CS2
L
V+
Figure 9. Software-Configurable Output Gain
V
OUT
DAC
OUT_
FB_
REFIN
V-
1/2 MAX5524
REF
OUT
DAC
TO ADC
TO ADC
Figure 7. Bipolar Output Circuit
I
F
R
F
FB
WE
1/2 MAX5525
REFIN
DAC
SENSOR
CE
VOUTA
V
OUT1
R2
R1
V
× N
1024
R2
R1
REFIN
DACA
V
=
1 +
OUT1
( )
FBA
REFOUT
BAND
GAP
N
IS THE NUMERIC VALUE
OF THE DAC A INPUT CODE.
DACA
TO ADC
C
L
1/2 MAX5524
DAC
VOUTB
FBB
V
OUT2
Figure 10. Self-Biased Two-Electrode Potentiostat Application
V
× N
DACB
1024
REFIN
V
OUT2
=
N
IS THE NUMERIC VALUE
DACB
OF THE DAC B INPUT CODE.
Figure 8. Separate Force-Sense Outputs Create Unity and
Greater-than-Unity DAC Gains Using the Same Reference
______________________________________________________________________________________ 19
Dual, Ultra-Low-Power,
10-Bit, Voltage-Output DACs
Pin Configurations (continued)
REF
TOP VIEW
OUTA
FBA
DAC
TO ADC
FBA
12
N.C. OUTA
I
F
R
F
11
10
CS
SCLK
DIN
1
2
3
9
8
7
GND
WE
MAX5525
SENSOR
CE
V
DD
MAX5524
MAX5525
REF
OUTB
OUTB
DAC
4
5
6
REFIN(MAX5524)
REFOUT(MAX5525)
N.C.
FBB
FBB
REFOUT
BAND
GAP
THIN QFN
TO ADC
C
L
Figure 11. Driven Two-Electrode Potentiostat Application
Chip Information
TRANSISTOR COUNT: 10,688
PROCESS: BiCMOS
20 ______________________________________________________________________________________
Dual, Ultra-Low-Power,
10-Bit, Voltage-Output DACs
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
PACKAGE OUTLINE
12, 16, 20, 24L THIN QFN, 4x4x0.8mm
1
C
21-0139
2
______________________________________________________________________________________ 21
Dual, Ultra-Low-Power,
10-Bit, Voltage-Output DACs
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
PACKAGE OUTLINE
12, 16, 20, 24L THIN QFN, 4x4x0.8mm
2
C
21-0139
2
22 ______________________________________________________________________________________
Dual, Ultra-Low-Power,
10-Bit, Voltage-Output DACs
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
4X S
8
8
MILLIMETERS
INCHES
DIM MIN
MAX
MAX
MIN
-
-
0.043
0.006
0.037
0.014
0.007
0.120
1.10
0.15
0.95
0.36
0.18
3.05
A
0.002
0.030
0.010
0.005
0.116
0.05
0.75
0.25
0.13
2.95
A1
A2
b
E
H
ÿ 0.50 0.1
c
D
e
0.0256 BSC
0.65 BSC
0.6 0.1
E
H
0.116
0.188
0.016
0∞
0.120
2.95
4.78
0.41
0∞
3.05
5.03
0.66
6∞
0.198
0.026
6∞
L
1
1
α
S
0.6 0.1
0.0207 BSC
0.5250 BSC
BOTTOM VIEW
D
TOP VIEW
A1
A2
A
c
α
e
L
b
SIDE VIEW
FRONT VIEW
PROPRIETARY INFORMATION
TITLE:
PACKAGE OUTLINE, 8L uMAX/uSOP
APPROVAL
DOCUMENT CONTROL NO.
REV.
1
21-0036
J
1
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 23
© 2004 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
相关型号：
MAX5524ETC-T
D/A Converter, 1 Func, Serial Input Loading, 12us Settling Time, 4 X 4 MM, 0.80 MM HEIGHT, MO-220-WGGB, TQFN-12
MAXIM
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