MAX5156BEEE+T_技术文档

19-1317; Rev 1; 12/97

Lo w -P o w e r, Du a l, 1 2 -Bit Vo lt a g e -Ou t p u t DACs

w it h Co n fig u ra b le Ou t p u t s

6/MAX157

_______________Ge n e ra l De s c rip t io n

____________________________Fe a t u re s

The MAX5156/MAX5157 low-power, serial, voltage-out-

put, dual 12-bit digital-to-analog converters (DACs)

consume only 500µA from a single +5V (MAX5156) or

+3V (MAX5157) supply. These devices feature Rail-to-

♦ 12-Bit Dual DAC with Configurable Output

Amplifier

♦ Single-Supply Operation: +5V (MAX5156)

+3V (MAX5157)

®

Rail output swing and are available in space-saving

♦ Rail-to-Rail Output Swing

16-pin QSOP and DIP packages. Access to the invert-

ing input allows for specific gain configurations, remote

sensing, and high output current capability, making

these devices ideally suited for industrial process con-

trols. These devices are also well suited for digitally

programmable (4–20mA) current loops.

♦ Low Quiescent Current: 500µA (normal operation)

2µA (shutdown mode)

♦ Power-On Reset Clears DAC Outputs to Zero

♦ SPI/QSPI and Microwire Compatible

♦ Space-Saving 16-Pin QSOP Package

The 3-wire s e ria l inte rfa c e is SPI™/QSPI™ a nd

Mic rowire ™ c omp a tib le . Ea c h DAC ha s a d oub le -

buffered input organized as an input register followed

by a DAC register, which allows the input and DAC reg-

isters to be updated independently or simultaneously.

Additional features include a programmable shutdown

(2µA), hardware-shutdown lockout, a separate voltage

reference for each DAC, power-on reset, and an active-

low clear input (CL) that resets all registers and DACs to

zero. The MAX5156/MAX5157 provide a programmable

logic output pin for added functionality, and a serial-

data output pin for daisy chaining.

_______________Ord e rin g In fo rm a t io n

INL

PART

TEMP. RANGE

PIN-PACKAGE

(LSB)

±1/2

±1

MAX5156ACPE

MAX5156BCPE

MAX5156ACEE

MAX5156BCEE

0°C to +70°C

16 Plastic DIP

16 QSOP

±1/2

±1

16 QSOP

________________________Ap p lic a t io n s

Ordering Information continued at end of data sheet.

Industrial Process Control Motion Control

Digital Offset and Gain

Adjustment

Digitally Programmable

4–20mA Current Loops

Pin Configuration appears at end of data sheet.

Remote Industrial Controls Automatic Test Equipment

_________________________________________________________Fu n c t io n a l Dia g ra m

V

DD

DOUT CL

PDL

DGND

REFA

AGND

INPUT

REG A

DAC

REG A

OUTA

FBA

DAC A

DECODE

CONTROL

16-BIT

SHIFT

REGISTER

MAX5156

MAX5157

INPUT

REG B

DAC

REG B

OUTB

FBB

DAC B

LOGIC

OUTPUT

SR

CONTROL

REFB

CS

DIN SCLK UPO

Rail-to-Rail is a registered trademark of Nippon Motorola Ltd. SPI and QSPI are trademarks of Motorola, Inc.

Microwire is a trademark of National Semiconductor Corp.

________________________________________________________________ Maxim Integrated Products

1

For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800.

For small orders, phone 408-737-7600 ext. 3468.

Lo w -P o w e r, Du a l, 1 2 -Bit Vo lt a g e -Ou t p u t DACs

w it h Co n fig u ra b le Ou t p u t s

ABSOLUTE MAXIMUM RATINGS

V

to AGND............................................................-0.3V to +6V

to DGND ...........................................................-0.3V to +6V

Continuous Power Dissipation (T = +70°C)

A

DD

V

Plastic DIP (derate 10.5mW/°C above +70°C) .............593mW

QSOP (derate 8.30mW/°C above +70°C).....................667mW

CERDIP (derate 10.00mW/°C above +70°C)................800mW

Operating Temperature Ranges

DD

AGND to DGND..................................................................±0.3V

FBA, FBB to AGND.....................................-0.3V to (V + 0.3V)

REF_, OUT_ to AGND.................................-0.3V to (V + 0.3V)

DD

Digital Inputs (SCLK, DIN, CS, CL, PDL)

to DGND................................................................-0.3V to +6V

Digital Outputs (DOUT, UPO) to DGND.....-0.3V to (V + 0.3V)

Maximum Current into Any Pin .........................................±20mA

MAX5152_C_E/MAX5153_C_E ...........................0°C to +70°C

MAX5152_E_E/MAX5153_E_E..........................-40°C to +85°C

MAX5152_MJE/MAX5153_MJE ......................-55°C to +125°C

Storage Temperature Range .............................-65°C to +160°C

Lead Temperature (soldering, 10sec) .............................+300°C

DD

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional

operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to

absolute maximum rating conditions for extended periods may affect device reliability.

ELECTRICAL CHARACTERISTICS—MAX5156

(V = +5V ±10%, V

= V

= 2.5V, R = 10kΩ, C = 100pF, T = T

to T , unless otherwise noted. Typical values are at

MAX

DD

REFA

REFB

L

A

MIN

T

A

= +25°C, output buffer connected in unity-gain configuration (Figure 9).)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

6/MAX157

STATIC PERFORMANCE

Resolution

N

12

Bits

MAX5156A

MAX5156B

±1/2

±1

Integral Nonlinearity

INL

DNL

(Note 1)

LSB

Differential Nonlinearity

Offset Error

Guaranteed monotonic

Code = 10

±1

LSB

mV

V

OS

±6

±3

Offset Tempco

Gain Error

TCV

Normalized to 2.5V

3

-0.5

3

ppm/°C

LSB

OS

Gain-Error Tempco

Normalized to 2.5V

ppm/°C

µV/V

V

DD

Power-Supply Rejection Ratio

PSRR

REF

4.5V ≤ V ≤ 5.5V

20

200

DD

REFERENCE INPUT

Reference Input Range

0

V

- 1.4

V

DD

Reference Input Resistance

R

Minimum with code 1554 hex

Input code = 1FFE hex,

14

20

kΩ

REF

MULTIPLYING-MODE PERFORMANCE

Reference 3dB Bandwidth

600

-85

82

kHz

dB

V

REF

= 0.67Vp-p at 2.5V

DC

Input code = 0000 hex,

= (V - 1.4Vp-p) at 1kHz

Reference Feedthrough

Signal-to-Noise plus

V

REF

DD

Input code = 1FFE hex,

= 1Vp-p at 2.5V , f = 25kHz

SINAD

dB

V

REF

Distortion Ratio

DC

DIGITAL INPUTS

Input High Voltage

Input Low Voltage

Input Hysteresis

V

3

V

CL, PDL, CS, DIN, SCLK

IH

V

IL

0.8

±1

V

HYS

200

0.001

8

mV

µA

pF

Input Leakage Current

Input Capacitance

I

IN

V

= 0V to V

IN DD

C

IN

2

_______________________________________________________________________________________

Lo w -P o w e r, Du a l, 1 2 -Bit Vo lt a g e -Ou t p u t DACs

w it h Co n fig u ra b le Ou t p u t s

6/MAX157

ELECTRICAL CHARACTERISTICS—MAX5156 (continued)

(V = +5V ±10%, V

= V

= 2.5V, R = 10kΩ, C = 100pF, T = T

to T , unless otherwise noted. Typical values are at

MAX

DD

REFA

REFB

L

A

MIN

T

A

= +25°C, output buffer connected in unity-gain configuration (Figure 9).)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

DIGITAL OUTPUTS (DOUT, UPO)

Output High Voltage

V

I

= 2mA

V - 0.5

DD

V

OH

SOURCE

Output Low Voltage

V

OL

I

= 2mA

0.13

0.40

SINK

DYNAMIC PERFORMANCE

Voltage Output Slew Rate

Output Settling Time

SR

0.75

15

V/µs

µs

To 1/2LSB of full-scale, V

= 2.5V

STEP

Output Voltage Swing

Current into FBA or FBB

Time Required to Exit Shutdown

Digital Feedthrough

Rail-to-rail (Note 2)

0 to V

V

DD

I

FB

0

25

5

±0.1

µA

µs

nV-s

CS = V , f

= 100kHz, V

= 5Vp-p

DD DIN

SCLK

Digital Crosstalk

5

POWER SUPPLIES

Positive Supply Voltage

Power-Supply Current

V

4.5

5.5

V

DD

I

DD

(Note 3)

0.5

2

0.65

mA

Power-Supply Current in

Shutdown

I

10

±1

µA

DD(SHDN)

Reference Current in Shutdown

0

TIMING CHARACTERISTICS

SCLK Clock Period

t

(Note 4)

100

40

ns

CP

SCLK Pulse Width High

SCLK Pulse Width Low

t

CH

t

40

CL

t

40

CS Fall to SCLK Rise Setup Time

CSS

CHS

t

0

40

0

ns

SCLK Rise to CS Rise Hold Time

DIN Setup Time

t

DS

DIN Hold Time

t

DH

SCLK Rise to DOUT Valid

Propagation Delay

t

C

= 200pF

80

ns

DO1

DO2

LOAD

SCLK Fall to DOUT Valid

Propagation Delay

t

10

40

ns

SCLK Rise to CS Fall Delay

CS Rise to SCLK Rise Hold

CS Pulse Width High

CS0

t

CS1

t

100

CSW

Note 1: Accuracy is specified from code 10 to code 4095.

Note 2: Accuracy is better than 1LSB for V greater than 6mV and less than V - 50mV. Guaranteed by PSRR test at the end points.

OUT

DD

Note 3: Digital inputs are set to either V or DGND, code = 0000 hex, R = ∞.

DD

L

Note 4: SCLK minimum clock period includes rise and fall times.

_______________________________________________________________________________________

3

Lo w -P o w e r, Du a l, 1 2 -Bit Vo lt a g e -Ou t p u t DACs

w it h Co n fig u ra b le Ou t p u t s

ELECTRICAL CHARACTERISTICS—MAX5157

(V = +2.7V to +3.6V, V

= V

= 1.25V, R = 10kΩ, C = 100pF, T = T

to T , unless otherwise noted. Typical values

MAX

DD

REFA

REFB

L

A

MIN

are at T = +25°C, output buffer connected in unity-gain configuration (Figure 9).)

A

PARAMETER

STATIC PERFORMANCE

Resolution

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

N

12

Bits

MAX5157A

MAX5157B

±1

±2

±1

±6

Integral Nonlinearity

INL

(Note 5)

LSB

Differential Nonlinearity

Offset Error

DNL

Guaranteed monotonic

Code = 20

LSB

mV

V

OS

Offset Tempco

Gain Error

TCV

Normalized to 1.25V

6

-0.5

6

ppm/°C

LSB

OS

±4

Gain-Error Tempco

Normalized to 1.25V

ppm/°C

µV/V

V

DD

Power-Supply Rejection Ratio

PSRR

REF

2.7V ≤ V ≤ 3.6V

20

320

DD

REFERENCE INPUT (V

)

REF

6/MAX157

Reference Input Range

0

V

DD

- 1.4

V

Reference Input Resistance

R

Minimum with code 1554 hex

Input code = 1FFE hex,

14

20

kΩ

REF

MULTIPLYING-MODE PERFORMANCE

Reference 3dB Bandwidth

600

-92

73

kHz

dB

V

= 0.67Vp-p at 1.25V

DC

REF(AC)

Input code = 0000 hex,

= (V - 1.4V) at 1kHz

Reference Feedthrough

V

REF

DD

Signal-to-Noise plus Distortion

Ratio

Input code = 1FFE hex,

= 1Vp-p at 1.25V , f = 15kHz

SINAD

dB

V

REF

DC

DIGITAL INPUTS

Input High Voltage

V

2.2

V

CL, PDL, CS, DIN, SCLK

IH

Input Low Voltage

V

IL

0.8

V

Input Hysteresis

V

200

0

mV

µA

pF

HYS

Input Leakage Current

Input Capacitance

I

V

IN

= 0V to V

DD

±0.1

IN

C

8

IN

DIGITAL OUTPUTS (DOUT, UPO)

Output High Voltage

V

I

= 2mA

V - 0.5

DD

V

OH

SOURCE

Output Low Voltage

V

OL

I

= 2mA

0.13

0.4

SINK

DYNAMIC PERFORMANCE

Voltage Output Slew Rate

Output Settling Time

SR

0.75

18

V/µs

µs

To 1/2LSB of full-scale, V

= 1.25V

STEP

Output Voltage Swing

Current into FBA or FBB

Time Required to Exit Shutdown

Digital Feedthrough

Rail-to-rail (Note 6)

0 to V

V

DD

I

FB

0

25

5

±0.1

µA

µs

nV-s

CS = V , f

= 100kHz, V

= 3Vp-p

DD DIN

SCLK

Digital Crosstalk

5

4

_______________________________________________________________________________________

Lo w -P o w e r, Du a l, 1 2 -Bit Vo lt a g e -Ou t p u t DACs

w it h Co n fig u ra b le Ou t p u t s

6/MAX157

ELECTRICAL CHARACTERISTICS—MAX5157 (continued)

(V = +2.7V to +3.6V, V

= V

= 1.25V, R = 10kΩ, C = 100pF, T = T

to T

, unless otherwise noted. Typical values

MAX

DD

REFA

REFB

L

A

MIN

are at T = +25°C, output buffer connected in unity-gain configuration (Figure 9).)

A

PARAMETER

POWER SUPPLIES

Positive Supply Voltage

Power-Supply Current

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

V

DD

2.7

3.6

0.6

V

I

DD

(Note 7)

0.5

1

mA

Power-Supply Current in

Shutdown

I

8

µA

DD(SHDN)

Reference Current in

Shutdown

±1

TIMING CHARACTERISTICS

SCLK Clock Period

t

(Note 4)

100

40

ns

CP

SCLK Pulse Width High

SCLK Pulse Width Low

t

CH

t

40

CL

CS Fall to SCLK Rise Setup

Time

t

40

0

ns

CSS

SCLK Rise to CS Rise Hold

Time

t

CHS

DIN Setup Time

DIN Hold Time

t

50

0

ns

DS

t

DH

SCLK Rise to DOUT Valid

Propagation Delay

t

C

= 200pF

120

ns

DO1

DO2

LOAD

SCLK Fall to DOUT Valid

Propagation Delay

t

10

40

ns

SCLK Rise to CS Fall Delay

CS Rise to SCLK Rise Hold

CS Pulse Width High

CS0

CS1

t

100

CSW

Note 5: Accuracy is specified from code 20 to code 4095.

Note 6: Accuracy is better than 1LSB for V greater than 6mV and less than V - 100mV. Guaranteed by PSRR test at the end

OUT

DD

points.

Note 7: Digital inputs are set to either V or DGND, code = 0000 hex, R = ∞.

DD

L

_______________________________________________________________________________________

5

Lo w -P o w e r, Du a l, 1 2 -Bit Vo lt a g e -Ou t p u t DACs

w it h Co n fig u ra b le Ou t p u t s

__________________________________________Typ ic a l Op e ra t in g Ch a ra c t e ris t ic s

(V = +5V, R = 10kΩ, C = 100pF, FB_ connected to OUT_, T = +25°C, unless otherwise noted.)

DD

L

A

MAX5156

SUPPLY CURRENT

vs. TEMPERATURE

REFERENCE VOLTAGE INPUT

FREQUENCY RESPONSE

TOTAL HARMONIC DISTORTION

PLUS NOISE vs. FREQUENCY

0

0.60

0.55

0.50

0.45

0.40

-30

-40

-50

-60

-70

-80

-90

V

REF

= 1Vp-p @ 2.5V

DC

R =

-2

-4

L

∞

CODE = 1FFE (HEX)

-6

-8

-10

-12

-14

-16

-18

-20

CODE = 0000 (HEX)

V

= 0.67Vp-p @ 2.5V

DC

REF

CODE = 1FFE (HEX)

6/MAX157

-60

-20

20

60

100

140

0

600 1200

1800

2400

3000

0

10

100

TEMPERATURE (°C)

FREQUENCY (kHz)

POWER-DOWN CURRENT

vs. TEMPERATURE

FULL-SCALE ERROR vs. RESISTIVE LOAD

REFERENCE FEEDTHROUGH AT 1kHz

-50

-60

0

3.0

2.5

2.0

1.5

1.0

0.5

0

V

= 3.6Vp-p @ 1.88V

DC

V

REF

= 2.5V

REF

CODE = 0000 (HEX)

-70

-0.1

-0.2

-0.3

-0.4

-80

-90

-100

-110

-120

-130

-140

-150

-0.5

-55 -35 -15

5

25 45 65 85 105 125

0.1

1

10

R (kΩ)

100

1000

0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

FREQUENCY (kHz)

TEMPERATURE (°C)

L

OUTPUT FFT PLOT

DYNAMIC-RESPONSE RISE TIME

DYNAMIC-RESPONSE FALL TIME

MAX5156 TOC08

MAX5156 TOC09

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

CS

5V/div

AC COUPLED

CS

5V/div

AC COUPLED

V

REF

= 3.6Vp-p @ 1.8V

DC

f = 1kHz

CODE = 1FFE (HEX)

NOTE: RELATIVE TO FULL SCALE

OUT_

500mV/div

OUT_

500mV/div

0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

FREQUENCY (kHz)

2µs/div

6

_______________________________________________________________________________________

Lo w -P o w e r, Du a l, 1 2 -Bit Vo lt a g e -Ou t p u t DACs

w it h Co n fig u ra b le Ou t p u t s

6/MAX157

____________________________Typ ic a l Op e ra t in g Ch a ra c t e ris t ic s (c o n t in u e d )

(V = +3V, R = 10kΩ, C = 100pF, FB_ connected to OUT_, T = +25°C, unless otherwise noted.)

DD

L

A

MAX5157

REFERENCE VOLTAGE INPUT

FREQUENCY RESPONSE

SUPPLY CURRENT

vs. TEMPERATURE

TOTAL HARMONIC DISTORTION

PLUS NOISE vs. FREQUENCY

0

0.60

0.55

0.50

0.45

0.40

-30

-40

-50

-60

-70

-80

-90

V

= 1Vp-p @ 1V

DC

REF

-2

-4

R =

L

∞

CODE = 1FFE (HEX)

-6

CODE = 1FFE (HEX)

-8

-10

-12

-14

-16

-18

-20

CODE = 0000 (HEX)

V

= 0.67Vp-p @ 1.25V

DC

REF

CODE = 1FFE (HEX)

0

500 1000

1500

2000

2500

-60

-20

20

60

100

140

0

10

100

FREQUENCY (kHz)

TEMPERATURE (°C)

FREQUENCY (kHz)

POWER-DOWN CURRENT

vs. TEMPERATURE

REFERENCE FEEDTHROUGH AT 1kHz

FULL-SCALE ERROR vs. RESISTIVE LOAD

-50

-60

0

-0.1

-0.2

-0.3

-0.4

-0.5

-0.6

3.0

2.5

2.0

1.5

1.0

0.5

0

V

REF

= 1.6Vp-p @ 0.88V

DC

CODE = 0000 (HEX)

-70

-80

-90

-100

-110

-120

-130

-140

-150

V

REF

= 1.25V

1

0.1

10

R (kΩ)

100

1000

0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

FREQUENCY (kHz)

-55 -35 -15

5

25 45 65 85 105 125

TEMPERATURE (°C)

L

OUTPUT FFT PLOT

DYNAMIC-RESPONSE RISE TIME

DYNAMIC-RESPONSE FALL TIME

MAX5156 TOC18

MAX5156 TOC17

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

V

REF

= 1.6Vp-p @ 0.88V

DC

f = 1kHz

CODE = 1FFE (HEX)

NOTE: RELATIVE TO FULL SCALE

CS

2V/div

CS

2V/div

OUT_

500mV/div

OUT_

500mV/div

0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

FREQUENCY (kHz)

2µs/div

_______________________________________________________________________________________

7

Lo w -P o w e r, Du a l, 1 2 -Bit Vo lt a g e -Ou t p u t DACs

w it h Co n fig u ra b le Ou t p u t s

____________________________Typ ic a l Op e ra t in g Ch a ra c t e ris t ic s (c o n t in u e d )

(V = +5V (MAX5156), V = +3V (MAX5157), R = 10kΩ, C = 100pF, FB_ connected to OUT_, T = T

to T , unless

MAX

DD

L

A

MIN

otherwise noted.)

MAX5156/MAX5157

MAX5156

MAX5157

SUPPLY CURRENT

vs. SUPPLY VOLTAGE

0.60

0.55

0.50

0.55

CODE = 1FFE (HEX)

CODE = 0000 (HEX)

0.50

0.45

0.40

CODE = 0000 (HEX)

0.45

0.40

0.35

0.30

6/MAX157

0.30

4.50

4.75

5.00

5.25

5.50

2.7

3.0

3.3

3.6

SUPPLY VOLTAGE (V)

MAX5156

MAJOR-CARRY TRANSITION

MAX5156 TOC20

CS

2V/div

OUT_

10mV/div

AC COUPLED

2µs/div

TRANSITION FROM 1000 (HEX) TO 0FFE (HEX)

MAX5156

ANALOG CROSSTALK

DIGITAL FEEDTHROUGH

MAX5156 TOC22

MAX5156 TOC21

SCLK

5V/div

OUTA

1V/div

OUTA

500µV/div

AC COUPLED

OUTB

200µV/div

AC COUPLED

1µs/div

200µs/div

8

_______________________________________________________________________________________

Lo w -P o w e r, Du a l, 1 2 -Bit Vo lt a g e -Ou t p u t DACs

w it h Co n fig u ra b le Ou t p u t s

6/MAX157

______________________________________________________________P in De s c rip t io n

NAME

FUNCTION

1

2

3

4

5

AGND

OUTA

FBA

Analog Ground

DAC A Output Voltage

DAC A Output Amplifier Feedback Input. Inverting input of the output amplifier.

Reference for DAC A

REFA

CL

Active-Low Clear Input. Resets all registers to zero. DAC outputs go to 0V.

6

Chip-Select Input

CS

DIN

7

Serial Data Input

8

SCLK

DGND

DOUT

UPO

Serial Clock Input

9

Digital Ground

10

11

12

13

14

15

16

Serial Data Output

User-Programmable Output

PDL

Power-Down Lockout. The device cannot be powered down when PDL is low.

Reference Input for DAC B

REFB

FBB

DAC B Output Amplifier Feedback Input. Inverting input of the output amplifier.

DAC B Output Voltage

OUTB

V

DD

Positive Power Supply

_______________De t a ile d De s c rip t io n

FB_

The MAX5156/MAX5157 dual, 12-bit, voltage-output

DACs are easily configured with a 3-wire serial inter-

face. These devices include a 16-bit data-in/data-out

shift register, and each DAC has a double-buffered

input comprised of an input register and a DAC register

(see Functional Diagram). Both DACs use an inverted

R-2R ladder network that produces a weighted voltage

proportional to the input voltage value. Each DAC has

its own reference input to facilitate independent full-

scale values. Figure 1 depicts a simplified circuit dia-

gram of one of the two DACs.

OUT_

R

2R

D0

2R

D9

2R

D10

2R

D11

REF_

AGND

Re fe re n c e In p u t s

The reference inputs accept both AC and DC values

SHOWN FOR ALL 1s ON DAC

with a voltage range extending from 0V to (V - 1.4V).

DD

Determine the output voltage using the following equa-

tion:

Figure 1. Simplified DAC Circuit Diagram

V

= V

x NB / 4096

Ou t p u t Am p lifie r

The output amplifier’s inverting input is available to the

user, allowing force and sense capability for remote

sensing and specific gain configurations. The inverting

input can be connected to the output to provide a unity-

gain buffered output. The output amplifiers have a typi-

cal slew rate of 0.75V/µs and settle to 1/2LSB within

15µs, with a load of 10kΩ in parallel to 100pF. Loads

less than 2kΩ degrade performance.

OUT

REF

where NB is the numeric value of the DAC’s binary input

code (0 to 4095) and V is the reference voltage.

REF

The reference input impedance ranges from 14kΩ (1554

hex) to several giga ohms (with an input code of 0000

hex). This reference input capacitance is code depen-

dent and typically ranges from 15pF with an input code

of all zeros to 50pF with a full-scale input code.

_______________________________________________________________________________________

9

Lo w -P o w e r, Du a l, 1 2 -Bit Vo lt a g e -Ou t p u t DACs

w it h Co n fig u ra b le Ou t p u t s

Table 1. Serial-Interface Programming Commands

16-BIT SERIAL WORD

FUNCTION

D11................D0

A0 C1 C0

S0

MSB

LSB

0

1

0

1

0

1

0

12 bits of DAC data

0

Load input register A; DAC register is unchanged.

Load input register B; DAC register is unchanged.

Load input register A; all DAC registers are updated.

Load input register B; all DAC registers are updated.

12 bits of DAC data

Load all DAC registers from the shift register (start up both DACs

with new data).

0

1

12 bits of DAC data

0

Update both DAC registers from their respective input registers

(start up both DACs with data previously stored in the input

registers).

1

0

xxxxxxxxxxxx

0

6/MAX157

1

0

1

0

1

0

xxxxxxxxxxxx

0

Shut down both DACs if PDL = 1.

Update DAC register A from input register A (start up DAC A with

data previously stored in input register A).

0 0 1 x xxxxxxxx

Update DAC register B from input register B (start up DAC B with

data previously stored in input register B).

0

1 0 1 x xxxxxxxx

0

1 1 0 x xxxxxxxx

1 1 1 x xxxxxxxx

0 1 0 x xxxxxxxx

0 1 1 x xxxxxxxx

1 0 0 1 xxxxxxxx

1 0 0 0 xxxxxxxx

0 0 0 x xxxxxxxx

0

Shut down DAC A when PDL = 1.

Shut down DAC B when PDL = 1.

UPO goes low (default).

UPO goes high.

Mode 1, DOUT clocked out on SCLK’s rising edge.

Mode 0, DOUT clocked out on SCLK’s falling edge (default).

No operation (NOP).

“x” = don’t care

Note: D11, D10, D9, and D8 become control bits when A0, C1, and C0 = 0. S0 is a sub bit, always zero.

updating the DAC with new information. When returning

to normal operation (exiting shutdown), wait 20µs for

output stabilization.

P o w e r-Do w n Mo d e

The MAX5156/MAX5157 feature a software-program-

mable shutdown mode that reduces the typical supply

current to 2µA. The two DACs can be shut down inde-

pendently or simultaneously by using the appropriate

programming word. For instance, enter shutdown mode

(for both DACs) by writing an input control word of

111XXXXXXXXXXXX0 (Table 1). In shutdown mode, the

reference inputs and amplifier outputs become high

impedance, and the serial interface remains active.

Da ta in the inp ut re g is te rs is s a ve d , a llowing the

MAX5156/MAX5157 to recall the output state prior to

entering shutdown when returning to normal mode. Exit

shutdown by recalling the previous condition or by

S e ria l In t e rfa c e

The MAX5156/MAX5157 3-wire serial interface is com-

patible with both Microwire (Figure 2) and SPI/QSPI

(Figure 3) serial-interface standards. The 16-bit serial

input word consists of an address bit, two control bits,

12 bits of data (MSB to LSB), and one sub bit as shown

in Figure 4. The address and control bits determine the

response of the MAX5156/MAX5157, as outlined in

Table 1.

10 ______________________________________________________________________________________

Lo w -P o w e r, Du a l, 1 2 -Bit Vo lt a g e -Ou t p u t DACs

w it h Co n fig u ra b le Ou t p u t s

6/MAX157

The MAX5156/MAX5157’s digital inputs are double

buffered, which allows any of the following: loading the

input register(s) without updating the DAC register(s),

updating the DAC register(s) from the input register(s),

or updating the input and DAC registers concurrently.

SCLK

SK

The address and control bits allow the DACs to act

independently.

MICROWIRE

PORT

Send the 16-bit data as one 16-bit word (QSPI) or two

8-bit packets (SPI, Microwire), with CS low during this

period. The address and control bits determine which

register will be updated, and the state of the registers

whe n e xiting s hutd own. The 3-b it a d d re s s /c ontrol

determines the following:

MAX5156

MAX5157

DIN

CS

SO

I/O

• registers to be updated

• clock edge on which data is clocked out via the seri-

al data output (DOUT)

Figure 2. Connections for Microwire

• state of the user-programmable logic output

• configuration of the device after shutdown

The general timing diagram in Figure 5 illustrates how

data is acquired. Driving CS low enables the device to

receive data. Otherwise, the interface control circuitry is

disabled. With CS low, data at DIN is clocked into the

register on the rising edge of SCLK. As CS goes high,

data is latched into the input and/or DAC registers

depending on the address and control bits. The maxi-

mum clock frequency guaranteed for proper operation

is 10MHz. Figure 6 depicts a more detailed timing dia-

gram of the serial interface.

V

CC

SS

DIN

MOSI

SCK

SPI/QSPI

PORT

MAX5156

SCLK

Serial Data Output (DOUT)

DOUT is the internal shift register’s output. It allows for

d a is y-c ha ining a nd d a ta re a d b a c k. The MAX5156/

MAX5157 c a n b e p rog ra mme d to s hift d a ta out of

DOUT on SCLK’s falling edge (Mode 0) or rising edge

(Mode 1). Mode 0 provides a lag of 16 clock cycles,

whic h ma inta ins c omp a tib ility with SPI/QSPI a nd

Microwire interfaces. In Mode 1, the output data lags

15.5 clock cycles. On power-up, the device defaults to

Mode 0.

MAX5157

CS

I/O

CPOL = 0, CPHA = 0

Figure 3. Connections for SPI/QSPI

User-Programmable Logic Output (UPO)

UPO allows an external device to be controlled through

the MAX5156/MAX5157 serial interface (Table 1), there-

by reducing the number of microcontroller I/O pins

required. On power-up, UPO is low.

MSB...................................................................................LSB

16 Bits of Serial Data

Sub

Bit

Address Bits

A0

Control Bits

MSB...DataBits...LSB

Power-Down Lockout Input (PDL)

PDL disables software shutdown when low. When in

shutdown, transitioning PDL from high to low wakes up

the part with the output set to the state prior to shut-

down. PDL can also be used to asynchronously wake

up the device.

C1, C0

D11.......................D0

12 Data Bits

S0

0

1 Address/2 Control Bits

Figure 4. Serial-Data Format

______________________________________________________________________________________ 11

Lo w -P o w e r, Du a l, 1 2 -Bit Vo lt a g e -Ou t p u t DACs

w it h Co n fig u ra b le Ou t p u t s

CS

COMMAND

EXECUTED

SCLK

1

8

9

16

D5 D4 D3 D2 D1 D0 S0

C1

DIN

A0

C0 D11 D10 D9 D8 D7

D6

Figure 5. Serial-Interface Timing Diagram

t

CSW

CS

t

CP

t

CSH

t

CH

CSS

t

CL

CSO

t

CS1

SCLK

6/MAX157

t

DS

t

DH

DIN

Figure 6. Detailed Serial-Interface Timing Diagram

SCLK

MAX5156

MAX5157

MAX5156

MAX5157

MAX5156

MAX5157

DIN

CS

DOUT

DIN

CS

DOUT

DIN

CS

DOUT

TO OTHER

SERIAL DEVICES

Figure 7. Daisy Chaining MAX5156/MAX5157s

Daisy Chaining Devices

Any numb e r of MAX5156/MAX5157s c a n b e d a is y

chained by connecting the DOUT pin of one device to the

DIN pin of the following device in the chain (Figure 7).

tive load. Refer to the digital output V and V speci-

OH OL

fications in the Electrical Characteristics.

Figure 8 shows an alternative method of connecting

several MAX5156/MAX5157s. In this configuration, the

data bus is common to all devices; data is not shifted

through a daisy-chain. More I/O lines are required in

this configuration because a dedicated chip-select

input (CS) is required for each IC.

Since the MAX5156/MAX5157’s DOUT has an internal

active pull-up, the DOUT sink/source capability deter-

mines the time required to discharge/charge a capaci-

12 ______________________________________________________________________________________

Lo w -P o w e r, Du a l, 1 2 -Bit Vo lt a g e -Ou t p u t DACs

w it h Co n fig u ra b le Ou t p u t s

6/MAX157

DIN

SCLK

CS1

CS2

TO OTHER

SERIAL DEVICES

CS3

CS

MAX5156

MAX5157

SCLK

MAX5156

MAX5157

SCLK

MAX5156

MAX5157

SCLK

DIN

Figure 8. Multiple MAX5156/MAX5157s Sharing a Common DIN Line

Table 2. Unipolar Code Table (Gain = +1)

DAC CONTENTS

ANALOG OUTPUT

+5V/+3V

REF_

MSB

LSB

4095

4096

V

DD

1 1 1 1

1 1 1 1 1 1 1 1 (0 )

+V

REF

MAX5156

MAX5157

FB_

2049

4096

1 0 0 0

0 1 1 1

0 0 0 0 0 0 0 1 (0 )

0 0 0 0 0 0 0 0 (0 )

1 1 1 1 1 1 1 1 (0 )

+V

REF

DAC

V

2048

4096

OUT_

REF

+V

=

REF

2

DGND

AGND

2047

+V

REF

4096

1

0 0 0 0

0 0 0 0 0 0 0 1 (0 )

0 0 0 0 0 0 0 0 (0 )

+V

REF

4096

Figure 9. Unipolar Output Circuit

0V

Note: ( ) are for the sub bit.

Bip o la r Ou t p u t

__________Ap p lic a t io n s In fo rm a t io n

The MAX5156/MAX5157 can be configured for a bipo-

lar output, as shown in Figure 11. The output voltage is

given by the equation:

Un ip o la r Ou t p u t

Figure 9 depicts the MAX5156/MAX5157 configured for

unity-gain, unipolar operation. Table 2 lists the unipolar

output codes. To increase dynamic range, specific

gain configurations can be used as shown in Figure 10.

V

OUT

= V

[((2 x NB) / 4096) - 1]

REF

where NB represents the numeric value of the DAC’s

binary input code. Table 3 shows digital codes and the

corresponding output voltage for Figure 11’s circuit.

______________________________________________________________________________________ 13

Lo w -P o w e r, Du a l, 1 2 -Bit Vo lt a g e -Ou t p u t DACs

w it h Co n fig u ra b le Ou t p u t s

+5V/+3V

REF_

+5V/+3V

10k

V

DD

R2

R1

V

DD

MAX5156

MAX5157

FB_

V+

FB_

MAX5156

MAX5157

V

OUT

DAC

V

OUT

OUT_

DAC _

OUT_

V-

DGND

N

AGND

DGND

AGND

=

+ R1

V

REF_

V

OUT

1

(

) (

)(

)

R2 4096

Figure 10. Configurable Output Gain

Figure 11. Bipolar Output Circuit

6/MAX157

Table 3. Bipolar Code Table

+5V/

+3V

DAC CONTENTS

+5V/+3V

ANALOG OUTPUT

26k

AC

MSB

LSB

MAX495

REF_

REFERENCE

INPUT

2047

1 1 1 1

1 1 1 1 1 1 1 1 (0 )

+V

REF

2048

1

10k

500mVp-p

1 0 0 0

0 1 1 1

0 0 0 0 0 0 0 1 (0 )

0 0 0 0 0 0 0 0 (0 )

1 1 1 1 1 1 1 1 (0 )

+V

V

DD

REF

2048

FB_

0V

1

-V

REF

2048

DAC_

OUT_

2047

0 0 0 0

0 0 0 0 0 0 0 1 (0 )

0 0 0 0 0 0 0 0 (0 )

-V

REF

2048

MAX5156

MAX5157

DGND

AGND

2048

-V

= - V

REF

2098

Note: ( ) are for the sub bit.

Figure 12. AC Reference Input Circuit

Us in g a n AC Re fe re n c e

Ha rm o n ic Dis t o rt io n a n d No is e

The total harmonic distortion plus noise (THD+N) is typ-

ically less than -80dB at full scale with a 1Vp-p input

swing at 5kHz. The typical -3dB frequency is 600kHz

for both devices, as shown in the Typical Operating

Characteristics.

In applications where the reference has an AC signal

component, the MAX5156/MAX5157 have multiplying

capabilities within the reference input voltage range

specifications. Figure 12 shows a technique for apply-

ing a sinusoidal input REF_, where the AC signal is off-

set before being applied to the reference input.

14 ______________________________________________________________________________________

Lo w -P o w e r, Du a l, 1 2 -Bit Vo lt a g e -Ou t p u t DACs

w it h Co n fig u ra b le Ou t p u t s

6/MAX157

Dig it a l Ca lib ra t io n a n d

Th re s h o ld S e le c t io n

Figure 13 shows the MAX5156/MAX5157 in a digital

calibration application. With a bright value applied to

V+

REF_

+5V/+3V

PHOTODIODE

the photodiode (on), the DAC is digitally ramped up

until it trips the comparator. The microprocessor stores

this high calibration value. Repeat the process with a

dim light (off) to obtain the dark current calibration. The

microprocessor then programs the DAC to set an out-

put voltage that is the midpoint of the two calibration

values. Applications include tachometers, motion sens-

ing, automatic readers, and liquid clarity analysis.

V

DD

MAX5156

MAX5157

V+

FB_

V

OUT

OUT_

Dig it a l Co n t ro l o f Ga in a n d Offs e t

The two DACs can be used to control the offset and

gain for curve-fitting nonlinear functions, such as trans-

ducer linearization or analog compression/expansion

applications. The input signal is used as the reference

for the gain-adjust DAC, whose output is summed with

the output from the offset-adjust DAC. The relative

weight of each DAC output is adjusted by R1, R2, R3,

and R4 (Figure 14).

DAC _

µP

V-

DIN

R

DGND

AGND

Figure 13. Digital Calibration

+5V/+3V

V

DD

FBA

V

IN

R1

REFA

DACA

CS

OUT_A

OUT_B

R2

DIN

SCLK

CL

V

OUT

R3

DACB

REFB

R4

1+

V

REF

FBB

MAX5156

MAX5157

V

OUT

= GAIN

- OFFSET

[

] [

]

(

)( )( ) ( ^NB)(^R4)

NA

R2

R4

=

V

REF

IN

[

_R3] [

]

4096

R1+R2

R3

DGND

AGND

NA IS THE NUMERIC VALUE OF THE INPUT CODE FOR DACA.

NB IS THE NUMERIC VALUE OF THE INPUT CODE FOR DACB.

Figure 14. Digital Control of Gain and Offset

______________________________________________________________________________________ 15

Lo w -P o w e r, Du a l, 1 2 -Bit Vo lt a g e -Ou t p u t DACs

w it h Co n fig u ra b le Ou t p u t s

Dig it a lly P ro g ra m m a b le Cu rre n t S o u rc e

Figure 15 depicts a digitally programmable, unidirec-

tional current source that can be used in industrial con-

trol applications. The output current is:

+5V/+3V REF_

I

= (V

/ R) (NB / 4096)

OUT

REF

V

L

where NB is the DAC code and R is the sense resistor.

V

DD

I

OUT

P o w e r-S u p p ly Co n s id e ra t io n s

On power-up, the input and DAC registers clear (resets

DAC_

OUT_

FB_

2N3904

to zero code). For rated performance, V

should be

REF_

at least 1.4V below V . Bypass the power supply with

DD

a 4.7µF capacitor in parallel with a 0.1µF capacitor to

GND. Minimize lead lengths to reduce lead inductance.

MAX5156

MAX5157

R

Gro u n d in g a n d La yo u t Co n s id e ra t io n s

Digital and AC transient signals on AGND can create

noise at the output. Connect AGND to the highest quali-

ty ground available. Use proper grounding techniques,

s uc h a s a multila ye r b oa rd with a low-ind uc ta nc e

ground plane. Carefully lay out the traces between

channels to reduce AC cross-coupling and crosstalk.

Wire-wrapped boards and sockets are not recommend-

e d . If nois e b e c ome s a n is s ue , s hie ld ing ma y b e

required.

DGND

AGND

6/MAX157

Figure 15. Digitally Programmable Current Source

__________________P in Co n fig u ra t io n

_Ord e rin g In fo rm a t io n (c o n t in u e d )

INL

PART

TEMP. RANGE

PIN-PACKAGE

TOP VIEW

(LSB)

±1/2

±1

AGND

OUTA

FBA

REFA

CL

1

2

3

4

5

6

7

8

16 V

DD

MAX5156AEPE -40°C to +85°C

MAX5156BEPE -40°C to +85°C

MAX5156AEEE -40°C to +85°C

MAX5156BEEE -40°C to +85°C

16 Plastic DIP

16 QSOP

15 OUTB

14 FBB

13 REFB

12 PDL

11 UPO

10 DOUT

±1/2

±1

16 QSOP

MAX5156

MAX5157

MAX5156BMJE -55°C to +125°C 16 CERDIP*

±1

MAX5157ACPE

MAX5157BCPE

MAX5157ACEE

MAX5157BCEE

0°C to +70°C

16 Plastic DIP

16 QSOP

±1

CS

±2

DIN

±1

16 QSOP

±2

SCLK

9 DGND

MAX5157AEPE -40°C to +85°C

MAX5157BEPE -40°C to +85°C

MAX5157AEEE -40°C to +85°C

MAX5157BEEE -40°C to +85°C

16 Plastic DIP

16 QSOP

±1

DIP/QSOP

±2

±1

16 QSOP

±2

MAX5157BMJE -55°C to +125°C 16 CERDIP*

±2

___________________Ch ip In fo rm a t io n

*Contact factory for availability.

TRANSISTOR COUNT: 3053

SUBSTRATE CONNECTED TO AGND

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are

implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

16 ____________________Ma x im In t e g ra t e d P ro d u c t s , 1 2 0 S a n Ga b rie l Drive , S u n n yva le , CA 9 4 0 8 6 4 0 8 -7 3 7 -7 6 0 0

Printed USA

is a registered trademark of Maxim Integrated Products.


型号：	MAX5156BEEE+T
厂家：	MAXIM INTEGRATED PRODUCTS
描述：	D/A Converter, 2 Func, Serial Input Loading, 16us Settling Time, PDSO16, 0.150 INCH, 0.025 INCH PITCH, ROHS COMPLIANT, QSOP-16
文件：	总16页 (文件大小：146K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MAX5156BEEE+T [MAXIM]

相关型号：

MAX5156BEPE

MAX5156BEPE+

MAX5156BMJE

MAX5157

MAX5157ACEE

MAX5157ACEE+

MAX5157ACEE+T

MAX5157ACEE-T

MAX5157ACPE

MAX5157AEEE

MAX5157AEEE+

MAX5157AEPE