MAX5100 [MAXIM]

+2.7V to +5.5V, Low-Power, Quad, Parallel 8-Bit DAC with Rail-to-Rail Voltage Outputs; + 2.7V至+ 5.5V ，低功耗，四通道，并行8位DAC，具有轨至轨电压输出


型号：	MAX5100
厂家：	MAXIM INTEGRATED PRODUCTS
描述：	+2.7V to +5.5V, Low-Power, Quad, Parallel 8-Bit DAC with Rail-to-Rail Voltage Outputs + 2.7V至+ 5.5V ，低功耗，四通道，并行8位DAC，具有轨至轨电压输出
文件：	总8页 (文件大小：402K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

19-1557; Rev 0; 10/99

+2.7V to +5.5V, Low-Power, Quad, Parallel

8-Bit DAC with Rail-to-Rail Voltage Outputs

General Description

Features

The MAX5100 parallel-input, voltage-output, quad 8-bit

digital-to-analog converter (DAC) operates from a sin-

gle +2.7V to +5.5V supply and comes in a space-sav-

ing 20-pin TSSOP package. Internal precision buffers

swing Rail-to-Rail^®, and the reference input range

includes both ground and the positive rail. All four

DACs share a common reference input.

ꢀ +2.7V to +5.5V Single-Supply Operation

ꢀ Ultra-Low Supply Current

0.4mA while Operating

1nA in Shutdown Mode

ꢀ Ultra-Small 20-Pin TSSOP Package

ꢀ Ground to V

Reference Input Range

The MAX5100 provides double-buffered logic inputs:

four 8-bit buffer registers followed by four 8-bit DAC

registers. This keeps the DAC outputs from changing

during the write operation. An asynchronous control

pin, LDAC, allows for simultaneous updating of the

DAC registers.

ꢀ Output Buffer Amplifiers Swing Rail-to-Rail

ꢀ Double-Buffered Registers for Synchronous

Updating

ꢀ Power-On Reset Sets All Registers to Zero

The MAX5100 features a shutdown mode that reduces

current to 1nA, as well as a power-on reset mode that

resets all registers to code 00 hex on power-up.

Ordering Information

INL

(LSB)

PART

TEMP. RANGE PIN-PACKAGE

MAX5100AEUP -40°C to +85°C 20 TSSOP

MAX5100BEUP -40°C to +85°C 20 TSSOP

Applications

Digital Gain and Offset Adjustments

Programmable Attenuators

Portable Instruments

Pin Configuration

TOP VIEW

OUTB

OUTA

20 OUTC

19 OUTD

18 GND

17 A0

Power-Amp Bias Control

REF

SHDN

MAX5100

16 A1

15 LDAC

13 D1

12 D2

11 D3

D4 10

TSSOP

Rail-to-Rail is a registered trademark of Nippon Motorola, Ltd.

________________________________________________________________ Maxim Integrated Products

For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800.

For small orders, phone 1-800-835-8769.

+2.7V to +5.5V, Low-Power, Quad, Parallel

8-Bit DAC with Rail-to-Rail Voltage Outputs

ABSOLUTE MAXIMUM RATINGS

to GND..............................................................-0.3V to +6V

Operating Temperature Range

D_, A_, WR, SHDN, LDAC to GND...........................-0.3V to +6V

REF to GND................................................-0.3V to (V + 0.3V)

MAX5100_EUP ..............................................-40°C to +85°C

Maximum Junction Temperature .....................................+150°C

Storage Temperature Range.............................-65°C to +150°C

Lead Temperature (soldering, 10sec) .............................+300°C

OUT_ to GND ...........................................................-0.3V to V

Maximum Current into Any Pin ......................................... 50mA

Continuous Power Dissipation (T = +70°C)

20-Pin TSSOP (derate 7.0mW/°C above +70°C) .......559mW

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional

operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to

absolute maximum rating conditions for extended periods may affect device reliability.

ELECTRICAL CHARACTERISTICS

= V

= +2.7V to +5.5V, R = 10kΩ, C = 100pF, T = T

to T

, unless otherwise noted. Typical values are at V

= V

DD REF

REF

MIN

MAX

= +3V and T = +25°C.)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

STATIC ACCURACY

Resolution

Bits

MAX5100A

MAX5100B

Integral Nonlinearity (Note 1)

INL

LSB

Differential Nonlinearity (Note 1)

Zero-Code Error

DNL

ZCE

Guaranteed monotonic

Code = 00 hex

LSB

Zero-Code-Error Supply

Rejection

Code = 00 hex, V

= 2.7V to 5.5V

Zero-Code Temperature

Coefficient

Code = 00 hex

Code = F0 hex

µV/°C

Gain Error (Note 2)

Gain-Error Temperature

Coefficient

0.001

LSB/°C

= 2.7V to 3.6V,

= 2.5V

REF

Power-Supply Rejection

Code = FF hex

LSB

= 4.5V to 5.5V,

= 4.096V

REF

REFERENCE INPUT

Input Voltage Range

Input Resistance

Input Capacitance

DAC OUTPUTS

320

460

600

kΩ

Output Voltage Range

R = ∞

REF

DIGITAL INPUTS

= 2.7V to 3.6V

Input High Voltage

= 3.6V to 5.5V

Input Low Voltage

Input Current

0.8

1.0

= V or GND

µA

Input Capacitance

_______________________________________________________________________________________

+2.7V to +5.5V, Low-Power, Quad, Parallel

8-Bit DAC with Rail-to-Rail Voltage Outputs

ELECTRICAL CHARACTERISTICS (continued)

= V

= +2.7V to +5.5V, R = 10kΩ, C = 100pF, T = T

to T

, unless otherwise noted. Typical values are at V

= V

DD REF

REF

MIN

MAX

= +3V and T = +25°C.)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

DYNAMIC PERFORMANCE

Output Voltage Slew Rate

From code 00 to code F0 hex

0.6

V/µs

µs

Output Settling Time (Note 3)

To 1/2LSB, from code 10 to code F0 hex

Channel-to-Channel Isolation

(Note 4)

Code 00 to code FF hex

Code 80 hex to code 7F hex

500

0.5

nVs

Digital Feedthrough (Note 5)

Digital-to-Analog Glitch Impulse

REF = 2.5Vp-p at

1kHz

= 1.5V,

= 3V,

REF(DC)

Signal-to-Noise plus Distortion

Ratio

SINAD

REF = 2.5Vp-p at

10kHz

code = FF hex

REF = 0.5Vp-p, V

= 1.5V,

REF(DC)

Multiplying Bandwidth

650

kHz

= 3V, -3dB bandwidth

Wideband Amplifier Noise

Shutdown Recovery Time

Time to Shutdown

µV

RMS

To 1/2LSB of final value of V

µs

SDR

OUT

< 5µA

SDN

POWER SUPPLIES

Power-Supply Voltage

2.7

5.5

700

Supply Current (Note 6)

Shutdown Current

370

µA

0.001

DIGITAL TIMING (Figure 1) (Note 7)

Address to WR Setup

Address to WR Hold

Data to WR Setup

Data to WR Hold

WR Pulse Width

LDAC Pulse Width (Note 8)

Note 1: Reduced digital code range (code 00 hex to code F0 hex) due to swing limitations when the output amplifier is loaded.

Note 2: Gain error is: [100 (V - ZCE - V ) / V ]. Where V is the DAC output voltage with input code F0 hex,

F0,meas

F0,ideal

REF

F0,meas

and V

is the ideal DAC output voltage with input code F0 hex (i.e., V_REF· 240 / 256).

F0,ideal

Note 3: Output settling time is measured from the 50% point of the falling edge of WR to 1/2LSB of V

’s final value.

OUT

Note 4: Channel-to-channel isolation is defined as the glitch energy at a DAC output in response to a full-scale step change on any

other DAC output. The measured channel has a fixed code of 80 hex.

Note 5: Digital feedthrough is defined as the glitch energy at any DAC output in response to a full-scale step change on all eight

data inputs with WR at V

Note 6: R = ∞, digital inputs at GND or V

Note 7: Timing measurement reference level is (V + V ) / 2.

Note 8: If LDAC is activated prior to WR’s rising edge, it must stay low for t (or longer) after WR goes high.

_______________________________________________________________________________________

+2.7V to +5.5V, Low-Power, Quad, Parallel

8-Bit DAC with Rail-to-Rail Voltage Outputs

ADDRESS

ADDRESS VALID

AH-

LDAC (NOTE 8)

DH-

DS-

DATA

DATA VALID

Figure 1. Timing Diagram

Typical Operating Characteristics

= V

= +3V, R = 10kΩ, C = 100pF, code = FF hex, T = +25°C, unless otherwise noted.)

REF

DAC ZERO-CODE OUTPUT VOLTAGE

vs. SINK CURRENT

DAC FULL-SCALE OUTPUT VOLTAGE

vs. SOURCE CURRENT

SUPPLY CURRENT vs. TEMPERATURE

340

320

300

280

260

240

220

200

180

1.2

1 DAC AT CODE 00 OR F0,

3 DACS AT 00 (R = ∞)

1.0

0.8

0.6

0.4

0.2

= 5V; CODE = F0 HEX

= 5V; CODE = 00 HEX

= V = 5V

REF

= V = 3V

REF

= V = 3V

REF

= 3V; CODE = F0 HEX

= V = 5V

REF

= 3V; CODE = 00 HEX

-40 -20

80 100

SINK CURRENT (mA)

SOURCE CURRENT (mA)

TEMPERATURE (°C)

SUPPLY CURRENT vs. REFERENCE VOLTAGE

TOTAL HARMONIC DISTORTION PLUS NOISE

AT DAC OUTPUT vs. REFERENCE AMPLITUDE

(V = 3V)

(V = 5V)

300

280

260

240

220

200

180

160

140

320

300

1 DAC AT CODE 00 OR F0, 3 DACS AT 00 (R = ∞)

= +3V

1 DAC AT CODE 00 OR F0, 3 DACS AT 00 (R = ∞)

DAC CODE = FF HEX

= SINE WAVE CENTERED AT 1.5V

-10

-20

-30

-40

-50

-60

-70

-80

CODE = F0

REF

CODE = F0

80kHz FILTER

280

260

240

220

10kHz REF SIGNAL

20kHz REF SIGNAL

CODE = 00

1kHz REF SIGNAL

0.5 1.0

REFERENCE AMPLITUDE (V

200

0.5

1.0

1.5

2.0

2.5

3.0

0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0

REFERENCE VOLTAGE (V)

1.5

2.0

2.5

REFERENCE VOLTAGE (V)

)

p-p

_______________________________________________________________________________________

+2.7V to +5.5V, Low-Power, Quad, Parallel

8-Bit DAC with Rail-to-Rail Voltage Outputs

Typical Operating Characteristics (continued)

= V

= +3V, R = 10kΩ, C = 100pF, code = FF hex, T = +25°C, unless otherwise noted.)

REF

REFERENCE INPUT

FREQUENCY RESPONSE

TOTAL HARMONIC DISTORTION PLUS NOISE

AT DAC OUTPUT vs. REFERENCE FREQUENCY

WORST-CASE 1LSB DIGITAL STEP CHANGE

(NEGATIVE)

= +3V

CH1 = LDAC, 2V/div

DAC CODE = FF HEX

= SINE WAVE CENTERED AT 1.5V

CH2 = V

, 50mV/div,

OUTA

-10

AC-COUPLED

DAC CODE FROM

80 TO 7F HEX

REF

-10

1kHz FREQUENCY

500kHz FILTER

-20

-30

-40

-50

-60

-70

-80

-20

-30

-40

-50

REF = 0.5V

p-p

REF = 1V

p-p

-60

-70

REF = 2V

p-p

CODE = FF HEX, REF IS 1V SIGNAL

-80

-90

p-p

= 1.5V

REF

1µs/div

0.01

0.1

100

FREQUENCY (MHz)

FREQUENCY (kHz)

WORST-CASE 1LSB DIGITAL STEP CHANGE

(POSITIVE)

DIGITAL FEEDTHROUGH GLITCH IMPULSE

(0 TO 1 DIGITAL TRANSITION)

DIGITAL FEEDTHROUGH GLITCH IMPULSE

(1 TO 0 DIGITAL TRANSITION)

CH1 = LDAC, 2V/div

CH1 = D7, 2V/div

OUTA

AC-COUPLED

0 TO 1 DIGITAL TRANSITION ON

ALL DATA BITS (WITH WR HIGH,

LDAC LOW)

CH1 = D7, 2V/div

OUTA

AC-COUPLED

1 TO 0 DIGITAL TRANSITION ON

ALL DATA BITS (WITH WR HIGH,

LDAC LOW)

CH2 = V

, 50mV/div,

CH2 = V

, 2mV/div,

CH2 = V

, 2mV/div,

OUTA

AC-COUPLED

DAC CODE FROM

7F TO 80 HEX

1µs/div

20ns/div

INTEGRAL AND DIFFERENTIAL NONLINEARITY

vs. DIGITAL CODE

POSITIVE SETTLING TIME

NEGATIVE SETTLING TIME

0.5

R = ∞

CH1 = WR, 2V/div

0.4

0.3

CH2 = V

, 2V/div

CH2 = V

, 2V/div

OUTA

DAC CODE FROM

OUTA

DAC CODE FROM

10 TO F0 HEX

0.2

DNL

0.1

-0.1

-0.2

-0.3

-0.4

-0.5

INL

1µs/div

32 64 96 128 160 192 224 256

DIGITAL CODE

_______________________________________________________________________________________

+2.7V to +5.5V, Low-Power, Quad, Parallel

8-Bit DAC with Rail-to-Rail Voltage Outputs

Pin Description

NAME

OUTB

OUTA

FUNCTION

DAC B Voltage Output

DAC A Voltage Output

Positive Supply Voltage. Bypass V

to GND using a 0.1µF capacitor.

REF

SHDN

Reference Voltage Input

Shutdown. Connect SHDN to GND for normal operation.

Write Input (active low). Use WR to load data into the DAC input latch selected by A0 and A1.

7–14

D7–D0

Data Inputs 7–0

Load DAC Input (active low). Drive the asynchronous LDAC input low to transfer the contents of all input

latches to their respective DAC latch.

LDAC

DAC Address Select Bit (MSB)

DAC Address Select Bit (LSB)

Ground

GND

OUTD

OUTC

DAC D Voltage Output

DAC C Voltage Output

device out of shutdown, allow 13µs for the output to

Detailed Description

Digital-to-Analog Section

stabilize.

Output Buffer Amplifiers

The DAC outputs are internally buffered by precision

amplifiers with a typical slew rate of 0.6V/µs. The typical

settling time to 1/2LSB at the output is 6µs when

loaded with 10kΩ in parallel with 100pF.

The MAX5100 uses a matrix decoding architecture for

the DACs. The external reference voltage is divided

down by a resistor string placed in a matrix fashion.

Row and column decoders select the appropriate tab

from the resistor string to provide the needed analog

voltages. The resistor network converts the 8-bit digital

input into an equivalent analog output voltage in pro-

portion to the applied reference voltage input. The

resistor string presents a code-independent input

impedance to the reference and guarantees a monoton-

ic output.

Reference Input

The MAX5100 provides a code-independent input

impedance on the REF input. The input impedance is

typically 460kΩ in parallel with 15pF, and the reference

input voltage range is 0 to V . The reference input

accepts positive DC signals as well as AC signals with

The device can be used in multiplying applications.

The voltages are buffered by rail-to-rail op amps con-

nected in a follower configuration to provide a rail-to-rail

output. The functional block diagram for the MAX5100

is shown in Figure 2.

peak values between 0 and V . The voltage at REF

sets the full-scale output voltage for the DAC. The out-

put voltage (V

) for any DAC is represented by a

OUT

digitally programmable voltage source as follows:

OUT

= (N · V ) / 256

REF

Low-Power Shutdown Mode

The MAX5100 features a shutdown mode that reduces

current consumption to 1nA. A high voltage on the

shutdown pin shuts down the DACs and the output

amplifiers. In shutdown mode, the output amplifiers

enter a high-impedance state. When bringing the

where N is the numeric value of the DAC binary input

code.

Digital Inputs and Interface Logic

In the MAX5100, address lines A0 and A1 select the

DAC that receives data from D0–D7, as shown in Table 1.

_______________________________________________________________________________________

+2.7V to +5.5V, Low-Power, Quad, Parallel

8-Bit DAC with Rail-to-Rail Voltage Outputs

INPUT

LATCH A

DAC A

LATCH

DAC A

OUTA

OUTB

OUTC

OUTD

INPUT

LATCH B

DAC B

LATCH

DAC B

DAC C

D0–D7

INPUT

LATCH C

DAC C

LATCH

INPUT

LATCH D

DAC D

LATCH

DAC D

CONTROL

LOGIC

MAX5100

LDAC

REF

SHDN

Figure 2. Functional Diagram

Applications Information

Table 1. MAX5100 Address Table (Partial)

External Reference

LATCH STATE

LDAC WR

The reference source resistance must be considerably

less than the reference input resistance. To keep within

Input and DAC data latched

DAC A input latch transparent

1LSB error in an 8-bit system, R must be less than

/ 256. Hence, maintain a value of R <1kΩ to

REF

ensure 8-bit accuracy. If V

is DC only, bypass REF

REF

All 4 DACs’ DAC latches

transparent

to GND with a 0.1µF capacitor. Values greater than this

improve noise rejection.

DAC A input registers transpar-

ent and all 4 DACs’ DAC

latches transparent

Power Sequencing

The voltage applied to REF should not exceed V

any time. If proper power sequencing is not possible,

DAC B input latch transparent

DAC C input latch transparent

DAC D input latch transparent

connect an external Schottky diode between REF and

to ensure compliance with the absolute maximum

ratings.

Power-Supply Bypassing and

Ground Management

H = High state, L = Low state, X = Don’t care

Digital or AC transient signals on GND can create noise

at the analog output. Return GND to the highest-quality

When WR is low, the addressed DAC’s input latch is

transparent. Data is latched when WR is high.

ground available. Bypass V

with a 0.1µF capacitor,

The MAX5100 LDAC feature allows simultaneous

updating of all four DACs. LDAC low latches the data in

the data registers to the DAC registers. If simultaneous

updating is not required, tie LDAC low to keep the DAC

latches transparent. If WR and LDAC are low simultane-

ously, avoid output glitches by ensuring that data is

valid before the two signals go low. When the device

located as close to V

and GND as possible.

Careful PC board ground layout minimizes crosstalk

between the DAC outputs and digital inputs.

Chip Information

TRANSISTOR COUNT: 6848

powers up (i.e., V

ramps up), all latches are internal-

ly preset with code 00 hex.

_______________________________________________________________________________________

+2.7V to +5.5V, Low-Power, Quad, Parallel

8-Bit DAC with Rail-to-Rail Voltage Outputs

Package Information

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are

implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

8 _____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600

Printed USA

is a registered trademark of Maxim Integrated Products.

MAX5100 [MAXIM]

相关型号：

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MAX5100AEUP+T

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MAX5100BEUP+

MAX5100BEUP-T

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MAX5101AEUE+T

MAX5101BEUE

MAX5101BEUE+

MAX5102