MAX5092BATE+ [MAXIM]
4V to 72V Input LDOs with Boost Preregulator; 4V至72V输入LDO，具有升压预调节器
| 型号： | MAX5092BATE+ |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | 4V to 72V Input LDOs with Boost Preregulator |
| 文件： | 总23页 (文件大小：1025K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-0659; Rev 0; 10/06
4V to 72V Input LDOs with Boost Preregulator
2/MAX5093
General Description
Features
♦ Wide Operating Input Voltage Range: 3.5V to 72V
The MAX5092A/MAX5092B/MAX5093A/MAX5093B low-
quiescent-current, low-dropout (LDO) regulators contain
simple boost preregulators operating at a high frequency.
The devices seamlessly provide a preset 3.3V
(MAX5092A/MAX5093A) or 5V (MAX5092B/MAX5093B)
LDO output voltage from an automotive cold-crank
through load-dump (3.5V to 80V) input voltage condi-
tions. The MAX5092_/MAX5093_ deliver up to 250mA
with excellent load and line regulation. During normal
operation, when the battery is healthy, the boost preregu-
lator is completely turned off, reducing quiescent current
to 65µA (typ). This makes the devices suitable for
always-on power supplies.
with a 4V Startup Voltage
♦ LDO Output Regulates to 5V Seamlessly from an
Input Voltage of 3.5V to 72V
♦ Up to 250mA Output Current
♦ Preset 3.3V, 5V, or Externally Programmable LDO
Output Voltage from 1.5V to 9V (MAX5092_) or
from 1.5V to 10V (MAX5093_)
♦ Preset 7V or Externally Programmable Boost
Output Voltage Up to 11V (MAX5092_) or Up to
12V (MAX5093_)
♦ 65µA Quiescent Current in LDO Mode (V ≥8V)
IN
♦ 5µA Shutdown Current
The buck-boost operation achieved by this combination
of LDO and boost preregulator offers the advantage of
using a single off-the-shelf inductor in place of the mul-
tiple-winding custom magnetics needed in typical sin-
gle-ended primary inductor converter (SEPIC) and
transformer-based flyback topologies. The high operat-
ing frequency of the boost regulator significantly
reduces component size. The MAX5092_ integrates a
blocking diode to further reduce the external compo-
nent count. The boost preregulator output voltage is
preset to 7V. Both LDO and boost output voltages are
programmable using external resistors. The boost pre-
regulator output voltage is adjustable up to 11V
(MAX5092_), or up to 12V (MAX5093_). The LDO output
voltage is adjustable from 1.5V to 9V (MAX5092_) or
from 1.5V to 10V (MAX5093_).
♦ Power-On Reset (RESET) with Programmable
Timeout Period
♦ Output Short-Circuit and Thermal Protection
♦ TQFN Package Capable of Dissipating Up to 2.7W
at +70°C
Ordering Information
PIN-
PACKAGE
PKG
CODE
PART
TEMP RANGE
MAX5092AATE+* -40°C to +125°C 16 TQFN-EP** T1655-3
MAX5092BATE+ -40°C to +125°C 16 TQFN-EP** T1655-3
MAX5093AATE+* -40°C to +125°C 16 TQFN-EP** T1655-3
MAX5093BATE+ -40°C to +125°C 16 TQFN-EP** T1655-3
+Denotes lead-free package.
*Future product—contact factory for availability.
**EP = Exposed pad.
The devices feature a shutdown mode with 5µA (typ)
shutdown current, a HOLD input to implement a self-hold-
ing circuit, and a power-on-reset output (RESET) with an
externally programmable timeout period. Additional fea-
tures include output overload, short-circuit, and thermal
protection.
Pin Configuration
TOP VIEW
The MAX5092_/MAX5093_ are available in a thermally
enhanced, 16-pin 5mm x 5mm thin QFN package and can
dissipate up to 2.7W at +70°C on a multilayer PC board.
12
11
10
9
OUT
8
7
6
5
BSFB 13
VL 14
Applications
OUT_SENSE
SET
Automotive—Body Electronics
Automotive—ECU
Industrial
MAX5092_/
MAX5093_
CT 15
16
PGND_LDO
RESET
+
1
2
3
4
Typical Operating Circuit and Selector Guide appear at end
of data sheet.
THIN QFN
(5mm x 5mm)
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
4V to 72V Input LDOs with Boost Preregulator
ABSOLUTE MAXIMUM RATINGS
IN, EN, LX, BSOUT to SGND..................................-0.3V to +80V
PGND_BST, PGND_LDO to SGND .......................-0.3V to +0.3V
VL, RESET, OUT, OUT_SENSE to SGND ...............-0.3V to +12V
BSOUT to LX (MAX5092_)......................................-0.3V to +12V
SET, BSFB, CT to SGND ..........................................-0.3V to +6V
RESET Sinking Current .........................................................5mA
Continuous Power Dissipation (T = +70°C)
A
16-Pin Thin QFN (derate 33.3mW/°C
above +70°C)...............................................2666mW (Note 1)
Operating Temperature Range .........................-40°C to +125°C
Maximum Junction Temperature .....................................+150°C
Storage Temperature Range.............................-60°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
HOLD to SGND….....................................-0.3V to (V
+ 0.3V)
OUT
OUT Current (I
) Short Circuit to PGND_LDO,
OUT
(V ≤ 28V) ..............................................................Continuous
IN
Note 1: As per JEDEC Standard 51 (Multilayer Board).
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V = V = 14V, I
= 1mA, C = 47µF, C
= 22µF, C
= 10µF, C = 1µF, T = T = -40°C to +125°C, unless otherwise
OUT VL A J
IN
EN
OUT
IN
BSOUT
noted. See Figures 4–7 as applicable. Typical specifications are at T = +25°C.) (Note 2)
A
2/MAX5093
PARAMETER
INPUT SUPPLY
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Input Voltage Range
V
(Note 3)
4
72
3.4
3.8
V
V
IN
V
V
V
V
falling
rising
3.0
3.4
3.2
3.6
UVLOF
UVLOR
IN
IN
Internal Input Undervoltage
Lockout
LDO mode,
= 100µA
T = -40°C to +125°C
J
(Note 4)
65
85
Supply Current (Boost Converter
Off)
I
OUT
I
µA
Q
LDO mode, I
= 250mA
70
100
1.0
OUT
Supply Current (Boost Converter
On)
I
V
V
= 5V
0.4
mA
µA
S
IN
T = -40°C to +125°C
J
(Note 4)
Shutdown Supply Current
I
≤ +0.4V
6
10
SHDN
EN
BOOST CONVERTER
Minimum BSOUT Output Current
I
V
V
= 4V
250
8.0
mA
V
BSOUT
IN
IN
Boost Converter Disable
Threshold
V
rising
7.5
8.5
BST_DIS
Boost Converter Disable
Threshold Hysteresis
0.5
V
V
V
BSOUT Output Voltage
V
V
= 4V, BSFB = SGND
6.65
1.18
7.00
11
7.35
BSOUT
V
BSOUT(MAX)
IN
MAX5092_
MAX5093_
Maximum BSOUT Output Voltage
12
BSFB Regulation Voltage
BSFB Input Bias Current
V
1.24
1.30
100
V
BSFB
I
nA
BSFB
Boost Internal Switch
On-Resistance
R
0.5
1
1.2
Ω
DS(ON)
Boost Internal Switch Minimum
Off-Time
t
0.80
1.25
µs
OFF
2
_______________________________________________________________________________________
4V to 72V Input LDOs with Boost Preregulator
2/MAX5093
ELECTRICAL CHARACTERISTICS (continued)
(V = V = 14V, I
= 1mA, C = 47µF, C
= 22µF, C
= 10µF, C = 1µF, T = T = -40°C to +125°C, unless otherwise
OUT VL A J
IN
EN
OUT
IN
BSOUT
noted. See Figures 4–7 as applicable. Typical specifications are at T = +25°C.) (Note 2)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
1.80
1.5
TYP
MAX
2.70
3.0
5
UNITS
µs
Boost Internal Switch Maximum
On-Time
t
2.25
ON-MAX
Internal Switch Current Limit
I
Measured in steady-state condition
A
LIM
Time from V
falling below regulation
BSOUT
Boost Turn-On Response Time
2
µs
to switch on-time
Internal Diode Forward Voltage
Drop
V
MAX5092_ only, I = 1A
0.95
V
F
F
LDO
Guaranteed Output Current
I
V
- V = 2V (Note 5)
OUT
250
mA
OUT
BSOUT
I
= 1mA
3.25
3.3
3.3
5
3.35
3.4
OUT
SET = SGND,
MAX5092A/
MAX5093A
100µA ≤ I
≤ 250mA
3.2
4.900
4.85
OUT
Output Voltage
V
V
OUT
I
= 1mA
5.075
5.10
OUT
SET = SGND,
MAX5092B/
MAX5093B
100µA ≤ I
≤ 250mA
5
OUT
Minimum Adjustable Output
Voltage
V
Boost operation, V = 4V, V
= 7V
1.5
9
V
V
ADJMIN
IN
BSOUT
MAX5092_,
= 11V
V
BSOUT
Maximum Adjustable Output
Voltage
Boost operation,
= 4V
V
ADJMAX
V
IN
MAX5093_,
= 12V
10
V
BSOUT
LDO operation, V ≥ V
(boost converter off) (Note 6)
IN
BST_DIS
Adjustable Output Voltage
Dropout Voltage
V
1.5
10.0
1.6
V
V
ADJ
∆V
I
= 250mA (Note 7)
0.9
DO
OUT
Rising edge of V
to the rising edge of
BSOUT
LDO Startup Response Time
200
µs
V
, R = 500Ω, SET = SGND
OUT L
MAX5092A/MAX5093A
MAX5092B/MAX5093B
0.4
0.5
7V ≤ V ≤ 72V,
IN
∆V
∆V
/
/
OUT
I
= 10mA
Line Regulation
LOAD
mV/V
IN
7V ≤ V ≤ 28V, I
= 250mA
1.6
1.235
0.5
IN
LOAD
SET Reference Voltage
SET Input Bias Current
V
1.205
1.265
100
V
SET
I
nA
SET
∆V
OUT
Load Regulation
I
= 1mA to 250mA
0.2
80
0.6
mV/mA
OUT
∆I
OUT
I
= 10mA, V
BSOUT(AC)
OUT
f = 100Hz
f = 1MHz
= 500mV , V
= 5V
P-P OUT
Power-Supply Rejection Ratio
Short-Circuit Current
PSRR
dB
I
= 10mA, V
BSOUT(AC)
OUT
60
= 500mV , V
= 5V
P-P OUT
I
255
490
mA
SC
_______________________________________________________________________________________
3
4V to 72V Input LDOs with Boost Preregulator
ELECTRICAL CHARACTERISTICS (continued)
(V = V = 14V, I
= 1mA, C = 47µF, C
= 22µF, C
= 10µF, C = 1µF, T = T = -40°C to +125°C, unless otherwise
OUT VL A J
IN
EN
OUT
IN
BSOUT
noted. See Figures 4–7 as applicable. Typical specifications are at T = +25°C.) (Note 2)
A
PARAMETER
ENABLE, HOLD and RESET
EN High Input Threshold
EN Low Input Threshold
EN Input Bias Current
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
EN
2.4
V
V
H
EN
0.4
2
L
I
0.25
µA
V
EN
HOLD Low Input Threshold
V
Regulator on, EN transition from high to low
EN = low
0.4
IL
V
-
OUT
0.4
HOLD Release Voltage
V
V
IH
HOLD Pullup Current
I
Internally connected to OUT
4
90
2
µA
%
%
V
HOLD
RESET Voltage Threshold
RESET Threshold Hysteresis
RESET Output Low Voltage
V
V
% of V
% of V
, V
falling
87
92
RESET
OUT OUT
RHYST
OUT
V
I
= 1mA
0.4
1
RL
SINK
2/MAX5093
RESET Output High Leakage
Current
I
V
= 5V
R E SE T
µA
µs
µs
V
RH
RESET Output Minimum Timeout
Period
C
C
not connected
not connected
25
CT
CT
EN to RESET Minimum Timeout
Delay
260
1.24
100
Delay Comparator Threshold
(Rising)
V
1.205
1.5
1.265
2.5
CTTH
Delay Comparator Threshold
Hysteresis
V
mV
CTTH-HYS
CT Charge Current
I
2
5
µA
CT-CHG
CT Discharge Current
I
mA
CT-DIS
Note 2: Limits at -40°C are guaranteed by design and characterization; not production tested.
Note 3: Guaranteed minimum operating voltage is 3.5V on V falling only.
IN
Note 4: Guaranteed by design and not production tested.
Note 5: The continuous maximum output current from the LDO is guaranteed according to the maximum power dissipation imposed
by the package thermal constraints.
Note 6: Maximum output adjustable value is conditioned by the maximum adjustable BSOUT Output Voltage Range minus the maxi-
mum dropout across the pass transistor.
Note 7: Dropout voltage is defined as (V
- V
) when V
is 2% below the value of V
for V
= V
+ 2V.
BSOUT
OUT
OUT
OUT
BSOUT
OUT
4
_______________________________________________________________________________________
4V to 72V Input LDOs with Boost Preregulator
2/MAX5093
Typical Operating Characteristics
(V = V = 14V, C = 47µF, C
= 22µF, C
= 10µF, C = 1µF, T = +25°C, unless otherwise noted.) (See Figures 4–7 as
OUT VL A
IN
EN
IN
BSOUT
applicable.)
INPUT CURRENT (I )
IN
vs. INPUT VOLTAGE (MAX5092B)
QUIESCENT SUPPLY CURRENT
vs. INPUT VOLTAGE (MAX5092B)
QUIESCENT SUPPLY CURRENT
vs. TEMPERATURE (MAX5092B)
100
100
90
80
70
60
50
40
90
85
80
75
70
65
60
55
50
BOOST CONVERTER NOT SWITCHING,
QUIESCENT SUPPLY CURRENT = I - I
IN OUT
I
= 10mA
OUT
I
= 100µA
OUT
10
1
I
= 10mA
OUT
I
= 100µA
OUT
I
= 10mA
OUT
I
= 100µA
OUT
BOOST CONVERTER NOT SWITCHING,
QUIESCENT SUPPLY CURRENT = I - I
BOOST CONVERTER SWITCHING
IN OUT
0.1
4.0
4.5
5.0
5.5
6.0
6.5
7.0
-40 -15
10
35
60
85 110 135
8
16 24 32 40 48 56 64 72
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
TEMPERATURE (°C)
QUIESCENT SUPPLY CURRENT
vs. TEMPERATURE (MAX5093B)
SHUTDOWN SUPPLY CURRENT
vs. INPUT VOLTAGE (MAX5093B)
SHUTDOWN SUPPLY CURRENT
vs. INPUT VOLTAGE (MAX5092B)
100
90
80
70
60
50
40
10
8
10
8
BOOST CONVERTER NOT SWITCHING,
QUIESCENT SUPPLY CURRENT = I - I
IN OUT
6
6
I
= 10mA
OUT
4
4
I
= 100µA
OUT
2
2
V = 0V
EN
V
= 0V
EN
0
0
-40 -15
10
35
60
85 110 135
4
14
24
34
44
54
64
74
4
14
24
34
44
54
64
74
TEMPERATURE (°C)
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
SHUTDOWN SUPPLY CURRENT
vs. TEMPERATURE (MAX5092B)
LINE-TRANSIENT RESPONSE
(V STEP FROM 4V TO 7V)
IN
MAX5092/93 toc08
10
8
I
= 250mA
OUT
V
5V (AC-COUPLED)
7V
OUT
50mV/div
6
V
IN
1V/div
4V
4
7V (AC-COUPLED)
V
BSOUT
1V/div
V
= 0V
EN
2
-40 -15
10
35
60
85 110 135
200µs/div
TEMPERATURE (°C)
_______________________________________________________________________________________
5
4V to 72V Input LDOs with Boost Preregulator
Typical Operating Characteristics (continued)
(V = V = 14V, C = 47µF, C
= 22µF, C
= 10µF, C = 1µF, T = +25°C, unless otherwise noted.) (See Figures 4–7 as
OUT VL A
IN
EN
IN
BSOUT
applicable.)
LINE-TRANSIENT RESPONSE
LINE-TRANSIENT RESPONSE
(V STEP FROM 3.5V TO 72V)
(V STEP FROM 3.5V TO 14V)
IN
IN
MAX5092/93 toc09
MAX5092/93 toc10
I
= 5mA
OUT
72V
V
IN
50V/div
V
OUT
3.5V
5V (AC-COUPLED)
14V
100mV/div
V
OUT
5V (AC-COUPLED)
V
BSOUT
50mV/div
5V/div
7V
14V
72V
7V
V
IN
V
BSOUT
5V/div
50V/div
3.5V
2/MAX5093
40ms/div
200µs/div
LDO OUTPUT VOLTAGE
vs. LDO LOAD CURRENT (MAX5092B)
POWER-SUPPLY REJECTION RATIO
DROPOUT VOLTAGE (V
- V
)
BSOUT
OUT
vs. FREQUENCY
vs. LDO LOAD CURRENT
MAX5092/93 toc13
5.15
5.10
5.05
5.00
4.95
4.90
4.85
0
V
= 14V, I
= 10mA
1000
800
600
400
200
0
T
A
= -40°C: C = 10µF, C
IN
= 4.7µF, C
OUT
= 10µF
IN
OUT
BSOUT
(CERAMIC)
T
= +25°C, +135°C: C = 47µF, C
= 22µF
A
IN
= 10µF (CERAMIC)
BSOUT
(ELECTROLYTIC), C
OUT
T
T
= +25°C, V = 4V
IN
A
= +25°C, V = 14V
A
IN
T
T
= -40°C, V = 4V
IN
A
10dB/div
= -40°C, V = 14V
A
IN
-70
T
T
= +135°C, V = 4V
IN
A
= +135°C, V = 14V
A
IN
0
100
200
300
0
50
100
150
200
250
100
1k
10k
100k
1M
LDO LOAD CURRENT (mA)
LDO LOAD CURRENT (mA)
FREQUENCY (Hz)
POWER-SUPPLY REJECTION RATIO
STARTUP THROUGH INPUT VOLTAGE
vs. FREQUENCY
MAX5092/93 toc15
MAX5092/93 toc14
0
I
= 250mA
OUT
V
= 8V, I
= 10mA
OUT
IN
V
IN
10V/div
0V
0V
V
BSOUT
10V/div
10dB/div
I
LX
-70
5A/div
0A
0V
V
OUT
5V/div
100
1k
10k
100k
1M
100µs/div
FREQUENCY (Hz)
6
_______________________________________________________________________________________
4V to 72V Input LDOs with Boost Preregulator
2/MAX5093
Typical Operating Characteristics (continued)
(V = V = 14V, C = 47µF, C
= 22µF, C
= 10µF, C = 1µF, T = +25°C, unless otherwise noted.) (See Figures 4–7 as
OUT VL A
IN
EN
IN
BSOUT
applicable.)
STARTUP THROUGH ENABLE
SHUTDOWN THROUGH V
IN
MAX5092/93 toc17
MAX5092/93 toc16
V
IN
14V
14V
I
= 250mA
OUT
10V/div
V
IN
10V/div
0V
V
BSOUT
10V/div
V
BSOUT
10V/div
0V
0A
0V
V
OUT
I
LX
5V/div
0V
0V
1A/div
V
EN
V
OUT
I
= 250mA
OUT
2V/div
5V/div
200µs/div
2ms/div
SHUTDOWN THROUGH ENABLE
RESET TIMING RESPONSE
MAX5092/93 toc18
MAX5092/93 toc19
V
IN
V
OUT
14V
14V
10V/div
2V/div
I
= 250mA
OUT
C = 680pF
T
V
BSOUT
10V/div
0V
V
RESET
2V/div
V
OUT
5V/div
0V
0V
0V
0V
V
EN
V
EN
2V/div
I
= 250mA
OUT
2V/div
200µs/div
200µs/div
V
OUT
vs. TEMPERATURE
(MAX5092B)
V
vs. TEMPERATURE
OUT
3.36
3.34
3.32
3.30
3.28
3.26
3.24
5.10
5.05
5.00
4.95
4.90
I
= 10mA, R5 = 100kΩ,
R4 = 165kΩ, FIGURE 6
OUT
I
= 1mA, V = 0V
SET
OUT
60
-40 -15
10
35
60
85 110 135
-40 -15
10
35
85 110 135
TEMPERATURE (°C)
TEMPERATURE (°C)
_______________________________________________________________________________________
7
4V to 72V Input LDOs with Boost Preregulator
Typical Operating Characteristics (continued)
(V = V = 14V, C = 47µF, C
= 22µF, C
= 10µF, C = 1µF, T = +25°C, unless otherwise noted.) (See Figures 4–7 as
IN
EN
IN
BSOUT
OUT VL A
applicable.)
LDO LOAD-TRANSIENT RESPONSE
(MAX5092B)
INPUT-VOLTAGE STEP RESPONSE
MAX5092/93 toc23
MAX5092/93 toc22
I
= 5mA
OUT
V
OUT
V
5V (AC-COUPLED)
72V
OUT
20mV/div
50mV/div
(AC-COUPLED)
V
IN
20V/div
I
OUT
100mA/div
0mA
3.5V
200ms/div
9
2ms/div
INTERNAL BOOST DIODE FORWARD DROP
(MAX5092)
ENABLE AND HOLD TIMING
MAX5092/93 toc24
1500
1250
1000
750
500
250
0
V
EN
5V/div
0V
0V
V
HOLD
5V/div
V
OUT
0V
5V/div
V
= 8V, BOOST CONVERTER
IN
NOT SWITCHING
0
0.5
1.0
1.5
2.0
2.5
3.0
200ms/div
DIODE CURRENT (A)
BOOST CONVERTER POWER LOSS
(V = 7V)
BOOST CONVERTER POWER LOSS
(V = 11V)
GROUND CURRENT DISTRIBUTION
(162 UNITS TESTED)
BSOUT
BSOUT
1.2
1.0
0.8
0.6
0.4
0.2
0
40
35
30
25
20
15
10
5
1.0
0.8
0.6
0.4
0.2
0
T
T
= T = +125°C
J
= T = -40°C
J
A
A
T
= +105°C: V = 4V
IN
A
V
= 4V
IN
T
= +105°C: V = 3.5V
V
V
= 5V
= 3.5V
A
IN
IN
IN
V
V
= 4V
= 5V
IN
IN
V
= 3.5V
IN
V
= 5V
IN
T
= +25°C: V = 3.5V
IN
A
V
V
= 4V
= 5V
IN
IN
0
0
50 100 150 200 250 300 350
(mA)
52 54 56 58 60 62 64 66 68
70
0
50 100 150 200 250 300 350
(mA)
I
I
(µA)
GND
I
OUT
OUT
8
_______________________________________________________________________________________
4V to 72V Input LDOs with Boost Preregulator
2/MAX5093
Pin Description
PIN
NAME
FUNCTION
Input Supply Voltage. Bypass IN to the power ground plane with a 47µF (low-ESR) aluminum electrolytic
capacitor in parallel with a 1µF ceramic capacitor placed as close to the IC as possible.
1
IN
Enable Input. Drive EN high to turn on the IC. Drive EN low to disable the IC. Connect EN directly to IN for
always-on operation.
2
3
EN
Signal Ground. Connect SGND to the signal ground plane and the exposed paddle. Connect the power
ground and signal ground plane together at the negative terminal of the input capacitor(s).
SGND
Output Hold. When HOLD is forced low, the regulator stores the on-state of the output, allowing the
regulator to remain enabled even if EN is pulled low. To shut down the regulator, release HOLD after EN is
pulled low. If HOLD is unused, either connect HOLD to OUT or leave unconnected. HOLD is internally
connected to OUT through a 4µA pullup current.
4
5
6
HOLD
PGND_LDO
SET
LDO Power Ground. Connect PGND_LDO to the power ground plane. Connect the PGND_LDO ground and
signal ground plane together.
Feedback Input for the LDO. Connect SET directly to SGND to set the output voltage of the LDO to the
preset voltage of 3.3V (MAX5092A/MAX5093A) or 5V (MAX5092B/MAX5093B). Connect SET to the center
tap of a resistor-divider connected between the LDO output and SGND to set the output voltage. V
regulates to 1.24V when using an adjustable output.
SET
7
8
OUT_SENSE LDO Regulator Output Sense. Connect OUT_SENSE to OUT at the output capacitor near the load.
LDO Regulator Output. Bypass OUT to the power ground plane with a 10µF ceramic capacitor. V
OUT
OUT
regulates to a preset voltage of 3.3V (MAX5092A/MAX5093A) or 5V (MAX5092B/MAX5093B), or is
adjustable from 1.5V to 9V (MAX5902_) or 1.5V to 10V (MAX5093_).
Boost Regulator Output Voltage. Bypass BSOUT to the PGND_BST ground plane with a 22µF (low-ESR)
aluminum electrolytic capacitor in parallel with a 1µF ceramic capacitor placed as close to the IC as
possible. Connect BSFB directly to SGND to regulate the BOOST output to a fixed voltage of 7V for V
≤
IN
9
BSOUT
7V. V
follows V for V > 7V. V
is programmable up to 11V (MAX5092_) or 12V (MAX5093_)
BSOUT
BSOUT
IN
IN
by connecting BSFB to the center tap of an external resistor-divider connected between the BOOST output
and PGND_BST.
Inductor Connection to the Drain of the Internal Power MOSFET. Connect LX to the switched side of the
inductor. Connect pins 10 and 11 together as close to the device as possible. For the MAX5093, also
connect LX to the anode of the external Schottky diode.
10, 11
12
LX
Boost Regulator Power Ground. Connect PGND_BST to the power ground plane. Connect the PGND_BST
ground plane and the signal ground plane together at the negative terminal of the input capacitor(s).
PGND_BST
BSFB
Feedback Input for the Boost Regulator. Connect BSFB directly to SGND to set the boost regulator output
voltage to 7V. Connect BSFB to the center tap of an external resistor-divider connected between BSOUT
13
and SGND to set the output voltage. V
regulates to 1.24V when using an adjustable output.
BSFB
Internal Regulator Output for IC Supply. Bypass VL to SGND with a 1µF/6.3V ceramic capacitor placed as
close to the IC as possible. V regulates to 5.5V with V ≥ 5.5V.
14
15
VL
CT
VL
BSOUT
RESET Timeout Programming Input. Connect a capacitor from CT to SGND to set the RESET timeout
period. See the CT Capacitor Selection section.
RESET Output. RESET is an open-drain output that goes high impedance when V
exceeds 92% of the
OUT
16
—
RESET
output voltage threshold after a programmed time delay. RESET pulls low immediately once V
below 90% of the regulated LDO output voltage.
drops
OUT
Exposed Paddle. Connect to the signal ground plane (SGND). Connect to a large-signal ground plane for
increased thermal performance.
EP
_______________________________________________________________________________________
9
4V to 72V Input LDOs with Boost Preregulator
Functional Diagrams
IN
VL
1µs
ONE-SHOT
VL
LX
INTERNAL
LDO
MAX5092_
OUT
IN
LX
BSOUT
Q
Q
DRIVER
S
R
CURRENT-LIMITING
COMPARATOR
R1
R
S
BSFB
2/MAX5093
V
PK
2.25µs
ONE-SHOT
MUX
OUT
IN
R2
V
V
REF
LDO
REF
OUT
ERROR AMPLIFIER
HOLD
EN
OUT_SENSE
CONTROL LOGIC,
THERMAL SHUTDOWN,
AND OVERCURRENT
PROTECTION
R3
R4
VL
MUX
SET
2µA
CT
CT
COMPARATOR
RESET
DELAY
COMPARATOR
0.92 x V
REF
PGND_LDO
P
PGND_BST
SGND
Figure 1. MAX5092_ Functional Diagram
10 ______________________________________________________________________________________
4V to 72V Input LDOs with Boost Preregulator
2/MAX5093
Functional Diagrams (continued)
IN
VL
1µs
ONE-SHOT
VL
LX
INTERNAL
LDO
MAX5093_
OUT
IN
LX
BSOUT
Q
Q
DRIVER
S
R
CURRENT-LIMITING
COMPARATOR
R1
R
S
BSFB
V
PK
2.25µs
ONE-SHOT
MUX
OUT
IN
R2
V
V
REF
LDO
REF
OUT
ERROR AMPLIFIER
HOLD
EN
OUT_SENSE
CONTROL LOGIC,
THERMAL SHUTDOWN,
AND OVERCURRENT
PROTECTION
R3
R4
VL
MUX
SET
2µA
CT
CT
COMPARATOR
RESET
DELAY
COMPARATOR
0.92 x V
REF
PGND_LDO
P
PGND_BST
SGND
Figure 2. MAX5093_ Functional Diagram
______________________________________________________________________________________ 11
4V to 72V Input LDOs with Boost Preregulator
Boost Converter
Detailed Description
The switch-mode converter uses a minimum off-time,
The MAX5092A/MAX5092B/MAX5093A/MAX5093B
maximum on-time pulse frequency modulation (PFM)
control scheme. The internal MOSFET turns on whenev-
include a step-up, switch-mode DC-DC converter and a
linear regulator to provide step-up/-down voltage con-
er V
falls below the regulation point determined
(see the Setting the Boost Output Voltage
) section). The MOSFET turns off when the
BSOUT
version over a wide range of input voltages. This combi-
nation of an LDO and a boost converter offers the
advantage of using a single off-the-shelf inductor in
place of the multiple-winding custom magnetics needed
in typical SEPIC or transformer-based flyback topolo-
gies. The boost preregulator is completely turned off
during normal automotive operation (V = 14V),
IN
reduces quiescent current to 65µA (typ), and makes the
devices suitable for always-on power supplies.
by V
BSFB
(V
BSOUT
inductor current reaches the peak current limit (2.5A
typ) or after 2.25µs maximum on-time, whichever
occurs first. The MOSFET is held off for at least 1µs
after the turn-on phase. A new switching cycle initiates
once V
falls below the threshold. In this control
BSOUT
scheme, switching frequency and output ripple are
functions of load current and input voltage. No frequen-
cy compensation is needed in the PFM control scheme.
The devices have an internal UVLO threshold of 3.8V
(max, V rising) that must be exceeded before the
IN
The output of the boost converter is preset to 7V and is
adjustable by using external resistors. See the Setting
device is enabled. When V is above V
, the inter-
UVLO
IN
nal boost converter starts switching and regulates
to the programmed boost output voltage. The
the Boost Output Voltage V
section. Due to the
BSOUT
V
BSOUT
2/MAX5093
integrated blocking diode in the MAX5092_, V
is
BSOUT
low quiescent-current LDO steps down V
to the
BSOUT
limited to 11V. Use the MAX5093_ for higher boost out-
put voltages (or to reduce the power dissipation in to
the package). The MAX5093_ requires an external
diode for the boost converter. Select the external diode
according to the Schottky Diode Selection (MAX5093_)
section.
programmed LDO output voltage. The boost output is
preset to 7V, and the LDO output is preset to 3.3V
(MAX5092A/MAX5093A) or 5V (MAX5092B/MAX5093B).
Both output voltages can be adjusted by using external
resistor-dividers.
If V rises above 8V (typ), the boost converter is dis-
IN
Linear Regulator
The MAX5092_/MAX5093_ contain an internal p-chan-
nel MOSFET used as the pass transistor for the LDO.
The output of the boost regulator is connected to the
source of the p-MOSFET. The LDO starts up 200µs
after the boost regulator starts up. The LDO supplies
up to 250mA with a typical dropout voltage of 0.9V. The
maximum LDO output current is determined by the
package power-dissipation limit as well as the internal
current limit. The LDO is designed to be a low-quies-
cent-current type. During normal operation when the
battery voltage is > 9V, the MAX5092_/MAX5093_ con-
sume only 75µA (max) at +85°C and 100µA load.
abled, forcing V
to follow V . If V falls below
IN IN
BSOUT
7.5V (typ), the boost converter starts switching and
regulates V to 7V if BSFB is directly connected to
BSOUT
SGND. The boost converter regulates V
for V
IN
BSOUT
down to 3.5V, providing uninterrupted operation during
low cold-crank voltages even if the programmed LDO
output voltage is greater than V (but less than 9V).
IN
The boost converter turn-on response time is less than
10µs, making cold-crank input glitches transparent to
the system even at full load.
The boost-converter output is followed by a high PSRR,
low-quiescent-current LDO. The LDO rejects the
switching noise present at BSOUT and provides a
clean, regulated output voltage. The linear regulator
uses an internal p-channel MOSFET pass element.
Additional features include a power-on-reset function
with an externally adjustable timeout, an enable (EN)
input, and a hold (HOLD) regulator control input.
The output voltage of the LDO is set using the SET
input. Connect SET to SGND to use the factory-preset
output voltage. Connect SET to the center of an exter-
nal resistor-divider connected from OUT to SGND to
program a different output voltage. See the Setting the
LDO Output Voltage (V
) section.
OUT
12 ______________________________________________________________________________________
4V to 72V Input LDOs with Boost Preregulator
2/MAX5093
Internal Regulator (VL)
An internal regulator (VL) is used to supply all internal
low-voltage blocks. Bypass VL to SGND with a 1µF
ceramic capacitor placed as close to the IC as possi-
Enable and Hold Inputs
The MAX5092_/MAX5093_ utilize two logic inputs, EN
(active-high) and HOLD (active low), to implement a
self-holding circuit with no additional components. For
example, an automotive ignition switch drives EN high
and the regulator turns on. If HOLD is then driven low,
the regulator remains on even if EN goes low. As long
as HOLD is forced low and remains low after initial reg-
ulator power-up, the regulator remains on. From this
state, release HOLD (an internal current source con-
nects HOLD to OUT), or connect HOLD to OUT to turn
the regulator off. Drive EN low and HOLD high to place
the IC into shutdown mode. Shutdown mode reduces
supply current to 5µA. Figure 3 shows the timing dia-
gram for the enable and hold functions. Table 1 shows
the state of the regulator output with respect to the volt-
age level at EN and HOLD with reference to Figure 3.
Connect HOLD to OUT or leave unconnected to dis-
able the hold feature and use EN as a standard on/off
control input.
ble. V regulates to 5.5V when V
is above 5.5V.
VL
BSOUT
V
tracks the voltage at BSOUT when V
below 5.5V.
is
BSOUT
VL
Power-On-Reset Output (RESET)
The MAX5092_/MAX5093_ contain an open-drain output
(RESET) that indicates when the LDO output (V ) is
OUT
out of regulation. If the output of the LDO falls below 90%
of the nominal output voltage, RESET pulls low after a
short delay. Once the output rises above 92% of the
nominal output voltage, RESET goes high impedance
after the programmed reset timeout period. Connect a
100kΩ pullup resistor from OUT to RESET. See the CT
Capacitor Selection section for details on setting the
RESET timeout period.
HOLD
EN
OUT
ORDER
1
2
4
5
6
3
Figure 3. Enable and Hold Timing Diagram
Table 1. Truth Table for Enable and Hold Timing Diagram
ORDER
EN
HOLD
OUT
COMMENTS
Initial State. EN has a 500nA pulldown to GND. HOLD has an internal current source to OUT.
HOLD follows OUT.
1
Low
X
Off
Regulator output is active when EN is pulled high. HOLD is in release state, and it follows
OUT.
2
3
High
Low
Released
Released
On
Off
HOLD is in release state. OUT follows EN.
HOLD is pulled low externally after OUT turns on. The regulator output is forced on
regardless of the state of EN. A self-holding state.
4
High
Low
On
5
5
Low
Released
X
Off
On
HOLD is released after EN is pulled low. Output turns off.
High
Regulator enabled. Normal turn-on behavior. Regulator follows EN and HOLD follows OUT.
______________________________________________________________________________________ 13
4V to 72V Input LDOs with Boost Preregulator
Applications Information
L1
4.7µH
10
LX
11
LX
INPUT
4V TO 72V
1
14
9
IN
VL
C2*
1µF
C6
1µF
C1*
47µF
U1
MAX5092A
7V
VOUT
BSOUT
C4*
22µF
C3*
1µF
R1
100kΩ
12
13
PGND_BST
BSFB
16
RESET
RESET
ON
2/MAX5093
2
3
4
OFF
EN
HOLD
µP
SIGNAL
SGND
7
8
OUT_SENSE
OUT
OUTPUT
3.3V AT 250mA**
C7
10µF
15
VOUT
CT
5
6
PGND_LDO
SET
C5
0.22µF
P
***
P
*THESE CAPACITORS MUST BE RATED AT THE HIGHEST V VOLTAGE.
IN
**OUTPUT CURRENT IS LIMITED BY THE TOTAL POWER-DISSIPATION CAPABILITY OF THE PACKAGE.
***SEE PC BOARD LAYOUT GUIDELINES SECTION.
Figure 4. MAX5092A Typical Application Circuit with Factory Preprogrammed LDO and Boost Output Voltages
14 ______________________________________________________________________________________
4V to 72V Input LDOs with Boost Preregulator
2/MAX5093
Applications Information (continued)
L1
4.7µH
10
LX
11
LX
INPUT
4V TO 72V
1
14
9
IN
VL
C2*
1µF
C6
1µF
C1*
47µF
U1
MAX5093A
7V
VOUT
BSOUT
C4*
22µF
C3*
1µF
R1
100kΩ
12
13
PGND_BST
BSFB
16
RESET
RESET
ON
2
3
4
OFF
EN
HOLD
µP
SIGNAL
SGND
7
8
OUT_SENSE
OUT
OUTPUT
3.3V AT 250mA**
C7
10µF
15
VOUT
CT
5
6
PGND_LDO
SET
C5
0.22µF
P
***
P
*THESE CAPACITORS MUST BE RATED AT THE HIGHEST V VOLTAGE.
IN
**OUTPUT CURRENT IS LIMITED BY THE TOTAL POWER-DISSIPATION CAPABILITY OF THE PACKAGE.
***SEE PC BOARD LAYOUT GUIDELINES SECTION.
Figure 5. MAX5093A Typical Application Circuit with Factory Preprogrammed Boost and LDO Output Voltages
______________________________________________________________________________________ 15
4V to 72V Input LDOs with Boost Preregulator
Applications Information (continued)
L1
4.7µH
10
LX
11
LX
INPUT
4V TO 72V
1
14
9
5.5V
IN
VL
C2*
1µF
C6
1µF
C1*
47µF
U1
MAX5092A
OUTPUT
8V (11V MAX)
VOUT
BSOUT
C4*
22µF
C3*
1µF
R3
100kΩ
R1
12
13
2.74MΩ (3.92MΩ)
PGND_BST
BSFB
16
2
RESET
RESET
EN
2/MAX5093
ON
R2
499kΩ
4
OFF
HOLD
µP
SIGNAL
3
VOUT
SGND
7
8
OUT_SENSE
OUT
OUTPUT
5V** (9V MAX)
C7
10µF
15
R4
CT
5
6
PGND_LDO
SET
301kΩ (619kΩ)
C5
0.22µF
P
***
R5
100kΩ
P
*THESE CAPACITORS MUST BE RATED AT THE HIGHEST V VOLTAGE.
IN
**OUTPUT CURRENT IS LIMITED BY THE TOTAL OUTPUT POWER AND THE DISSIPATION CAPABILITY OF THE PACKAGE.
***SEE PC BOARD LAYOUT GUIDELINES SECTION.
Figure 6. MAX5092A Typical Application Circuit with User-Programmed LDO and Boost Output Voltages
16 ______________________________________________________________________________________
4V to 72V Input LDOs with Boost Preregulator
2/MAX5093
Applications Information (continued)
L1
4.7µH
10
LX
11
LX
INPUT
4V TO 72V
1
14
IN
VL
C6
1µF
C2*
1µF
C1*
47µF
U1
MAX5093A
OUTPUT
9V (12V MAX)
9
VOUT
BSOUT
C4*
22µF
C3*
1µF
R3
100kΩ
R1
12
13
3.16MΩ (4.32MΩ)
PGND_BST
BSFB
16
2
RESET
RESET
EN
ON
R2
4
OFF
HOLD
µP
SIGNAL
499kΩ
3
VOUT
SGND
7
8
OUT_SENSE
OUT
OUTPUT
5V** (10V MAX)
C7
10µF
15
R4
CT
5
6
PGND_LDO
SET
301kΩ (698kΩ)
C5
0.22µF
***
R5
100kΩ
P
*THESE CAPACITORS MUST BE RATED AT THE HIGHEST V VOLTAGE.
IN
**OUTPUT CURRENT IS LIMITED BY THE TOTAL OUTPUT POWER AND THE DISSIPATION CAPABILITY OF THE PACKAGE.
***SEE PC BOARD LAYOUT GUIDELINES SECTION.
Figure 7. MAX5093A Typical Application Circuit with User-Programmable Boost Output Voltage and LDO Output Voltage
______________________________________________________________________________________ 17
4V to 72V Input LDOs with Boost Preregulator
where ∆V
is 75% of total peak-to-peak ripple at
ESRBS
Design Guidelines
BSOUT, I
is the internal switch current limit (3A max),
LIM
OUT
Input Capacitor (C ) and
IN
and I
is the LDO output current. Use a 100mΩ or
Boost Capacitor (C
) Selection
lower ESR electrolytic capacitor. Make sure the ESR at
cold temperatures does not cause excessive ripple
voltage. Alternately, use a 10µF ceramic capacitor in
parallel with the electrolyte capacitor.
BSOUT
The input current waveform of the boost converter is
continuous, and usually does not demand high capaci-
tance at its input. However, the MAX5092_/MAX5093_
boost converter is designed to fully turn on as soon as
the input drops below a certain voltage in order to ride
out cold-crank droops. This operation demands low
input source impedance for proper operation. If the
source (battery) is located far from the IC, high-capaci-
During the switch on-time, the BSOUT capacitor dis-
charges while supplying I
. The ripple caused by
CBS
OUT
the capacitor discharge (∆V
) is estimated by using
the following equation:
ty, low-ESR capacitors are recommended for C . The
IN
I
× 2.7 ×10−6
OUT
worst-case peak capacitor current could be as high as
3A. Use a 47µF, 100mΩ low-ESR capacitor placed as
close as possible to the input of the device. Note that
the aluminum electrolytic capacitor ESR increases sig-
nificantly at cold temperatures. In the cold temperature
case, choose an electrolyte capacitor with ESR lower
than 40mΩ or connect a low-ESR ceramic capacitor
(10µF) in parallel with the electrolytic capacitor.
∆V
=
CBS
C
BSOUT
where I
is the LDO output current and C
is
BSOUT
OUT
the BSOUT capacitance.
2/MAX5093
Inductor Selection
The control scheme of the MAX5092/MAX5093 permits
flexibility in choosing an inductor value. Smaller induc-
tance values typically offer smaller physical size for a
given series resistance, allowing the smallest overall
circuit dimensions. Circuits using larger inductance
may provide higher efficiency and exhibit less ripple,
but also may reduce the maximum output current. This
occurs when the inductance is sufficiently large to pre-
The boost converter output (BSOUT) is fed to the input
of the internal 250mA LDO. The boost-converter output
current waveform is discontinuous and requires high-
capacity, low-ESR capacitors at BSOUT to ensure low
V
ripple. During the on-time of the internal MOSFET,
BSOUT
the BSOUT capacitor supplies 250mA current to the
LDO input. During the off-time, the inductor dumps cur-
rent into the output capacitor while supplying the output
load current. The internal 250mA LDO is designed with
high PSRR; however, high-frequency spikes may not be
rejected by the LDO. Thus, high-value, low-ESR elec-
vent the LX current limit (I
before the maximum on-time (t
) from being reached
ON-MAX
LIM
) expires.
For maximum output current, choose the inductor value
so that the controller reaches the current limit before
the maximum on-time is reached:
trolytic capacitors are recommended for C
.
BSOUT
Peak-to-peak V
ripple depends on the ESR of the
BSOUT
V
× t
−
IN ON MAX
electrolyte capacitor. Use the following equation to cal-
L≤
I
LIM
culate the required ESR (ESR
capacitor:
) of the BSOUT
BSOUT
where t
LIM
is typically 2.25µs, and the current limit
ON-MAX
(I
) is a maximum of 3A (see the Electrical
∆V
ESRBS
− I
Characteristics). Choose an inductor with the maximum
saturation current (I ) greater than 3A.
ESR
=
BSOUT
I
LIM OUT
SAT
18 ______________________________________________________________________________________
4V to 72V Input LDOs with Boost Preregulator
2/MAX5093
Setting the Boost
Output Voltage (V
Schottky Diode Selection (MAX5093_)
The MAX5093_ requires an external diode connected
between LX and BSOUT (Figures 5 and 7). Proper
selection of an external diode can offer a lower forward-
voltage drop and a higher reverse-voltage handling
capability. Since the high switching frequency of the IC
demands a high-speed rectifier, Schottky diodes are
recommended for most applications because of their
fast recovery time and low forward-voltage drop.
Ensure that the diode’s peak current rating is greater
than or equal to the peak current limit of internal boost
converter MOSFET. A diode average forward current
rating of at least 1A is recommended. Additionally, the
diode reverse breakdown voltage must be greater than
the worst-case load-dump-condition voltage.
)
BSOUT
The MAX5092_/MAX5093_ feature Dual Mode™ opera-
tion for the internal boost converter output voltage.
These devices operate in a preset output-voltage mode
or an adjustable output-voltage mode. In preset mode,
internal trimmed feedback resistors set V
to a
BSOUT
fixed 7V. Select the preset mode by directly connecting
BSFB to SGND (Figures 4 and 5). Ensure a low-imped-
ance path between BSFB and SGND to limit the tran-
sient at BSFB to below 100mV. In adjustable mode,
connect BSFB to the center tap of an external resistor-
divider connected between BSOUT and SGND to pro-
gram V
(Figures 6 and 7). Note that the current
BSOUT
drawn by the resistor-divider at BSOUT adds to the qui-
escent current and the shutdown current of the IC. Use
CT Capacitor Selection
The MAX5092_/MAX5093_ contain an open-drain
power-on-reset output (RESET) that indicates when the
the resistor-divider only if V
is required to be sig-
BSOUT
nificantly different than 7V. Select 499kΩ or lower resis-
tance value for the bottom resistor (R2) of the divider
connected to SGND. The top resistor (R1) value is cal-
culated as:
LDO output voltage (V
OUT
) is out of regulation. When
OUT
V
rises above 92% of the nominal output voltage,
RESET goes high impedance after a user-programma-
⎛
⎞
V
V
ble time delay. This time duration is programmable by a
BSOUT
R1= R2 ×
−1
⎟
⎜
capacitor (C ) from CT to SGND (Figures 4–7). For a
CT
⎝
⎠
BSFB
chosen RESET active timeout period (t
the required capacitor value as:
), calculate
DELAY
where V
typ) and V
BSOUT.
is the regulation voltage at BSFB (1.24V
BSFB
is the desired output voltage for
2 ×10−6 × t
BSOUT
DELAY
C
=
CT
1.24
Setting the LDO Output Voltage (V
)
OUT
When V
drops below 90% of the LDO output regula-
The LDO output voltage is also Dual Mode (preset and
adjustable). Preset mode is selected by connecting
OUT
tion voltage, a 5mA pulldown current from CT to SGND
discharges C . The time required to discharge CT
CT
SET to SGND (Figures 4 and 5). In preset mode, V
OUT
determines the delay necessary to pull RESET low. This
delay provides glitch immunity to the RESET function.
The glitch immunity delay is directly proportional to the
CT capacitor and is approximately 70µs for a 0.1µF
capacitor at CT.
regulates to 3.3V (MAX5092A/MAX5093A) or 5V
(MAX5092B/MAX5093B) by internal trimmed feedback
resistors. Adjustable mode is selected by connecting
SET to the center tap of an external resistor-divider
connected between OUT and SGND (Figures 6 and 7).
Note that the current drawn by the resistor-divider at
OUT adds to the quiescent current of the LDO. Use the
resistor-divider only if V
is required to be signifi-
OUT
cantly different than the preset voltage. Select 100kΩ or
lower value for the bottom resistor (R5) of the divider
connected to SGND. The top resistor (R4) value is cal-
culated as:
⎛
⎞
V
V
OUT
R4 = R5 ×
−1
⎟
⎜
⎝
⎠
SET
where V
OUT
output.
is the regulation voltage at SET (1.24V typ)
SET
and V
is the desired output voltage for the LDO
Dual Mode is a trademark of Maxim Integrated Products, Inc.
______________________________________________________________________________________ 19
4V to 72V Input LDOs with Boost Preregulator
P
includes the losses in the boost converter opera-
DISS
MAXIMUM POWER DISSIPATION
vs. AMBIENT TEMPERATURE
tion and the LDO itself. The boost converter loss
, depends on V , V , and I . See
P
LOSS(BST)
IN
BSOUT
OUT
3.0
2.5
2.0
1.5
1.0
0.5
0
the Boost Converter Power Loss graphs in the Typical
Operating Characteristics to estimate the losses at a
given V and V
at room temperature. At a higher
BSOUT
IN
ambient temperature of +105°C, P
by up to 20% due to higher R
increases
LOSS(BST)
and switching loss-
DS-ON
es of the internal boost converter MOSFET. (Note:
must be less than 250mA).
I
OUT_MAX
PC Board Layout Guidelines
Good PC board (PCB) layout and routing are required
in high-frequency switching power supplies to achieve
proper regulation and stability. It is strongly recom-
mended that the evaluation kit PCB layouts be followed
as closely as possible. Refer to the MAX5092 EV kit for
an example layout. Follow these guidelines for good
PCB layout:
-40 -25 -10
5 20 35 50 65 80 95 110 125
AMBIENT TEMPERATURE (°C)
2/MAX5093
Figure 8. MAX5092/MAX5093 Package Power Dissipation
1) For SGND, use a large copper plane under the IC
and solder it to the exposed paddle. To effectively
use this copper area as a heat exchanger between
the PCB and ambient, expose this copper area on
the top and bottom side of the PCB. Do not make a
direct connection from the EP copper plane to pin 3
(SGND) underneath the IC so as to minimize
ground bounce.
Maximum Output Current (I
OUT_MAX
)
The MAX5092_/MAX5093_ high input voltage (+72V
max) provides up to 250mA of current from OUT.
Package power-dissipation limits the amount of output
current available for a given input/output voltage and
ambient temperature. Figure 8 depicts the maximum
power-dissipation curve for the devices. The graph
assumes that the exposed metal pad of the IC package
is soldered to the PC board copper according to the
JEDEC 51 standard (multilayer board). Use Figure 8 to
determine the allowable package dissipation for a
given ambient temperature. Alternately, use the follow-
ing formula to calculate the allowable package dissipa-
2) Isolate the power components and high-current
path from the sensitive analog circuit.
3) Keep the high-current paths short, especially at the
ground terminals. This practice is essential for sta-
ble, jitter-free operation.
4) Connect the return terminals of input capacitors
and boost output capacitors to the PGND_BST
power ground plane. Connect the power ground
(PGND_BST) and signal ground (SGND) planes
together at the negative terminal of the input capac-
itors. Do not connect them anywhere else. Connect
PGND_LDO ground plane to SGND ground plane
at a single point.
tion (P
) in watts:
DISS
For T ≤ +70°C:
A
P
= 2.67
DISS
For +70°C < T ≤ +125°C:
A
P
= 2.67 - (0.0333 x (T - 70))
A
DISS
where +70°C < T ≤ +125°C and 0.0333W/°C is the
A
5) Ensure that the feedback connections are short and
direct. Ensure a low-impedance path between
BSFB and SGND to limit the transient at BSFB to
100mV.
package thermal derating. After determining the allow-
able package dissipation, calculate the maximum out-
put current (I
) using the following formula:
OUT_MAX
P
− P
LOSS(BST)
DISS
6) Route high-speed switching nodes away from the
sensitive analog areas. Use the internal PCB layer
for SGND as an EMI shield to keep radiated noise
away from the IC, feedback dividers, and bypass
capacitors.
I
=
OUT_MAX
V
− V
OUT
IN
where P
tion and P
is the allowable package power dissipa-
DISS
is the boost converter power loss.
LOSS(BST)
20 ______________________________________________________________________________________
4V to 72V Input LDOs with Boost Preregulator
2/MAX5093
Typical Operating Circuit
INPUT
4V TO 72V
LX
LX
IN
VL
MAX5092B
+7V OUTPUT
VOUT
BSOUT
PGND_BST
BSFB
RESET
OUTPUT
RESET
EN
ENABLE
HOLD
SGND
OUT_SENSE
+5V OUTPUT
OUT
PGND_LDO
SET
VOUT
*
CT
P
P
*SEE PC BOARD LAYOUT GUIDELINES SECTION.
Selector Guide
PRESET LDO
OUTPUT (V)
ADJUSTABLE
LDO OUTPUT
PRESET BSOUT
OUTPUT (V)
ADJUSTABLE BSOUT
OUTPUT
PART
BOOST DIODE
MAX5092AATE+
MAX5092BATE+
MAX5093AATE+
MAX5093BATE+
3.3
5
Yes
Yes
Yes
Yes
7
7
7
7
Yes
Yes
Yes
Yes
Internal
Internal
External
External
3.3
5
Chip Information
PROCESS: BiCMOS
______________________________________________________________________________________ 21
4V to 72V Input LDOs with Boost Preregulator
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages.)
2/MAX5093
22 ______________________________________________________________________________________
4V to 72V Input LDOs with Boost Preregulator
2/MAX5093
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages.)
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 23
© 2006 Maxim Integrated Products
is a registered trademark of Maxim Integrated Products, Inc.
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