MAX4983EEVB+ [MAXIM]
DPDT, 2 Func, 2 Channel, BICMOS, 1.40 X 1.80 MM, LEAD FREE, UTQFN-10;
| 型号： | MAX4983EEVB+ |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | DPDT, 2 Func, 2 Channel, BICMOS, 1.40 X 1.80 MM, LEAD FREE, UTQFN-10 信息通信管理 光电二极管 输出元件 |
| 文件： | 总12页 (文件大小：184K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-403ꢀ; Rev 2; 9/08
Hi-Speed USB 2.0 Switches
with ±±15k ESD
3/MAX984E
General Description
Features
The MAX4983E/MAX4984E are high ESD-protected
analog switches that combine the low on-capacitance
and low on-resistance necessary for high-performance
switching applications. COM1 and COM2 are protected
against 1ꢀ5k ESD withoꢁt latchꢁp or damage. The
devices are ideal for USB 2.0 Hi-Speed applications at
480Mbps. The switches also handle all the reqꢁire-
ments for USB low- and fꢁll-speed signaling.
♦ USB Hi-Speed Switching
♦ ESD Protection on COM
±±15k Hꢀumn Bodꢁ Modeꢂ
±±15k ꢃEC ꢄ±ꢅꢅꢅ-ꢆ-ꢇ ꢈir ꢉmp
±ꢊ5k ꢃEC ꢄ±ꢅꢅꢅ-ꢆ-ꢇ Contmct
♦ Power-Sꢀppꢂꢁ Rmnge: +ꢇ.ꢊk to +1.1k
♦ Low 1Ω (tꢁp) On-Resistmnce (R
♦ -3dB Bmndwidth: 91ꢅMHz (tꢁp)
)
ON
The MAX4983E/MAX4984E doꢁble-pole/doꢁble-throw
(DPDT) switches are fꢁlly specified to operate from a
single +2.8k to +ꢀ.ꢀk power sꢁpply and are protected
against a +ꢀ.ꢀk short to COM1 and COM2. This featꢁre
ma5es the MAX4983E/MAX4984E fꢁlly compliant with
the USB 2.0 specification of kBUS faꢁlt protection. The
devices featꢁre low-threshold-voltage logic inpꢁts, per-
mitting them to be ꢁsed with low I/O voltage systems.
The MAX4983E featꢁres an active-low enable inpꢁt
(EN) that when driven high sets the device in shꢁtdown
mode. The MAX4984E featꢁres an active-high enable
inpꢁt (EN) that when driven low sets the device in shꢁt-
down mode. When the device is in shꢁtdown mode, the
qꢁiescent sꢁpply cꢁrrent is redꢁced to 0.1µA.
♦ Coupmtibꢂe with Logic ꢃ/O Down to ±.ꢆk
♦ COM ꢈnmꢂog ꢃnpꢀts Fmꢀꢂt Protected ꢈgminst
Shorts to +1.1k
♦ Low Sꢀppꢂꢁ Cꢀrrent ꢅ.ꢄµꢈ (tꢁp)
♦ Enmbꢂe ꢃnpꢀt:
ꢈctive-Low (EN) MꢈXꢆ9ꢊ3E
ꢈctive-High (EN) MꢈXꢆ9ꢊꢆE
♦ Sumꢂꢂ ±ꢅ-Pin, ±.ꢆuu x ±.ꢊuu UTQFN
The MAX4983E/MAX4984E are available in a space-
saving, 10-pin, 1.4mm x 1.8mm UTQFN pac5age, and
operate over a -40°C to +8ꢀ°C temperatꢁre range.
Ordering Information
PꢈRT
PꢃN-PꢈCKꢈꢉE
10 Ultra-Thin QFN
10 Ultra-Thin QFN
TOP MꢈRK
AAA
Applications
MꢈXꢆ9ꢊ3EEkB+
MꢈXꢆ9ꢊꢆEEkB+
AAB
Cell Phones
PDAs
Noteboo5 Compꢁters
kideo Switching
Bꢁs Switches
Note: All devices operate over the -40°C to +8ꢀ°C extended
temperatꢁre range.
+Denotes a lead-free pac5age.
Digital Still Cameras
GPS
Eye Diagram
Pin Configuration
TOP VIEW
MAX4983E
MAX4984E
7
6
8
9
5
4
3
COM2
GND
EN (EN)
MAX4983E/
MAX4984E
V
CC
USB 2.0
Hi-SPEED
TRANSMIT
TEMPLATE
10
COM1
CB
1
2
UTQFN
(EN) FOR MAX4984E ONLY.
________________________________________________________________ Mmxiu ꢃntegrmted Prodꢀcts
±
For pricing, deꢂiverꢁ, mnd ordering inforumtion, pꢂemse contmct Mmxiu Direct mt ±-ꢊꢊꢊ-ꢄꢇ9-ꢆꢄꢆꢇ,
or visit Mmxiu’s website mt www.umxiu-ic.cou.
Hi-Speed USB 2.0 Switches
with ±±15k ESD
ꢈBSOLUTE MꢈXꢃMUM RꢈTꢃNꢉS
(All voltages referenced to GND.)
, COM_, NO_, NC_, EN, EN, CB.................... -0.3k to +6.0k
Continꢁoꢁs Cꢁrrent into Any Terminal............................. 30mA
Jꢁnction-to-Ambient Thermal Resistance (θ ) (Note 1)
JA
k
CC
10-Pin UTQFN........................................................ 143.1°C/W
Operating Temperatꢁre Range .......................... -40°C to +8ꢀ°C
Jꢁnction Temperatꢁre Range ......................................... +1ꢀ0°C
Storage Temperatꢁre Range............................ -6ꢀ°C to +1ꢀ0°C
Lead Temperatꢁre (soldering 10s) ..................................+300°C
Continꢁoꢁs Power Dissipation (T = +70°C)
A
10-Pin UTQFN (derate 6.9mW/°C above +70°C)........ ꢀꢀ9mW
Jꢁnction-to-Case Thermal Resistance (θ ) (Note 1)
JC
10-Pin UTQFN ...........................................................20.1°C/W
Note ±: Pac5age thermal resistances were obtained ꢁsing the method described in JEDEC specification JESDꢀ1-7, ꢁsing a foꢁr-
layer board. For detailed information on pac5age thermal considerations, refer to www.umxiu-ic.cou/therumꢂ-tꢀtorimꢂ.
Stresses beyond those listed ꢁnder “Absolꢁte Maximꢁm Ratings” may caꢁse permanent damage to the device. These are stress ratings only, and fꢁnctional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposꢁre to
absolꢁte maximꢁm rating conditions for extended periods may affect device reliability.
ELECTRꢃCꢈL CHꢈRꢈCTERꢃSTꢃCS
(k
= +2.8k to +ꢀ.ꢀk, T = -40°C to +8ꢀ°C, ꢁnless otherwise noted. Typical valꢁes are at k
= +3.0k, T = +2ꢀ°C.) (Note 2)
CC A
CC
A
PꢈRꢈMETER
SYMBOL
CONDꢃTꢃONS
MꢃN
TYP
MꢈX
ꢀ.ꢀ
UNꢃTS
Operating Power-Sꢁpply Range
k
2.8
k
CC
k
k
= 3.0k
= ꢀ.ꢀk
0.6
3
1.ꢀ
8
CC
CC
k
k
= 0k or k
,
CC
CB
Sꢁpply Cꢁrrent
I
µA
µA
µA
CC
= 0k or k = k
EN
EN
CC
6.ꢀ
Shꢁtdown Sꢁpply Cꢁrrent
Increase in Sꢁpply Cꢁrrent
with k , k koltage
CB EN
I
Switch disabled (k = k
or k = 0k)
0.1
SHDN
EN
CC
EN
0 ≤ k ≤ k or k ≤ k ≤ k
or 0 ≤ k
EN
CB
IL
IH
CB
CC
2
≤ k or k ≤ k ≤ k
IL IH EN CC
k
, k
,
COM NO
k
Analog Signal Range
Faꢁlt-Protection Trip Threshold
On-Resistance
k
= k
or k = 0k (Note 3)
0
k
CC
k
k
EN
CC
EN
NC
k
+
k
+
k
CC
+
CC
0.6
CC
0.8
k
COM_ only, T = +2ꢀ°C
A
FP
1
k
k
= 0k to k
= 3.6k, k
ꢀ
10
COM
COM
CC
R
Ω
ON
= 3.0k
ꢀ.ꢀ
CC
On-Resistance Match Between
Channels
ΔR
k
k
= 3.0k, k
= 2k (Note 4)
0.1
0.1
1
Ω
Ω
ON
CC
COM
On-Resistance Flatness
R
FLAT
= 3.0k, k
= 4.ꢀk, k
= 0k to k
(Note ꢀ)
CC
CC
COM
CC
k
k
= 0k or 4.ꢀk,
COM
-2ꢀ0
-2ꢀ0
+2ꢀ0
180
nA
, k
NO NC
= 4.ꢀk or 0k
Off-Lea5age Cꢁrrent
I
COM(OFF)
k
k
= ꢀ.ꢀk, k
= 0k or ꢀ.ꢀk,
CC
COM
µA
nA
, k
NO NC
with ꢀ0µA sin5 cꢁrrent to GND
k
k
= ꢀ.ꢀk, k
= 0k or ꢀ.ꢀk,
CC
COM
On-Lea5age Cꢁrrent
I
+2ꢀ0
COM(ON)
BW
, k
NO NC
= ꢁnconnected
ꢈC PERFORMꢈNCE
On-Channel -3dB Bandwidth
R = R = ꢀ0Ω, signal = 0dBm
9ꢀ0
-48
-20
-17
MHz
dB
L
S
f = 10MHz
f = 2ꢀ0MHz
f = ꢀ00MHz
k
, k
NO NC
= 0dBm,
Off-Isolation
k
R = R = ꢀ0Ω
(Figꢁre 1)
ISO
L S
ꢇ
_______________________________________________________________________________________
Hi-Speed USB 2.0 Switches
with ±±15k ESD
3/MAX984E
ELECTRꢃCꢈL CHꢈRꢈCTERꢃSTꢃCS (continꢀed)
(k
= +2.8k to +ꢀ.ꢀk, T = -40°C to +8ꢀ°C, ꢁnless otherwise noted. Typical valꢁes are at k
= +3.0k, T = +2ꢀ°C.) (Note 2)
CC A
CC
A
PꢈRꢈMETER
SYMBOL
CONDꢃTꢃONS
f = 10MHz
= 0dBm,
NO NC
MꢃN
TYP
-73
-ꢀ4
-33
MꢈX
UNꢃTS
k
, k
Crosstal5 (Note 6)
k
R = R = ꢀ0Ω,
f = 2ꢀ0MHz
dB
CT
L
S
Figꢁre 1
f = ꢀ00MHz
LOꢉꢃC ꢃNPUT
Inpꢁt Logic-High
Inpꢁt Logic-Low
Inpꢁt Lea5age Cꢁrrent
DYNꢈMꢃC
k
1.4
k
k
IH
k
0.ꢀ
IL
I
IN
-2ꢀ0
+2ꢀ0
nA
k
k
or k = 1.ꢀk, R = 300Ω, C = 3ꢀpF,
NC L L
NO
Tꢁrn-On Time
t
20
100
ꢀ
µs
ON
= k to 0k or k = 0k to k (Figꢁre 2)
EN
CC
EN
CC
k
k
or k = 1.ꢀk, R = 300Ω, C = 3ꢀpF,
NC L L
NO
EN
Tꢁrn-Off Time
t
1
µs
ps
µs
OFF
= k to 0k or k = 0k to k (Figꢁre 2)
CC
EN
CC
Propagation Delay
t
, t
R = R = ꢀ0Ω, Figꢁre 3
100
PLH PHL
L
S
Faꢁlt Protection Response
Time
k
k
= 0k to ꢀk step, R = R = ꢀ0Ω,
COM L S
t
0.ꢀ
ꢀ.0
FP
= 3.3k (Figꢁre 4)
CC
Faꢁlt Protection Recovery
Time
k
k
= ꢀk to 0k step, R = R = ꢀ0Ω,
COM L S
t
100
µs
ps
pF
pF
pF
%
FPR
= 3.3k (Figꢁre 4)
CC
Oꢁtpꢁt S5ew Between
Switches
S5ew between switch 1 and 2, R = R = ꢀ0Ω,
L S
(Figꢁre 3, Note 7)
t
40
2
SK
C
C
or
NO(OFF)
NO_ or NC_ Off-Capacitance
f = 1MHz (Figꢁre ꢀ, Note 7)
NC(OFF)
f = 1MHz
ꢀ.ꢀ
4.8
6.ꢀ
ꢀ.ꢀ
COM Off-Capacitance
(Figꢁre ꢀ, Note 7)
C
COM(OFF)
f = 240MHz
f = 1MHz
COM On-Capacitance
(Figꢁre ꢀ, Note 7)
C
COM(ON)
f = 240MHz
Total Harmonic Distortion Plꢁs
Noise
k
= 1k , k
= 1k, R = R = ꢀ0Ω,
COM
P-P BIAS L S
THD+N
0.03
f = 20Hz to 205Hz
ESD PROTECTꢃON
COM1, COM2
All Pins
Hꢁman Body Model
1ꢀ
1ꢀ
8
IEC 61000-4-2 Air-Gap Discharge
IEC 61000-4-2 Contact Discharge
Hꢁman Body Model
5k
2
Note ꢇ: All devices are 100% prodꢁction tested at T = +2ꢀ°C. All temperatꢁre limits are gꢁaranteed by design.
A
Note 3: The switch tꢁrns off for voltages above k , protecting downstream circꢁits in case of a faꢁlt condition.
FP
Note ꢆ: ΔR
= ABS(R
- R
).
ON(MAX)
ON(CH1)
ON(CH2)
Note 1: Flatness is defined as the difference between the maximꢁm and minimꢁm valꢁe of on-resistance, as measꢁred over specified
analog signal ranges.
Note ꢄ: Between any two switches.
Note 7: Switch off-capacitance, switch on-capacitance, and oꢁtpꢁt s5ew between switches are not prodꢁction tested; gꢁaranteed by
design.
_______________________________________________________________________________________
3
Hi-Speed USB 2.0 Switches
with ±±15k ESD
Test Circuits/Timing Diagrams
V
V
OUT
OFF-ISOLATION = 20log
CROSSTALK = 20log
IN
NETWORK
ANALYZER
V
V
OUT
50Ω
50Ω
V
V
0V OR V
IN
CC
CB
IN
COM1
NO1*
NC1
MAX4983E/
MAX4984E
MEAS
REF
OUT
50Ω
50Ω
50Ω
SWITCH IS ENABLED.
MEASUREMENTS ARE STANDARDIZED AGAINST SHORTS AT IC TERMINALS.
*FOR CROSSTALK THIS PIN IS NO2.
NC2 AND COM2 ARE OPEN.
OFF-ISOLATION IS MEASURED BETWEEN COM_ AND "OFF" NO_ OR NC_ TERMINAL ON EACH SWITCH.
CROSSTALK IS MEASURED FROM ONE CHANNEL TO THE OTHER CHANNEL.
SIGNAL DIRECTION THROUGH SWITCH IS REVERSED; WORST VALUES ARE RECORDED.
Figꢁre 1. Off-Isolation and Crosstal5
3/MAX984E
MAX4983E/
MAX4984E
t
t
< 5ns
< 5ns
R
F
V
IH
LOGIC
INPUT
50%
V
IL
NO
COM
V
IN_
V
OUT
OR NC
t
OFF
R
L
C
L
EN (EN)
V
OUT
0.9 x V
0UT
0.1 x V
OUT
LOGIC
INPUT
SWITCH
OUTPUT
0V
t
ON
C INCLUDES FIXTURE AND STRAY CAPACITANCE.
L
IN DEPENDS ON SWITCH CONFIGURATION;
INPUT POLARITY DETERMINED BY SENSE OF SWITCH.
R
L
V
= V
IN_
OUT
(
)
ON
R + R
L
Figꢁre 2. Switching Time
ꢆ
_______________________________________________________________________________________
Hi-Speed USB 2.0 Switches
with ±±15k ESD
3/MAX984E
Test Circuits/Timing Diagrams (continued)
MAX4983E/
MAX4984E
NC1 OR
NO1
R
R
S
S
COM1
V
V
IN+
OUT+
t
= t
OR t
OR t
PLH PLHX
PLHY
PHLY
| OR |t
t
t
t
= t
PHL PHLX
R
R
L
L
= |t
= |t
- t
- t
|
|
SK(O)
SK(P)
PLHX PLHY
PHLX PHLY
- t
| OR |t
- t
PLHX PHLX
PLHY PHLY
NC2 OR
NO2
COM2
V
V
IN-
OUT-
CB
V
TO V
IH
IL
t
INFALL
t
INRISE
10%
V
V
CC
90%
90%
V
IN+
50%
50%
50%
10%
0V
CC
V
50%
IN-
0V
CC
t
t
OUTRISE
10%
OUTFALL
t
t
PLHX
PHLX
V
90%
90%
V
OUT+
50%
50%
10%
0V
CC
V
50%
50%
V
OUT-
0V
t
t
PHLY
PLHY
Figꢁre 3. Oꢁtpꢁt Signal S5ew, Rise/Fall Time, Propagation Delay
_______________________________________________________________________________________
1
Hi-Speed USB 2.0 Switches
with ±±15k ESD
Test Circuits/Timing Diagrams (continued)
5V
3V
V
CC
= 3.3V
MAX4983E/
MAX4984E
V
COM
0V
t
FP
t
FPR
V
FP
3V
0V
V
V
NO
NC
Figꢁre 4. Faꢁlt-Protection Response/Recovery Time
COM
3/MAX984E
MAX4983E/
MAX4984E
CB
V
OR V
IL
IH
CAPACITANCE
METER
NC_ OR
NO_
Figꢁre ꢀ. Channel Off-/On-Capacitance
ꢄ
_______________________________________________________________________________________
Hi-Speed USB 2.0 Switches
with ±±15k ESD
3/MAX984E
Typical Operating Characteristics
(k
CC
= 3.0k, T = +2ꢀ°C, ꢁnless otherwise noted.)
A
COM LEAKAGE CURRENT
vs. TEMPERATURE
ON-RESISTANCE vs. V
ON-RESISTANCE vs. V
COM
COM
7
6
5
4
3
2
1
0
6
5
4
3
2
1
0
80
70
60
50
40
30
20
10
0
COM ON-LEAKAGE
V
V
= 2.8V
= 5.5V
CC
CC
T
A
= +85°C
T
A
= +25°C
T = -40°C
A
COM OFF-LEAKAGE
0
1
2
3
4
5
6
1
2
0
3
-40
-15
10
35
60
85
V
(V)
V
(V)
TEMPERATURE (°C)
COM
COM
QUIESCENT SUPPLY CURRENT
vs. TEMPERATURE
LOGIC-INPUT THRESHOLD
vs. SUPPLY VOLTAGE
QUIESCENT SUPPLY CURRENT
vs. LOGIC LEVEL
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
1.2
1.0
0.8
0.6
0.4
0.2
0
5
4
3
2
1
0
V
V
= 5.5V
= 2.8V
CC
CC
V
V
IL
IH
-40
-15
10
35
60
85
2.8
3.8
4.8
0
1
2
3
TEMPERATURE (°C)
SUPPLY VOLTAGE (V)
LOGIC LEVEL (V)
TOTAL HARMONIC DISTORTION
PLUS NOISE vs. FREQUENCY
FREQUENCY RESPONSE
0
1
R = 600Ω
L
-10
-20
ON-LOSS
-30
-40
0.1
OFF-ISOLATION
-50
-60
-70
-80
CROSSTALK
100
0.01
-90
0.001
-100
1
10
1,000
10
100
1,000
10,000
100,000
FREQUENCY (MHz)
FREQUENCY (Hz)
_______________________________________________________________________________________
7
Hi-Speed USB 2.0 Switches
with ±±15k ESD
Pin Description
PꢃN
NꢈME
FUNCTꢃON
MꢈXꢆ9ꢊ3E
MꢈXꢆ9ꢊꢆE
1
2
3
4
ꢀ
6
7
1
2
3
4
ꢀ
6
7
NC1
NO1
Normally Closed Terminal for Switch 1
Normally Open Terminal for Switch 1
Common Terminal for Switch 1
Groꢁnd
COM1
GND
COM2
NO2
Common Terminal for Switch 2
Normally Open Terminal for Switch 2
Normally Closed Terminal for Switch 2
NC2
Active-Low Enable Inpꢁt. Drive EN high to pꢁt switches in high impedance. Drive EN
low for normal operation.
8
—
9
—
8
EN
Active-High Enable Inpꢁt. Drive EN low to pꢁt switches in high impedance. Drive EN
high for normal operation.
EN
Positive Sꢁpply koltage Inpꢁt. Bypass k
close as possible to the device.
to GND with a 0.1µF ceramic capacitor as
CC
9
k
CC
Digital Control Inpꢁt. Drive CB low to connect COM_ to NC_. Drive CB high to connect
COM_ to NO_.
3/MAX984E
10
10
CB
oꢁtpꢁts. The charge-pꢁmp-assisted n-channel architec-
Detailed Description
tꢁre allows the switch to pass analog signals that
The MAX4983E/MAX4984E are 1ꢀ5k ESD-protected
DPDT analog switches. The devices are ideal for USB
2.0 Hi-Speed (480Mbps) switching applications and
also meet USB low- and fꢁll-speed reqꢁirements.
exceed k
ꢁp to the overvoltage faꢁlt protection
CC
threshold. This allows USB signals that exceed k
to
CC
pass, allowing compliance with USB reqꢁirements for
voltage levels.
The MAX4983E/MAX4984E are fꢁlly specified to oper-
Overvoltage Fault Protection
The MAX4983E/MAX4984E featꢁre overvoltage faꢁlt pro-
tection on COM_. Faꢁlt protection protects the switch and
USB transceiver from damaging voltage levels. When
voltages on COM exceed the faꢁlt protection threshold,
ate from a single +2.8k to +ꢀ.ꢀk sꢁpply. The low k
IH
threshold of the devices permits them to be ꢁsed with
logic levels as low as 1.4k. The MAX4983E/MAX4984E
are based on a charge-pꢁmp-assisted n-channel archi-
tectꢁre. The devices featꢁre a shꢁtdown mode to
redꢁce the qꢁiescent cꢁrrent to less than 0.1µA (typ).
(k ), COM_, NC_ and NO_ are high impedance.
FP
Enable Input
Digital Control Input
The MAX4983E/MAX4984E provide a single-bit control
logic inpꢁt, CB. CB controls the position of the switches
as shown in the Fꢁnctional Diagram/Trꢁth Table.
Driving CB rail-to-rail minimizes power consꢁmption.
With a +2.8k to +ꢀ.ꢀk sꢁpply voltage range, the device
is +1.4k logic compatible.
The MAX4983E/MAX4984E featꢁre a shꢁtdown mode that
redꢁces the sꢁpply cꢁrrent to less than 0.1µA and places
COM_ in high impedance. Drive EN high for the
MAX4983E or EN low for the MAX4984E to place the
devices in shꢁtdown mode. When EN is driven low or EN
is driven high, the devices are in normal operation.
Applications Information
Analog Signal Levels
The on-resistance of the MAX4983E/MAX4984E is very
low and stable as the analog inpꢁt signals are swept
USB Switching
The MAX4983E/MAX4984E analog switches are fꢁlly com-
pliant with the USB 2.0 specification. The low on-resis-
tance and low on-capacitance of these switches ma5e
them ideal for high-performance switching applications.
from groꢁnd to k (see the Typical Operating Character-
CC
istics). These switches are bidirectional, allowing NO_,
NC_, and COM_ to be configꢁred as either inpꢁts or
ꢊ
_______________________________________________________________________________________
Hi-Speed USB 2.0 Switches
with ±±15k ESD
3/MAX984E
The MAX4983E/MAX4984E are ideal for roꢁting USB
Functional Diagram/Truth Table
data lines (see Figꢁre 6) and for applications that
reqꢁire switching between mꢁltiple USB hosts (see
Figꢁre 7). The MAX4983E/MAX4984E also featꢁre
overvoltage faꢁlt protection to gꢁard systems against
shorts to the USB kBUS voltage that is reqꢁired for all
USB applications.
V
EN (EN)
CC
MAX4983E/
MAX4984E
CB
Extended ESD Protection
As with all Maxim devices, ESD-protection strꢁctꢁres
are incorporated on all pins to protect against electro-
static discharges encoꢁntered dꢁring handling and
assembly. COM1 and COM2 are fꢁrther protected
against static electricity. The ESD strꢁctꢁres withstand
high ESD in normal operation and when the device is
powered down. After an ESD event, the MAX4983E/
MAX4984E continꢁe to fꢁnction withoꢁt latchꢁp.
NO1
NC1
COM1
COM2
NO2
NC2
The MAX4983E and MAX4984E are characterized for
protection to the following limits:
GND
•
•
•
1ꢀ5k ꢁsing Hꢁman Body Model
85k ꢁsing IEC 61000-4-2 Contact Discharge method
1ꢀ5k ꢁsing IEC 61000-4-2 Air-Gap Discharge method
MAX4983E
N0_
EN
CB
0
NC_ COM_
0
0
1
OFF
ON
OFF
OFF
—
—
ESD Test Conditions
1
ON
ESD performance depends on a variety of conditions.
Contact Maxim for a reliability report that docꢁments
test setꢁp, test methodology, and test resꢁlts.
X
OFF
HI-Z
X = DON'T CARE.
Human Body Model
Figꢁre 8a shows the Hꢁman Body Model and Figꢁre 8b
shows the cꢁrrent waveform it generates when dis-
charged into a low impedance. This model consists of a
100pF capacitor charged to the ESD voltage of interest,
which is then discharged into the test device throꢁgh a
1.ꢀ5Ω resistor.
MAX4984E
N0_ NC_ COM_
EN
1
CB
0
OFF
ON
OFF
OFF
—
—
1
1
ON
0
X
OFF
HI-Z
X = DON'T CARE.
IEC 6±000-4-2
The main difference between tests done ꢁsing the Hꢁman
Body Model and IEC 61000-4-2 is higher pea5 cꢁrrent in
IEC 61000-4-2. Becaꢁse series resistance is lower in the
IEC 61000-4-2 ESD test model (Figꢁre 9a), the ESD-with-
stand voltage measꢁred to this standard is generally
lower than that measꢁred ꢁsing the Hꢁman Body Model.
Figꢁre 9b shows the cꢁrrent waveform for the 85k
IEC 61000-4-2 Level 4 ESD Contact Discharge test.
Ensꢁre that bypass capacitors are as close as possible
to the device. Use large groꢁnd planes where possible.
Power-Supply Sequencing
Cmꢀtion: Do not exceed the mbsoꢂꢀte umxiuꢀu rmt-
ings becmꢀse stresses beꢁond the ꢂisted rmtings
umꢁ cmꢀse perumnent dmumge to the device.
Proper power-sꢁpply seqꢁencing is recommended for all
The Air-Gap Discharge test involves approaching the
device with a charged probe. The Contact Discharge
method connects the probe to the device before the
probe is energized.
devices. Always apply k
before applying analog sig-
CC
nals, especially if the analog signal is not cꢁrrent limited.
Layout
USB Hi-Speed reqꢁires carefꢁl PCB layoꢁt with 4ꢀΩ
controlled-impedance matched traces of eqꢁal lengths.
Chip Information
PROCESS: BiCMOS
_______________________________________________________________________________________
9
Hi-Speed USB 2.0 Switches
with ±±15k ESD
ASIC I
D+
HI-SPEED
USB
TRANSCEIVER
MAX4983E/
MAX4984E
MAX4983E/
MAX4984E
D+
D-
V
BUS
D-
USB
HOST I
NC1
NO1
NC1
NO1
COM1
D+
D-
COM1
D+
HI-SPEED
USB
TRANSCEIVER
NC2
NO2
NC2
NO2
COM2
COM2
ASIC II
D+
D-
D-
D+
D-
USB
HOST II
HI-SPEED
USB
TRANSCEIVER
GND
USB
CONNECTOR
3/MAX984E
Figꢁre 6. USB Data Roꢁting/Typical Application Circꢁit
Figꢁre 7. Switching Between Mꢁltiple USB Hosts
R
R
D
C
1500Ω
1MΩ
I
P
100%
90%
PEAK-TO-PEAK RINGING
(NOT DRAWN TO SCALE)
I
R
DISCHARGE
RESISTANCE
CHARGE-CURRENT-
LIMIT RESISTOR
AMPERES
HIGH-
VOLTAGE
DC
DEVICE
UNDER
TEST
36.8%
C
100pF
STORAGE
CAPACITOR
s
10%
0
SOURCE
TIME
0
t
RL
t
DL
CURRENT WAVEFORM
Figꢁre 8a. Hꢁman Body ESD Test Model
Figꢁre 8b. Hꢁman Body Cꢁrrent Waveform
R
C
R
D
50MΩ to 100MΩ
330Ω
I
100%
90%
DISCHARGE
RESISTANCE
CHARGE-CURRENT-
LIMIT RESISTOR
HIGH-
VOLTAGE
DC
DEVICE
UNDER
TEST
C
s
150pF
STORAGE
CAPACITOR
SOURCE
10%
= 0.7ns to 1ns
30ns
t
t
R
60ns
Figꢁre 9a. IEC 61000-4-2 ESD Test Model
Figꢁre 9b. IEC 61000-4-2 ESD Generator Cꢁrrent Waveform
±ꢅ ______________________________________________________________________________________
Hi-Speed USB 2.0 Switches
with ±±15k ESD
3/MAX984E
Pac5age Information
For the latest pac5age oꢁtline information, go to www.umxiu-ic.cou/pmc5mges.
PꢈCKꢈꢉE TYPE
PꢈCKꢈꢉE CODE
DOCUMENT NO.
ꢇ±-ꢅꢅꢇꢊ
10 Ultra-Thin QFN
k101A1CN-1
______________________________________________________________________________________ ±±
Hi-Speed USB 2.0 Switches
with ±±15k ESD
Revision History
REkꢃSꢃON
NUMBER
REkꢃSꢃON
DꢈTE
PꢈꢉES
CHꢈNꢉED
DESCRꢃPTꢃON
0
1
2
2/08
ꢀ/08
9/08
Initial release
—
1, 8, 9, 10
3
Removal of fꢁtꢁre prodꢁct asteris5s, global change to Hi-Speed
Changes to EC table
3/MAX984E
Maxim cannot assꢁme responsibility for ꢁse of any circꢁitry other than circꢁitry entirely embodied in a Maxim prodꢁct. No circꢁit patent licenses are
implied. Maxim reserves the right to change the circꢁitry and specifications withoꢁt notice at any time.
±ꢇ ____________________Maxim Integrated Products, ±20 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2008 Maxim Integrated Prodꢁcts
is a registered trademar5 of Maxim Integrated Prodꢁcts, Inc.
相关型号：
MAX4986
SAS/SATA Single Lane 2:1/1:2 Multiplexer/Demultiplexer Plus Redriver with Equalization
MAXIM
MAX4986CTO+
SAS/SATA Single Lane 2:1/1:2 Multiplexer/Demultiplexer Plus Redriver with Equalization
MAXIM
MAX4986ETO+
SAS/SATA Single Lane 2:1/1:2 Multiplexer/Demultiplexer Plus Redriver with Equalization
MAXIM
©2020 ICPDF网 联系我们和版权申明