MAX4806 [MAXIM]
Dual, Unipolar/Bipolar, High-Voltage Digital Pulsers;
| 型号： | MAX4806 |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Dual, Unipolar/Bipolar, High-Voltage Digital Pulsers |
| 文件： | 总20页 (文件大小：221K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-4366; Rev 0; 11/08
Dual, Unipolar/Bipolar, High-Voltage
Digital Pulsers
67/MAX408
General Description
Features
The MAX4806/MAX4807/MAX4808 integrated circuits
generate high-voltage, high-frequency, unipolar or bipo-
lar pulses from low-voltage logic inputs. These dual
pulsers feature independent logic inputs, independent
high-voltage pulser outputs with active clamps, and
independent high-voltage supply inputs.
♦ Highly Integrated, High-Voltage, High-Frequency
Unipolar/Bipolar Pulser
♦ 6Ω Output Impedance and 2A (min) Output
Current
♦ 20Ω Active Clamp
The MAX4806/MAX4807/MAX4808 feature a 6Ω output
impedance for the high-voltage outputs, and a 20Ω
impedance for the active clamp. The high-voltage out-
puts are guaranteed to provide 2A of output current.
♦ Pulser and Clamp Overvoltage Protection
(MAX4806/MAX4807)
♦ 0 to +220V Unipolar or ±±±0V Bipolar Outputs
All devices use three logic inputs per channel to control
the positive and negative pulses and active clamp. Also
included are two independant enable inputs. Disabling
EN_ ensures the output MOSFETs are not accidentally
turned on during fast power-supply ramping. This allows
for faster ramp times and smaller delays between puls-
ing modes. A low-power shutdown mode reduces
power consumption to less than 1µA. All digital inputs
are CMOS compatible.
♦ Matched Rise/Fall Times and Matched
Propagation Delays
♦ CMOS-Compatible Logic Inputs
♦ 56-Pin, 7mm x 7mm, TQFN Package
Pin Configuration
The MAX4806 includes clamp output overvoltage pro-
tection, while the MAX4807 features both pulser output
and clamp output overvoltage protection. The MAX4808
does not provide overvoltage protection (see the
Ordering Information/Selector Guide).
TOP VIEW
42 41 40 39 38 37 36 35 34 33 32 31 30 29
The MAX4806/MAX4807/MAX4808 are available in a
56-pin (7mm x 7mm), TQFN exposed-pad package and
are specified over the 0°C to +70°C commercial tem-
perature range.
28
27
26
25
24
23
22
21
20
19
C
GND
43
44
45
46
47
48
49
50
51
52
53
54
DP2
GND
V
CC2
V
INN2
INC2
INP2
EN2
CC2
GC2
DC2
C
C
Applications
Ultrasound Medical
Imaging
Flaw Detection
V
EE2
Piezoelectric Drivers
Test Instruments
V
AGND
SHDN
EN1
DD
Industrial Sensors
MAX4806
MAX4807
MAX4808
V
SS
EE1
V
Ordering Information/
Selector Guide
OUTPUT
C
C
V
INP1
DC1
GC1
CC1
18 INC1
17 INN1
*EP
PROTECTED
PIN-
GND 55
56
16
V
CC1
+
PART
CURRENT
(A)
OUTPUTS
PACKAGE
C
15 GND
DP1
1
2
3
4
5
6
7
8
9
10 11 12 13 14
MAX4806CTN+ OCP_, OCN_
2
2
2
56 TQFN-EP**
56 TQFN-EP**
56 TQFN-EP**
OCP_, OCN_,
MAX4807CTN+
OP_, ON_
TQFN
7mm x 7mm
MAX4808CTN+*
None
Note: All devices are specified over the 0°C to +70°C operat-
ing temperature range.
*EP = EXPOSED PAD; CONNECT EP TO V
.
SS
+Denotes a lead-free/RoHS-compliant package.
*Future product. Contact factory for availability.
**EP = Exposed pad.
Warning: The MAX4806/MAX4807/MAX4808 are designed to
operate with high voltages. Exercise caution.
________________________________________________________________ Maxim Integrated Products
±
For pricing, delivery, and ordering information, please contact Maxim Direct at ±-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
Dual, Unipolar/Bipolar, High-Voltage
Digital Pulsers
ABSOLUTE MAXIMUM RATINGS
(Voltages referenced to GND.)
C
, C
, C
Voltage .....................................-0.3V to V
DC_ DP_ DN_ CC_
V
V
V
V
V
V
V
Logic Supply Voltage........................................-0.3V to +6V
Peak Current per Output Channel...................................... 3.0A
DD
Output Driver Positive Supply Voltage..........-0.3V to +15V
Output Driver Negative Supply Voltage.........-15V to +0.3V
High Positive Supply Voltage.......................-0.3V to +230V
High Negative Supply Voltage....................-230V to +0.3V
Continuous Power Dissipation (T = +70°C) (Note 1)
CC_
EE_
PP_
NN_
A
56-Pin TQFN (derate 40mW/°C above +70°C) ..........3200mW
Thermal Resistance (Note 2)
θ
JC
.............................................................................+25°C/W
............................................................................+0.8°C/W
JA
θ
Voltage................................................(V
- 250V) to V
SS
PP_
NN_
- V
, V
NN1 PP2
- V Supply Voltage............-0.3V to +250V
Operating Temperature Range...............................0°C to +70°C
Junction Temperature......................................................+150°C
Storage Temperature Range.............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
PP1
NN2
INP_, INN_, INC_, EN_, SHDN Logic Input..-0.3V to (V + 0.3V)
OP_, OCP_, OCN_, ON_...........(-0.3V + V
C
C
C
DD
) to (-0.3V to V
) to (+15V + V
Voltage .............................(+0.3V + V ) to (-15V + V
)
)
)
NN_
NN_
PP_
PP_
NN_
PP_
Voltage............................(-0.3V + V
GN_
GP_
GC_
Voltage...........................................................-15V to +15V
Note ±: This specification is based on the thermal characteristic of the package, the maximum junction temperature, and the setup
described by JEDEC 51. The maximum power dissipation for the MAX4806/MAX4807/MAX4808 might be limited by the thermal
protection included in the device.
Note 2: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-
layer board. For detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V = +2.7V to +6V, V
= +4.75V to +12.6V, V
= -12.6V to -4.75V, V
= -200V to 0V, V
= 0V to (V + 200V), V ≤ the lower
NN_ SS
DD
CC_
, T = T = T
EE_
NN_
PP_
of V
or V
to T
, unless otherwise noted. Typical values are at T = +25°C.) (Note 3)
NN1
NN2
A
J
MIN
MAX A
PARAMETER
POWER SUPPLY (V , V
SYMBOL
, V _, V , V
CONDITIONS
MIN
TYP
MAX
UNITS
67/MAX408
)
DD CC_ EE
PP_ NN_
Logic Supply Voltage
V
+2.7
+4.75
-12.6
+3
+12
-12
+6
V
V
V
DD
Positive Drive Supply Voltage
Negative Drive Supply Voltage
V
+12.6
-4.75
CC_
V
EE_
PP_
NN_
V
+
NN_
220
High-Side Supply Voltage
Low-Side Supply Voltage
V
0
V
V
-200
0
0
V
V
V
- V
Supply Voltage
+220
PP_
NN_
SUPPLY CURRENT (Single Channel)
V
= V
= 0, V = 0
SHDN
1
INN_
EN_
INP_
V
Supply Current
I
µA
µA
DD
DD
V
V
= V , V
= V , V
= 0 or
DD SHDN
DD INC_
100
350
1
, V
DD INN_
= V
, f = 5MHz
INP_
V
= 0, channel 1 and channel 2
SHDN
V
= V , V
= V , channel 1 and
DD
EN_
DD SHDN
130
18
200
channel 2
V
V
V
= V , V
= V , V
= 0 or
, f = 5MHz, V = 5V,
INP_ CC
EN_
DD SHDN
DD INC_
V
Supply Current
I
CC_
CC_
, V
DD INN_
= V
= 3V, only one channel switching
DD
mA
V
V
V
= V , V
= V , V
= 0 or
EN_
DD SHDN
DD INC_
, V
DD INN_
= V
, f = 5MHz, V
= 12V,
CC_
44
INP_
= 3V, only one channel switching
DD
2
_______________________________________________________________________________________
Dual, Unipolar/Bipolar, High-Voltage
Digital Pulsers
67/MAX408
ELECTRICAL CHARACTERISTICS (continued)
(V = +2.7V to +6V, V
= +4.75V to +12.6V, V
= -12.6V to -4.75V, V
= -200V to 0V, V
= 0V to (V + 200V), V ≤ the lower
NN_ SS
DD
CC_
, T = T = T
EE_
NN_
PP_
of V
or V
to T
, unless otherwise noted. Typical values are at T = +25°C.) (Note 3)
NN1
NN2
A
J
MIN
MAX A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
V
V
= 0, channel 1 and channel 2
1
SHDN
= V , V
= V , channel 1 and
DD
EN_
DD SHDN
1
channel 2
V
V
= V , V
= V , V
, f = 5MHz, V
= 0 or
= -5V,
EE_
EN_
DD SHDN
DD INC_
V
Supply Current
I
µA
EE_
EE_
, V
= V
200
DD INN_
INP_
only 1 channel switching
V
V
= V , V
= V , V
, f = 5MHz, V
= 0 or
= -12V,
EE_
EN_
DD SHDN
DD INC_
, V
= V
200
DD INN_
INP_
only 1 channel switching
V
= 0, channel 1 and channel 2
1
SHDN
µA
mA
µA
V
= V , V
= V , channel 1 and
DD
EN_
DD SHDN
90
13
160
channel 2
V
V
= V , V
= V , V
= 0 or V
,
DD
EN_
DD SHDN
DD INC_
= V
, f = 5MHz, V
INP_
= +5V, V
=
INN_
PP_
NN_
V
Supply Current
I
PP_
PP_
-5V, no load, only 1 channel switching
V
V
= V , V
= V , V
= 0 or V
,
DD
EN_
PP_
DD SHDN
DD INC_
= +80V, V
= -80V, pulse repetition
NN_
0.65
frequency = 10kHz, f = 10MHz, four periods,
no load, only 1 channel switching
V
= 0, channel 1 and channel 2
1
SHDN
V
= V , V
= V , channel 1 and
DD
EN_
DD SHDN
40
13
80
channel 2
V
V
V
= V , V
= V , V
= 0 or
EN_
DD SHDN
DD INC_
, V
DD INN_
= V
, f = 5MHz, V
= -5V,
NN_
INP_
V
Supply Current
I
NN_
NN_
= +5V, no load, only 1 channel
PP_
mA
V
V
= V , V
= +80V, V
= V , V
= -80V, pulse repetition
= 0 or V
,
DD
EN_
PP_
DD SHDN
DD INC_
NN_
0.65
frequency = 10kHz, f = 10MHz, four periods,
no load, only 1 channel switching
LOGIC INPUTS (EN_, SHDN, INN_, INP_, INC_)
Low-Level Input Voltage
High-Level Input Voltage
Logic-Input Capacitance
Logic-Input Leakage
OUTPUT (OUT_)
V
0.25 x V
V
V
IL
IH
IN
IN
DD
V
0.75 x V
DD
C
5
pF
µA
I
V
= 0 or V
1
IN
DD
No load at OUT_
V
V
PP_
NN_
Unprotected outputs (see the Ordering
Information/Selector Guide), 100mA load
V
+
V
-
NN_
1.5
PP_
1.5
OUT_ Output Voltage Range
V
V
OUT_
Protected outputs (see the Ordering
Information/Selector Guide), 100mA load
V
+
V
-
NN_
2.5
PP_
2.5
I
= -100mA, V
= +12V 5%, DC-coupled
5
5
12
12
OP_
CC_
Low-Side Small-Signal Output
Impedance (MAX4806)
R
Ω
OUT_LS
I
= -100mA, V
= +5V 5%, DC-coupled
OP_
CC_
_______________________________________________________________________________________
3
Dual, Unipolar/Bipolar, High-Voltage
Digital Pulsers
ELECTRICAL CHARACTERISTICS (continued)
(V = +2.7V to +6V, V
= +4.75V to +12.6V, V
= -12.6V to -4.75V, V
= -200V to 0V, V
= 0V to (V + 200V), V ≤ the lower
NN_ SS
DD
CC_
, T = T = T
EE_
NN_
PP_
of V
or V
to T
, unless otherwise noted. Typical values are at T = +25°C.) (Note 3)
NN1
NN2
A
J
MIN
MAX A
PARAMETER
SYMBOL
CONDITIONS
= -100mA, V = +12V 5%, DC-coupled
MIN
TYP
MAX
13
UNITS
I
6
6
6
8
7
9
OP_
CC_
Low-Side Small-Signal Output
Impedance (MAX4807)
R
Ω
OUT_LS
OUT_HS
OUT_HS
I
= -100mA, V
= +5V 5%, DC-coupled
13
OP_
CC_
I
= -100mA, V
= +12V 5%, DC-coupled
12
OP_
CC_
High-Side Small-Signal Output
Impedance (MAX4806)
R
R
Ω
Ω
I
= -100mA, V
= +5V 5%, DC-coupled
15
OP_
CC_
I
= -100mA, V
= +12V 5%, DC-coupled
13
OP_
CC_
High-Side Small-Signal Output
Impedance (MAX4807)
I
= -100mA, V
= +5V 5%, DC-coupled
17
OP_
CC_
Low-Side Output Current
High-Side Output Current
I
V
V
= +12V 5%, V
= +12V 5%, V
- V
- V
= 100V
= 100V
2
2
A
A
OL
CC_
CC_
OUT_
NN_
I
OH
OUT_
PP_
OP_, ON_, OCP_ and OCN_
connected together;
MAX4806
MAX4807
110
70
Off-Output Capacitance
C
pF
µA
O(OFF)
V
= +100V, V
= -100V
PP_
NN_
V
= -100V, V
= 100V, EN_ = 0,
NN_
PP_
Off-Output Leakage Current
I
LK
-1
+1
40
OUT_ = -100V to +100V
I
= -30mA, DC-coupled, V
= +12V
CC_
OCN_
20
20
20
33
5%, V
= -V
CC_
EE_
Low-Side Signal-Clamp Output
Impedance
R
Ω
Ω
CLS
I
= -30mA, DC-coupled, V
= +5V
OCN_
CC_
50
5%, V
= -V
CC_
EE_
I
= -30mA, DC-coupled, V
= +12V
CC_
OCP_
40
5%, V
= -V
CC_
EE_
High-Side Signal-Clamp Output
Impedance
R
CHS
I
= -30mA, DC-coupled, V
= +5V
OCP_
CC_
67/MAX408
50
5%, V
= -V
CC_
EE_
V
= +12V 5%, V
= -V
= -V
= -V
= -V
, I
=
CC_
EE_
EE_
EE_
EE_
CC_ CGN_
100
10
Ω
kΩ
Ω
10mA, V
= 0
EN_
Low-Side Gate Short Impedance
High-Side Gate Short Impedance
R
LSH
V
= +12V 5%, V
, I
CC_ CGN_
=
=
=
CC_
5
5
7.5
7.5
10mA, EN_ = V
DD
V
= +12V 5%, V
, I
CC_ CGN_
CC_
100
10
10mA, V
= 0
EN_
R
HSH
V
= +12V 5%, V
, I
CC_ CGN_
CC_
kΩ
10mA, EN_ = V
DD
THERMAL SHUTDOWN
Thermal Shutdown
T
Junction temperature rising
+155
20
°C
°C
SHDN
Thermal-Shutdown Hysteresis
DYNAMIC CHARACTERISTICS (R = ±00Ω, C = ±00pF, unless otherwise noted. See Figures 4–7.)
L
L
Logic Input to Output Rise
Propagation Delay
V
= +12V, V
= +5V, V
= +5V, V
= +5V, V
= +5V, V
= -5V,
= -5V,
= -5V,
= -5V,
CC_
PP_
PP_
PP_
PP_
NN_
NN_
NN_
NN_
t
t
15
15
15
15
ns
ns
ns
ns
PLH
Figure 4
Logic Input to Output Fall
Propagation Delay
V
CC_
Figure 4
= +12V, V
PHL
Logic Input to Output Rise
Propagation Delay
V
CC_
Figure 4
= +12V, V
t
POH
Logic Input to Output Fall
Propagation Delay
V
CC_
Figure 4
= +12V, V
t
POL
4
_______________________________________________________________________________________
Dual, Unipolar/Bipolar, High-Voltage
Digital Pulsers
67/MAX408
ELECTRICAL CHARACTERISTICS (continued)
(V = +2.7V to +6V, V
= +4.75V to +12.6V, V
= -12.6V to -4.75V, V
= -200V to 0V, V
= 0V to (V + 200V), V ≤ the lower
NN_ SS
DD
CC_
, T = T = T
EE_
NN_
PP_
of V
or V
to T
, unless otherwise noted. Typical values are at T = +25°C.) (Note 3)
NN1
NN2
A
J
MIN
MAX A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Logic Input to Output-Rise
Propagation Delay Clamp
V
= +12V, V
= +5V, V
= -5V,
= -5V,
CC_
PP_
NN_
t
15
15
ns
PLO
Figure 4
Logic Input to Output-Fall
Propagation Delay Clamp
V
CC_
Figure 4
= +12V, V
= +5V, V
PP_
NN_
t
t
ns
ns
ns
ns
ns
ns
ns
ns
ns
PHO
V
V
V
V
V
V
= +100V, V
= -100V, V
= +12V
PP_
NN_
CC_
CC_
CC_
CC_
CC_
CC_
OUT_ Rise Time (GND to V
)
t
20
35
35
20
35
35
PP_
R0P
RN0
RNP
5%, V
= - V
, Figure 4
CC_
EE_
= +100V, V
= -100V, V
= +12V
= +12V
= +12V
= +12V
= +12V
PP_
NN_
OUT_ Rise Time (V
OUT_ Rise Time (V
to GND)
NN_
NN_
5%, V
= - V
, Figure 4
CC_
EE_
= +100V, V
= -100V, V
PP_
NN_
to V
)
t
PP_
5%, V
= - V
, Figure 4
CC_
EE_
= +100V, V
= -100V, V
PP_
NN_
OUT_ Fall Time (GND to V
)
t
F0N
NN_
5%, V
= - V
, Figure 4
CC_
EE_
= +100V, V
= -100V, V
PP_
NN_
OUT_ Fall Time (V
OUT_ Fall Time (V
to GND)
t
PP_
FP0
FPN
5%, V
= - V
, Figure 4
CC_
EE_
= +100V, V
= -100V, V
PP_
NN_
to V
)
t
PP_
NN_
5%, V
= - V
, Figure 4
CC_
EE_
V
V
V
V
V
V
V
= +12V 5%, V
= -V
CC_
100
150
100
150
150
150
CC_
CC_
CC_
CC_
CC_
CC_
EE_
OUT_ Enable Time from EN_
(Figure 5)
t
EN
= +5V 5%, V
= -V
EE_
CC_
= +12V 5%, V
= +5V 5%, V
= -V
CC_
EE_
OUT_ Disable Time from EN_
(Figure 5)
t
DI
= -V
0
0
EE_
CC_
Clamp Enable Time from INC_
t
= +12V 5%, V
= +12V 5%, V
= -V
= -V
, Figure 6
, Figure 6
= +12V
ns
ns
EN-CL
EE_
EE_
CC_
CC_
Clamp Disable Time from INC_
t
DI-CL
= +12V, V
= -12V, V
, Figure 7
PP_
NN_
CC_
CC_
CC_
CC_
Short Enable Time from EN_
t
1000
250
ns
ns
ns
dB
EN_SH
5%, V
= -V
EE_
V
V
V
= +12V, V
= -12V, V
, Figure 7
= +12V
= +12V
= -5V,
PP_
NN_
CC_
Short Disable Time from EN_
Recovery Time from SHDN
Crosstalk
t
DI_SH
5%, V
= -V
EE_
= +12V, V
= -12V, V
PP_
NN_
CC_
36.8
69
5%, V
= -V
EE_
= V
= +5V, V
= V
NN_ EE_
PP_
CC_
f = 5MHz
V
= +100V, V
= -100V,
PP_
NN_
2nd Harmonic Distortion
RMS Output Jitter
2HD
40
9
dB
ps
f
= 5MHz, V = +12V
CC_
OUT
t
V
CC_
= +12V
J
Note 3: Specifications are guaranteed for the stated global conditions, unless otherwise noted and are 100% production tested at
= +25°C and T = +70°C. Specifications at T = 0°C are guaranteed by design.
T
A
A
A
_______________________________________________________________________________________
5
Dual, Unipolar/Bipolar, High-Voltage
Digital Pulsers
Typical Operating Characteristics
(V = +3.3V, V _ = +12V, V _ = -12V, V = -100V, V _ = +100V, V _ = -100V, f
= 5MHz, T = +25°C, unless otherwise noted.)
A
DD
CC
EE
SS
PP
NN
OUT
I
vs. OUTPUT FREQUENCY
I
vs. OUTPUT FREQUENCY
I
vs. TEMPERATURE
CC_
CC_
CC_
40
35
30
25
20
15
10
5
0.70
0.70
0.68
0.66
0.64
0.62
0.60
0.58
0.56
0.54
0.52
0.50
CONTINUOUS SWITCHING,
4 PULSES, PRF = 10kHz
4 PULSES AT 10MHz, PRF = 10kHz
0.68
0.66
0.64
0.62
0.60
0.58
0.56
0.54
0.52
0.50
V
V
V
= V
= +5V,
PP_
CC_
= V = -5V,
EE_
NN_
= +3.3V, NO LOAD
DD
0
1
2
3
4
5
6
7
8
9
10
1
3
5
7
9
11
13
15
0
10
20
30
40
50
60
70
FREQUENCY (MHz)
FREQUENCY (MHz)
TEMPERATURE (°C)
I
vs. TEMPERATURE
I
vs. OUTPUT FREQUENCY
PP_
I
vs. OUTPUT FREQUENCY
PP_
CC_
30
14
13
12
11
10
9
0.80
0.76
0.72
0.68
0.64
0.60
0.56
0.52
0.48
0.44
0.40
4 PULSES, PRF = 10kHz
CONTINUOUS SWITCHING,
CONTINUOUS SWITCHING,
= 2.5MHz,
V
V
V
= V
= +5V,
f
PP_
NN_
CC_
OUT
PP_
NN_
25
20
15
10
5
= V = -5V,
EE_
V
V
V
= V
CC_
= +5V,
= +3.3V, NO LOAD
= V = -5V,
DD
EE_
= +3.3V, NO LOAD
DD
67/MAX408
8
0
7
0
10
20
30
40
50
60
70
1
3
5
7
9
11
13
15
1
2
3
4
5
6
7
8
9
10
TEMPERATURE (°C)
FREQUENCY (MHz)
FREQUENCY (MHz)
I
vs. TEMPERATURE
I
vs. TEMPERATURE
I
vs. OUTPUT FREQUENCY
PP_
PP_
NN_
0.80
0.76
0.72
0.68
0.64
0.60
0.56
0.52
0.48
0.44
0.40
10
9
8
7
6
5
4
3
2
1
0
0.80
0.76
0.72
0.68
0.64
0.60
0.56
0.52
0.48
0.44
0.40
4 PULSES AT 10MHz, PRF = 10kHz
4 PULSES, PRF = 10kHz
CONTINUOUS SWITCHING,
= 2.5MHz,
f
OUT
V
V
V
= V
= +5V,
PP_
NN_
DD
CC_
EE_
= V = -5V,
= +3.3V, NO LOAD
0
10
20
30
40
50
60
70
0
10
20
30
40
50
60
70
1
3
5
7
9
11
13
15
TEMPERATURE (°C)
TEMPERATURE (°C)
FREQUENCY (MHz)
6
_______________________________________________________________________________________
Dual, Unipolar/Bipolar, High-Voltage
Digital Pulsers
67/MAX408
Typical Operating Characteristics (continued)
(V = +3.3V, V _ = +12V, V _ = -12V, V = -100V, V _ = +100V, V _ = -100V, f
= 5MHz, T = +25°C, unless otherwise noted.)
A
DD
CC
EE
SS
PP
NN
OUT
I
vs. OUTPUT FREQUENCY
I
vs. TEMPERATURE
I
vs. TEMPERATURE
NN_
NN_
NN_
30
25
20
15
10
5
0.80
0.76
0.72
0.68
0.64
0.60
0.56
0.52
0.48
0.44
0.40
10
9
8
7
6
5
4
3
2
1
0
CONTINUOUS SWITCHING,
4 PULSES AT 10MHz, PRF = 10kHz
CONTINUOUS SWITCHING,
f = 2.5MHz,
OUT
V
V
V
= V
= +5V,
PP_
NN_
CC_
= V = -5V,
EE_
V
V
V
= V
CC_
= +5V,
PP_
NN_
DD
= +3.3V, NO LOAD
DD
= V = -5V,
EE_
= +3.3V, NO LOAD
0
1
2
3
4
5
6
7
8
9
10
0
10
20
30
40
50
60
70
0
10
20
30
40
50
60
70
FREQUENCY (MHz)
TEMPERATURE (°C)
TEMPERATURE (°C)
OUT_ FALL TIME (GND TO V
)
)
INP-TO-OUT RISE PROPAGATION DELAY
vs. V /V SUPPLY VOLTAGE
NN_
PP_
vs. V /V
SUPPLY VOLTAGE
CC_ EE_
CC_ EE_
22
20
18
16
14
12
10
8
22
20
18
16
14
12
10
8
24
22
20
18
16
14
12
10
8
R = 100Ω, C = 100pF
R = 100Ω, C = 100pF
L
L
R = 100Ω, C = 100pF
L
L
L
L
6
6
6
4
4
4
2
2
2
0
0
0
+4.75/-4.75
V
+7.5/-7.5
+10/-10
/V SUPPLY VOLTAGE (V)
+12/-12
+4.75/-4.75
V
+7.5/-7.5
+12/-12
+4.75/-4.75
V
+7.5/-7.5
+10/-10
/V SUPPLY VOLTAGE (V)
+12/-12
+5/-5
+12.6/-12.6
+5/-5
+10/-10
+12.6/-12.6
+5/-5
+12.6/-12.6
/V SUPPLY VOLTAGE (V)
CC_ EE_
CC_ EE_
CC_ EE_
INP-TO-OUT FALL PROPAGATION DELAY
vs. V , V SUPPLY VOLTAGE
INP-TO-OUT FALL PROPAGATION DELAY
vs. TEMPERATURE
INP-TO-OUT RISE PROPAGATION DELAY
vs. TEMPERATURE
CC_ EE_
22
21
20
19
18
17
16
15
14
13
12
11
10
20
18
16
14
12
10
8
20
18
16
14
12
10
8
R = 100Ω, C = 100pF
R = 100Ω, C = 100pF
R = 100Ω, C = 100pF
L
L
L
L
L
L
6
6
4
4
2
2
0
0
+4.75/-4.75
V
+7.5/-7.5
+10/-10
/V SUPPLY VOLTAGE (V)
+12/-12
0
10
20
30
40
50
60
70
0
10
20
30
40
50
60
70
+5/-5
+12.6/-12.6
TEMPERATURE (°C)
TEMPERATURE (°C)
CC_ EE_
_______________________________________________________________________________________
7
Dual, Unipolar/Bipolar, High-Voltage
Digital Pulsers
Pin Description
PIN
NAME
FUNCTION
Channel 1 High-Side Gate Input. Connect a 1nF to 10nF capacitor between C
possible to the device.
and C
as close as
GP1
DP1
C
1
GP1
Channel 1 High-Side Positive Supply Voltage Input. Bypass V
as possible to the device. (See Power Supplies and Bypassing in the Applications Information section.)
to GND with a 0.1µF capacitor as close
PP1
V
2, 3
PP1
Depending on the application, additional bypassing may be required.
4, 10, 33,
39
N.C.
No Connection. Not connected internally.
5
6
OP1
Channel 1 High-Side Drain Output
Channel 1 High-Side Clamp Output
OCP1
7, 15, 28,
36, 44, 55
GND
Ground
8
9
OCN1
ON1
Channel 1 Low-Side Clamp Output
Channel 1 Low-Side Drain Output
Channel 1 High-Side Negative Supply Voltage Input. Bypass V
close as possible to the device. (See Power Supplies and Bypassing in the Applications Information
to GND with a 0.1µF capacitor as
NN1
V
11, 12
NN1
section.) Depending on the application, additional bypassing may be required.
Channel 1 Low-Side Gate Input. Connect a 1nF to 10nF capacitor between C
possible to the device.
and C
as close as
GN1
DN1
C
13
14
GN1
Channel 1 Low-Side Driver Output. Connect a 1nF to 10nF capacitor between C
as possible to the device.
and C
as close
GN1
DN1
C
DN1
Channel 1 Gate-Drive Supply Voltage Input. Bypass V
possible to the device. (See Power Supplies and Bypassing in the Applications Information section.)
to GND with a 0.1µF capacitor as close as
CC1
V
16, 54
CC1
67/MAX408
Depending on the output, additional bypassing may be required.
17
18
19
20
INN1
INC1
INP1
EN1
Channel 1 Low-Side Logic Input (See Table 1)
Channel 1 Clamp Logic Input. Clamps OCP1 and OCN1 are turned on when INC1 is high and when INP1
and INN1 are low (see Table 1).
Channel 1 High-Side Logic Input (See Table 1)
Channel 1 Enable Logic Input. Drive EN1 high to enable OP1 and ON1. Pull EN1 low to turn on the gate-
source short circuit (see Table 1).
21
22
Shutdown Logic Input (See Table 1)
SHDN
AGND
Analog Ground. Must be connected to common GND.
Channel 2 Enable Logic Input. Drive EN2 high to enable OP2 and ON2. Pull EN2 low to turn on the gate-
source short circuit (see Table 1).
23
24
25
26
EN2
INP2
INC2
INN2
Channel 2 High-Side Logic Input (See Table 1)
Channel 2 Clamp Logic Input. Clamps OCP2 and OCN2 are turned on when INC2 is high and when INP2
and INN2 are low (see Table 1).
Channel 2 Low-Side Logic Input (See Table 1)
Channel 2 Gate-Drive Supply Voltage Input. Bypass V
possible to the device. (See Power Supplies and Bypassing in the Applications Information section.)
to GND with a 0.1µF capacitor as close as
CC2
V
27, 45
CC2
Depending on the application, additional bypassing may be required.
Channel 2 Low-Side Driver Output. Connect a 1nF to 10nF capacitor between C
as possible to the device.
and C
as close
GN2
DN2
C
29
30
DN2
Channel 2 Low-Side Gate Input. Connect a 1nF to 10nF capacitor between C
possible to the device.
and C
as close as
GN2
DN2
C
GN2
8
_______________________________________________________________________________________
Dual, Unipolar/Bipolar, High-Voltage
Digital Pulsers
67/MAX408
Pin Description (continued)
PIN
NAME
FUNCTION
Channel 2 High-Side Negative Supply Voltage Input. Bypass V
close as possible to the device. (See Power Supplies and Bypassing in the Applications Information
to GND with a 0.1µF capacitor as
NN2
V
31, 32
NN2
section.) Depending on the application, additional bypassing may be required.
34
35
37
38
ON2
OCN2
OCP2
OP2
Channel 2 Low-Side Drain Output
Channel 2 Low-Side Clamp Output
Channel 2 High-Side Clamp Output
Channel 2 High-Side Drain Output
Channel 2 High-Side Positive Supply Voltage Input. Bypass V
as possible to the device. (See Power Supplies and Bypassing in the Applications Information section.)
to GND with a 0.1µF capacitor as close
PP2
V
40, 41
PP2
Depending on the application, additional bypassing may be required.
Channel 2 High-Side Gate Input. Connect a 1nF to 10nF capacitor between C
possible to the device.
and C
as close as
GP2
DP2
C
42
43
46
47
GP2
Channel 2 High-Side Driver Output. Connect a 1nF to 10nF capacitor between C
as possible to the device.
and C
as close
GP2
DP2
C
DP2
Channel 2 High-Side Clamp Gate Input. Connect a 1nF to 10nF capacitor between C
close as possible to the device.
and C
as
GC2
DC2
C
GC2
Channel 2 High-Side Clamp Driver Output. Connect a 1nF to 10nF capacitor between C
close as possible to the device.
and C
as
GC2
DC2
C
DC2
Channel 2 Negative Supply Input. Gate-drive supply voltage for the OCP2 clamp. Bypass V
with a 0.1µF capacitor as close as possible to the device. (See Power Supplies and Bypassing in the
Applications Information section.) Depending on the application, additional bypassing may be required.
to GND
EE2
V
48
EE2
Logic Supply Voltage Input. Bypass V to GND with a 0.1µF capacitor as close as possible to the
device. (See Power Supplies and Bypassing in the Applications Information section.) Depending on the
DD
V
49
50
51
DD
application, additional bypassing may be required.
Substrate Voltage. Connect V to a voltage equal to or more negative than the more negative of V
or
SS
NN1
V
SS
V
.
NN2
Channel 1 Negative Supply Input. Gate-drive supply voltage for the OCP1 clamp. Bypass V
with a 0.1µF capacitor as close as possible to the device. (See Power Supplies and Bypassing in the
Applications Information section.) Depending on the application, additional bypassing may be required.
to GND
EE1
V
EE1
Channel 1 High-Side Clamp Driver Output. Connect a 1nF to 10nF capacitor between C
close as possible to the device.
and C
as
GC1
DC1
C
52
53
DC1
Channel 1 High-Side Clamp Gate Input. Connect a 1nF to 10nF capacitor between C
close as possible to the device.
and C
as
GC1
DC1
C
GC1
Channel 1 High-Side Driver Output. Connect a 1nF to 10nF capacitor between C
as possible to the device.
and C
as close
GP1
DP1
C
56
—
DP1
Exposed Pad. EP must be connected to V . Do not use EP as the only V connection for the device.
EP
SS
SS
ly when the device is not pulsing to the positive or nega-
tive high-voltage supplies. (See Figures 1, 2, and 3.)
Detailed Description
The MAX4806/MAX4807/MAX4808 are dual high-volt-
age, high-speed pulsers that can be independently con-
figured for either unipolar or bipolar pulse outputs. These
devices have independent logic inputs for full pulse con-
trol and independent active clamps. The clamp input,
INC_, can be set high to activate the clamp automatical-
Logic Inputs (INP_, INN_, INC_, EN_, SHDN)
The MAX4806/MAX4807/MAX4808 have a total of nine
logic input signals. SHDN controls power-up and -down
of the device. There are two sets of INP_, INN_, INC_
and EN_ signals: one for each channel. INP_ controls the
_______________________________________________________________________________________
9
Dual, Unipolar/Bipolar, High-Voltage
Digital Pulsers
Table ±. Truth Table
INPUTS
OUTPUTS
ON_
STATE
OCP_,
OCN_
EN_ INP_ INN_ INC_
OP_
SHDN
High
High
High
Powered down, INP_/INN_ disabled, gate-source
0
0
1
1
1
1
1
1
1
X
X
0
0
1
1
1
1
1
X
X
X
X
0
0
0
1
1
X
X
X
X
0
0
1
0
1
0
1
0
1
0
1
X
X
X
Impedance Impedance Impedance short disabled
High
High
Powered down, INP_/INN_ disabled, gate-source
short disabled
GND
Impedance Impedance
High High
Impedance Impedance Impedance enabled
High
Powered up, INP_/INN_ disabled, gate-source short
High
High
Powered up, INP_/INN_ disabled, gate-source short
enabled
GND
Impedance Impedance
High High
Impedance Impedance Impedance disabled
High
Powered up, all inputs enabled, gate-source short
High
High
Powered up, all inputs enabled, gate-source short
disabled
GND
High
Impedance Impedance
High
Powered up, all inputs enabled, gate-source short
V
NN_
Impedance
High
Impedance disabled
High Powered up, all inputs enabled, gate-source short
V
PP_
Impedance Impedance disabled
High
Impedance
V
V
NN_
Not allowed (3ns maximum overlap)
PP_
X = Don’t care.
0 = Logic-low.
1 = Logic-high.
67/MAX408
on and off states of the high-side FET, INN_ controls the
on and off states of the low-side FET, INC_ controls the
active clamp, and EN_ controls the gate-to-source short.
These signals give complete control of the output stage
of each driver (see Table 1 for all logic combinations).
Active Clamps
The MAX4806/MAX4807/MAX4808 feature an active
clamp circuit to improve pulse quality and reduce 2nd
harmonic output. The clamp circuit consists of an n-
channel (DC-coupled) and a p-channel (AC and DC
delay coupled) high-voltage FETs that are switched on
or off by the logic clamp input (INC_). The MAX4806
and the MAX4807 feature protected clamp devices
allowing the clamp circuit to be used in bipolar pulsing
circuits (see Figures 1 and 2). A diode in series with the
OCN_ output prevents the body diode of the low-side
FET from turning on when a voltage lower than GND is
present. Another diode in series with the OCP_ output
prevents the body diode of the high-side FET from turn-
ing on when a voltage higher than ground is present.
The MAX4808 does not have diode protection on the
clamp outputs. Thus, the device is suitable for use in
circuits where only unipolar pulsing is required.
The MAX4806/MAX4807/MAX4808 logic inputs are
CMOS logic compatible, and the logic level is refer-
enced to V
for maximum flexibility. The low 5pF (typ)
DD
input capacitance of the logic inputs reduces loading
and increases switching speed.
High-Voltage Output Protection
(MAX4807 Only)
The high-voltage outputs of the MAX4807 feature an
integrated overvoltage protection circuit that allows the
user to implement multilevel pulsing by connecting the
outputs of multiple pulser channels in parallel. Internal
diodes in series with the ON_ and OP_ outputs prevent
the body diode of the high-side and low-side FETs from
The user can connect the active clamp input (INC_) to a
logic-high voltage and drive only the INP_ and INN_
inputs to minimize the number of signals used to drive the
switching on when a voltage greater than V
is present on the output (see Figure 9).
or V
PP_
NN_
±0 ______________________________________________________________________________________
Dual, Unipolar/Bipolar, High-Voltage
Digital Pulsers
67/MAX408
device. In this case, whenever both the INP_ and INN_
pation limit. See the Typical Operating Characteristics
section for more information on typical supply currents
versus switching frequencies.
inputs are low and the INC_ input is high, the active clamp
circuit pulls the output to GND through the OCP_ and
OCN_ outputs (see Table 1 for more information).
The device consumes most of the supply current from
V
supply to charge and discharge internal nodes
CC_
Power-Supply Ramping and
Gate-Source Short Circuit
such as the gate capacitance of the high-side FET (C )
P
and the low-side FET (C ). Neglecting the small quies-
N
The MAX4806/MAX4807/MAX4808 include a gate-
source short circuit that is controlled by the enable input
(EN_). When SHDN is high and EN_ is low, a 60Ω switch
shorts together the gate and source of the high-side out-
put FET. At the same time, a similar switch shorts the
gate and source of the low-side output FET (Table 1).
The gate-source short circuit prevents accidental turn-
on of the output FETs due to the ramping voltage on
cent supply current and a small amount of current used
to charge and discharge the capacitances at the inter-
nal gate clamp FETs, the power consumption can be
estimated as follows:
2
2
⎡
⎤
× BRF × BTD
P
=
C
× V
× f + C × V
× f
IN
(
⎥
⎦
)
(
)
(
)
VCC_
N
CC_
IN
P
CC_
⎢
⎣
f
= f
= f
IN INN_
INP_
V
and V
, and allows for faster ramping rates and
PP_
NN_
smaller delay times between pulsing modes.
Where f
and f
are the switching frequency of
INP_
INN_
Shutdown Mode
the inputs INN_ and INP_ respectively, and where BRF
is the Burst Repetition Frequency and BTD is the Burst
Time Duration. The typical value gate capacitances of
SHDN is common to both channel 1 and channel 2 and
powers up or down the device. Drive SHDN low to power
down all internal circuits (except the clamp circuits).
When SHDN is low, the device is in the lowest power
state (1µA) and the gate-source short circuit is disabled.
The device takes 36.8ns (typ) to become active when
SHDN is disabled.
the power FET are C = 0.3µF and C = 0.6µF.
N
P
For an output load that has a resistance of R and
capacitance of C , the MAX4806/MAX4807/MAX4808
power dissipation can be estimated as follows (assume
square-wave output and neglect the resistance of the
switches):
L
L
Thermal Protection
A thermal-shutdown circuit with a typical threshold of
+155°C prevents damage due to excessive power dis-
2
⎧
⎪
⎫
⎪
⎡
⎢
⎤
⎥
V
2
1
2
PP _
sipation. When the junction temperature exceeds T =
J
⎡
⎤
P
=
C
+ C × f × V
− V
NN_
+
×
× BRF × BTD
(
)
(
)
⎨
(
)
⎬
VPP_
O
L
IN
PP_
⎢
⎣
⎥
⎦
R
⎢
⎣
⎥
⎦
L
+150°C, all outputs are disabled. Normal operation typ-
ically resumes after the IC’s junction temperature drops
below +130°C.
⎪
⎩
⎪
⎭
Where C is the output capacitance of the device.
O
Applications Information
Power Supplies and Bypassing
The MAX4806/MAX4807/MAX4808 operate from inde-
AC-Coupling Capacitor Selection
pendent supply voltage sets (only V
and V
are
SS
DD
The value of all AC-coupling capacitors (between C
DP_
) should be
common to both channels). The logic input circuit oper-
ates from a +2.7V to +6V single supply (V ). The
and C
, and between C
and C
GP_
DN_
GN_
DD
between 1nF to 10nF. The voltage rating of the capaci-
tor should be greater than V and V . The capaci-
level-shift driver dual supplies, V
/V
operate from
CC_ EE_
PP_
NN_
4.75V to 12.6V.
tors should be placed as close as possible to the
device.
The V
/V
high-side and low-side supplies are dri-
PP_ NN_
ven from a single positive supply up to +220V, from a
single negative supply up to -200V, or from 110V dual
Because INP_ and part of INC_ are AC-coupled to the
output devices, they cannot be driven high indefinitely
when the device is active.
supplies. Either V
or V
can be set at 0V. Bypass
PP_
NN_
each supply input to ground with a 0.1µF capacitor as
close as possible to the device.
Power Dissipation
The power dissipation of the MAX4806/MAX4807/
MAX4808 consists of three major components caused
Depending on the application, additional bypassing
may be needed to maintain the input of both V
and
NN_
by the current consumption from V
, V
VCC_
, and V
.
NN_
CC_ PP_
V
stable during output transitions. For example, with
PP_
The sum of these components (P
, P
, and
VPP_
C
OUT
= 100pF and R
= 100Ω load, the use of an
OUT
P
VNN_
) must be kept below the maximum power-dissi-
______________________________________________________________________________________ ±±
Dual, Unipolar/Bipolar, High-Voltage
Digital Pulsers
V
C
DP_
C
GP_
V
CC_
DD
V
PP_
V
V
DD
CC_
LEVEL
SHIFTER
INP_
C
DP_
C
GP_
OP_
GND
V
SS
V
DD
LEVEL
SHIFTER
INC_
C
DC_
C
GC_
V
V
EE_
OCP_
SHDN
EN_
V
SS
SHORT
CIRCUIT
MAX4806
V
SS
OCN_
V
SS
V
DD
CC_
LEVEL
SHIFTER
GND
ON_
67/MAX408
V
SS
V
V
DD
CC_
C
GN_
LEVEL
SHIFTER
INN_
C
DN_
V
NN_
V
C
C
GC_
C
DN_
C
GN_
GND
EE_
DC_
Figure 1. MAX4806 Simplified Functional Diagram for One Channel
additional 10µF (typ) electrolytic capacitor is recom-
connect EP to a similarly sized pad on the component
side of the PCB. This pad should be connected through
to the solder-side copper by several plated holes to a
large heat-spreading copper area to conduct heat
away from the device.
mended. V is the substrate voltage. Connect V to a
SS
SS
voltage equal to or more negative than the lower of
or V
V
NN1
.
NN2
Exposed Pad and Layout Concerns
The MAX4806/MAX4807/MAX4808 provide an exposed
pad (EP) underneath the TQFN package for improved
The MAX4806/MAX4807/MAX4808 high-speed pulsers
require low-inductance bypass capacitors to their sup-
ply inputs. High-speed PCB trace design practices are
recommended. Pay particular attention to minimize trace
thermal performance. EP is internally connected to V
.
SS
Connect EP to V externally. To aid heat dissipation,
SS
±2 ______________________________________________________________________________________
Dual, Unipolar/Bipolar, High-Voltage
Digital Pulsers
67/MAX408
V
C
DP_
C
GP_
V
CC_
DD
V
PP_
V
V
DD
CC_
LEVEL
SHIFTER
INP_
C
DP_
C
GP_
OP_
GND
V
SS
V
DD
LEVEL
SHIFTER
INC_
C
C
GC_
DC_
V
V
EE_
OCP_
SHDN
EN_
V
SS
SHORT
CIRCUIT
MAX4807
V
SS
OCN_
V
SS
V
DD
CC_
LEVEL
SHIFTER
GND
ON_
V
SS
V
V
DD
CC_
C
GN_
LEVEL
SHIFTER
INN_
C
DN_
V
NN_
V
C
DC_
C
C
DN_
C
GN_
GND
EE_
GC_
Figure 2. MAX4807 Simplified Functional Diagram for One Channel
lengths and use sufficient trace width to reduce inductance.
Use of surface-mount components is recommended.
Typical Application Circuits
Figures 8, 9, and 10 show typical applications for the
MAX4806/MAX4807/MAX4808. Figure 8 shows the
MAX4806 used in a bipolar pulsing connection.
Figure 9 shows the MAX4807 in a five-level pulsing
application, and Figure 10 shows the MAX4808 used in
a unipolar application.
Supply Sequencing
V
must be lower than or equal to the more negative
SS
voltage of V
or V
at all times, and must be
NN2
NN1
turned on before other supply voltages. No other
power-supply sequencing is required for the MAX4806/
MAX4807/MAX4808.
______________________________________________________________________________________ ±3
Dual, Unipolar/Bipolar, High-Voltage
Digital Pulsers
V
C
DP_
C
GP_
V
CC_
DD
V
PP_
V
V
DD
CC_
LEVEL
SHIFTER
INP_
C
DP_
C
GP_
OP_
GND
V
SS
V
DD
LEVEL
SHIFTER
INC_
C
C
GC_
DC_
V
V
EE_
OCP_
SHDN
EN_
V
SS
SHORT
CIRCUIT
MAX4808
V
SS
OCN_
V
SS
V
DD
CC_
LEVEL
SHIFTER
4
GND
ON_
V
SS
V
V
DD
CC_
C
GN_
LEVEL
SHIFTER
INN_
C
DN_
V
NN_
V
C
DC_
C
C
DN_
C
GN_
GND
EE_
GC_
Figure 3. MAX4808 Simplified Functional Diagram for One Channel
±4 ______________________________________________________________________________________
Dual, Unipolar/Bipolar, High-Voltage
Digital Pulsers
67/MAX408
t
FPN
V
PP_
90%
10%
90%
10%
t
t
RNO
FON
OUT_
90%
10%
10%
GND
90%
t
t
ROP
FPO
90%
10%
10%
V
NN_
t
t
t
RNP
POH
PHO
50%
50%
50%
50%
50%
INP_
INN_
t
t
PHL
PLH
t
t
PLO
POL
V
DD
50%
50%
50%
GND
INC_ = HIGH
Figure 4. Detailed Timing (R = 100Ω, C = 100pF)
L
L
OUT_ (INP_ = HIGH)
GND
10%
OUT_ (INN_ = HIGH)
10%
t
t
EN
DI
EN_
50%
50%
INC_ = HIGH
Figure 5. Enable Timing (R = 100Ω, C = 100pF)
L
L
______________________________________________________________________________________ ±5
Dual, Unipolar/Bipolar, High-Voltage
Digital Pulsers
OUT_ (V
)
PP_
1kΩ PULLUP RESISTOR TO V
PP_
GND
10%
10%
1kΩ PULLDOWN RESISTOR TO V
NN_
10%
OUT_ (V
)
NN_
t
t
DI-CL
EN-CL
INC_
Figure 6. Active Clamp Timing
67/MAX408
90%
+12V
C
GN_
GND
GND
10%
10%
C
GP_
-12V
10%
t
t
EN-SH
DI-SH
EN_
50%
1kΩ PULLUP RESISTOR BETWEEN CGN_ AND +12V.
1kΩ PULLDOWN RESISTOR BETWEEN CGP_ AND -12V.
Figure 7. Short-Circuit Timing
±6 ______________________________________________________________________________________
Dual, Unipolar/Bipolar, High-Voltage
Digital Pulsers
67/MAX408
-100V
-12V
+3V
-12V
+12V
+12V
56 55 54 53 52 51 50 49 48 47 46 45 44 43
1
2
3
4
5
6
7
8
9
C
V
42
41
40
39
38
37
36
35
34
C
GP1
GP2
V
V
PP1
PP1
PP2
+100V
+100V
V
PP2
N.C.
N.C.
OP2
OP1
OCP1
GND
OCN1
ON1
OCP2
GND
OCN2
ON2
OUT1
OUT2
MAX4806
10 N.C.
N.C. 33
V
V
11
12
13
14
V
32
31
30
29
NN1
NN1
NN2
NN2
GN2
DN2
-100V
-100V
V
C
C
C
C
GN1
DN1
15 16 17 18 19 20 21 22 23 24 25 26 27 28
V
DD
V
DD
+12V
+12V
Figure 8. MAX4806: Dual Bipolar Pulsing, 100V, GND
______________________________________________________________________________________ ±7
Dual, Unipolar/Bipolar, High-Voltage
Digital Pulsers
-100V
-12V
+3V
-12V
+12V
+12V
56 55 54 53 52 51 50 49 48 47 46 45 44 43
1
2
3
4
5
6
7
8
9
C
V
42
41
40
39
38
37
36
35
34
C
GP1
GP2
V
V
PP1
PP1
PP2
PP2
+50V
+100V
V
N.C.
N.C.
OP2
OP1
OCP1
GND
OCN1
ON1
OCP2
GND
OCN2
ON2
OUT1
OUT1
MAX4807
10 N.C.
N.C. 33
V
V
11
12
13
14
V
32
31
30
29
NN1
NN1
NN2
NN2
GN2
DN2
-50V
-100V
V
C
C
C
GN1
DN1
C
67/MAX408
15 16 17 18 19 20 21 22 23 24 25 26 27 28
+12V
+12V
Figure 9. MAX4807: Five-Level Pulsing, 100V, 50V, GND
±8 ______________________________________________________________________________________
Dual, Unipolar/Bipolar, High-Voltage
Digital Pulsers
67/MAX408
+3V
+12V
+12V
56 55 54 53 52 51 50 49 48 47 46 45 44 43
C
C
AC
AC
1
2
3
4
5
6
7
8
9
C
V
42
41
40
39
38
37
36
35
34
C
GP1
GP2
V
V
PP1
PP1
PP2
PP2
+100V
C
+100V
V
C
PP
PP
N.C.
N.C.
OP2
OP1
OCP1
GND
OCN1
ON1
OCP2
GND
OCN2
ON2
OUT1
OUT2
MAX4808
10 N.C.
N.C. 33
V
V
11
12
13
14
V
32
31
30
29
NN1
NN1
NN2
NN2
GN2
DN2
V
C
C
C
C
GN1
DN1
15 16 17 18 19 20 21 22 23 24 25 26 27 28
+12V
+12V
Figure 10. MAX4808: Dual Unipolar Pulsing, +100V, GND
______________________________________________________________________________________ ±9
Dual, Unipolar/Bipolar, High-Voltage
Digital Pulsers
Package Information
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages.
PACKAGE TYPE
PACKAGE CODE
DOCUMENT NO.
2±-0±44
56 TQFN
T5677-1
67/MAX408
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
20 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2008 Maxim Integrated Products
is a registered trademark of Maxim Integrated Products, Inc.
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