MAX4760 [MAXIM]
High-Bandwidth, Quad DPDT Switches; 高带宽，四通道双刀双掷开关
| 型号： | MAX4760 |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | High-Bandwidth, Quad DPDT Switches |
| 文件： | 总14页 (文件大小：702K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-3037; Rev 1; 11/04
High-Bandwidth, Quad DPDT Switches
General Description
Features
♦ USB 1.1 and USB 2.0 (Full Speed) Signal-
The MAX4760/MAX4761 (DPDT) analog switches operate
from a single +1.8V to +5.5V supply. These switches
feature a low 25pF capacitance for high-speed data
switching applications.
Switching Compliant
♦ Data and Audio Signal Routing
♦ Low-Capacitance (25pF) Data Switches
♦ Less than 0.2ns Skew
The MAX4760 is a quad double-pole/double-throw
(DPDT) switch and the MAX4761 is an octal single-
pole/double-throw (SPDT) switch. They have eight 3.5Ω
on-resistance, low-capacitance switches to route audio
and data signals. The MAX4760 has 4 logic inputs to
control the switches in pairs. The MAX4761 has one
logic control input and an enable input (EN) to disable
the switches.
♦ -3dB Bandwidth: 325MHz
♦ 0.2Ω Channel-to-Channel Matching
♦ 0.8Ω On-Resistance Flatness
♦ Rail-to-Rail Signal Handling
♦ 0.03% THD
♦ +1.8V to +5.5V Supply Range
♦ Tiny 36-Bump UCSP (3mm x 3mm)
♦ 36-Pin Thin QFN (6mm x 6mm)
The MAX4760/MAX4761 are available in a small 36-pin
(6mm x 6mm) thin QFN and 36-bump (3mm x 3mm)
chip-scale package (UCSP™).
Ordering Information
Applications
USB Signal Switching
PART
TEMP RANGE PIN-PACKAGE
Audio-Signal Routing
MAX4760EBX-T -40°C to +85°C 36 UCSP-36
Cellular Phones
MAX4760ETX
-40°C to +85°C 36 Thin QFN (6mm x 6mm)
PDAs/Hand-Held Devices
Notebook Computers
MAX4761EBX-T -40°C to +85°C 36 UCSP-36
MAX4761ETX
-40°C to +85°C 36 Thin QFN (6mm x 6mm)
Functional Diagrams
INA
INA
NO1
NO1
DATA 1
DATA 2
DATA 1
DATA 2
COM1
COM2
COM1
COM2
NC1
NO2
NC1
NO2
NC2
NC2
NO3
INB
NO3
DATA 3
DATA 4
DATA 3
DATA 4
COM3
COM4
COM3
COM4
NC3
NO4
NC3
NO4
NC4
NC4
NO5
INC
NO5
DATA 5
DATA 6
DATA 5
DATA 6
COM5
COM6
COM5
COM6
NC5
NO6
NC5
NO6
NC6
NC6
NO7
IND
NO7
DATA 7
DATA 8
DATA 7
DATA 8
COM7
COM8
COM7
COM8
NC7
NO8
NC7
NO8
NC8
NC8
EN
MAX4760
MAX4761
Pin Configurations/Functional Diagrams/Truth Table continued at end of data sheet.
UCSP is a trademark of Maxim Integrated Products, Inc.
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
High-Bandwidth, Quad DPDT Switches
ABSOLUTE MAXIMUM RATINGS
(All voltages referenced to GND.)
ESD per Method 3015.7....................................................... 2kV
V+, IN_, EN...............................................................-0.3V to +6V
COM_, NO_, NC_ (Note 1) ...........................-0.3V to (V+ + 0.3V)
Continuous Current
NO_, NC_, COM_ ....................................................... 100mA
Peak Current
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range.............................-65°C to +150°C
Lead Temperature (soldering, 10s) ................................ +300°C
Bump Temperature (soldering)
(pulsed at 1ms, 10% duty cycle)................................ 200mA
(pulsed at 1ms, 50% duty cycle)............................... 300mA
Infrared (15s) ...............................................................+220°C
Vapor Phase (60s) .......................................................+215°C
Continuous Power Dissipation (T = +70°C)
A
36-Bump UCSP (derate 15.3mW/°C above +70°C).... 1221mW
36-Pin Thin QFN (derate 26.3mW/°C above +70°C)... 2105mW
Note 1: Signals on NO_, NC_, COM_ exceeding V+ or GND are clamped by internal diodes. Limit forward-diode current to maximum
current rating.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V+ = +2.7V to +5.5V, T = -40°C to +85°C, unless otherwise noted. Typical values are at V+ = 3V, T = +25°C.) (Notes 2, 3)
A
A
PARAMETER
SYMBOL
CONDITIONS
T
MIN
TYP MAX UNITS
A
ANALOG SWITCH
V
,
COM_
Analog Signal Range
T
T
to T
0
V+
V
MIN
MAX
V
V
NO_, NC_
+25°C
to T
2.0
0.2
3.5
4
V+ = 2.7V, I
= 10mA,
= 0V or V+
COM_
On-Resistance (Note 4)
R
Ω
ON
V
or V
NO_
NC_
MIN
MAX
On-Resistance Match
Between Channels
(Notes 4, 5)
+25°C
to T
0.4
V+ = 2.7V, I
= 10mA,
= 1.5V
COM_
∆R
Ω
Ω
ON
V
or V
NO_
NC_
T
T
0.55
MIN
MAX
+25°C
to T
0.8
1.5
1.8
On-Resistance Flatness
(Note 6)
V+ = 2.7V, I
or V
=10mA,
COM_
R
FLAT(ON)
I
NO_(OFF),
V
= 0V or V+
NO_
NC_
MIN
MAX
V+ = 3.6V;
+25°C
to T
-5
+5
NO_, NC_ Off-Leakage
Current
V
V
= 3.3V, 0.3V;
= 0.3V, 3.3V
NC_
nA
COM_
or V
I
NC_(OFF)
T
-25
+25
MIN
MAX
NO_
+25°C
to T
-5
-25
-5
0.01
+5
+25
+5
V+ = 3.6V (MAX4761); V
= 3.3V,
COM_
= 0.3V, 3.3V
COM_ Off-Leakage Current
nA
nA
0.3V; V
or V
NC_
NO_
T
T
MIN
MAX
+25°C
to T
V+ = 3.6V; V
= 3.3V, 0.3V;
COM_
COM_ On-Leakage Current
DYNAMIC
I
COM_(ON)
V
V
or V
= 3.3V, 0.3V or floating
NO_
NC_
-25
+25
MIN
MAX
+25°C
to T
45
25
140
150
50
or V
NC_
= 1.5V;
NO_
Turn-On Time
t
ns
ns
ON
R = 50Ω; C = 35pF, Figure 2
L
L
T
T
MIN
MAX
+25°C
to T
V+ = 2.7V, V
or V
= 1.5V;
NO_
NC_
Turn-Off Time
t
OFF
R = 50Ω; C = 35pF, Figure 2
L
L
60
MIN
MAX
2
_______________________________________________________________________________________
High-Bandwidth, Quad DPDT Switches
ELECTRICAL CHARACTERISTICS (continued)
(V+ = +2.7V to +5.5V, T = -40°C to +85°C, unless otherwise noted. Typical values are at V+ = 3V, T = +25°C.) (Notes 2, 3)
A
A
PARAMETER
SYMBOL
CONDITIONS
V+ = 2.7V, V or V = 1.5V;
T
MIN
TYP MAX UNITS
A
+25°C
to T
15
NO_
NC_
Break-Before-Make (Note 7)
Skew (Note 7)
t
ns
BBM
R = 50Ω, C = 35pF, Figure 3
L
L
T
2
MIN
MAX
t
R = 39Ω, C = 50pF, Figure 4
+25°C
+25°C
+25°C
+25°C
0.2
15
0.5
ns
pC
SKEW
S
L
V
= 0V, R
= 0,
GEN
GEN
Charge Injection
Q
C = 1.0nF, Figure 5
L
On-Channel -3dB Bandwidth
Off-Isolation (Note 8)
BW
Signal = 0dBm, C = 5pF, R = 50Ω
320
100
MHz
dB
L
L
C = 5pF, R = 50Ω, V
= 1V
,
L
L
COM_
P-P
V
ISO
f = 100kHz, Figure 6
C = 5pF, R = 50Ω, V
f = 100kHz, Figure 6
= 1V
,
L
L
COM_
P-P
Crosstalk (Note 9)
V
+25°C
+25°C
+25°C
95
0.03
25
dB
%
CT
Total Harmonic Distortion
NO_, NC_ Off-Capacitance
THD
f = 20Hz to 20kHz, 1V
R = 600Ω
P-P, L
C
C
V
, V
NO_ NC_
= GND, f = 1MHz,
NO_(OFF),
pF
Figure 7
NC_(OFF)
V
, V
= GND, f = 1MHz,
NO_ NC_
Figure 7
COM_ On-Capacitance
C
+25°C
+25°C
54
25
pF
pF
COM(ON)
V
= GND, f = 1MHz (MAX4761),
COM_
COM_ Off-Capacitance
DIGITAL I/O (IN_, EN)
Input Logic High
C
COM(OFF)
Figure 7
V+ = 2.7V to 3.6V
V+ = 3.6V to 5.5V
V+ = 2.7V to 3.6V
V+ = 3.6V to 5.5V
T
T
T
T
T
to T
to T
to T
to T
to T
1.4
2.0
MIN
MIN
MIN
MIN
MIN
MAX
MAX
MAX
MAX
MAX
V
V
IH
0.5
0.6
1
Input Logic Low
V
V
IL
Input Leakage Current
POWER SUPPLY
I
IN
V
= 0 or V+
IN
µA
Power-Supply Range
V+
I+
T
to T
1.8
5.5
1.0
V
MIN
MAX
+25°C
to T
0.01
Positive Supply Current
V+ = 5.5V, V
= 0V or V+
µA
IN_
T
MIN
MAX
Note 2: The algebraic convention is used in this data sheet; the most negative value is shown in the minimum column.
Note 3: UCSP packages are 100% tested at +25°C and limits across the full temperature range are guaranteed by correlation and
design. Thin QFN packages are 100% tested at +85°C and limits across the full temperature range are guaranteed by cor-
relation and design.
Note 4: R
and ∆R
matching specifications are guaranteed by design.
ON
ON
Note 5: ∆R
= R
- R
.
ON
ON(MAX)
ON(MIN)
Note 6: Flatness is defined as the difference between the maximum and minimum value of on-resistance as measured over the
specified analog signal ranges.
Note 7: Guaranteed by design, not production tested.
Note 8: Off-isolation = 20log [V
/ (V
or V
)], V
= output, V
or V
= input to off switch.
10 COM_
NO_
NC_
COM_
NO_
NC_
Note 9: Between any two switches.
_______________________________________________________________________________________
3
High-Bandwidth, Quad DPDT Switches
Typical Operating Characteristics
(V+ = 3V, T = +25°C, unless otherwise noted.)
A
ON-RESISTANCE
ON-RESISTANCE
vs. V
AND TEMPERATURE
vs. V
AND TEMPERATURE
ON-RESISTANCE vs. V
COM
COM
COM
5
4
3
2
1
0
5
4
3
2
1
0
10
9
V+ = 5V
V+ = 3V
V+ = 1.8V
8
7
6
T
= +85°C
T = +25°C
A
A
T
= +85°C
= -40°C
T
A
= +25°C
A
V+ = 2V
5
V+ = 2.3V
4
V+ = 2.7V
3
V+ = 5V
T
= -40°C
A
2
T
A
V+ = 3V
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
(V)
1
0
0.5
1.0
1.5
2.0
2.5
3.0
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
(V)
0
V
COM
(V)
V
COM
V
COM
COM OFF-LEAKAGE CURRENT
vs. TEMPERATURE
NO/NC OFF-LEAKAGE CURRENT
vs. TEMPERATURE
COM ON-LEAKAGE CURRENT
vs. TEMPERATURE
10
1
10
1
10
1
V+ = 3V/5V
V+ = 3V/5V
V+ = 3V/5V
V+ = 5V
V+ = 5V
V+ = 5V
0.1
0.1
V+ = 3V
V+ = 3V
0.1
0.01
V+ = 3V
0.01
0.001
0.01
0.001
-40
-15
10
35
60
85
-40
-15
10
35
60
85
-40
-15
10
35
60
85
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
SUPPLY CURRENT vs. SUPPLY VOLTAGE
CHARGE INJECTION vs. V
SUPPLY CURRENT vs. TEMPERATURE
COM
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
60
50
40
30
20
10
0
1000
10
C = 1nF
L
V+ = 5V
V+ = 5V
V+ = 3V
V+ = 3V
0.1
0.001
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
SUPPLY VOLTAGE (V)
0
1
2
3
4
5
-40
-15
10
35
60
85
V
(V)
TEMPERATURE (°C)
COM
4
_______________________________________________________________________________________
High-Bandwidth, Quad DPDT Switches
Typical Operating Characteristics (continued)
(V+ = 3V, T = +25°C, unless otherwise noted.)
A
LOGIC THRESHOLD
vs. SUPPLY VOLTAGE
TURN-ON/OFF TIME
vs. SUPPLY VOLTAGE
TURN-ON/OFF TIMES
vs. TEMPERATURE
2.0
1.6
1.2
0.8
0.4
0
80
70
60
50
40
30
20
10
0
70
60
50
40
30
20
10
0
t
ON
t
, V+ = 3V
ON
V
IH
V
t
, V+ = 5V
IL
ON
t
OFF
t
, V+ = 3V
, V+ = 5V
-15
OFF
t
OFF
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
SUPPLY CURRENT (V)
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
SUPPLY VOLTAGE (V)
-40
10
35
60
85
TEMPERATURE (°C)
SKEW vs. TEMPERATURE
FREQUENCY RESPONSE
SKEW vs. SUPPLY VOLTAGE
600
500
400
300
200
100
0
20
0
600
500
400
300
200
100
0
INPUT RISE/FALL TIME = 15ns
C = 50pF, FIGURE 3
L
INPUT RISE/FALL TIME = 15ns
C = 50pF, FIGURE 3
L
V+ = 4.2V
-20
-40
-60
-80
-100
-120
-140
ON-LOSS
CROSSTALK
OFF-ISOLATION
-40
-15
10
35
60
85
0.0001
0.01
1
100
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
SUPPLY VOLTAGE (V)
TEMPERATURE (°C)
FREQUENCY (MHz)
TOTAL HARMONIC DISTORTION
vs. FREQUENCY
1
R = 600Ω
L
0.1
0.01
10
100
1k
10k
100k
FREQUENCY (Hz)
_______________________________________________________________________________________
5
High-Bandwidth, Quad DPDT Switches
Pin Description
PIN
MAX4760
MAX4761
NAME
FUNCTION
THIN
THIN
UCSP
UCSP
QFN
QFN
1
2
3
A1
B2
A2
1
2
3
A1
B2
A2
NC1
COM2
NC2
Analog Switch 1, Normally Closed Terminal 1
Analog Switch 2, Common Terminal 2
Analog Switch 2, Normally Closed Terminal 2
Logic Control Digital Input for the MAX4760 Switch 1 and Switch 2.
Digital control input for all MAX4761 switches.
4
A3
4
A3
INA
5
6
C3, D4
A4
5
—
7
C3, D4
—
V+
INB
Positive Supply Voltage
Logic Control Digital Input for Switches 3 and 4
Analog Switch 3, Normally Closed Terminal 3
Analog Switch 3, Common Terminal 2
Analog Switch 4, Normally Closed Terminal 4
Analog Switch 4, Common Terminal 4
7
A5
A5
NC3
8
B5
8
B5
COM3
NC4
9
A6
9
A6
10
B6
10
B6
COM4
11, 14,
17, 29,
32, 35
6, 11, 14,
17, 24,
29, 32, 35
—
A4, F3
N.C.
No Connection. Not internally connected.
12
13
15
16
18
19
20
21
22
23
24
25
26
27
28
30
31
33
34
36
—
C5
C6
D6
D5
E6
12
13
15
16
18
19
20
21
—
C5
C6
D6
D5
E6
NO3
NO4
NO8
NO7
COM8
NC8
COM7
NC7
IND
Analog Switch 3, Normally Open Terminal 3
Analog Switch 4, Normally Open Terminal 4
Analog Switch 8, Normally Open Terminal 8
Analog Switch 7, Normally Open Terminal 7
Analog Switch 8, Common Terminal 8
Analog Switch 8, Normally Closed Terminal 8
Analog Switch 7, Common Terminal 7
Analog Switch 7, Normally Closed Terminal 7
Logic Control Digital Input for Switches 7 and 8
Ground
F6
F6
E5
E5
F5
F5
F4
—
C4, D3
F3
23
—
C4, D3
—
GND
INC
Logic Control Digital Input for Switches 5 and 6
Analog Switch 6, Normally Closed Terminal 2
Analog Switch 6, Common Terminal 6
Analog Switch 5, Normally Closed Terminal 5
Analog Switch 5, Common Terminal 5
Analog Switch 6, Normally Open Terminal 6
Analog Switch 5, Normally Open Terminal 5
Analog Switch 1, Normally Open Terminal 1
Analog Switch 2, Normally Open Terminal 1
Analog Switch 1, Common Terminal 1
Output Enable, Active Low
F2
25
26
27
28
30
31
33
34
36
22
EP
F2
NC6
COM6
NC5
COM5
NO6
NO5
NO1
NO2
COM1
EN
E2
E2
F1
F1
E1
E1
D2
D1
C1
C2
B1
—
D2
D1
C1
C2
B1
F4
EP
—
—
EP
Exposed Pad, Connect to GND.
6
_______________________________________________________________________________________
High-Bandwidth, Quad DPDT Switches
Detailed Description
The MAX4760 quad double-pole/double-throw (DPDT)
POSITIVE SUPPLY
V+
and the MAX4761 octal single-pole/double-throw
(SPDT) analog switches operate from a single +1.8V to
+5.5V supply. These devices are fully specified for +3V
applications.
D1
MAX4760
MAX4761
The MAX4760/MAX4761 have a guaranteed 3.5Ω (max)
on-resistance to switch data or audio signals. The low
25pF capacitance and 0.2ns change in skew makes
them ideal for data switching applications. The MAX4760
has 4 logic inputs to control two switches in pairs and the
MAX4761 has one logic control input and an enable input
(EN) to disable the switches.
NO
COM
GND
Applications Information
Digital Control Inputs
The MAX4760/MAX4761 logic inputs accept up to
+5.5V regardless of the supply voltage. For example,
with a +3.3V supply, IN_ can be driven low to GND and
high to +5.5V, which allows mixed logic levels in a sys-
tem. Driving the control logic inputs rail-to-rail also mini-
mizes power consumption. For a +3V supply voltage,
the logic thresholds are 0.5V (low) and 1.4V (high).
Figure 1. Overvoltage Protection Using an External Blocking
Diode
Power-Supply Sequencing
CMOS devices require proper power-supply sequenc-
ing. Always apply V+ before the analog signals, espe-
cially if the input signal is not current limited. If
sequencing is not possible, and the input signal is not
current limited to less than 20mA, add a small-signal
diode (Figure 1). Adding the diode reduces the analog
range to a diode drop (0.7V) below V+ and increases
the on-resistance slightly. The maximum supply voltage
must not exceed +6V at any time.
For the MAX4761, drive EN low to enable. When EN is
high, COM_ is high impedance.
Analog Signal Levels
Analog signal inputs over the full voltage range (0V to V+)
are passed through the switch with minimal change in on-
resistance (see the Typical Operating Characteristics).
The switches are bidirectional so NO_, NC_, and COM_
can be either inputs or outputs.
UCSP Applications Information
For the latest application details on UCSP construction,
dimensions, tape carrier information, printed circuit
board techniques, bump-pad layout, and recommend-
ed reflow temperature profile, as well as the latest infor-
mation on reliability testing results, go to the Maxim
website at www.maxim-ic.com/ucsp for the Application
Note, “UCSP—A Wafer-Level Chip-Scale Package.”
Power-Supply Bypassing
Power-supply bypassing improves noise margin and
prevents switching noise from propagating from the V+
supply to other components. A 0.1µF capacitor connect-
ed from V+ to GND is adequate for most applications.
_______________________________________________________________________________________
7
High-Bandwidth, Quad DPDT Switches
Timing Circuits/Timing Diagrams
MAX4760
MAX4761
V+
t < 5ns
r
V+
0V
t < 5ns
f
LOGIC
INPUT
50%
V+
COM_
50%
NO_
V
N_
V
OUT
OR NC_
t
OFF
R
L
C
L
IN_
V
OUT
0.9 x V
0.9 x V
OUT
0UT
GND
LOGIC
INPUT
SWITCH
OUTPUT
0V
C INCLUDES FIXTURE AND STRAY CAPACITANCE.
L
IN DEPENDS ON SWITCH CONFIGURATION;
INPUT POLARITY DETERMINED BY SENSE OF SWITCH.
R
L
V
OUT
= V
N_
(
)
ON
R + R
L
Figure 2. Switching Time
V+
V+
MAX4760
MAX4761
V+
0V
LOGIC
INPUT
50%
NC_
NO_
V
OUT
V
N_
COM_
R
L
C
L
IN_
LOGIC
INPUT
GND
0.9 x V
OUT
V
OUT
t
BBM
C INCLUDES FIXTURE AND STRAY CAPACITANCE.
L
Figure 3. Break-Before-Make Interval
8
_______________________________________________________________________________________
High-Bandwidth, Quad DPDT Switches
Timing Circuits/Timing Diagrams (continued)
t
ri
90%
50%
B
10%
90%
A
INPUT A
TxD+
t
skew_i
R
s
C
L
INPUT A-
50%
10%
t
fi
t
ro
90%
50%
B-
10%
90%
A-
OUTPUT B
OUTPUT B-
TxD-
t
skew_o
C
L
R
s
R = 39Ω
s
C = 50pF
L
50%
fo
10%
t
|t t | DELAY DUE TO SWITCH FOR RISING INPUT AND RISING OUTPUT SIGNALS.
ro - ri
|t t | DELAY DUE TO SWITCH FOR FALLING INPUT AND FALLING OUTPUT SIGNALS.
fo - fi
|t
| CHANGE IN SKEW THROUGH THE SWITCH FOR OUTPUT SIGNALS.
skew_o
|t
|
CHANGE IN SKEW THROUGH THE SWITCH FOR INPUT SIGNALS.
skew_i
Figure 4. Input/Output Skew Timing Diagram
V+
∆V
OUT
MAX4760
MAX4761
V+
V
OUT
R
GEN
COM_
NC_
V
OUT
IN
OR NO_
OFF
OFF
OFF
OFF
C
L
ON
V
GEN
GND
IN_
ON
Q = (∆V )(C )
V
TO V
IH
IL
IN
OUT
L
LOGIC INPUT WAVEFORMS INVERTED FOR SWITCHES
THAT HAVE THE OPPOSITE LOGIC SENSE.
Figure 5. Charge Injection
_______________________________________________________________________________________
9
High-Bandwidth, Quad DPDT Switches
Timing Circuits/Timing Diagrams (continued)
+5V
V+
10nF
V
V
OUT
OFF-ISOLATION = 20log ✕
ON-LOSS = 20log ✕
IN
NETWORK
ANALYZER
V
OUT
50Ω
50Ω
V
V
0V OR V+
IN
IN_
V
IN
COM1
NO1*
V
OUT
CROSSTALK = 20log ✕
NC1
MAX4760
MAX4761
V
IN
MEAS
REF
OUT
50Ω
GND
50Ω
50Ω
*FOR CROSSTALK THIS PIN IS NO2.
NC2 AND COM2 ARE OPEN.
MEASUREMENTS ARE STANDARDIZED AGAINST SHORTS AT IC TERMINALS.
OFF-ISOLATION IS MEASURED BETWEEN COM_ AND OFF NO_ OR NC_ TERMINAL ON EACH SWITCH.
ON-LOSS IS MEASURED BETWEEN COM_ AND ON NO_ OR NC_ TERMINAL ON EACH SWITCH.
CROSSTALK IS MEASURED FROM ONE CHANNEL TO THE OTHER CHANNEL.
SIGNAL DIRECTION THROUGH SWITCH IS REVERSED; WORST VALUES ARE RECORDED.
Figure 6. On-Loss, Off-Isolation, and Crosstalk
Typical Operating Circuit
V+
INA
NO1
10nF
HEADPHONES
COM1
RIGHT
NC1
NO2
V+
COM_
MAX4760
MAX4761
NC2
HEADPHONES
COM2
LEFT
IN
V
IL
OR V
IH
CAPACITANCE
METER
NC_ or
NO_
INO
NO7
f = 1MHz
GND
COM7
SWITCHING DATA SIGNALS
NC7
NO8
COM8
Figure 7. Channel On-/Off-Capacitance
NC8
MAX4760
10 ______________________________________________________________________________________
High-Bandwidth, Quad DPDT Switches
Pin Configurations/Truth Tables
TOP VIEW
MAX4760
(BUMP SIDE DOWN)
1
2
3
4
5
6
NC1
NC2
INA
NC3
INB
NC4
A
NC1
COM2
NC2
INA
NC5
COM6
NC6
INC
1
2
3
4
5
6
27
26
25
24
23
22
COM1
NO1
COM2
NO2
COM3
NO3
COM4
NO4
B
V+
GND
V+
C
D
E
MAX4760
V+
GND
IND
NO5
NO6
GND
NO7
NO8
INB
COM5
NC5
COM6
NC6
COM7
NC7
COM8
NC8
NC3
7
8
9
21 NC7
20
19
COM3
NC4
COM7
NC8
INC
IND
F
UCSP
MAX4760
THIN QFN
NOTE: EXPOSED PADDLE CONNECTED TO GND OR FLOATING.
INA NO1/NO2 NC1/NC2
LOW
HIGH
OFF
ON
ON
OFF
MAX4761
INB NO3/NO4 NC3/NC4
EN
INA
NO_
NC_
LOW
HIGH
OFF
ON
ON
LOW
LOW
HIGH
HIGH
LOW
HIGH
X
OFF
ON
ON
OFF
OFF
OFF
OFF
INC NO5/NO6 NC5/NC6
OFF
OFF
LOW
HIGH
OFF
ON
ON
X
OFF
IND NO7/NO8 NC7/NC8
LOW
HIGH
OFF
ON
ON
OFF
______________________________________________________________________________________ 11
High-Bandwidth, Quad DPDT Switches
Pin Configurations/Truth Tables (continued)
TOP VIEW
MAX4761
(BUMP SIDE DOWN)
1
2
3
4
5
6
NC1
NC2
INA
NC3
N.C.
NC4
A
NC1
COM2
NC2
INA
NC5
COM6
NC6
N.C.
GND
EN
1
2
3
4
5
6
27
26
25
24
23
22
COM1
NO1
COM2
NO2
COM3
NO3
COM4
NO4
B
V+
GND
V+
C
D
E
MAX4761
V+
NO5
NO6
GND
NO7
NO8
N.C.
NC3
COM5
NC5
COM6
NC6
COM7
NC7
COM8
NC8
7
8
9
21 NC7
20
19
COM3
NC4
COM7
NC8
N.C.
EN
F
UCSP
THIN QFN
NOTE: EXPOSED PADDLE CONNECTED TO GND.
Chip Information
TRANSISTOR COUNT: 1432
PROCESS: CMOS
12 ______________________________________________________________________________________
High-Bandwidth, Quad DPDT Switches
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
D2
D
C
L
b
D/2
D2/2
k
E/2
E2/2
(NE-1) X
e
C
L
E
E2
k
L
e
(ND-1) X
e
e
L
C
C
L
L
L1
L
L
e
e
A
A1
A2
PACKAGE OUTLINE
36, 40, 48L THIN QFN, 6x6x0.8mm
1
E
21-0141
2
NOTES:
1. DIMENSIONING & TOLERANCING CONFORM TO ASME Y14.5M-1994.
2. ALL DIMENSIONS ARE IN MILLIMETERS. ANGLES ARE IN DEGREES.
3. N IS THE TOTAL NUMBER OF TERMINALS.
4. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL CONFORM TO JESD 95-1
SPP-012. DETAILS OF TERMINAL #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE
ZONE INDICATED. THE TERMINAL #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE.
5. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.25 mm AND 0.30 mm
FROM TERMINAL TIP.
6. ND AND NE REFER TO THE NUMBER OF TERMINALS ON EACH D AND E SIDE RESPECTIVELY.
7. DEPOPULATION IS POSSIBLE IN A SYMMETRICAL FASHION.
8. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS.
9. DRAWING CONFORMS TO JEDEC MO220, EXCEPT FOR 0.4mm LEAD PITCH PACKAGE T4866-1.
10. WARPAGE SHALL NOT EXCEED 0.10 mm.
PACKAGE OUTLINE
36, 40, 48L THIN QFN, 6x6x0.8mm
2
E
21-0141
2
______________________________________________________________________________________ 13
High-Bandwidth, Quad DPDT Switches
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
PACKAGE OUTLINE, 6x6 UCSP
1
21-0082
J
1
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
14 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2004 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
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