MAX4731 [MAXIM]
50 зDual SPST Analog Switches in UCSP; 50 зDual SPST模拟开关,UCSP封装型号: | MAX4731 |
厂家: | MAXIM INTEGRATED PRODUCTS |
描述: | 50 зDual SPST Analog Switches in UCSP |
文件: | 总12页 (文件大小:319K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
19-2645; Rev 0; 10/02
50 Dual SPST Analog Switches in UCSP
General Description
Features
ꢀ 1.52mm ✕ 1.52mm UCSP Package
The MAX4731/MAX4732/MAX4733 low-voltage, dual,
single-pole/single-throw (SPST) analog switches oper-
ate from a single +2V to +11V supply and handle Rail-
ꢀ Guaranteed On-Resistance (R
25 (max) at +5V
)
ON
®
to-Rail analog signals. These switches exhibit low
50 (max) at +3V
leakage current (0.1nA) and consume less than 0.5nW
(typ) of quiescent power, making them ideal for battery-
powered applications.
ꢀ On-Resistance Matching
3
(max) at +5V
3.5 (max) at +3V
When powered from a +3V supply, these switches fea-
ꢀ Guaranteed <0.1nA Leakage Current at
ture 50 (max) on-resistance (R ) with 3.5 (max)
ON
T = +25°C
A
matching between channels, and 9 (max) flatness
over the specified signal range.
ꢀ Single-Supply Operation from +2.0V to +11V
ꢀ TTL/CMOS-Logic Compatible
ꢀ -108dB Crosstalk (1MHz)
ꢀ -72dB Off-Isolation (1MHz)
ꢀ Low Power Consumption: 0.5nW (typ)
ꢀ Rail-to-Rail Signal Handling
The MAX4731 has two normally open (NO) switches,
the MAX4732 has two normally closed (NC) switches,
and the MAX4733 has one NO and one NC switch. The
MAX4731/MAX4732/MAX4733 are available in a
9-bump chip-scale package (UCSP™) and an 8-pin
µMAX package. The tiny UCSP occupies a 1.52mm ✕
1.52mm area and significantly reduces the required PC
board area.
Ordering Information
TEMP
RANGE
PIN/BUMP-
PACKAGE
TOP
MARK
PART
Applications
MAX4731EUA
MAX4731EBL-T*
MAX4732EUA
MAX4732EBL-T*
MAX4733EUA
MAX4733EBL-T*
-40°C to +85°C 8 µMAX
-40°C to +85°C 9 UCSP-9**
-40°C to +85°C 8 µMAX
-40°C to +85°C 9 UCSP-9**
-40°C to +85°C 8 µMAX
-40°C to +85°C 9 UCSP-9**
—
ABV
—
Battery-Powered Systems
Audio/Video-Signal Routing
Low-Voltage Data-Acquisition Systems
Cell Phones
ABT
—
Communications Circuits
PDAs
ABS
Note: Requires special solder temperature profile described in
the Absolute Maximum Ratings section.
*Future product—contact factory for availability.
UCSP is a trademark of Maxim Integrated Products, Inc.
Rail-to-Rail is a registered trademark of Nippon Motorola, Ltd.
**UCSP reliability is integrally linked to the user’s assembly
methods, circuit board material, and environment. See the UCSP
Reliability section of this data sheet for more information.
Pin Configurations/Functional Diagrams/Truth Tables
TOP VIEW
(BUMPS
ON BOTTOM)
MAX4731
COM1
MAX4732
COM1
MAX4733
COM1
NO1
IN1
V+
A1
B1
C1
A2
A3
B3
A1
B1
A2
A3
B3
A1
B1
A2
A3
B3
GND
IN2
NC1
IN1
GND
IN2
NO1
IN1
GND
IN2
C3 NO2
V+ C1
C3 NC2
V+ C1
C3 NC2
C2
C2
C2
COM2
UCSP
COM2
UCSP
COM2
UCSP
MAX4731
MAX4732
MAX4733
IN_
NO_
OFF
ON
IN_
NC_
ON
IN_
0
NO1
OFF
ON
NC2
ON
0
1
0
1
Pin Configurations/Functional Diagrams/
OFF
1
OFF
Truth Tables continued at end of data sheet.
SWITCHES SHOWN
FOR LOGIC "0" INPUT
SWITCHES SHOWN
FOR LOGIC "0" INPUT
SWITCHES SHOWN FOR LOGIC "0" INPUT
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
50 Dual SPST Analog Switches in UCSP
ABSOLUTE MAXIMUM RATINGS
(All Voltages Referenced to GND)
Operating Teꢁperature Range ...........................-40°C to +85°C
V+...........................................................................-0.3V to +12V
IN_% COM_% NO_% NC_ (Note 1)....................-0.3V to (V+ + 0.3V)
Continuous Current (any pin) ........................................... 10ꢁA
Peak Current (any pin% pulsed at 1ꢁs% 10ꢀ duty cycle)... 20ꢁA
Storage Teꢁperature Range.............................-65°C to +150°C
Maxiꢁuꢁ Junction Teꢁperature .....................................+150°C
Lead Teꢁperature (soldering% 10s) .................................+300°C
Buꢁp Teꢁperature (soldering% Note 2)
Infrared (15s) ...............................................................+220°C
Vapor Phase (60s) .......................................................+215°C
Continuous Power Dissipation (T = +70°C)
A
8-Pin µMAX (derate 4.5ꢁW/°C above +70°C).............362ꢁW
9-Buꢁp UCSP (derate 4.7ꢁW/°C above +70°C).........379ꢁW
Note 1: Signals on IN_% NO_% NC_% or COM_ exceeding V+ or GND are claꢁped by internal diodes. Liꢁit forward-diode current to
ꢁaxiꢁuꢁ current rating.
Note 2: This device is constructed using a unique set of packaging techniques that iꢁpose a liꢁit on the therꢁal profile the device
can be exposed to during board level solder attach and rework. This liꢁit perꢁits only the use of the solder profiles recoꢁ-
ꢁended in the industry-standard specification% JEDEC 020A% paragraph 7.6% Table 3 for IR/VPR and Convection reflow. Pre-
heating is required. Hand or wave soldering is not allowed.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS—Single +3V Supply
(V+ = +3V 10ꢀ% V = +2.0V% V = +0.8V% T = T
to T % unless otherwise noted. Typical values are at V+ = +3V% T = +25°C.)
MAX A
IH
IL
A
MIN
(Notes 3% 4)
PARAMETER
SYMBOL
CONDITIONS
T
MIN
TYP
MAX
UNITS
A
ANALOG SWITCH
V
%
COM_
% V
Analog Signal Range
0
V+
50
V
V
NO_ NC_
+25°C
to
T
MAX
19
0.8
2.3
V+ = +2.7V%
I = 5ꢁA;
COM_
On-Resistance
R
ON
T
MIN
60
V
or V
= +1.5V
NO_
NC_
+25°C
to
3.5
4.5
9
V+ = +2.7V%
I = 5ꢁA;
COM_
On-Resistance Matching
Between Channels (Notes 5% 6)
R
ON
T
MIN
V
or V
= +1.5V
NC_
NO_
T
MAX
+25°C
V+ = +2.7V%
= 5ꢁA;
On-Resistance Flatness
(Note 7)
R
I
FLAT(ON)
COM_
T
to
MIN
11
V
or V
= +1V% +1.5V% +2V
NC_
NO_
T
MAX
+25°C
-0.1
-2
+0.1
+2
V+ = +3.6V%
NO_ or NC_ Off-Leakage Current
(Note 8)
I
I
NO_(OFF)
V
V
= +0.3V% +3V;
nA
nA
COM_
T
to
MIN
NC_(OFF)
or V
= +3V% +0.3V
= +3V% +0.3V
NC_
NO_
NC_
T
MAX
+25°C
T to
MIN
-0.1
-2
+0.1
+2
V+ = +3.6V%
COM_ Off-Leakage Current
(Note 8)
I
V
V
= +0.3V% +3V;
or V
COM_(OFF)
COM_
NO_
T
MAX
+25°C
-0.2
+0.2
V+ = +3.6V%
COM_ On-Leakage Current
(Note 8)
V
V
= +0.3V% +3.0V;
COM_
I
nA
COM_(ON)
T
T
to
MAX
MIN
or V
= +0.3V% +3V% or
NC_
NO_
-4
+4
floating
2
_______________________________________________________________________________________
50 Dual SPST Analog Switches in UCSP
ELECTRICAL CHARACTERISTICS—Single +3V Supply (continued)
(V+ = +3V 10ꢀ% V = +2.0V% V = +0.8V% T = T
to T % unless otherwise noted. Typical values are at V+ = +3V% T = +25°C.)
MAX A
IH
IL
A
MIN
(Notes 3% 4)
PARAMETER
SYMBOL
CONDITIONS
T
MIN
TYP
MAX
UNITS
ns
A
DYNAMIC CHARACTERISTICS
+25°C
to
70
150
170
60
V
or V
= +1.5V%
NC_
R = 300 %
L
C = 35pF% Figure 2
NO_
Turn-On Tiꢁe
t
ON
T
MIN
L
T
MAX
+25°C
30
40
V
or V
= +1.5V%
NC_
NO_
Turn-Off Tiꢁe
t
ns
R = 300 % C = 35pF%
OFF
L
L
T
to
MIN
70
Figure 2
T
MAX
+25°C
V
or V
= +1.5V%
NC_
NO_
Break-Before-Make
(MAX4733 Only% Note 8)
t
R = 300 % C = 35pF%
ns
BBM
L
L
T
to
MIN
1
Figure 3
T
MAX
V
= 0V% R
= 0% C = 1.0nF%
GEN
GEN L
Charge Injection
Q
+25°C
+25°C
7.5
pC
Figure 4
On-Channel -3dB Bandwidth
BW
Signal = 0dBꢁ% 50 in and out
300
MHz
f = 1MHz% V
= 1V
%
%
COM_
RMS
RMS
Off-Isolation (Note 9)
Crosstalk (Note 10)
V
R = 50 % C = 5pF%
+25°C
+25°C
-72
dB
dB
ISO
L
L
Figure 5
f = 1MHz% V
= 1V
COM_
V
R = 50 % C = 5pF%
-108
CT
L
L
Figure 6
NO_ or NC_ Off-Capacitance
COM_ Off-Capacitance
COM_ On-Capacitance
LOGIC INPUT
C
f = 1MHz% Figure 7
f = 1MHz% Figure 7
f = 1MHz% Figure 7
+25°C
+25°C
+25°C
20
20
40
pF
pF
pF
OFF
C
COM_(OFF)
C
COM_(ON)
Input Logic High
V
2.0
-1
V
V
IH
Input Logic Low
V
0.8
+1
IL
Input Leakage Current
SUPPLY
I
IN
V
= 0V or V+
IN_
+0.005
0.0001
µA
Power-Supply Range
V+
I+
2.0
11
1
V
V+ = +5.5V% V
all switches on or off
= 0V or V+%
IN_
Positive Supply Current
µA
_______________________________________________________________________________________
3
50 Dual SPST Analog Switches in UCSP
ELECTRICAL CHARACTERISTICS—Single +5V Supply
(V+ = +5V 10ꢀ% V = +2.0V% V = +0.8V% T = T
to T % unless otherwise noted. Typical values are at V+ = +5V% T = +25°C.)
MAX A
IH
IL
A
MIN
(Notes 3% 4)
PARAMETER
SYMBOL
CONDITIONS
T
MIN
TYP
MAX
UNITS
A
ANALOG SWITCH
V
%
COM_
% V
Analog Signal Range
0
V+
25
30
3
V
V
NO_ NC_
+25°C
to
8.5
0.2
2
V+ = +4.5V%
I = 5ꢁA%
COM_
On-Resistance
R
ON
T
MIN
V
or V
= +3.5V
NC_
NO_
T
MAX
+25°C
T to
MIN
V+ = +4.5V%
= 5ꢁA%
On-Resistance Matching
Between Channels (Notes 5% 6)
R
I
ON
COM_
4
V
or V
= +3.5V
NC_
NO_
T
MAX
+25°C
5
V+ = +4.5V%
= 5ꢁA%
On-Resistance Flatness
(Note 7)
R
I
FLAT(ON)
COM_
T
to
MIN
7
V
or V
= +1V% +2V% +3V
NC_
NO_
T
MAX
+25°C
-0.1
-2
+0.1
+2
+0.1
+2
+0.2
V+ = +5.5V%
NO_ or NC_ Off-Leakage Current
(Note 8)
I
I
NO_(OFF)
V
V
= +1V% +4.5V;
nA
nA
COM_
T
to
MIN
NC_(OFF)
or V
= +4.5V% +1V
= +4.5V% +1V
NC_
NO_
NC_
T
MAX
+25°C
-0.1
-2
V+ = +5.5V%
V
V
COM_ Off-Leakage Current
(Note 8)
I
= +1V% +4.5V;
COM_(OFF)
COM_
T
to
MIN
or V
NO_
T
MAX
+25°C
-0.2
V+ = +5.5V%
COM_ On-Leakage Current
(Note 8)
V
V
= +1V% +4.5V;
COM_
I
nA
COM_(ON)
T
T
to
MAX
MIN
or V
= +1V% +4.5V% or
NO_
NC_
-4
+4
floating
DYNAMIC CHARACTERISTICS
+25°C
to
47
23
25
85
95
45
55
V
or V
= +3.0V%
NO_
NC_
Turn-On Tiꢁe
t
ns
ns
ns
R = 300 % C = 35pF%
Figure 2
ON
L
L
T
MIN
T
MAX
+25°C
V
or V
= +3.0V%
NC_
NO_
Turn-Off Tiꢁe
t
R = 300 % C = 35pF%
Figure 2
OFF
L
L
T
MIN
to
T
MAX
+25°C
V
or V
= +3.0V%
NC_
NO_
Break-Before-Make
(MAX4733 Only% Note 8)
t
R = 300 % C = 35pF%
Figure 3
BBM
L
L
T
MIN
to
1
T
MAX
V
= 0V% R
= 0%
GEN
GEN
Charge Injection
Q
+25°C
+25°C
7.5
pC
C = 1.0nF% Figure 4
L
Signal = 0dBꢁ%
50 in and out
On-Channel Bandwidth
BW
300
MHz
f = 1MHz% V
= 1V
%
RMS
COM_
Off-Isolation (Note 9)
V
R = 50 % C = 5pF%
+25°C
-72
dB
ISO
L
L
Figure 5
4
_______________________________________________________________________________________
50 Dual SPST Analog Switches in UCSP
ELECTRICAL CHARACTERISTICS—Single +5V Supply
(V+ = +5V 10ꢀ% V = +2.0V% V = +0.8V% T = T
to T % unless otherwise noted. Typical values are at V+ = +5V% T = +25°C.)
MAX A
IH
IL
A
MIN
(Notes 3% 4)
PARAMETER
SYMBOL
CONDITIONS
f = 1MHz% V = 1V
T
MIN
TYP
MAX
UNITS
A
%
RMS
COM_
Crosstalk (Note 10)
V
R = 50 % C = 5pF%
+25°C
-108
dB
CT
L
L
Figure 6
NO_ or NC_ Off-Capacitance
COM_ Off-Capacitance
COM_ On-Capacitance
LOGIC INPUT
C
f = 1MHz% Figure 7
f = 1MHz% Figure 7
f = 1MHz% Figure 7
+25°C
+25°C
+25°C
20
20
40
pF
pF
pF
OFF
C
COM_(OFF)
C
COM_(ON)
Input Logic High
V
2.0
-1
V
V
IH
Input Logic Low
V
0.8
+1
IL
Input Leakage Current
SUPPLY
I
IN
V
= 0V or V+
IN_
+0.005
0.0001
µA
Power-Supply Range
V+
I+
2.0
11
1
V
V+ = +5.5V% V
all switches on or off
= 0V or V+%
IN_
Positive Supply Current
µA
Note 3: The algebraic convention% where the ꢁost negative value is a ꢁiniꢁuꢁ and the ꢁost positive value a ꢁaxiꢁuꢁ% is used
in this data sheet.
Note 4: UCSP parts are 100ꢀ tested at +25°C only% and guaranteed by design over teꢁperature. µMAX parts are 100ꢀ tested at
+85°C and +25°C and guaranteed by design over teꢁperature.
Note 5:
R
ON
= R
- R
.
ON(MAX)
ON(MIN)
Note 6: UCSP on-resistance ꢁatching between channels and on-resistance flatness guaranteed by design.
Note 7: Flatness is defined as the difference between the ꢁaxiꢁuꢁ and ꢁiniꢁuꢁ value of on-resistance as ꢁeasured over the
specified analog signal range.
Note 8: Guaranteed by design.
Note 9: Off-Isolation = 20 log (V
/V
)% V
= output% V
= input to off switch.
10 NO_ COM_
NO_
COM_
Note 10: Between any two switches.
_______________________________________________________________________________________
5
50 Dual SPST Analog Switches in UCSP
Typical Operating Characteristics
(T = +25°C% unless otherwise noted.)
A
ON-RESISTANCE
vs. V
(V+ = +3.0V)
ON-RESISTANCE vs. V
COM
COM
30
25
20
15
10
5
30
25
20
15
10
5
50
V+ = +2.0V
40
T = +85 C
A
T
= +85 C
A
30
V+ = +3.0V
20
V+ = +5.0V
T
= -40 C
A
V+ = +10.0V
T
= +25 C
T
= +25 C
A
A
10
0
T
= -40 C
2.5
A
0
0
0.5
1.0
V
1.5
2.0
3.0
0
0.5
1.0
V
1.5
(V)
2.0
2.5
0
2
4
6
8
10
(V)
COM
V
(V)
COM
COM
ON-RESISTANCE
ON/OFF-LEAKAGE CURRENT
vs. TEMPERATURE
vs. V
(V+ = +5.0V)
CHARGE INJECTION vs. V
COM
COM
20
16
12
8
1000
100
10
1
45
V+ = +5V
40
35
30
25
20
15
10
5
V+ = +5.0V
T
A
= +85 C
ON-LEAKAGE
V+ = +3.0V
T
= +25 C
A
4
OFF-LEAKAGE
T
= -40 C
4
A
0
0
0
0
1
2
3
5
-40
-20
0
20
40
60
80
0
1
2
3
4
5
V
(V)
TEMPERATURE ( C)
V
(V)
COM
COM
LOGIC THRESHOLD VOLTAGE
vs. SUPPLY VOLTAGE
TURN-ON/OFF TIME
vs. SUPPLY VOLTAGE
SUPPLY CURRENT vs. TEMPERATURE
3.0
2.5
2.0
1.5
1.0
0.5
0
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
120
100
80
60
40
20
0
V
IN
RISING OR
FALLING
V+ = +5V, +3V
t
ON
t
OFF
2
4
6
8
10
-40
-20
0
20
40
60
80
2
4
6
8
10
V+ (V)
TEMPERATURE ( C)
V+ (V)
6
_______________________________________________________________________________________
50 Dual SPST Analog Switches in UCSP
Typical Operating Characteristics (continued)
(T = +25°C% unless otherwise noted.)
A
TOTAL HARMONIC DISTORTION
vs. FREQUENCY
TURN-ON/OFF TIME
vs. TEMPERATURE
FREQUENCY RESPONSE
80
70
60
50
40
30
20
10
0
1
0.1
V
= 2V
P-P
COM
BW = 30kHz
0
-20
R = 1k
L
V+ = +3.0V
t
,
ON
V+ = +3.0V
ON-LOSS
t
,
ON
V+ = +5.0V
-40
R = 1k
L
V+ = +5.0V
OFF-ISOLATION
0.01
-60
R = 100k
L
V+ = +3.0V
-80
0.001
0.0001
CROSSTALK
-100
-120
R = 100k
L
V+ = +5.0V
t
,
OFF
V+ = +3.0V
t
,
OFF
V+ = +5.0V
40 60
TEMPERATURE ( C)
V+ = +3V
100M 1G
-40
-20
0
20
80
10
100
1k
10k
100k
10k
100k
1M
10M
FREQUENCY (Hz)
FREQUENCY (Hz)
Pin Description
PIN
MAX4732
UCSP µMAX
NAME
FUNCTION
MAX4731
µMAX
MAX4733
UCSP
A1
A2
A3
B1
B3
C1
C2
C3
—
UCSP
µMAX
1
2
—
A2
A3
B1
B3
C1
C2
—
—
2
A1
A2
A3
B1
B3
C1
C2
—
1
2
NO1
COM1
GND
IN1
Analog-Switch Norꢁally Open Terꢁinal
Analog-Switch Coꢁꢁon Terꢁinal
Ground. Connect to digital ground.
Logic-Control Digital Input
4
4
4
7
7
7
3
3
3
IN2
Logic-Control Digital Input
8
8
8
V+
Positive Supply Voltage Input
6
6
6
COM2
NO2
NC1
NC2
Analog-Switch Coꢁꢁon Terꢁinal
Analog-Switch Norꢁally Open Terꢁinal
Analog-Switch Norꢁally Closed Terꢁinal
Analog-Switch Norꢁally Closed Terꢁinal
5
—
1
—
—
5
—
—
A1
C3
—
—
5
C3
be driven rail-to-rail. For exaꢁple% with a +11V supply%
IN1 and IN2 should be driven low to 0V and high to
11V. With a +3.3V supply% IN1 and IN2 should be dri-
ven low to 0V and high to 3.3V. Driving IN1 and IN2 rail-
to-rail ꢁiniꢁizes power consuꢁption.
Applications Information
Operating Considerations for
High-Voltage Supply
The MAX4731/MAX4732/MAX4733 operate to +11V
with soꢁe precautions. The absolute ꢁaxiꢁuꢁ rating
for V+ is +12V (referenced to GND). When operating
near this region% bypass V+ with a ꢁiniꢁuꢁ 0.1µF
capacitor to ground as close to the IC as possible.
Analog Signal Levels
Analog signals that range over the entire supply volt-
age (GND to V+) pass with very little change in R
ON
(see Typical Operating Characteristics). The bidirec-
tional switches allow NO_% NC_% and COM_ connec-
tions to be used as either inputs or outputs.
Logic Levels
The MAX4731/MAX4732/MAX4733 are TTL coꢁpatible
when powered froꢁ a single +5V supply. When pow-
ered froꢁ other supply voltages% the logic inputs should
_______________________________________________________________________________________
7
50 Dual SPST Analog Switches in UCSP
Power-Supply Sequencing and
Overvoltage Protection
UCSP Reliability
The chip-scale package (UCSP) represents a unique
package that greatly reduces board space coꢁpared
to other packages. UCSP reliability is integrally linked
to the user’s asseꢁbly ꢁethods% circuit board ꢁaterial%
and usage environꢁent. The user should closely review
these areas when considering a UCSP. Perforꢁance
through Operation Life Test and Moisture Resistance is
equal to conventional package technology as the
wafer-fabrication process priꢁarily deterꢁines it.
However% this forꢁ factor ꢁay not perforꢁ equally to a
packaged product through traditional ꢁechanical relia-
bility tests.
CAUTION: Do not exceed the absolute maximum
ratings. Stresses beyond the listed ratings can
cause permanent damage to the devices.
Proper power-supply sequencing is recoꢁꢁended for
all CMOS devices. Always apply V+ before applying
analog signals% especially if the analog signal is not
current liꢁited. If this sequencing is not possible% and if
the analog inputs are not current liꢁited to <20ꢁA% add
a sꢁall-signal diode% D1% as shown in Figure 1. If the
analog signal can dip below GND% add D2. Adding
protection diodes reduces the analog signal range to a
diode drop (about 0.7V) below V+ (for D1)% and to a
diode drop above ground (for D2). Leakage is unaffect-
ed by adding the diodes. On-resistance increases
slightly at low supply voltages. Maxiꢁuꢁ supply volt-
age (V+) ꢁust not exceed +11V.
Mechanical stress perforꢁance is a greater considera-
tion for a UCSP. UCSP solder joint contact integrity
ꢁust be considered since the package is attached
through direct solder contact to the user’s PC board.
Testing done to characterize the UCSP reliability perfor-
ꢁance shows that it is capable of perforꢁing reliably
through environꢁental stresses. Results of environꢁen-
tal stress test and additional usage data and recoꢁ-
ꢁendations are detailed in the UCSP application note%
which can be found on Maxiꢁ’s website at
www.ꢁaxiꢁ-ic.coꢁ.
Adding protection diodes causes the logic thresholds to
be shifted relative to the power-supply rails. The ꢁost
significant shift occurs when using low supply voltages
(+5V or less). With a +5V supply% TTL coꢁpatibility is
not guaranteed when protection diodes are added.
Driving IN1 and IN2 all the way to the supply rails (i.e.%
to a diode drop higher than the V+ pin% or to a diode
drop lower than the GND pin) is always acceptable.
Protection diodes D1 and D2 also protect against soꢁe
overvoltage situations. Using the circuit in Figure 1% no
daꢁage results if the supply voltage is below the
absolute ꢁaxiꢁuꢁ rating (+12V) and if a fault voltage
up to the absolute ꢁaxiꢁuꢁ rating (V+ + 0.3V) is
applied to an analog signal terꢁinal.
Test Circuits/Timing Diagrams
V+
D1
EXTERNAL BLOCKING DIODE
MAX4731
MAX4732
MAX4733
UCSP Package Consideration
For general UCSP package inforꢁation and PC layout
considerations% please refer to the Maxiꢁ Application
Note% “Wafer-Level Chip-Scale Packages.”
V+
*
*
*
NO_
COM_
*
GND
EXTERNAL BLOCKING DIODE
D2
GND
*INTERNAL PROTECTION DIODES.
Figure 1. Overvoltage Protection Using External Blocking Diodes
_______________________________________________________________________________________
8
50 Dual SPST Analog Switches in UCSP
Test Circuits/Timing Diagrams (continued)
MAX4731
MAX4732
MAX4733
V+
t < 5ns
t < 5ns
f
r
V
IH
LOGIC
INPUT
50%
V+
COM_
NO_
OR NC_
V
IL
V
OUT
V
N_
C
R
L
L
300
t
OFF
35pF
IN_
V
OUT
0.9 x V
0.9 x V
OUT
OUT
SWITCH
OUTPUT
GND
LOGIC
INPUT
0V
t
ON
C INCLUDES FIXTURE AND STRAY CAPACITANCE.
L
LOGIC INPUT WAVEFORMS INVERTED FOR SWITCHES
THAT HAVE THE OPPOSITE LOGIC SENSE.
R
L
(
)
ON
V
OUT
= V
N_
R + R
L
Figure 2. Switching Time
V+
V+
t < 5ns
f
r
MAX4733
V+
0V
t < 5ns
LOGIC
INPUT
50%
V
OUT1
COM1
COM2
NO1
V
N_
V
OUT2
C
C
35pF
NC2
IN1
R
L1
SWITCH
L1
300
0.9 x V
0UT1
OUTPUT 1
R
L2
300
(V
)
0V
0V
OUT1
L2
35pF
IN2
LOGIC
INPUT
SWITCH
GND
0.9 x V
OUTPUT 2
OUT2
(V
)
OUT2
t
t
BBM
BBM
C INCLUDES FIXTURE AND STRAY CAPACITANCE.
L
Figure 3. Break-Before-Make Interval (MAX4733 only)
V+
V
OUT
MAX4731
MAX4732
MAX4733
V+
COM
V
OUT
R
GEN
NC_
OR NO_
V
OUT
IN
C
L
OFF
OFF
OFF
1nF
ON
V
GEN
GND
IN_
ON
V
OFF
IN
V
TO V
IH
Q = (
)(C )
L
IL
OUT
IN DEPENDS ON SWITCH CONFIGURATION;
INPUT POLARITY DETERMINED BY SENSE OF SWITCH.
Figure 4. Charge Injection
_______________________________________________________________________________________
9
50 Dual SPST Analog Switches in UCSP
Test Circuits/Timing Diagrams (continued)
V+
10nF
V+
V+
MAX4731
MAX4732
MAX4733
10nF
MAX4731
MAX4732
MAX4733
SIGNAL
GENERATOR 0dBm
SIGNAL
GENERATOR 0dBm
V+
COM1
50
COM_
NO1/NC1
IN2
IN1
V
IL
OR V
IH
IN_
0 OR 2.4V
ANALYZER
0 OR 2.4V
NC_
ANALYZER
COM2
OR NO_
NO2/NC2
N.C.
GND
V-
GND
V-
R
R
L
L
10nF
10nF
NOTE: DUAL SUPPLIES USED TO ACCOMODATE GROUND-REFERENCED INSTRUMENTS.
NOTE: DUAL SUPPLIES USED TO ACCOMODATE GROUND-REFERENCED INSTRUMENTS.
Figure 6. Crosstalk
Figure 5. Off-Isolation/On-Channel Bandwidth
V+
10nF
MAX4731
MAX4732
MAX4733
V+
COM_
Chip Information
TRANSITOR COUNT: 68
IN_
V
OR V
IH
IL
CAPACITANCE
METER
NC_ OR
NO_
PROCESS: CMOS
f = 1MHz
GND
Figure 7. Channel Off/On-Capacitance
Pin Configurations/Functional Diagrams/Truth Tables (continued)
TOP VIEW
MAX4731
MAX4732
MAX4733
NO1
COM1
IN2
NC1
COM1
IN2
1
2
3
4
8
7
6
5
8
7
6
5
NO1
COM1
IN2
8
7
6
5
V+
1
2
3
4
1
2
3
4
V+
V+
IN1
IN1
IN1
COM2
COM2
COM2
NC2
GND
GND
GND
NO2
NC2
MAX
MAX
MAX
10 ______________________________________________________________________________________
50 Dual SPST Analog Switches in UCSP
Package Information
(The package drawing(s) in this data sheet ꢁay not reflect the ꢁost current specifications. For the latest package outline inforꢁation%
go to www.maxim-ic.com/packages.)
______________________________________________________________________________________ 11
50 Dual SPST Analog Switches in UCSP
Package Information (continued)
(The package drawing(s) in this data sheet ꢁay not reflect the ꢁost current specifications. For the latest package outline inforꢁation%
go to www.maxim-ic.com/packages.)
4X S
8
8
MILLIMETERS
INCHES
DIM MIN
MAX
MAX
MIN
-
-
0.043
0.006
0.037
0.014
0.007
0.120
1.10
0.15
0.95
0.36
0.18
3.05
A
0.002
0.030
0.010
0.005
0.116
0.05
0.75
0.25
0.13
2.95
A1
A2
b
E
H
ÿ 0.50±0.1
c
D
e
0.0256 BSC
0.65 BSC
0.6±0.1
E
H
0.116
0.188
0.016
0∞
0.120
2.95
4.78
0.41
0∞
3.05
5.03
0.66
6∞
0.198
0.026
6∞
L
1
1
0.6±0.1
S
0.0207 BSC
0.5250 BSC
BOTTOM VIEW
D
TOP VIEW
A1
A2
A
c
e
L
b
SIDE VIEW
FRONT VIEW
PROPRIETARY INFORMATION
TITLE:
PACKAGE OUTLINE, 8L uMAX/uSOP
APPROVAL
DOCUMENT CONTROL NO.
REV.
1
21-0036
J
1
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
12 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2002 Maxiꢁ Integrated Products
Printed USA
is a registered tradeꢁark of Maxiꢁ Integrated Products.
相关型号:
MAX4732
50<img src=http://dbserv.maxim-ic.com/images/ohm.gif width=12 height=9 Dual SPST Analog Switches in UCSP
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