MAX4685EUB [MAXIM]
0.5 з/0.8 зLow-Voltage, Dual SPDT Analog Switches in UCSP; 0.5 з / 0.8 зLow电压，双路SPDT模拟开关，UCSP封装
| 型号： | MAX4685EUB |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | 0.5 з/0.8 зLow-Voltage, Dual SPDT Analog Switches in UCSP |
| 文件： | 总12页 (文件大小：335K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-1977; Rev 3; 2/03
0.5Ω/0.8Ω Low-Voltage, Dual SPDT
Analog Switches in UCSP
General Description
Features
✕ 12-Bump, 0.5mm-Pitch UCSP
The MAX4684/MAX4685 low on-resistance (R ), low-
ON
✕ NC Switch R
voltage, dual single-pole/double-throw (SPDT) analog
switches operate from a single +1.8V to +5.5V supply.
ON
0.5Ω max (+2.7V Supply) (MAX4684)
0.8Ω max (+2.7V Supply) (MAX4685)
The MAX4684 features a 0.5Ω (max) R
for its NC
ON
✕ NO Switch R
ON
switch and a 0.8Ω (max) R
for its NO switch at a
ON
0.8Ω max (+2.7V Supply)
+2.7V supply. The MAX4685 features a 0.8Ω max on-
resistance for both NO and NC switches at a +2.7V
supply.
✕ R
✕ R
Match Between Channels
0.06Ω (max)
Flatness Over Signal Range
ON
ON
Both parts feature break-before-make switching action
0.15Ω (max)
(2ns) with t
= 50ns and t
= 40ns at +3V. The digi-
ON
OFF
✕ +1.8V to +5.5V Single-Supply Operation
✕ Rail-to-Rail® Signal Handling
✕ 1.8V Logic Compatibility
tal logic inputs are 1.8V logic-compatible with a +2.7V to
+3.3V supply.
The MAX4684/MAX4685 are packaged in the chipscale
package (UCSP)™, significantly reducing the required
✕ Low Crosstalk: -68dB (100kHz)
✕ High Off-Isolation: -64dB (100kHz)
✕ THD: 0.03%
✕
PC board area. The chip occupies only a 2.0mm
✕
1.50mm area. The 4 3 array of solder bumps are
✕ 50nA (max) Supply Current
✕ Low Leakage Currents
spaced with a 0.5mm bump pitch.
1nA (max) at T = +25°C
A
Ordering Information
________________________Applications
Speaker Headset Switching
PIN/BUMP-
PACKAGE
TOP
MARK
PART
TEMP RANGE
-40°C to +85°C
-40°C to +85°C
MP3 Players
MAX4684EBC
MAX4684ETB
12 UCSP*
AAF
Power Routing
10 Thin QFN
(3 ✕ 3)
Battery-Operated Equipment
Relay Replacement
Audio and Video Signal Routing
Communications Circuits
PCMCIA Cards
AAG
MAX4684EUB
-40°C to +85°C
-40°C to +85°C
10 µMAX
12 UCSP*
—
MAX4685EBC
AAG
10 Thin QFN
(3 ✕ 3)
MAX4685ETB
MAX4685EUB
-40°C to +85°C
-40°C to +85°C
AAH
—
10 µMAX
Cellular Phones
Modems
Note: Requires special solder temperature profile describing
the Absolute Maximum Ratings section.
UCSP is a trademark of Maxim Integrated Products, Inc.
Rail-to-Rail is a registered trademark of Nippon Motorola, Ltd.
*UCSP reliability is integrally linked to the user’s assembly
methods, circuit board material, and environment. Refer to the
UCSP Reliability Notice in the UCSP Reliability section of this
data sheet for more information.
Pin Configurations/Functional Diagrams/Truth Table
TOP VIEW
MAX4684/MAX4685
MAX4684/MAX4685
GND
C1
C2
B1
A1
A2
NC1
IN1
NC2
IN2
1
2
3
4
5
10 NO2
V+
NO1
9
COM2
MAX4684/MAX4685
IN2
8
7
COM1
IN1
IN_
0
NO_
OFF
ON
NC_
ON
COM1 C3
A3 COM2
NC2
GND
NO1
C4
NO2
A4
1
OFF
B4
NC1
6
SWITCHES SHOWN FOR LOGIC "0" INPUT
V+
Continued at end of data sheet.
µMAX
UCSP
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
0.5Ω/0.8Ω Low-Voltage, Dual SPDT
Analog Switches in UCSP
ABSOLUTE MAXIMUM RATINGS
(All Voltages Referenced to GND)
Continuous Power Dissipation (T = +70°C)
A
V+, IN_......................................................................-0.3V to +6V
COM_, NO_, NC_ (Note1) ........................... -0.3V to (V+ + 0.3V)
Continuous Current NO_, NC_, COM_ .......................... 300mA
Peak Current NO_, NC_, COM_
(pulsed at 1ms, 50% duty cycle)................................. 400mA
Peak Current NO_, NC_, COM_
12-Bump UCSP (derate 11.4mW/°C above +70°C) ...909mW
10-Pin µMAX (derate 5.6mW/°C above +70°C)..........444mW
Operating Temperature Ranges..........................-40°C to +85°C
Storage Temperature Range.............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Bump Temperature (soldering) (Note 2)
(pulsed at 1ms, 10% duty cycle)................................. 500mA
Infared (15s)................................................................+220°C
Vapor Phase (60s) ......................................................+215°C
Note 1: Signals on NO_, NC_, and COM_ exceeding V+ or GND are clamped by internal diodes. Limit forward-diode current to
maximum current rating.
Note 2: This device is constructed using a unique set of packaging techniques that impose a limit on the thermal profile the device
can be exposed to during board level solder attach and rework. This limit permits only the use of the solder profiles recom-
mended in the industry-standard specification, JEDEC 020A, paragraph 7.6, Table 3 for IR/VPR and Convection reflow. Pre-
heating is required. Hand or wave soldering is not allowed.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS—+3V SUPPLY
(V+ = +2.7V to +3.3V, V = +1.4V, V = +0.5V, T = T
to T , unless otherwise noted. Typical values are at +3V and +25°C.)
MAX
IH
IL
A
MIN
(Notes 3, 9, 10)
PARAMETER
SYMBOL
CONDITIONS
T
MIN
TYP
MAX
UNITS
A
ANALOG SWITCH
V
_, V _,
NC
NO
V
Analog Signal Range
E
0
V+
V
_
COM
+25°C
0.3
0.5
0.5
0.8
0.8
0.8
0.8
MAX4684
MAX4685
E
+25°C
E
NC_ On-Resistance
(Note 4)
V+ = 2.7V; I
_ = 100mA;
COM
R
Ω
ON(NC)
ON(NO)
V
_= 0 to V+
NC
0.45
0.45
+25°C
E
NO_ On-Resistance
(Note 4)
V+ = 2.7V; I
_ = 100mA;
COM
R
Ω
Ω
V
_ = 0 to V+
NO
On-Resistance Match
Between Channels
(Notes 4, 5)
+25°C
0.06
V+= 2.7V; I
_ = 100mA;
COM
∆R
ON
V
_or V _ = 1.5V
NC
NO
E
E
E
0.06
0.15
0.35
MAX4684
MAX4685
NC_ On-Resistance
Flatness (Note 6)
V+ = 2.7V; I
= 100mA;
COM
R
Ω
Ω
FLAT (NC)
V _ = 0 to V+
NC
NO_ On-Resistance
Flatness (Note 6)
V+ = 2.7V; I
= 100mA;
COM
R
E
+25°C
E
0.35
1
FLAT (NO)
V
_= 0 to V+
NO
-1
NO_ or NC_ Off-
Leakage Current
(Note 7)
I
_(OFF) or
V+ = 3.3V; V _ or V _ = 3V, 0.3V;
NO NC
NO
nA
nA
I
_(OFF)
V
_ = 0.3V, 3V
COM
NC
-10
10
+25°C
-2
2
COM_ On-Leakage
Current (Note 7)
V+ = 3.3V; V _ or V _ = 3V, 0.3V, or
NO NC
I
_(ON)
COM
floating; V
_ = 3V, 0.3V, or floating
COM
E
-20
20
DYNAMIC CHARACTERISTICS
Turn-On Time
+25°C
30
50
60
V+ = 2.7V, V _ or V _ = 1.5V;
NO
NC
t
ns
ON
R = 50Ω; C = 35pF; Figure 2
L
L
E
2
_______________________________________________________________________________________
0.5Ω/0.8Ω Low-Voltage, Dual SPDT
Analog Switches in UCSP
ELECTRICAL CHARACTERISTICS—+3V SUPPLY (continued)
(V+ = +2.7V to +3.3V, V = +1.4V, V = +0.5V, T = T
to T , unless otherwise noted. Typical values are at +3V and +25°C.)
MAX
IH
IL
A
MIN
(Notes 3, 9, 10)
PARAMETER
UNITS
SYMBOL
CONDITIONS
V+ = 2.7V, V _ or V _ = 1.5V;
T
MIN
TYP
MAX
30
A
+25°C
25
NO
NC
Turn-Off Time
t
ns
OFF
R = 50Ω; C = 35pF; Figure 2
L
L
E
40
Break-Before-Make
Delay
V+ = 2.7V, V _, or V _ = 1.5V;
NO NC
t
E
2
15
200
-64
ns
pC
dB
BBM
R = 50Ω; C = 35pF; Figure 3
L
L
Charge Injection
Q
COM_ = 0; R = 0; C = 1nF; Figure 4
+25°C
+25°C
S
L
C = 5pF; R = 50Ω; f = 100kHz;
L
L
Off-Isolation (Note 8)
V
ISO
V
_ = 1V
COM
; Figure 5
RMS
C = 5pF; R = 50Ω; f = 100kHz;
L
L
Crosstalk
V
+25°C
+25°C
-68
dB
%
CT
V
_ = 1V
COM
; Figure 5
RMS
Total Harmonic
Distortion
R = 600Ω, IN_ = 2Vp-p, f = 20Hz to
L
THD
0.03
20kHz
NC_ Off-Capacitance
NO_ Off-Capacitance
NC_ On-Capacitance
NO_ On-Capacitance
DIGITAL I/O
C
C
f = 1MHz; Figure 6
f = 1MHz; Figure 6
f = 1MHz; Figure 6
f = 1MHz; Figure 6
+25°C
+25°C
+25°C
+25°C
84
37
pF
pF
pF
pF
NC_(OFF)
NO_(OFF)
C
190
150
NC_(ON)
NO_(ON)
C
Input Logic High
V
V
E
E
1.4
-1
V
V
IH
IL
Input Logic Low
0.5
1
IN_ Input Leakage
Current
I
IN
_
V
_ = 0 or V+
IN
E
µA
POWER SUPPLY
Power-Supply Range
V+
I+
E
+25°C
E
1.8
-50
5.5
50
V
0.04
Supply Current (Note 4)
V+= 5.5V; V _ = 0 or V+
nA
IN
-200
200
Note 3: The algebraic convention used in this data sheet is where the most negative value is a minimum and the most positive
value a maximum.
Note 4: Guaranteed by design.
Note 5: ∆R
= R
- R
, between NC1 and NC2 or between NO1 and NO2.
ON(MIN)
ON
ON(MAX)
Note 6: Flatness is defined as the difference between the maximum and minimum value of on-resistance as measured over the
specified analog signal ranges.
Note 7: Leakage parameters are 100% tested at T = +85°C, and guaranteed by correlation over rated temperature range.
A
Note 8: Off-isolation = 20log (V
/ V ), V
NO
= output, V
= input to off switch.
10 COM
COM
NO
Note 9: UCSP and QFN parts are 100% tested at +25°C only and guaranteed by design and correlation at the full hot-rated
temperature.
Note 10: -40°C specifications are guaranteed by design.
_______________________________________________________________________________________
3
0.5Ω/0.8Ω Low-Voltage, Dual SPDT
Analog Switches in UCSP
Typical Operating Characteristics
(T = +25°C, unless otherwise noted.)
A
MAX4684
MAX4685
NC ON-RESISTANCE vs. COM VOLTAGE
NC ON-RESISTANCE vs. COM VOLTAGE
NO ON-RESISTANCE vs. COM VOLTAGE
1.8
2.0
1.8
2.5
2.0
1.5
1.0
0.5
0
V+ = +1.8V
V+ = +2.0V
1.6
V+ = +1.8V
V+ = +1.8V
1.6
1.4
1.2
1.4
1.2
V+ = +2.0V
1.0
0.8
0.6
0.4
0.2
0
V+ = +2.0V
V+ = +2.3V
V+ = +5.0V
1.0
0.8
0.6
0.4
0.2
0
V+ = +2.3V
V+ = +2.5V
V+ = +2.3V
V+ = +2.5V
V+ = +2.5V
V+ = +3.0V
V+ = +5.0V
V+ = +3.0V
V+ = +5.0V
V+ = +3.0V
0
1
2
3
4
5
0
1
2
3
4
5
0
1
2
3
4
5
V
(V)
V
(V)
V
(V)
COM
COM
COM
MAX4684
MAX4685
NC ON-RESISTANCE vs. COM VOLTAGE
NC ON-RESISTANCE vs. COM VOLTAGE
NO ON-RESISTANCE vs. COM VOLTAGE
0.45
0.40
0.35
0.30
0.25
0.20
0.15
0.28
0.26
0.40
V+ = +5V
V+ = +5V
V+ = +5V
0.35
0.30
0.25
0.20
0.15
0.10
0.24
0.22
0.20
0.18
0.16
0.14
0.12
T = +85°C
A
T = +85°C
A
T = +85°C
A
T = +25°C
A
T = +25°C
A
T = +25°C
A
T = -40°C
A
T = -40°C
A
T = -40°C
A
0.10
0.10
0
1
2
3
4
5
0
1
2
3
4
5
0
1
2
3
4
5
V
(V)
V
(V)
V
(V)
COM
COM
COM
MAX4684
MAX4684
NC ON-RESISTANCE vs. COM VOLTAGE
NC ON-RESISTANCE vs. COM VOLTAGE
NO ON-RESISTANCE vs. COM VOLTAGE
0.35
0.30
0.25
0.20
0.15
0.10
0.50
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
V+ = +3V
V+ = +3V
0.45
0.40
0.35
V+ = +1.8V
T = +85°C
A
T = +85°C
A
T = +25°C
A
V+ = +2.0V
V+ = +2.3V
V+ = +5.0V
0.30
0.25
0.20
0.15
0.10
V+ = +2.5V
T = +25°C
A
T = -40°C
A
T = -40°C
A
V+ = +3.0V
0
0.5
1.0
1.5
2.0
2.5
3.0
0
1
2
3
4
5
0
0.5
1.0
1.5
2.0
(V)
2.5
3.0
V
(V)
V
(V)
V
COM
COM
COM
4
_______________________________________________________________________________________
0.5Ω/0.8Ω Low-Voltage, Dual SPDT
Analog Switches in UCSP
Typical Operating Characteristics (continued)
(T = +25°C, unless otherwise noted.)
A
TURN-ON/TURN-0FF TIMES
vs. SUPPLY VOLTAGE
TURN-ON/TURN-0FF TIMES
vs. TEMPERATURE
SUPPLY CURRENT vs. SUPPLY VOLTAGE
50
45
40
35
30
25
20
15
10
5
80
70
60
50
100
V+ = +3V
80
60
40
20
0
t
ON
t
ON
40
30
t
OFF
20
10
0
t
OFF
0
1.8 2.3 2.8 3.3 3.8 4.3 4.8 5.3
(V)
0
1
2
3
4
5
6
-40
-15
10
35
60
85
V
V
(V)
TEMPERATURE (°C)
SUPPLY
SUPPLY
MAX4684
ON/OFF-LEAKAGE CURRENT
vs. TEMPERATURE
LOGIC THRESHOLD VOLTAGE
vs. SUPPLY VOLTAGE
CHARGE INJECTION vs. COM VOLTAGE
2.0
1.5
1.0
0.5
0
1000
100
10
300
200
100
0
V
RISING
IN
-100
-200
-300
-400
-500
V
FALLING
IN
I
COM(ON)
I
COM(OFF)
60
1
0
1
2
3
4
5
6
-40
-15
10
35
85
0
1
2
3
4
5
6
V
(V)
TEMPERATURE (°C)
SUPPLY
V
(V)
COM
MAX4685
ON/OFF-LEAKAGE CURRENT
vs. TEMPERATURE
TOTAL HARMONIC DISTORTION
PLUS NOISE vs. FREQUENCY
FREQUENCY RESPONSE (µMAX)
0.1
0
1000
100
10
ON-
RESPONSE
-20
OFF-
ISOLATION
-40
-60
I
COM(ON)
CROSSTALK
-80
I
COM(OFF)
60
-100
-120
0.01
1
10
100
1k
10k
100k
-40
-15
10
35
85
0.001
0.01
0.1
1
10
100
FREQUENCY (Hz)
TEMPERATURE (°C)
FREQUENCY (MHz)
_______________________________________________________________________________________
5
0.5Ω/0.8Ω Low-Voltage, Dual SPDT
Analog Switches in UCSP
Pin Description
PIN
NAME
FUNCTION
UCSP
A1, C1
A2, C2
A3, C3
A4, C4
B4
µMAX
5, 7
4, 8
3, 9
2, 10
1
NC_
IN_
Analog Switch—Normally Closed Terminal
Digital Control Input
COM_
NO_
V+
Analog Switch—Common Terminal
Analog Switch—Normally Open Terminal
Positive Supply Voltage Input
Ground
GND
B1
6
Power-Supply Sequencing and
Overvoltage Protection
Detailed Description
The MAX4684/MAX4685 are low on-resistance, low-
voltage, dual SPDT analog switches that operate from a
+1.8V to +5.5V supply. The devices are fully specified
for nominal 3V applications. The MAX4684/MAX4685
have break-before-make switching and fast switching
Caution: Do not exceed the absolute maximum rat-
ings because stresses beyond the listed ratings
may cause permanent damage to devices.
Proper power-supply sequencing is recommended for
all CMOS devices. Always apply V+ before applying
analog signals, especially if the analog signal is not
current limited. If this sequencing is not possible, and if
the analog inputs are not current limited to <20mA, add
a small signal diode (D1) as shown in Figure 1. Adding
a protection diode reduces the analog range to a diode
speeds (t
= 50ns max, t
= 40ns max).
OFF
ON
The MAX4684 offers asymmetrical normally closed
(NC) and normally open (NO) R for applications that
ON
require asymmetrical loads (examples include speaker
headsets and internal speakers). The part features a
0.5Ω max R
for its NC switch and a 0.8Ω max RON
ON
drop (about 0.7V) below V+ (for D1). R
increases
ON
for its NO switch at the 2.7V supply. The MAX4685 fea-
tures a 0.8Ω max on-resistance for both NO and NC
switches at the +2.7V supply.
slightly at low supply voltages. Maximum supply volt-
age (V+) must not exceed +6V. Protection diode D1
also protects against some overvoltage situations. No
damage will result on Figure 1’s circuit if the supply
voltage is below the absolute maximum rating applied
to an analog signal pin.
Applications Information
Digital Control Inputs
The MAX4684/MAX4685 logic inputs accept up to
+5.5V regardless of supply voltage. For example, with
a +3.3V supply, IN_ may be driven low to GND and
high to 5.5V. Driving IN_ rail-to-rail minimizes power
consumption. Logic levels for a +1.8V supply are 0.5V
(low) and 1.4V (high).
POSITIVE SUPPLY
D1
V+
MAX4684
MAX4685
Analog Signal Levels
Analog signals that range over the entire supply volt-
age (V+ to GND) are passed with very little change in
on-resistance (see Typical Operating Characteristics).
The switches are bidirectional, so the NO_, NC_, and
COM_ pins can be either inputs or outputs.
NO
COM
V
g
GND
Figure 1. Overvoltage Protection Using Two External Blocking
Diodes
6
_______________________________________________________________________________________
0.5Ω/0.8Ω Low-Voltage, Dual SPDT
Analog Switches in UCSP
Mechanical stress performance is a greater considera-
tion for a UCSP package. UCSPs are attached through
direct solder contact to the user’s PC board, foregoing
the inherent stress relief of a packaged product lead
frame. Solder joint contact integrity must be consid-
ered. Information on Maxim’s qualification plan, test
data, and recommendations are detailed in the UCSP
application note, which can be found on Maxim’s web-
site at www.maxim-ic.com.
UCSP Package Consideration
For general UCSP package information and PC layout
considerations, please refer to the Maxim Application
Note (Wafer-Level Ultra-Chip-Board-Scale Package).
UCSP Reliability
The chip-scale package (UCSP) represents a unique
packaging form factor that may not perform equally to a
packaged product through traditional mechanical relia-
bility tests. UCSP reliability is integrally linked to the
user’s assembly methods, circuit board material, and
usage environment. The user should closely review
these areas when considering use of a UCSP package.
Performance through Operating Life Test and Moisture
Resistance remains uncompromised as it is primarily
determined by the wafer-fabrication process.
Chip Information
TRANSISTOR COUNT: 198
Test Circuits/Timing Diagrams
MAX4684
MAX4685
V+
t < 5ns
t < 5ns
f
r
V
IH
LOGIC
INPUT
50%
V+
COM_
V
IL
NO_
V
IN_
V
OUT
OR NC
R
50Ω
C
35pF
L
L
t
OFF
IN_
V
OUT
0.9 x V
0.9 x V
OUT
0UT
GND
LOGIC
INPUT
SWITCH
OUTPUT
0
t
ON
C INCLUDES FIXTURE AND STRAY CAPACITANCE.
L
LOGIC INPUT WAVEFORMS INVERTED FOR SWITCHES
THAT HAVE THE OPPOSITE LOGIC SENSE.
R
L
V
OUT
= V
N_
(
)
R + R
L
ON
Figure 2. Switching Time
V+
V+
MAX4684
MAX4685
V
IH
LOGIC
INPUT
50%
V
IL
NC_
NO_
V
V
OUT
N_
COM_
R
50Ω
L
C
35pF
L
IN_
LOGIC
INPUT
GND
0.9 x V
OUT
V
OUT
t
D
C INCLUDES FIXTURE AND STRAY CAPACITANCE.
L
Figure 3. Break-Before-Make Interval
_______________________________________________________________________________________
7
0.5Ω/0.8Ω Low-Voltage, Dual SPDT
Analog Switches in UCSP
Test Circuits/Timing Diagrams (continued)
V+
∆V
OUT
MAX4684
MAX4685
V+
V
OUT
R
GEN
COM_
NC_
V
OUT
IN
OR NO_
OFF
OFF
OFF
OFF
C
L
ON
V
GEN
GND
IN_
ON
IN
V
TO V
IH
Q = (∆V )(C )
IL
OUT
L
IN DEPENDS ON SWITCH CONFIGURATION;
INPUT POLARITY DETERMINED BY SENSE OF SWITCH.
Figure 4. Charge Injection
+5V 10nF
V+
V
V
OUT
OFF-ISOLATION = 20log
ON-LOSS = 20log
V
IN
NETWORK
ANALYZER
50Ω
50Ω
OUT
V
V
0V OR V+
IN
IN_
V
IN
COM
V
OUT
MAX4684
MAX4685
CROSSTALK = 20log
NC_
V
IN
MEAS
REF
OUT
NO
50Ω
GND
50Ω
50Ω
MEASUREMENTS ARE STANDARDIZED AGAINST SHORTS AT IC TERMINALS.
OFF-ISOLATION IS MEASURED BETWEEN COM_ AND "OFF" NO_ OR NC_ TERMINAL ON EACH SWITCH.
ON-LOSS IS MEASURED BETWEEN COM_ AND "ON" NO_ OR NC_ TERMINAL ON EACH SWITCH.
CROSSTALK IS MEASURED FROM ONE CHANNEL TO ALL OTHER CHANNELS.
SIGNAL DIRECTION THROUGH SWITCH IS REVERSED; WORST VALUES ARE RECORDED.
Figure 5. On-Loss, Off-Isolation, and Crosstalk
Pin Configurations (continued)
V+
10nF
TOP VIEW
MAX4684/MAX4685
V+
COM_
MAX4684
MAX4685
V+
NO1
1
2
3
4
5
NO2
COM2
IN2
10
9
V
IL
IN
OR
CAPACITANCE
METER
V
IH
NC_ or
NO_
8
7
6
COM1
IN1
NC2
GND
f = 1MHz
GND
NC1
✕
3
3 THIN QFN
Figure 6. Channel Off/On-Capacitance
8
_______________________________________________________________________________________
0.5Ω/0.8Ω Low-Voltage, Dual SPDT
Analog Switches in UCSP
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
_______________________________________________________________________________________
9
0.5Ω/0.8Ω Low-Voltage, Dual SPDT
Analog Switches in UCSP
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
e
4X S
10
10
INCHES
MAX
MILLIMETERS
MAX
1.10
0.15
0.95
3.05
3.00
3.05
3.00
5.05
0.70
DIM MIN
MIN
-
A
-
0.043
0.006
0.037
0.120
0.118
0.120
0.118
0.199
A1
A2
D1
D2
E1
E2
H
0.002
0.030
0.116
0.114
0.116
0.114
0.187
0.05
0.75
2.95
2.89
2.95
2.89
4.75
0.40
H
ÿ 0.50 0.1
0.6 0.1
L
0.0157 0.0275
0.037 REF
L1
b
0.940 REF
0.007
0.0106
0.177
0.270
0.200
1
1
e
0.0197 BSC
0.500 BSC
0.6 0.1
c
0.0035 0.0078
0.0196 REF
0.090
BOTTOM VIEW
0.498 REF
S
α
TOP VIEW
0∞
6∞
0∞
6∞
D2
E2
GAGE PLANE
A2
c
A
E1
b
L
α
A1
D1
L1
FRONT VIEW
SIDE VIEW
PROPRIETARY INFORMATION
TITLE:
PACKAGE OUTLINE, 10L uMAX/uSOP
APPROVAL
DOCUMENT CONTROL NO.
REV.
1
21-0061
I
1
10 ______________________________________________________________________________________
0.5Ω/0.8Ω Low-Voltage, Dual SPDT
Analog Switches in UCSP
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
L
A
D2
D
A2
PIN 1 ID
1
N
1
C0.35
b
[(N/2)-1] x e
REF.
E
E2
PIN 1
INDEX
AREA
DETAIL A
e
k
A1
C
L
C
L
L
L
e
e
A
DALLAS
SEMICONDUCTOR
PROPRIETARY INFORMATION
TITLE:
PACKAGE OUTLINE, 6, 8 & 10L,
TDFN, EXPOSED PAD, 3x3x0.80 mm
APPROVAL
DOCUMENT CONTROL NO.
REV.
NUMBER OF LEADS SHOWN ARE FOR REFERENCE ONLY
1
2
21-0137
D
______________________________________________________________________________________ 11
0.5Ω/0.8Ω Low-Voltage, Dual SPDT
Analog Switches in UCSP
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
COMMON DIMENSIONS
SYMBOL
MIN.
0.70
2.90
2.90
0.00
0.20
MAX.
0.80
3.10
3.10
0.05
0.40
A
D
E
A1
L
k
0.25 MIN.
0.20 REF.
A2
PACKAGE VARIATIONS
PKG. CODE
T633-1
N
6
D2
E2
e
JEDEC SPEC
MO229 / WEEA
MO229 / WEEC
b
[(N/2)-1] x e
1.90 REF
1.95 REF
2.00 REF
1.50 0.10 2.30 0.10 0.95 BSC
1.50 0.10 2.30 0.10 0.65 BSC
0.40 0.05
0.30 0.05
T833-1
8
T1033-1
10
1.50 0.10 2.30 0.10 0.50 BSC MO229 / WEED-3 0.25 0.05
DALLAS
SEMICONDUCTOR
PROPRIETARY INFORMATION
TITLE:
PACKAGE OUTLINE, 6, 8 & 10L,
TDFN, EXPOSED PAD, 3x3x0.80 mm
APPROVAL
DOCUMENT CONTROL NO.
REV.
2
2
21-0137
D
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
12 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2003 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
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