MAX3971A_V01 [MAXIM]
3.3V, 10.7Gbps Limiting Amplifier;
| 型号： | MAX3971A_V01 |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | 3.3V, 10.7Gbps Limiting Amplifier |
| 文件： | 总9页 (文件大小：454K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-2391; Rev 2; 2/07
+3.3V, 10.7Gbps Limiting Amplifier
MX3971A
General Description
Features
The MAX3971A is a compact 10.7Gbps limiting amplifier.
It accepts signals over a wide range of input voltage levels
and provides constant-level output voltages with con-
trolled edge speeds. It functions as a data quantizer with
♦ Single +3.3V Power Supply
♦ 2mV Input Sensitivity
♦ 1.8ps Typical Deterministic Jitter (V = 800mV
♦ Dice and 4mm × 4mm QFN or Thin QFN Package
Available
♦ Output Disable Feature
P-P
)
IN
P-P
a 240mV
differential CML output signal with a 100Ω dif-
P-P
ferential termination. The MAX3971A has a disable func-
tion that allows the outputs to be squelched if required by
the application.
The MAX3971A is designed to work with the MAX3970
transimpedance amplifier (TIA). The limiting amplifier
operates on a single +3.3V supply and functions over a
0°C to +85°C temperature range.
The MAX3971A is offered in die form and in a compact
4mm × 4mm 20-pin QFN and thin QFN package.
Ordering Information
Applications
PKG
TEMP RANGE PIN-PACKAGE
CODE
PART
VSR OC-192 Receivers
G2044-4
T2044-3
T2044-3
—
MAX3971AUGP
MAX3971AUTP
0°C to +85°C 20 QFN-EP*
10Gbps Ethernet Optical Receivers
10Gbps Fibre Channel Receivers
0°C to +85°C 20 Thin QFN-EP*
MAX3971AUTP+ 0°C to +85°C 20 Thin QFN-EP*
MAX3971AU/D
0°C to +85°C Dice**
*EP = Exposed pad.
**Dice are designed to operate over a 0°C to +110°C junction-
temperature (T ) range, but are tested and guaranteed at
J
T
= +25°C.
A
Pin Configurations appear at end of data sheet.
+Denotes lead-free package.
Typical Application Circuit
+3.3V
0.1μF
SUPPLY FILTER
+3.3V
CZ-
CZ+
V
CC1
V
V
CC2 CC3
GNDIN+
IN+
0.1μF
0.1μF
0.1μF
50Ω
50Ω
OUT+
OUT-
TIA
100Ω
0.1μF
IN-
GNDIN-
MAX3970
MAX3971A
DISABLE
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
+3.3V, 10.7Gbps Limiting Amplifier
ABSOLUTE MAXIMUM RATINGS
Voltage at IN+, IN-, DISABLE, CZ+, CZ-,
OUT+, OUT-.........................................+0.5V to (V
Differential Voltage Between CZ+ and CZ- ........................... 1V
Supply Voltage, V
, V
, V
......................-0.5V to +5.0 V
Operating Ambient Temperature Range.............-40°C to +85°C
Storage Temperature Range.............................-55°C to +150°C
Die Attach Temperature...................................................+400°C
Lead Temperature (soldering, 10s) .................................+300°C
CC1 CC2 CC3
+ 0.5V)
CC
Differential Voltage Between IN+ and IN-........................... 2.5V
Continuous Power Dissipation (T = +85°C)
A
20-Pin QFN (derate 20mW/°C above +85°C) .................1.3W
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
MX3971A
ELECTRICAL CHARACTERISTICS
(V
= +3.0V to +3.6V, output load = 50Ω to V , T = 0°C to +85°C, unless otherwise noted. All AC parameters are measured with
CC A
CC
23
a 2 - 1 PRBS pattern applied to the input at 10.7Gbps. Typical values are at V
= +3.3V, T = +25°C, unless otherwise noted.)
A
CC
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
50
10
2
MAX
UNITS
mA
Supply Current
I
85
CC
Small-Signal Bandwidth
Input Sensitivity
BW
GHz
V
(Notes 1, 2)
(Note 1)
5
mV
mV
IN-min
IN-max
P-P
P-P
Input Overload
V
1200
Low-Frequency Cutoff
CZ = 0.1µF (Note 1)
5mV input (Notes 1, 3)
60
5.2
3.5
1.8
1.9
0.6
20
75
16.0
14.0
7.0
kHz
P-P
10mV
input (Notes 1, 3)
P-P
Deterministic Jitter
ps
800mV
input (Notes 1, 3)
P-P
1200mV
input (Notes 1, 3)
11.0
1.1
P-P
Random Jitter
20mV
< input < 1200mV (Notes 1, 4)
ps
P-P
P-P
RMS
Transition Time
t , t
r
20% to 80%, differential output (Note 1)
Single ended
30
ps
f
Data Input Impedance
42
50
58
Ω
Differential signal amplitude between
OUT+ and OUT-
Data Output-Voltage Swing
190
240
400
50
mV
P-P
Data Output Voltage when
Disabled
Differential signal amplitude
between OUT+ and OUT-
0.25
mV
P-P
Data Output Common-Mode
Voltage
V
-
CC
75
mV
Data Output Impedance
Single ended
42
2
50
75
30
58
200
60
Ω
Data Output Offset when
DISABLE is High
mV
Disable Input Current
DISABLE High Voltage
DISABLE Low Voltage
Disable Response Time
µA
V
V
IH
V
0.8
V
IL
20
ns
Note 1: Guaranteed by design and characterization.
✕
Note 2: The output signal amplitude at the sensitivity is > .95 the amplitude with large input.
Note 3: Deterministic jitter is measured with K28.5 pattern (0011 1110 1011 0000 0101) at 10.7Gbps. It is the peak-to-peak devia-
tion from the ideal time crossing, measured at the zero-level crossing of the differential output.
-12
✕
Note 4: For a bit-error rate of 10 , the peak-to-peak random jitter is 14.1 the RMS random jitter.
2
_______________________________________________________________________________________
+3.3V, 10.7Gbps Limiting Amplifier
MX3971A
Typical Operating Characteristics
(V
CC
= +3.3V, output load = 50Ω to V , T = +25°C, unless otherwise noted.)
CC
A
OUTPUT EYE DIAGRAM
OUTPUT EYE DIAGRAM
OUTPUT EYE DIAGRAM
(INPUT SIGNAL = 10mV , AT 10.7Gbps)
(INPUT SIGNAL = 5mV , AT 10.3Gbps)
P-P
P-P
(INPUT SIGNAL = 1200mV , AT 10.3Gbps)
P-P
23
23
23
2
- 1PRBS
2
- 1PRBS
2
- 1PRBS
45mV/div
45mV/div
45mV/div
20ps/div
20ps/div
20ps/div
OUTPUT EYE DIAGRAM
SUPPLY CURRENT
vs. AMBIENT TEMPERATURE
(INPUT SIGNAL = 800mV , AT 10.7Gbps)
SMALL-SIGNAL GAIN
P-P
60
58
56
54
52
50
48
46
44
42
40
50
23
2
- 1PRBS
45
40
35
30
25
20
15
10
5
MAX3971A UGP
45mV/div
0
20ps/div
0
10 20 30 40 50 60 70 80
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
TEMPERATURE (°C)
FREQUENCY (GHz)
DETERMINISTIC JITTER
vs. INPUT AMPLITUDE
OUTPUT VOLTAGE vs. INPUT VOLTAGE
RANDOM JITTER vs. INPUT AMPLITUDE
6
5
4
3
2
1
0
270
250
230
210
190
170
150
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
10.7Gbps, K28.5,
V
CC
= +3V, TEMP = 85°C
1
10
100
1000
10,000
0
1
2
3
4
5
6
1
10
100
1000
10,000
INPUT AMPLITUDE (mV
)
V
IN
(mV
P-P
)
INPUT AMPLITUDE (mV
)
P-P
P-P
_______________________________________________________________________________________
3
+3.3V, 10.7Gbps Limiting Amplifier
Typical Operating Characteristics (continued)
(V
CC
= +3.3V, output load = 50Ω to V , T = +25°C, unless otherwise noted.)
CC
A
DETERMINISTIC JITTER
vs. TEMPERATURE
INPUT RETURN LOSS (S11)
(V = +3.3V)
OUTPUT RETURN LOSS (S22)
(V = +3.3V)
CC
CC
7
6
5
4
3
2
1
0
0
-5
0
-5
10.7Gbps with K28.5
MAX3971A
V
= 5mV
IN
-10
-15
-20
-25
-30
-35
-40
-45
-10
-15
-20
-25
-30
MX3971A
MAX3971A
V
= 800mV
IN
0
10 20 30 40 50 60 70 80
0
1
2
3
4
5
6
7
8
9
10
0
1
2
3
4
5
6
7
8
9
10
AMBIENT TEMPERATURE (°C)
FREQUENCY (GHz)
FREQUENCY (GHz)
POWER-SUPPLY REJECTION RATIO
vs. FREQUENCY
OUTPUT NOISE POWER
(INPUT CONNECTED TO 50Ω TO GND)
INPUT COMMON-MODE REJECTION
RATIO vs. FREQUENCY
45
40
35
30
70
65
60
55
50
45
40
-19.0
-19.1
-19.2
-19.3
-19.4
-19.5
-19.6
V
IN
= V = V
IN+
IN-
PSRR = -20log ΔV /ΔV
CMRR = -20log(V /V
)
OUT
CC
OUT IN
10k
100k
1M
FREQUENCY (Hz)
10M
100M
100
1M
10M
100M
1G
10G
0
10 20 30 40 50 60 70 80
TEMPERATURE (°C)
FREQUENCY (Hz)
4
_______________________________________________________________________________________
+3.3V, 10.7Gbps Limiting Amplifier
MX3971A
Pin Description
PIN
NAME
GNDIN+
IN+
FUNCTION
Input Ground for Shielding Input Signal IN+. Not connected internally.
Noninverting Input Signal
1
2
3
4
IN-
Inverting Input Signal
GNDIN-
N.C.
Input Ground for Shielding Input Signal IN-. Not connected internally.
No Connection. Leave unconnected.
Ground
5, 7, 9, 10
6, 8, 11
12, 15
13
GND
V
CC3
Output Circuitry Power Supply
OUT-
Inverting Output of Amplifier
14
OUT+
Noninverting Output of Amplifier
When DISABLE is connected to V or left floating, outputs are disabled. When DISABLE is
CC
connected to GND, outputs are enabled.
16
17
18
DISABLE
V
CC2
Power Supply to Circuitry other than Input and Output Circuits
Filter Capacitor for Offset Correction. Connect CZ between pin 18 and pin 19. See the Detailed
Description section.
CZ+
CZ-
Filter Capacitor for Offset Correction. Connect CZ between pin 18 and pin 19. See the Detailed
Description section.
19
20
—
V
Input Circuitry Power Supply
CC1
EP
Exposed Pad. Must be soldered to supply ground for proper electrical and thermal operation.
Gain Stage and Offset Correction
Detailed Description and
Applications Information
Figure 1 is a functional diagram of the MAX3971A limit-
ing amplifier. The signal path consists of an input buffer
followed by a gain stage and output amplifier. A feed-
back loop provides offset correction by driving the
average value of the differential output to zero.
The limiting amplifier provides approximately 42dB
gain. The large gain makes the amplifier susceptible to
small DC offsets, which cause deterministic jitter. A
low-frequency loop is integrated into the limiting ampli-
fier to reduce output offset, typically to less than 2mV.
The external capacitor (CZ) is required for stability and
to set the low-frequency cutoff for the offset correction
loop. The time constant of the loop is set by the product
of an equivalent 20kΩ on-chip resistor and the value of
the off-chip capacitor (CZ). For stable operation, the
minimum value of CZ is 0.01µF. To minimize pattern-
dependent jitter, CZ should be as large as possible.
For 10Gbps ethernet and SONET applications, the typi-
cal value of CZ is 0.1µF. Keep CZ close to the package
to reduce parasitic inductance.
CZ
CZ-
CZ+
DISABLE
MAX3971A
OFFSET
CORRECTION
AMP
LOWPASS
FILTER
GNDIN+
IN+
OUT+
CML Input Circuit
The input buffer is designed to accept CML input sig-
nals such as the output from the MAX3970 transimped-
ance amplifier. An equivalent circuit for the input is
shown in Figure 2. For lowest deterministic jitter in all
operating conditions, AC-coupling capacitors are rec-
ommended on the input.
INPUT
AMPLIFIER
OUTPUT
AMPLIFIER
GAIN
42dB
100Ω
OUT-
IN-
GNDIN-
Figure 1. Functional Diagram
_______________________________________________________________________________________
5
+3.3V, 10.7Gbps Limiting Amplifier
+3.3V
V
CC1
GNDIN+
IN+
50Ω
50Ω
100kΩ
IN-
GNDIN-
MX3971A
ESD
STRUCTURES
DISABLE
20μA
Figure 2. CML Input Equivalent Circuit
V
CC3
Figure 4. TTL Input Stage
50Ω
50Ω
OUT+
OUT-
+3.3V
DISABLE
DATA
Q3
Q4
Q1
Q2
ESD
STRUCTURES
L
SUPPLY FILTER
0.001μF
0.001μF
0.001μF
V
CC1
V
CC2
V
CC3
Figure 3. CML Output Equivalent Circuit
CML Output Circuit
An equivalent circuit for the output network is shown in
Figure 3. It consists of a pair of 50Ω resistors connect-
MAX3971A
ed to V
driven by the collectors of an output differen-
CC
tial transistor pair (Q1 and Q2). The differential output
signals are clamped by transistors Q3 and Q4 when
the DISABLE input is high.
Figure 5. Power-Supply Filter
DISABLE Function
A logic signal can be applied to the DISABLE pin to
squelch the output signal. When the output is disabled,
an offset is added to the output, preventing the follow-
ing stage from oscillating, if DC-coupled. See Figure 4
for the input stage of the DISABLE function.
6
_______________________________________________________________________________________
+3.3V, 10.7Gbps Limiting Amplifier
MX3971A
Layout Considerations
Pin Configurations
Circuit board layout and design can significantly affect
the performance of the MAX3971A. Use good high-fre-
quency techniques, including fixed-impedance trans-
mission lines for the high-frequency data signal. Use a
multilayer board with solid ground plane. Minimize the
inductance between the MAX3971A and the ground
plane.
20
19 18 17
16
15
14
1
2
3
4
5
V
CC3
GNDIN+
OUT+
OUT-
The MAX3971A uses three power-supply pins (V
,
IN+
IN-
CC1
V
, and V
). The input circuitry of the MAX3971A is
CC2
supplied by V
supply (V
CC3
CC1
13
12
. The output drivers have a separate
MAX3971A
), which usually has large pulsing currents.
CC3
V
CC3
GNDIN-
N.C.
All other circuitry is powered by V
. It is possible to
CC2
11
GND
simply connect the three pins together. However, using a
supply filter ensures better isolation of the input circuitry.
For optimal isolation, Figure 5 shows a possible supply-
filtering circuit. Element L, a ferrite bead, provides isola-
6
7
8
9
10
tion between a noisy V
and a sensitive V
.
CC3
CC1
QFN
4mm x 4mm
Chip Information
THE EXPOSED PAD MUST BE SOLDERED TO GND FOR
PROPER THERMAL AND ELECTRICAL PERFORMANCE.
TRANSISTOR COUNT: 324
PROCESS: SiGe Bipolar
SUBSTRATE: Electrically Isolated
TOP VIEW
20
19
18
17
16
V
15
14
GNDIN+
IN+
1
2
3
4
5
CC3
OUT+
13 OUT-
IN-
MAX3971A
GNDIN-
12
11
V
CC3
GND
N.C.
6
7
8
9
10
THIN QFN
4mm x 4mm
THE EXPOSED PAD MUST BE CONNECTED TO GROUND FOR
PROPER THERMAL AND ELECTRICAL PERFORMANCE.
_______________________________________________________________________________________
7
+3.3V, 10.7Gbps Limiting Amplifier
Chip Topography
V
CC1
CZ-
CZ+
V
CC2
DISABLE
V
CC3
MX3971A
GNDIN+
IN+
OUT+
OUT-
IN-
0.052"
(1.33mm)
V
CC3
GNDIN-
NC
GND
(0, 0)
GND
N.C.
GND
N.C.
N.C.
0.042"
(1.10mm)
8
_______________________________________________________________________________________
+3.3V, 10.7Gbps Limiting Amplifier
MX3971A
Chip Topography (continued)
MAX3971A
•
•
Pad dimensions:
X DIMENSION
(µm)
Y DIMENSION
(µm)
✕
PASSIVATION OPENING: 94.4µm 94.4µm
PAD NUMBER
✕
METAL: 102.4µm 102.4µm
1
2
16
554
418
287
151
39
All measurements specify the lower left corner of
the pad. Refer to Application Note H Fan-08.0:
Understanding Bonding Coordinates and Physical
Die Size.
26
3
26
4
16
5
16
6
191
303
415
527
639
978
978
974
974
978
825
713
601
489
377
-92
-92
-92
-92
-92
67
Package Information
7
For the latest package outline information, go to
8
www.maxim-ic.com/packages.
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Revision History
Rev 0; 4/02: Initial data sheet release.
Rev 1; 5/03: Added package code to Ordering Information and deleted EP references from Ordering Information
(page 1); updated package drawing (page 10).
Rev 2; 2/07: Added thin QFN package (pages 1 and 7); removed package drawing.
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 _____________________ 9
© 2007 Maxim Integrated Products
is a registered trademark of Maxim Integrated Products.
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