MAX3825U [MAXIM]
+3.3V, 2.5Gbps Quad Transimpedance Amplifier for System Interconnects; + 3.3V ， 2.5Gbps的四跨阻放大器的系统互连
| 型号： | MAX3825U |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | +3.3V, 2.5Gbps Quad Transimpedance Amplifier for System Interconnects |
| 文件： | 总8页 (文件大小：616K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-1855 Rev 0; 11/00
+3.3V, 2.5Gbps Quad Transimpedance Amplifier
for System Interconnects
General Description
Features
The MAX3825 is a quad transimpedance amplifier (TIA)
intended for 2.5Gbps system interconnect applications.
Each of the four channels converts a small photodiode
current to a measurable differential voltage with a tran-
simpedance gain of 3.7kΩ. The circuit features
o Single +3.3V Supply
o 93mW per Channel Power Dissipation
o 460nA Input-Referred Noise
RMS
o 20ps Deterministic Jitter
460nA
of input-referred noise per channel corre-
RMS
o 2.4GHz Small-Signal Bandwidth
o No External Compensation
sponding to an optical input sensitivity of -22.3dBm
(BER ≤ 1 × 10-14). The quad transimpedance amplifier
has 20ps of deterministic jitter and a 2.4GHz small-sig-
nal bandwidth. The MAX3825 is optimized for use with
a quad PIN photodetector array with a standard fiber
pitch of 250µm.
o 40dB Power-Supply Rejection Ratio
o Compact Die with 250µm Channel Pitch
o 100Ω Differential Output Impedance
The MAX3825 operates from a single +3.3V supply
over a 0°C to +85°C temperature range. With a +3.3V
supply, each channel dissipates 93mW of power. A DC
cancellation circuit on each channel provides a true dif-
ferential output swing over a wide range of input cur-
rents.
Ordering Information
PART
TEMP. RANGE
PIN-PACKAGE
MAX3825U/D
0°C to +85°C
Dice*
*Dice are designed to operate with a 0°C to +120°C junction
temperature, but are tested and guaranteed only at T = +25°C.
A
Each channel has an independent supply and ground
to allow all or any combination of channels to be con-
nected. This device is available in dice only.
Applications
ATM Switching
Networks
High-Speed Parallel
Optical Links
System Interconnects
SDH/SONET
Backplanes
Typical Operating Circuit appears at end of data sheet.
Dense Digital Cross-
Connects
Chip Topography/Pad Configuration
V
V
V
V
V
OUT3+ OUT3- V
V
OUT4+ OUT4-V
OUT1-
34
OUT2+ OUT2-
CCO3
CCO1 OUT1+
CCO1 CCO2
CCO2
CCO3 CCO4
CCO4
N.C.
36
35
33
32
31
30
29
28
27
26
25
24 23 22
21
20
GNDO4
GNDO1
37
19
18
GNDO3
ENABLE
GNDO2
GNDF
38
39
17
16
GNDI3
VCCI3
GNDI2
VCCI2
40
41
15
14
VCCI4
GNDI4
VCCI1
GNDI1
42
43
V
44
1
2
3
4
5
6
7
8
9
10
11
12
13
CCFILT
N.C. N.C. FILTER
IN1 FILT1 IN2 FILT2 IN3 FILT3 IN4 FILT4
N.C. N.C.
________________________________________________________________ Maxim Integrated Products
1
For price, delivery, and to place orders, please contact Maxim Distribution at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
+3.3V, 2.5Gbps Quad Transimpedance Amplifier
for System Interconnects
ABSOLUTE MAXIMUM RATINGS
Supply Voltage
Output Voltage OUT1 , OUT2 ,
V
V
, V
, V
, V
, V
,
OUT3 , OUT4 ............................(V - 1.5V) to (V + 0.5V)
CCO1 CCO2 CCO3 CCO4
CC
CC
, V
, V
, V
...............-0.5V to +6.0V
ENABLE Voltage.........................................-0.5V to (V
+ 0.5V)
CCI1 CCI2 CCI3 CCI4 CCFILT
CC
Input Current: IN1, IN2, IN3, IN4...........................-4mA to +4mA
FILTER Current..................................................-24mA to +24mA
Filter Current: FILT1, FILT2, FILT3, FILT4 .............-6mA to +6mA
Operating Temperature Range (TA)........................0°C to +85°C
Storage Temperature Range.............................-55°C to +150°C
Operating Junction Temperature (T )................-55°C to +150°C
J
Processing Temperature..................................................+400°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(V
= +3.14V to +3.6V, T = 0°C to +85°C. Typical values are at +3.3V, T = +25°C, unless otherwise noted.)
CC
A
A
MIN
TYP
MAX
PARAMETER
SYMBOL
CONDITIONS
UNITS
Single channel
Dual channel
Quad channel
28
56
40
80
Supply Current
I
mA
CC
112
0.89
160
0.99
Input Bias Voltage
DC Input Overload
Transimpedance
I
= 0
V
mA
kΩ
Ω
IN
1.7
3.0
3.7
180
720
50
4.5
57
Z
10µAp-p, 100 Ω differential load
21
Filter Resistor RFILTER
R
FILTER
Filter Resistors RFILT1–4
R
Ω
FILT_
43
50
Single-Ended Output Impedance
Transimpedance Linear Range
R
Ω
O
(Note 1)
µAp-p
Maximum Differential Output
Range
I
= 2mAp-p
mVp-p
230
-5
340
480
+5
IN
Output Offset Voltage
V
I
IN
= 10µAp-p
mV
V
offset
V
- 0.09
Output Common Mode Voltage
50Ω loads to V
CC
CC
Note 1: Gain at 50µAp-p is within 10% of the small signal gain.
AC ELECTRICAL CHARACTERISTICS
(V
= +3.14V to +3.6V, T = 0°C to +85°C. Typical values are at +3.3V, T = +25°C, unless otherwise noted. Total source capaci-
CC
A
A
tance = 0.7pF.) (Note 2)
MIN
TYP
MAX
PARAMETER
AC Input Overload
SYMBOL
CONDITIONS
UNITS
2
(Note 3)
(Note 4)
mAp-p
460
60
600
100
Input Referred Noise
Low-Frequency Cutoff
I
nA
rms
N
kHz
Deterministic Jitter (Note 5)
Power-Supply Rejection Ratio
Small-Signal Bandwidth
DJ
PSRR
BW
I
> 100µAp-p
20
40
45
ps
dB
IN
(Note 6)
2.4
GHz
ps
50
Maximum Skew (Note 7)
Any two channels within a chip
2
_______________________________________________________________________________________
+3.3V, 2.5Gbps Quad Transimpedance Amplifier
for System Interconnects
AC ELECTRICAL CHARACTERISTICS (continued)
(V
= +3.14V to +3.6V, T = 0°C to +85°C. Typical values are at +3.3V, T = +25°C, unless otherwise noted. Total source capaci-
CC
A
A
tance = 0.7pF.) (Note 2)
Note 2: AC characteristics are guaranteed by design and characterization.
Note 3: The maximum input current is specified with output deterministic jitter ≤ 45ps.
Note 4: No external compensation capacitors are used. Measured with I = 30µA
Note 5: Deterministic jitter is the arithmetic sum of pattern-dependent jitter and pulse width distortion. Measured with a 2 -1 PRBS
with 100 consecutive 0s and 100 consecutive 1s applied to a single channel. See Typical Operating Characteristics.
.
avg
IN
13
Note 6: PSRR = -20log(∆V
/ V ), f ≤ 2MHz. Measured by applying DC current = 30µA, and applying 100mVp-p signal
noise(on VCC)
OUT
at power supply.
Note 7: Measured by applying the same input signal to all channels. Skew measurements are made at the 50% point of the transition.
Typical Operating Characteristics
(V
= +3.3V, T = +25°C, unless otherwise noted.)
CC
A
INPUT-REFERRED RMS NOISE CURRENT
vs. DC INPUT CURRENT
DETERMINISTIC JITTER
vs. INPUT AMPLITUDE
FREQUENCY RESPONSE
50
1400
1200
1000
800
600
400
200
0
75
70
65
60
55
50
45
40
35
30
25
20
15
10
5
C
IN
= 0.7pF
0
10
100
DC INPUT CURRENT (µA)
1000
1
10
100
1000
10,000
0
400
800
1200
1600
2000
FREQUENCY (MHz)
INPUT CURRENT AMPLITUDE (µAp-p)
DIFFERENTIAL OUTPUT AMPLITUDE
vs. TEMPERATURE
DC TRANSFER FUNCTION
410
390
370
350
330
310
290
270
250
200
INPUT = 2mAp-p
V
CC
= +3.6V
100
0
V
CC
= +3.14V
-100
-200
-15
10
35
60
85
-100
-50
0
50
100
AMBIENT TEMPERATURE (°C)
INPUT CURRENT (µA)
_______________________________________________________________________________________
3
+3.3V, 2.5Gbps Quad Transimpedance Amplifier
for System Interconnects
Typical Operating Characteristics (continued)
(V
= +3.3V, T = +25°C, unless otherwise noted.)
CC
A
ELECTRICAL EYE DIAGRAM
ELECTRICAL EYE DIAGRAM
INPUT = 2mAp-p, 2.5Gbps, 213 - 1 PRBS
INPUT = 20µAp-p, 2.5Gbps, 213 - 1 PRBS
10mV/div
10mV/div
R
L
= 100Ω DIFFERENTIAL
R
L
= 100Ω DIFFERENTIAL
50ps/div
50ps/div
Pad Description
PAD
NAME
N.C.
FUNCTION
No Connection. Leave open and unconnected.
Connection to internal 180Ω Filter Resistor to V
1, 2, 12, 13
3
FILTER
IN1 to IN4
for Photodiode Array Cathode Bias
CCFILT
4, 6, 8, 10
Signal Inputs. Channel 1 to channel 4 signal inputs.
Filter Connections. Channel 1 to channel 4 connection to internal filter resistors (720Ω to
5, 7, 9, 11
FILT1 to FILT4
V
).
CCFILT
14, 17, 40, 43
15, 16, 41, 42
GNDI4 to GNDI1
to V
Input Stage Ground Connections. Channel 4 to channel 1 input stage ground.
Input Stage Supply Connections. Channel 4 to channel 1 input stage positive supply.
DC Feedback Disable. Disables DC feedback of all four channels when connected to the
V
CCI4
CCI1
18
ENABLE
positive supply (V ). Left unconnected for normal operation.
CC
20, 19, 38, 37
21, 24
GNDO4 to GNDO1 Output Stage Ground Connections. Channel 4 to channel 1 output stage ground.
V
Channel 4 Output Stage Positive Supply
CCO4
22, 26, 30, 34
23, 27, 31, 35
25, 28
OUT4- to OUT1-
Inverting Outputs. Channel 4 to channel 1 negative outputs.
OUT4+ to OUT1+ Noninverting Outputs. Channel 4 to channel 1 positive outputs.
V
V
V
Channel 3 Output Stage Positive Supply
Channel 2 Output Stage Positive Supply
Channel 1 Output Stage Positive Supply
Ground Connection for the Filters. Filter grounds.
Power Supply Connection for Filter Resistor
CCO3
CCO2
CCO1
29, 32
33, 36
39
GNDF
44
V
CCFILT
4
_______________________________________________________________________________________
+3.3V, 2.5Gbps Quad Transimpedance Amplifier
for System Interconnects
Functional Diagram
V
CC
FILT
720Ω
FILT_
D2
D1
V
CCO_
R1
50Ω
OUT_+
R = 1.3kΩ
F
Q2
VCCI_
V
CCO_
IN_
Q1
R2
50Ω
C1
PARAPHASE
AMP
OUT_-
GNDI_
R5
Q3
VCCI_
Q5
REFERENCE
AMP
R3
R4
GNDI_
GNDI_
DC
Q4
CANCELLATION
AMP
MAX3825
ENABLE
GNDO_
Figure 1. Functional Diagram for One Channel of the MAX3825
DC Cancellation Loop
Detailed Description
The DC cancellation loop removes the DC component
of the input signal by using low-frequency feedback.
This feature centers the signal within the MAX3825’s
dynamic range, reducing pulse-width distortion.
The MAX3825 quad TIA circuit is designed for 2.5Gbps
SONET/SDH applications. It comprises a transimped-
ance amplifier, a paraphase amplifier with CML out-
puts, and a DC cancellation loop to reduce pulse-width
distortion (Figure 1).
The output of the paraphrase amplifier is sensed through
resistors R3 and R4 and then filtered, amplified, and fed
back to the base of transistor Q4. The transistor draws
the DC component of the input signal away from the
transimpedance amplifier’s summing node.
Transimpedance Amplifier
The signal current at IN_ flows into the summing node
of a high-gain amplifier. Shunt feedback through R
F
converts this current to a voltage with a gain of 1300Ω.
Diodes D1 and D2 clamp the output voltage for large
input currents. GNDI_ is a direct connection to the emit-
ter of the input transistor and must be connected
directly to the photodetector AC ground return for best
performance.
The MAX3825 DC cancellation loop is internally com-
pensated and does not require external capacitors in
most 2.5Gbps applications. The DC cancellation loop
for all channels can be disabled by connecting
ENABLE to the positive supply (V ). ENABLE is inter-
CC
_______________________________________________________________________________________
5
+3.3V, 2.5Gbps Quad Transimpedance Amplifier
for System Interconnects
nally pulled low, so it does not need to be bonded out
for the DC cancellation loop to function.
Table 1. Optical Power Relations
PARAMETER
Average Power
SYMBOL
RELATION
= (P + P )/2
The MAX3825 minimizes pulse-width distortion for data
sequences exhibiting a 50% duty cycle and mark den-
sity. An input signal with a duty cycle and mark density
significantly different from 50% will cause the MAX3825
to operate improperly.
P
P
AVG
AVG
0
1
Extinction Ratio
r
r = P /P
e 1 0
e
Optical Power of a “1”
Optical Power of a “0”
P
P
P = 2P
(r )/(r + 1)
e e
1
0
1
AVG
P = 2P
/(r + 1)
e
0
AVG
DC cancellation current drawn from the input creates
noise. This is not a problem for a low-level signal with
little or no DC component. Preamplifier noise increases
for a signal with significant DC component (see Typical
Operating Characteristics).
P
= P - P = 2P
1 0 AVG
IN
Signal Amplitude
P
IN
(r - 1)/(r + 1)
e
e
Note: Assuming a 50% input duty cycle and mark density
Paraphase Amplifier and Output Stage
The paraphase amplifier converts single-ended inputs
to differential outputs, and introduces a voltage gain of
2.8. This signal drives an internally biased emitter cou-
pled pair, Q2 and Q3, which forms the output stage
(Figure 1). Resistors R1 and R2 provide back-termina-
tion at the outputs, absorbing reflections between the
MAX3825 and its load.
POWER
PI
P
IN
P
AVG
The differential outputs are designed to drive a 100Ω
load between OUT_+ and OUT_-. The MAX3825 can
also drive higher output impedances, resulting in
increased gain and output voltage swing.
PO
TIME
Applications Information
The MAX3825 is a quad TIA that is ideal for 2.5Gbps
SONET/SDH receivers. Its features allow easy design
into a fiberoptic module.
Figure 2. Optical Power Definitions
where ρ is the photodiode responsivity in A/W and I is
N
Optical Power Relations
Many of the MAX3825 specifications relate to the input
signal amplitude. When working with fiberoptic
receivers, the input is usually expressed in terms of
average optical power and extinction ratio. Table 1
shows relations that are helpful for converting optical
power to an input signal when designing with the
MAX3825 (Figure 2). The definitions are true if the mark
density and duty cycle of the input data are 50%.
in µA.
Input Optical Overload
The overload is the largest input that the MAX3825
accepts while meeting specifications. The optical over-
load can be estimated in terms of average power with
the following equation:
I
MAX
2ρ
Overload =10log
10
dBm
Optical Sensitivity Calculation
The input-referred RMS noise current (I ) of the
N
MAX3825 generally determines the receiver sensitivity.
To obtain a system bit error rate (BER) of 1 × 10-14, the
signal-to-noise ratio must always exceed 15.3. The
input sensitivity, expressed in average power, can be
estimated as:
where ρ is the photodiode responsivity in A/W and I
MAX
is in mA.
Optical Linear Range
The MAX3825’s outputs limit when the input signal
exceeds 50µAp-p. The MAX3825 operates in a linear
range for inputs not exceeding:
15.3I (r +1)
N e
Sensitivity =10log
10
2ρ(r −1) × 1000
e
6
_______________________________________________________________________________________
+3.3V, 2.5Gbps Quad Transimpedance Amplifier
for System Interconnects
V
CCI_
50µA(r +1)
e
Linear Range =10log
dBm
10
2ρ(r −1) × 1000
e
500Ω
where ρ is the photodiode responsivity in A/W.
Ground
V
CCI_
Connect all input ground connections as close as pos-
sible to the AC ground of the photodetector diode. The
photodetector AC ground is usually the ground of the
filter capacitor from the photodetector cathode. The
total loop (from GNDI_, through the bypass capacitor
and the diode, and back to IN_) should be as short as
possible.
1.3kΩ
IN_
0.1pF
200Ω
Photodiode Filter
GNDI_
Supply voltage noise at the cathode of the photodiode
produces a current I = C
∆V/∆t, which reduces the
is the photodiode capaci-
PD
Figure 3. Equivalent Input Circuit
receiver sensitivity (C
PD
tance). The filter resistor of the MAX3825, combined
with an external capacitor, can be used to reduce this
noise (see the Typical Application Circuit). Current gen-
erated by the supply noise voltage is divided between
V
CCO_
C
and C . The input noise current due to supply
PD
FILTER
noise is (assuming the filter capacitor is much larger
than the photodiode capacitance):
50Ω
50Ω
(V
)(C
)
PD
OUT+
NOISE
I
=
NOISE
(R
)(C
)
FILTER
FILTER
OUT-
Another important parameter is the inductance at the
photodiode array’s common cathode. It is important to
keep this inductance to a minimum to reduce the cou-
pling between the photodiodes. To keep this inductance
small, keep all bond wires as short as possible.
Wire Bonding
For high current density and reliable operation, the
MAX3825 uses gold metalization. Connections to the
die should be made with gold wire only, using ball
bonding techniques. Wedge bonding is not recom-
mended. Die thickness is typically 14 mils (mm).
Interface Models
Refer to Figures 3 and 4 for the equivalent input and
output circuits of the MAX3825.
Chip Information
TRANSISTOR COUNT: 1469
GNDO_
PROCESS: BIPOLAR (SILICON GERMANIUM)
DIE SIZE: 65 ✕ 99mils/(1651 ✕ 2515 microns)
Figure 4. Equivalent Output Circuit
_______________________________________________________________________________________
7
+3.3V, 2.5Gbps Quad Transimpedance Amplifier
for System Interconnects
Typical Application Circuit
V
CC
R
R
= 180Ω
FILTER
V
CC
FILTER
FILT1
PIN ARRAY
= 720Ω
= 720Ω
FILT1
IN1+
IN1-
OUT1+
OUT1-
OUT1+
OUT1-
50Ω
50Ω
IN1
R
FILT2
FILT2
IN2
IN2+
IN2-
OUT2+
OUT2-
OUT2+
OUT2-
50Ω
50Ω
R
R
= 720Ω
= 720Ω
FILT3
FILT3
IN3
IN3+
IN3-
OUT3+
OUT3-
OUT3+
OUT3-
50Ω
50Ω
FILT4
FILT4
IN4
OUT4+
OUT4-
IN4+
IN4-
OUT4+
OUT4-
50Ω
50Ω
MAX3825
QUAD TIA
MAX3822
QUAD LIMITING AMP
C
FILTER
LOP
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
8 _____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2000 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
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