MAX3690_V01 [MAXIM]
3.3V, 622Mbps, SDH/SONET 8:1 Serializer with Clock Synthesis and TTL Inputs;
| 型号： | MAX3690_V01 |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | 3.3V, 622Mbps, SDH/SONET 8:1 Serializer with Clock Synthesis and TTL Inputs |
| 文件： | 总8页 (文件大小：444K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-4774; Rev 2; 7/04
+3.3V, 622Mbps, SDH/SONET 8:1 Serializer
with Clock Synthesis and TTL Inputs
General Description
____________________________Features
The MAX3690 serializer is ideal for converting 8-bit-
wide, 77Mbps parallel data to 622Mbps serial data in
ATM and SDH/SONET applications. Operating from a
single +3.3V supply, this device accepts TTL clock and
data inputs, and delivers a 3.3V differential PECL serial-
data output. A fully integrated PLL synthesizes an inter-
nal 622MHz serial clock from a low-speed crystal
reference clock (77.76MHz, 51.84MHz, or 38.88MHz).
ꢀ Selectable Reference Clock Frequency:
77.76MHz, 51.84MHz, or 38.88MHz
ꢀ Single +3.3V Supply
ꢀ 77Mbps (8-bit) Parallel to 622Mbps Serial
Conversion
ꢀ Clock Synthesis for 622Mbps Serial Data
ꢀ 200mW Power
The MAX3690 is available in the extended-industrial
temperature range (-40°C to +85°C) in a 32-pin TQFP
package.
ꢀ TTL Parallel Clock and Data Inputs
ꢀ Differential 3.3V PECL Serial-Data Output
________________________Applications
622Mbps SDH/SONET Transmission Systems
622Mbps ATM/SONET Access Nodes
Add/Drop Multiplexers
Ordering Information
PART
TEMP RANGE
-40°C to +85°C
-40°C to +85°C
PIN-PACKAGE
32 TQFP
MAX3690ECJ
MAX3690ECJ+
32 TQFP
+Denotes lead-free package.
Digital Cross Connects
Pin Configuration appears at end of data sheet.
Typical Operating Circuit
V
CC
= +3.3V
38.88MHz TTL CRYSTAL
REFERENCE
1µF
1µF
PCLKI
PD0
RCLK
V
CKSET
CC
PD1
PD2
PD3
PD4
PD5
PD6
PD7
OVERHEAD
GENERATION
MAX3690
FIL+
FIL-
PCLKO
SD- SD+
GND
V
= +3.3V
CC
V
= +3.3V
CC
130Ω
130Ω
MAX3668
82Ω
82Ω
THIS SYMBOL REPRESENTS A TRANSMISSION LINE
OF CHARACTERISTIC IMPEDANCE (Z = 50Ω).
0
________________________________________________________________ Maxim Integrated Products
1
For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800.
For small orders, phone 1-800-835-8769.
+3.3V, 622Mbps, SDH/SONET 8:1 Serializer
with Clock Synthesis and TTL Inputs
ABSOLUTE MAXIMUM RATINGS
Terminal Voltage (with respect to GND)
Continuous Power Dissipation (T = +85°C)
A
V
.......................................................................-0.5V to +5V
TQFP (derate 10.2mW/°C above +85°C).....................663mW
Operating Temperature Range ...........................-40°C to +85°C
Storage Temperature Range.............................-60°C to +160°C
Lead Temperature (soldering, 10sec) .............................+300°C
CC
All Inputs, FIL-, FIL+, PCLKO.................-0.5V to (V
Output Current
PECL Outputs (SD ).......................................................50mA
+ 0.5V)
CC
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(V
= +3.0V to +3.6V, PECL loads = 50Ω 1ꢀ to (V
- 2V), T = -40°C to +85°C, unless otherwise noted. Typical values are at
A
CC
CC
V
= +3.3V, T = +25°C.)
CC
A
PARAMETER
SYMBOL
CONDITIONS
PECL outputs unterminated
CKSET = 0 or V
MIN
TYP
MAX
100
UNITS
mA
Supply Current
I
60
CC
CKSET Input Current
PECL OUTPUTS (SD )
I
500
µA
CKSET
CC
T
A
T
A
T
A
T
A
= 0°C to +85°C
V
V
V
V
- 1.025
V
- 0.88
- 0.88
- 1.62
- 1.555
CC
CC
CC
CC
CC
CC
CC
CC
Output High Voltage
Output Low Voltage
V
V
V
OH
= -40°C
- 1.085
- 1.81
- 1.83
V
V
V
= 0°C to +85°C
= -40°C
V
OL
TTL INPUTS AND OUTPUTS (PCLKI, RCLK, PCLKO, PD_)
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
Output High Voltage
Output Low Voltage
V
2.0
V
V
IH
V
0.8
10
10
IL
I
IH
V
V
= V
= 0
-10
-10
2.4
µA
µA
V
IN
IN
CC
I
IL
V
I
I
= 400µA
= -400µA
OH
OH
OL
V
0.44
V
OL
AC ELECTRICAL CHARACTERISTICS
(V
= +3.0V to +3.6V, PECL loads = 50Ω 1ꢀ to (V
- 2V), all TTL thresholds set to V /2, T = -40°C to +85°C, unless otherwise
A
CC CC
CC
noted. Typical values are at V
= +3.3V, T = +25°C.) (Note 1)
CC
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
MHz
ps
Serial Clock Rate
f
622.08
SCLK
Parallel Data Setup Time
Parallel Data Hold Time
t
1200
1000
SU
t
ps
H
Allowable Parallel Clock Output
to Parallel Clock Input Delay
t
0
5.0
11
ns
SKEW
Φ
0
Output Random Jitter
ps
RMS
PECL Differential Output
Rise/Fall Time
t
t
20ꢀ to 80ꢀ
200
ps
R, F
TTL Output Rise Time
TTL Output Fall Time
t
C
C
= 15pF, V
= 15pF, V
= 0.8V to 2.0V
= 0.8V to 2.0V
650
550
ns
ns
R
LOAD
OUT
t
F
LOAD
OUT
Note 1: AC characteristics guaranteed by design and characterization.
Note 2: All TTL thresholds set to V / 2.
CC
2
_______________________________________________________________________________________
+3.3V, 622Mbps, SDH/SONET 8:1 Serializer
with Clock Synthesis and TTL Inputs
__________________________________________Typical Operating Characteristics
(V
= +3.3V, T = +25°C, unless otherwise noted.)
A
CC
PARALLEL DATA SETUP TIME
vs. TEMPERATURE
PARALLEL DATA HOLD TIME
vs. TEMPERATURE
SUPPLY CURRENT vs. TEMPERATURE
270
265
260
255
250
-55
-60
-65
-70
-75
-80
-85
-90
75
70
65
60
55
50
45
245
240
235
230
-95
100
-25
-40
-25
0
25
50
75
85
-40
0
25
50
75
85
-50
-25
0
25
50
75
TEMPERATURE (°C)
TEMPERATURE (¡C)
TEMPERATURE (°C)
SERIAL DATA RANDOM JITTER
(R = 77.76MHz)
SERIAL-DATA OUTPUT EYE DIAGRAM
(622Mbps, PRBS)
ALLOWED PCLKO to PCLKI SKEW
vs. TEMPERATURE
CLKI
15
V
= 3.3V
CC
10
5
2mV/
div
100mV/
div
0
RJ = 4.66ps
RMS
-5
5ps/div
TEMPERATURE (°C)
200ps/div
0
-50
0
50
100
TEMPERATURE (°C)
_______________________________________________________________________________________
3
+3.3V, 622Mbps, SDH/SONET 8:1 Serializer
with Clock Synthesis and TTL Inputs
______________________________________________________________Pin Description
PIN
NAME
FUNCTION
1–8
PD0–PD7
TTL Parallel-Data Inputs. Data is clocked in on the PCLKI signal’s positive transition.
9, 10, 17,
18, 19, 24,
25, 26,
GND
Ground
31, 32
TTL Parallel-Clock Output. Use positive transition of PCLKO to clock the overhead management
circuit.
11
PCLKO
12, 13, 16,
21, 28, 29
V
CC
+3.3V Supply Voltage
14
15
SD-
Inverting PECL Serial-Data Output
SD+
Noninverting PECL Serial-Data Output
Reference Clock Rate Programming Pin.
CKSET = open: Reference clock rate = 77.76MHz
CKSET = 20kΩ to GND: Reference clock rate = 51.84MHz
CKSET = GND: Reference clock rate = 38.88MHz
20
CKSET
22
23
FIL-
Filter Capacitor Input. Connect a 1µF capacitor between FIL- and V
Filter Capacitor Input. Connect a 1µF capacitor between FIL- and V
.
.
CC
FIL+
CC
TTL Reference-Clock Input. Connect a crystal reference clock (77.76MHz, 51.84MHz or 38.88MHz) to
the RCLK input. The active edge is the positive transitioning edge.
27
30
RCLK
PCLKI
TTL Parallel-Clock Input. Connect the incoming parallel-data-clock signal to the PCLKI input. The
active edge is the positive transitioning edge.
allel data is clocked into the MAX3690 on the rising
_______________Detailed Description
transition of the parallel-clock-input signal (PCLKI). The
control and timing logic ensure proper operation if the
parallel-input register is latched within a window of time
that is defined with respect to the parallel-clock-output
signal (PCLKO). PCLKO is the synthesized 622MHz
internal serial-clock signal divided by eight. Parallel-
clock output to parallel-clock-input delay (skew) must
be observed. Figure 2 shows the timing diagram.
The MAX3690 serializer comprises an 8-bit parallel
input register, an 8-bit shift register, control and timing
logic, a PECL output buffer, TTL input/output buffers,
and a frequency-synthesizing PLL (consisting of a
phase/frequency detector, loop filter/amplifier, voltage-
controlled oscillator, and programmable prescaler).
This device converts 8-bit-wide, 77Mbps parallel data
to 622Mbps serial data (Figure 1).
PECL Outputs
The PLL synthesizes an internal 622MHz reference
used to clock the output shift register. This clock is
generated by locking onto the external crystal refer-
ence clock signal (RCLK) operating at either
77.76MHz, 51.84MHz, or 38.88MHz. The incoming par-
The serial-data PECL outputs (SD+, SD-) require 50Ω
DC termination to (V
- 2V). See the Alternative PECL-
CC
Output Termination section.
4
_______________________________________________________________________________________
+3.3V, 622Mbps, SDH/SONET 8:1 Serializer
with Clock Synthesis and TTL Inputs
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
TTL
TTL
8-BIT
PARALLEL
TTL
INPUT
REGISTER
TTL
TTL
TTL
TTL
TTL
PCLKI
CKSET
TTL
PRE-
SCALER
SHIFT
8-BIT
SHIFT
REGISTER
SDOH
SDOL
PECL
PHASE/FREQ
DETECT
RCLK
TTL
VCO
CONTROL
TTL
LATCH
MAX3690
FIL+ FIL-
PCLKO
Figure 1. Functional Diagram
PCLKO
PCLKI
PD_
t
SKEW
t
t
H
SU
VALID PARALLEL DATA
SD
D7 D6 D5 D4 D3 D2 D1 D0
NOTE: PD7 = D7, PD6 = D6, PD5 = D5, PD4 = D4, PD3 = D3, PD2 = D2, PD1 = D1, PD0 = D0
Figure 2. Timing Diagram
_______________________________________________________________________________________
5
+3.3V, 622Mbps, SDH/SONET 8:1 Serializer
with Clock Synthesis and TTL Inputs
__________Applications Information
+3.3V
Alternative PECL-Output Termination
Figure 3 shows alternative PECL-output-termination
methods. Use Thevenin-equivalent termination when a
CC
130Ω
130Ω
MAX3690
(V
- 2V) termination voltage is not available. If AC
SD+
SD-
Z = 50Ω
0
coupling is necessary, be sure that the coupling
capacitor is placed following the 50Ω or Thevenin-
equivalent DC termination.
PECL
INPUTS
Z = 50Ω
0
Layout Techniques
For best performance, use good high-frequency layout
techniques. Filter voltage supplies and keep ground
connections short. Use multiple vias where possible.
Also, use controlled-impedance transmission lines to
interface with the MAX3690 data outputs.
82Ω
82Ω
MAX3690
SD+
SD-
Z = 50Ω
0
HIGH-
IMPEDENCE
INPUTS
Z = 50Ω
0
50Ω
50Ω
V
CC
- 2V
Figure 3. Alternative PECL-Output Termination
6
_______________________________________________________________________________________
+3.3V, 622Mbps, SDH/SONET 8:1 Serializer
with Clock Synthesis and TTL Inputs
Pin Configuration
TOP VIEW
16
15
14
13
12
11
10
9
V
CC
SD+
SD-
GND
GND
RCLK
25
26
27
28
29
30
31
32
V
CC
V
CC
MAX3690
V
CC
V
CC
PCLKO
GND
GND
PCLKI
GND
GND
TQFP
_______________________________________________________________________________________
7
+3.3V, 622Mbps, SDH/SONET 8:1 Serializer
with Clock Synthesis and TTL Inputs
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
8 _____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2004 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
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