MAX3680AEAIT [MAXIM]
Serial to Parallel/Parallel to Serial Converter, 1-Func, PDSO28, 5.30 MM, MO-150, SSOP-28;
| 型号： | MAX3680AEAIT |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Serial to Parallel/Parallel to Serial Converter, 1-Func, PDSO28, 5.30 MM, MO-150, SSOP-28 ATM 异步传输模式 电信 光电二极管 电信集成电路 |
| 文件： | 总8页 (文件大小：117K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-1210; Rev 3; 3/07
+3.3V, 622Mbps, SDH/SONET
1:8 Deserializer with TTL Outputs
/MX3680A
_________________General Description
______________________________Features
♦ Single +3.3V Supply
♦ 622Mbps Serial to 77Mbps Parallel Conversion
♦ 165mW Power
The MAX3680/MAX3680A deserializer is ideal for con-
verting 622Mbps serial data to 8-bit-wide, 77Mbps par-
allel data in ATM and SDH/SONET applications.
Operating from a single +3.3V supply, this device
accepts PECL serial clock and data inputs, and deliv-
ers TTL clock and data outputs. The MAX3680 also pro-
vides a TTL synchronization input that enables data
realignment and reframing.
♦ Synchronization Input for Data Realignment and
Reframing (MAX3680)
♦ Differential 3.3V PECL Clock and Data Inputs
♦ TTL Data Outputs
The MAX3680/MAX3680A is available in the extended-
industrial temperature range (-40°C to +85°C), in a 28-
pin SSOP package.
__________________________Applications
________________Ordering Information
622Mbps SDH/SONET Transmission Systems
622Mbps ATM/SONET Access Nodes
Add/Drop Multiplexers
PART
TEMP RANGE
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
PIN-PACKAGE
28 SSOP
MAX3680EAI
MAX3680EAI+
MAX3680AEAI
28 SSOP
28 SSOP
Digital Cross-Connects
+Denotes lead-free package.
Pin Configuration appears at end of data sheet.
___________________________________________________________________Typical Operating Circuit
V
CC
= +3.3V
V
CC
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
V
= +3.3V
CC
V
CC
= +3.3V
MAX3680/
MAX3680A
130Ω
130Ω
SD+
SD-
PHOTODIODE
MAX3675
OVERHEAD
TERMINATION
82Ω
82Ω
DATA
AND
CLOCK
RECOVERY
LIMITING
AMP
PREAMP
100Ω
V
CC
= +3.3V
MAX3664
130Ω
130Ω
SCLK+
SCLK-
82Ω
82Ω
PCLK
SYNC
GND
THIS SYMBOL REPRESENTS A TRANSMISSION LINE OF CHARACTERISTIC IMPEDANCE Z = 50Ω.
0
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
+3.3V, 622Mbps, SDH/SONET
1:8 Deserializer with TTL Outputs
ABSOLUTE MAXIMUM RATINGS
Terminal Voltage (with respect to GND)
Continuous Power Dissipation (T = +85°C)
A
V
........................................................................-0.5V to +5V
SSOP (derate 9.52mW/°C above +85°C) .....................619mW
CC
PECL Inputs (SD+/-, SCLK+/-)................-0.5V to (V
TTL Input (SYNC) ....................................-0.5V to (V
TTL Outputs (PCLK, PD_)........................-0.5V to (V
+ 0.5V)
+ 0.5V)
+ 0.5V)
Operating Temperature Range ...........................-40°C to +85°C
Storage Temperature Range.............................-65°C to +160°C
Lead Temperature (soldering, 10s) .................................+300°C
CC
CC
CC
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(V
CC
= +3.0V to +3.6V, T = -40°C to +85°C, unless otherwise noted. Typical values are at V
= +3.3V, T = +25°C.)
CC A
A
PARAMETER
Supply Current
SYMBOL
CONDITIONS
TTL outputs = high
MIN
25
TYP
50
MAX
90
UNITS
mA
I
CC
PECL INPUTS (SD+/-, SCLK+/-)
Input High Voltage
Input Low Voltage
V
V
V
- 1.16
V
V
- 0.88
V
V
IH
CC
CC
CC
V
- 1.81
- 1.48
10
IL
CC
/MX3680A
Input High Current
Input Low Current
I
IH
V
V
= V
= V
-10
µA
µA
IN
IH(MAX)
I
IL
-10
2.0
10
IN
IL(MAX)
TTL INPUT AND OUTPUTS (SYNC, PCLK, PD_) (Note 1)
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
Output High Voltage
Output Low Voltage
V
IH
V
V
V
0.8
10
10
IL
I
IH
V
V
= V
= V
-10
-10
2.4
0
µA
µA
V
IN
IH(MAX)
I
IL
IN
IL(MAX)
V
OH
Output sourcing = 400µA
Output sinking = 400µA
V
CC
V
OL
0.44
V
Note 1: The SYNC input is available only on the MAX3680.
AC ELECTRICAL CHARACTERISTICS
(V
CC
= +3.0V to +3.6V, T = +25°C, unless otherwise noted.) (Note 2)
A
PARAMETER
Maximum Serial Clock Frequency
SYMBOL
f
SCLK
CONDITIONS
MIN
622
800
50
TYP
MAX
UNITS
MHz
ps
Serial Data Setup Time
t
SU
Serial Data Hold Time
t
H
ps
Parallel Clock to Data Output Delay
t
V
CC
= +3.3V, C = 18pF
-200
500
2000
ps
L
CLK-Q
Note 2: AC characteristics guaranteed by design and characterization.
2
_______________________________________________________________________________________
+3.3V, 622Mbps, SDH/SONET
1:8 Deserializer with TTL Outputs
/MX3680A
__________________________________________Typical Operating Characteristics
(V
CC
= +3.0V to +3.6V, unless otherwise noted.)
MAXIMUM SERIAL-CLOCK FREQUENCY
vs. TEMPERATURE
SERIAL DATA SETUP TIME
vs. TEMPERATURE
1.3
1.2
1.1
1.0
0.9
0.8
400
360
320
280
240
200
-50
-25
0
25
50
75
100
-50
-25
0
25
50
75
100
TEMPERATURE (°C)
TEMPERATURE (°C)
SUPPLY CURRENT
vs. TEMPERATURE
SERIAL DATA HOLD TIME
vs. TEMPERATURE
70
60
50
40
30
20
10
0
-100
-160
-220
-280
-340
-400
V
= +3.6V
CC
V
CC
= +3.3V
V
= +3.0V
CC
-50
-25
0
25
50
75
100
-50
-25
0
25
50
75
100
TEMPERATURE (°C)
TEMPERATURE (°C)
_______________________________________________________________________________________
3
+3.3V, 622Mbps, SDH/SONET
1:8 Deserializer with TTL Outputs
Pin Description
PIN
NAME
FUNCTION
MAX3680 MAX3680A
1, 2, 5, 8,
14, 18, 25
1, 2, 5, 8,
14, 18, 25
V
CC
+3.3V Supply Voltage
Noninverting PECL Serial Data Input. Data is clocked on the SCLK signal’s positive
transition.
3
4
3
4
SD+
SD-
Inverting PECL Serial Data Input. Data is clocked on the SCLK signal’s positive transition.
6
7
6
7
SCLK+ Noninverting PECL Serial Clock Input
SCLK-
Inverting PECL Serial Clock Input
9, 11, 12,
16, 20, 23,
27
11, 12, 16,
20, 23, 27
GND
Ground
TTL Synchronization Pulse Input. Pulse high for at least two SCLK periods to shift the data
alignment by dropping one bit in the serial input data stream.
10
—
SYNC
/MX3680A
—
9, 10
13
N.C.
No Connection
13
PCLK
TTL Parallel Clock Output
15, 17, 19,
21, 22, 24,
26, 28
15, 17, 19,
21, 22, 24,
26, 28
TTL Parallel Data Outputs. Data is updated on the falling edge of PCLK. See Figure 2 for the
relationship between serial-data-bit position and output-data-bit assignment.
PD0–PD7
Detailed Description
PD7
The MAX3680/MAX3680A deserializer uses an 8-bit
shift register, 8-bit parallel output register, 3-bit counter,
PECL input buffers, and TTL input/output buffers to
convert 622Mbps serial data to 8-bit-wide, 77Mbps par-
allel data (Figure 1).
TTL
TTL
TTL
TTL
TTL
SD+
SD-
PD6
PD5
PD4
PD3
PECL
PECL
8-BIT
SHIFT
REGISTER
SCLK+
SCLK-
The input shift register continuously clocks incoming
data on the positive transition of the serial clock (SCLK)
input signal. The 3-bit counter generates a parallel output
clock (PCLK) by dividing down the serial clock frequen-
cy. The PCLK signal is used to clock the parallel output
register. During normal operation, the counter divides the
SCLK frequency by eight, causing the output register to
latch every eight bits of incoming serial data.
8-BIT
PARALLEL
OUTPUT
REGISTER
PD2
PD1
TTL
TTL
The MAX3680 synchronization input (SYNC) is used for
data realignment and reframing. When the SYNC signal
is pulsed high for at least two SCLK cycles, PCLK is
delayed by one SCLK cycle, causing the first incoming
bit of the serial input data stream to be dropped. This
realignment is guaranteed to occur within two PCLK
cycles of the SYNC rising edge.
MAX3680/
MAX3680A
PD0
TTL
TTL
3-BIT
COUNTER
PCLK
SYNC
TTL
See Figure 2 for the functional timing diagrams and
Figure 3 for the timing parameters diagram.
Figure 1. Functional Diagram
4
_______________________________________________________________________________________
+3.3V, 622Mbps, SDH/SONET
1:8 Deserializer with TTL Outputs
/MX3680A
SCLK*
SD*
D1-
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
PCLK
D8-
D0
D1
D2
D3
D4
D5
D6
D7
PD7
PD6
D8
D7-
D6-
D5-
D4-
D3-
D2-
D1-
D9
D10
D11
D12
D13
D14
D15
PD5
PD4
PD3
PD2
PD1
PD0
* SIGNAL SHOWN IS DIFFERENTIAL. FOR EXAMPLE, SCLK = (SCLK+) - (SCLK-).
Figure 2a. Functional Timing Diagram—Normal Operation
_______________________________________________________________________________________
5
+3.3V, 622Mbps, SDH/SONET
1:8 Deserializer with TTL Outputs
SCLK*
D1-
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
SD*
SYNC
PCLK
D8-
D1
D2
D3
D4
D5
D6
D7
D8
D9
PD7
PD6
D7-
D6-
D5-
D4-
D3-
D2-
D1-
D10
D11
D12
D13
D14
D15
D16
PD5
PD4
PD3
PD2
/MX3680A
PD1
PD0
* SIGNAL SHOWN IS DIFFERENTIAL. FOR EXAMPLE, SCLK = (SCLK+) - (SCLK-).
Figure 2b. Functional Timing Diagram—SYNC Operation (MAX3680)
t
= 1 / f
SCLK
SCLK
SCLK*
t
t
H
SU
SD*
PCLK
t
CLK-Q
PD0–PD7
* SIGNAL SHOWN IS DIFFERENTIAL. FOR EXAMPLE, SCLK = (SCLK+) - (SCLK-).
Figure 3. Timing Parameters
6
_______________________________________________________________________________________
+3.3V, 622Mbps, SDH/SONET
1:8 Deserializer with TTL Outputs
/MX3680A
PECL Inputs
The serial data and clock PECL inputs (SD+, SD-,
THEVENIN-EQUIVALENT TERMINATION
SCLK+, SCLK-) require 50Ω termination to (V
- 2V)
CC
+3.3V
when interfacing with a PECL source (see Alternative
PECL Input Termination).
130Ω
130Ω
MAX3680/
MAX3680A
Z
O
= 50Ω
= 50Ω
Applications Information
Alternative PECL Input Termination
Figure 4 shows alternative PECL input-termination
methods. Use Thevenin-equivalent termination when a
PECL
INPUTS
Z
O
(V
- 2V) termination voltage is not available. If AC
CC
82Ω
coupling is necessary, such as when interfacing with
an ECL-output device, use the ECL AC-coupling termi-
nation.
82Ω
Layout Techniques
For best performance, use good high-frequency layout
techniques. Filter voltage supplies and keep ground
connections short. Use multiple vias where possible.
Also, use controlled impedance transmission lines to
interface with the MAX3680 data inputs.
ECL AC-COUPLING TERMINATION
+3.3V
1.6k
1.6k
Z
Z
= 50Ω
O
MAX3680/
MAX3680A
50Ω
PECL
INPUTS
Pin Configuration
-2V
-2V
= 50Ω
O
TOP VIEW
50Ω
2.7k
2.7k
28
27
26
25
24
V
V
PD7
GND
PD6
1
2
CC
CC
SD+
SD-
3
Figure 4. Alternative PECL Input Termination
V
CC
4
PD5
V
5
CC
MAX3680/
MAX3680A
SCLK+
SCLK-
23 GND
6
Chip Information
PD4
PD3
7
22
21
V
CC
8
GND
(N.C.)
TRANSISTOR COUNT: 1346
9
20 GND
SYNC
PD2
19
18
10
11
(N.C.)
GND
V
CC
GND 12
17 PD1
16
13
14
PCLK
GND
V
15 PD0
CC
SSOP
() MAX3680A ONLY.
_______________________________________________________________________________________
7
+3.3V, 622Mbps, SDH/SONET
1:8 Deserializer with TTL Outputs
________________________________________________________Package Information
2
1
INCHES
MILLIMETERS
DIM
A
A1
B
MIN
0.068
MAX
MIN
1.73
0.05
0.25
0.09
MAX
1.99
0.21
0.38
0.20
INCHES
MIN
MAX
0.239 0.249
0.239 0.249
0.278 0.289
0.317 0.328
MILLIMETERS
MIN
6.07
6.07
7.07
8.07
MAX
6.33
N
14L
0.078
D
D
D
D
D
0.002 0.008
0.010 0.015
0.004 0.008
SEE VARIATIONS
0.205 0.212 5.20
0.0256 BSC
6.33 16L
7.33
8.33 24L
20L
C
E
H
D
0.397 0.407 10.07 10.33 28L
E
5.38
e
0.65 BSC
H
0.301 0.311 7.65
0.025 0.037 0.63
7.90
0.95
8∞
L
0∞
8∞
0∞
N
/MX3680A
A
C
B
L
e
A1
D
NOTES:
1. D&E DO NOT INCLUDE MOLD FLASH.
2. MOLD FLASH OR PROTRUSIONS NOT TO EXCEED .15 MM (.006").
3. CONTROLLING DIMENSION: MILLIMETERS.
4. MEETS JEDEC MO150.
PROPRIETARY INFORMATION
TITLE:
PACKAGE OUTLINE, SSOP, 5.3 MM
APPROVAL
DOCUMENT CONTROL NO.
REV.
5. LEADS TO BE COPLANAR WITHIN 0.10 MM.
1
21-0056
C
1
Revision History
Rev 0; 3/97: Initial MAX3680 release.
Rev 1; 11/00: Changed t
max from 1300ps to 2000ps (page 2); replaced TOC3 (page 3).
CLK-Q
Rev 2; 7/04: Added lead-free package to Ordering Information table (page 1).
Rev 3; 3/07: Added MAX3680A (pages 1, 2, 4, 6, 7).
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
8 _____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2007 Maxim Integrated Products
is a registered trademark of Maxim Integrated Products, Inc.
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