MAX3645EEE+ [MAXIM]
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| 型号： | MAX3645EEE+ |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
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19-3026; Rev 0; 10/03
+2.97V to +5.5V, 125Mbps to 200Mbps Limiting
Amplifier with Loss-of-Signal Detector
General Description
Features
The MAX3645 limiting amplifier functions as a data
quantizer and is pin compatible with the Mindspeed
MC2045-2 and MC2045-2Y postamplifiers. The amplifi-
er accepts a wide range of input voltages and provides
constant-level positive emitter-coupled logic (PECL)
output voltages with controlled edge speeds.
ꢀ Pin Compatible with the Mindspeed
MC2045-2/MC2045-2Y
ꢀ 500µV Input Sensitivity (BER = 10-12
ꢀ Compatible with 4B/5B Data Coding
ꢀ Programmable LOS Threshold
)
The MAX3645 features an integrated power detector
with complementary PECL loss-of-signal (LOS) outputs
that indicate when the input power level drops below a
programmable threshold. An optional squelch function
holds the data outputs at static levels during a
LOS condition.
ꢀ Stable LOS Threshold Over Supply Range
ꢀ Output Disable Function and Automatic Squelch
ꢀ Single +3.3V or +5.0V Power Supply
ꢀ 18mA Supply Current
Ordering Information
The MAX3645 operates from a single +3.3V or +5.0V
power supply over a -40°C to +85°C temperature
range. It is available in 16-pin SO and 16-pin QSOP
packages.
PART
MAX3645ESE
MAX3645EEE
TEMP RANGE
-40°C to +85°C
-40°C to +85°C
PIN-PACKAGE
16 SO
16 QSOP
Pin Configuration
Applications
SONET 155Mbps Transceivers
Fast Ethernet Receivers
FDDI 125Mbps Receivers
FTTx Receivers
TOP VIEW
CAZ2
1
2
3
4
5
6
7
8
16 TH
CAZ1
GNDA
DIN+
DIN-
15 N.C.
14
V
CCE
ESCON Receivers
MAX3645
13 DOUT+
12 DOUT-
11 GNDE
10 LOS
V
CCA
CSD
DIS
9
LOS
SO/QSOP
Typical Application Circuit
V
V
CC
CC
C
AZ
0.1µF
V
V
CC
CC
C
SD
1nF
V
V
CSD CCA CAZ1 CAZ2 CCE
N.C.
0.1µF
0.1µF
PIN K
IN
DIN+
DIN-
DOUT+
OUT+
OUT-
DOUT-
LOS
MAX3645
MAX3644*
GNDA TH
LOS GNDE
GND
50Ω
50Ω
50Ω
R
TH
100Ω
50Ω
*FUTURE PRODUCT
V
- 2V
CC
V
CC
- 2V
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
+2.97V to +5.5V, 125Mbps to 200Mbps Limiting
Amplifier with Loss-of-Signal Detector
ABSOLUTE MAXIMUM RATINGS
Power-Supply Voltage (V
, V
) ....................-0.5V to +7.0V
Continuous Power Dissipation (T = +85°C)
CCA CCE
A
Voltage at CAZ1, CAZ2, DIN+,
DIN-, CSD, DIS, TH ................................-0.5V to (V
PECL Output Current (DOUT+, DOUT-, LOS, LOS) ...........50mA
Differential Voltage between CAZ1 and CAZ2......-1.5V to +1.5V
Differential Voltage between DIN+ and DIN- ........-1.5V to +1.5V
16-Pin SO (derate 8.7mW/°C above +85°C)................565mW
+ 0.5V)
16-Pin QSOP (derate 8.3mW/°C above +85°C)...........540mW
CC
Storage Ambient Temperature Range (T )…….-65°C to +160°C
S
Lead Temperature (soldering, 10s)...........……………….+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V
= +2.97V to +5.5V, PECL outputs are terminated with 50Ω to V
- 2V, R = 100Ω, C = 0.1µF, C = 1nF, T = -40°C to
CC TH AZ SD A
CC
+85°C. Typical values are at V
= +3.3V, T = +25°C, unless otherwise noted.)
CC
A
PARAMETER
POWER SUPPLY
SYMBOL
CONDITIONS
MIN
TYP
18
MAX
UNITS
mA
Supply Current
I
Excludes PECL termination currents
27
CC
INPUT SPECIFICATIONS
Input Resistance
R
Single ended; V
Single ended
Differential
=
2ꢀꢀmV
3.3
4.8
6.4
ꢀ.5
1.ꢀ
k
IN
IN
Input Sensitivity (Note 1)
Input Overload (Note 1)
Input-Referred Offset Voltage
V
mV
mV
IN-MIN
P-P
P-P
Single ended
Differential
75ꢀ
V
IN-MAX
15ꢀꢀ
Unterminated input, output offset divided by
DC gain (Note 2)
2
4ꢀ
5ꢀ
µV
V
-
CC
Input Common-Mode Voltage
Input-Referred RMS Noise
DIS Input High
V
V
CMM
ꢀ.87
V
(Notes 2, 3)
36
µV
RMS
IN-NOISE
V
-
CC
V
PECL or CMOS logic
V
mV
IH
CC
116ꢀ
V
148ꢀ
-
CC
DIS Input Low
V
PECL or CMOS logic
ꢀ
mV
µA
IL
DIS Input Current
I , I
IL IH
ꢀV
V
DIS
V
CC
-1ꢀ
+1ꢀ
OUTPUT SPECIFICATIONS
V
1ꢀ85
-
V
88ꢀ
-
-
CC
CC
PECL Output-Voltage High
PECL Output-Voltage Low
(Notes 1, 2)
(Notes 1, 2)
mV
mV
V
183ꢀ
-
V
CC
1555
CC
Data Output Transition Time
Pulse-Width Distortion
t , t
2ꢀ% to 8ꢀ% (Notes 1, 2, 4)
(Notes 1, 2, 4, 5)
ꢀ.7
3ꢀ
1.4
ns
ps
R
F
PWD
2ꢀꢀ
2
_______________________________________________________________________________________
+2.97V to +5.5V, 125Mbps to 200Mbps Limiting
Amplifier with Loss-of-Signal Detector
ELECTRICAL CHARACTERISTICS (continued)
(V
= +2.97V to +5.5V, PECL outputs are terminated with 5ꢀΩ to V
- 2V, R = 1ꢀꢀΩ, C = ꢀ.1µF, C = 1nF, T = -4ꢀ°C to
CC TH AZ SD A
CC
+85°C. Typical values are at V
= +3.3V, T = +25°C, unless otherwise noted.)
CC
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
TRANSFER CHARACTERISTICS
Bandwidth
Gain = 6ꢀdB
15ꢀ
25ꢀ
5ꢀꢀ
ꢀ.5
MHz
kHz
C
C
= open
= ꢀ.1µF
AZ
AZ
Low-Frequency Cutoff
LOSS-OF-SIGNAL SPECIFICATIONS (Notes 2, 4, 6)
LOS Sensitivity Range
LOS Hysteresis
ꢀ
R
2k
2
2ꢀ
mV
P-P
TH
1ꢀlog (V
(Note 7)
/V
)
1.4
2.3
ꢀ.5
4.8
12
2
dB
µs
DEASSERT ASSERT
LOS Assert/Deassert Time
8ꢀ.ꢀ
1.3
8.3
22
R
R
R
R
R
R
= ꢀ , low setting
ꢀ.9
6.6
17
TH
TH
TH
TH
TH
TH
LOS Assert Level
= 1k , medium setting
= 2k , high setting
= ꢀ , low setting
mV
P-P
P-P
1.1
8.ꢀ
2ꢀ
1.5
1ꢀ.8
28
1.9
13.5
36
LOS Deassert Level
= 1k , medium setting
= 2k , high setting
mV
k
Signal-Dectect Filter Resistance
R
Pin 7
14
2ꢀ
26
SD
Note 1: Between sensitivity and overload, the output amplitude is >95% of the fully limited amplitude and all AC specifications are met.
Note 2: Guaranteed by design and characterization.
Note 3: Noise is derived from BER measurement.
Note 4: The data input transition time is controlled by a 4th-order Bessel filter with f
= ꢀ.75 × data rate.
-3dB
Note 5: PWD = [(width of wider pulse) - (width of narrower pulse)] / 2, measured with 155Mbps ꢀꢀ11 pattern.
23
Note 6: All LOS specifications are measured using a 155Mbps 2 - 1 PRBS pattern.
Note 7: The signal at the input is switched between two amplitudes, SIGNAL_ON and SIGNAL_OFF, as shown in Figure 1.
V
IN
SIGNAL ON
1dB
MAXIMUM DEASSERT LEVEL
6dB
MAXIMUM POWER-DETECT WINDOW
MINIMUM ASSERT LEVEL
SIGNAL OFF
0V
TIME
Figure 1. Signal Levels for LOS Assert/Deassert Time
Measurement
_______________________________________________________________________________________
3
+2.97V to +5.5V, 125Mbps to 200Mbps Limiting
Amplifier with Loss-of-Signal Detector
Typical Operating Characteristics
(V = 3.3V, PECL outputs terminated with 5ꢀΩ to V - 2V, R = 1ꢀꢀΩ, C = ꢀ.1µF, C = 1nF, T = +25°C, unless otherwise noted.)
CC
CC
TH
AZ
SD
A
OUTPUT EYE DIAGRAM
P-P
SUPPLY CURRENT vs. TEMPERATURE
(EXCLUDES PECL OUTPUT CURRENTS)
OUTPUT EYE DIAGRAM
(V = 1500mV , 155Mbps, 223 - 1PRBS)
(V = 1mV , 155Mbps, 223 - 1PRBS)
IN
IN
P-P
MAX3654 toc02
MAX3645 toc03
50
45
40
35
30
25
20
15
10
5
200mV/
div
200mV/
div
V
= 5.0V
CC
V
= 3.3V
60
CC
1ns/div
-40
-15
10
35
85
1ns/div
TEMPERATURE (°C)
INPUT-REFERRED RMS NOISE
vs. TEMPERATURE
BIT-ERROR RATIO vs.
DIFFERENTIAL INPUT VOLTAGE
TRANSFER FUNCTION
10-3
85
80
75
70
65
60
55
50
45
40
35
30
25
20
15
2000
1800
1600
1400
1200
1000
800
155Mbps, 223 - 1 PRBS
10-4
10-5
10-6
10-7
10-8
R
= 0Ω
TH
R
= 100Ω
TH
V
CC
= +5.0V
R
= 1kΩ
TH
10-9
10-10
10-11
10-12
R
= 2kΩ
TH
V
= +3.3V
CC
600
400
-40
-15
10
35
60
85
0.01
0.1
1
10
100
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8
TEMPERATURE (°C)
DIFFERENTIAL INPUT VOLTAGE (mV
)
P-P
DIFFERENTIAL INPUT VOLTAGE (mV
)
P-P
LOSS-OF-SIGNAL HYSTERESIS
vs. TEMPERATURE
LOSS-OF-SIGNAL THRESHOLD
SMALL-SIGNAL GAIN vs. R
vs. R (V = +3.3V AND +5.0V)
TH
TH CC
3.2
3.0
2.8
2.6
2.4
2.2
2.0
1.8
1.6
1.4
1.2
100
90
80
70
60
50
40
30
20
10
0
30
28
26
24
22
20
18
16
14
12
10
8
155Mbps, 223 - 1 PRBS
155Mbps, 223 - 1 PRBS
R
TH
= 2kΩ
LOS DEASSERT
R
= 1kΩ
TH
R
TH
= 100Ω
6
4
2
0
LOS ASSERT
V
= 0.1mV
IN
P-P
-40
-15
10
35
60
85
0
0.2 0.5 0.7 1.0 1.2 1.5 1.7 2.0
(kΩ)
0
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
TEMPERATURE (°C)
R
R
TH
(kΩ)
TH
4
_______________________________________________________________________________________
+2.97V to +5.5V, 125Mbps to 200Mbps Limiting
Amplifier with Loss-of-Signal Detector
Typical Operating Characteristics (continued)
(V = 3.3V, PECL outputs terminated with 5ꢀΩ to V - 2V, R = 1ꢀꢀΩ, C = ꢀ.1µF, C = 1nF, T = +25°C, unless otherwise noted.)
CC
CC
TH
AZ
SD
A
LOSS-OF-SIGNAL WITH SQUELCH
(155Mbps, 223 - 1PRBS)
PULSE-WIDTH DISTORTION
vs. DIFFERENTIAL INPUT VOLTAGE
MAX3654 toc10
100
90
80
70
60
50
40
30
20
10
0
155Mbps 0011 PATTERN
V
IN
V
OUT
LOS
10µs/div
0.1
1
10
100
1000 10,000
DIFFERENTIAL INPUT VOLTAGE (mV
)
P-P
DATA OUTPUT TRANSITION TIME
vs. DIFFERENTIAL INPUT VOLTAGE
3.0
2.5
2.0
1.5
1.0
0.5
0
0.1
1
10
100
1000 10,000
DIFFERENTIAL INPUT VOLTAGE (mV
)
P-P
_______________________________________________________________________________________
5
+2.97V to +5.5V, 125Mbps to 200Mbps Limiting
Amplifier with Loss-of-Signal Detector
Pin Description
MINDSPEED
MAXIM
MC2045-2
MC2045-2Y
PIN NAME
PIN
MAX3645
PIN NAME
FUNCTION
Offset-Correction-Loop Capacitor Connection. A capacitor connected between this pin and
CAZ1 sets the time constant of the offset correction loop. The offset correction is disabled
when the CAZ1 and CAZ2 pins are shorted together.
1
2
CAZ-
CAZ2
CAZ1
Offset-Correction-Loop Capacitor Connection. A capacitor connected between this pin and
CAZ2 sets the time constant of the offset correction loop. The offset correction is disabled
when the CAZ2 and CAZ1 pins are shorted together.
CAZ+
GNDA
3
4
5
6
GNDA
DIN+
DIN-
Analog Supply Ground. Must be at the same potential as the GNDE pin.
D
D
Positive Data Input
Negative Data Input
IN
IN
V
V
+2.97V to +5.5V Analog Supply Voltage. Must be at same potential as the V
pin.
CCA
CCA
CCE
7
C
CSD
Signal-Detect-Filter Capacitor Connection. Connect the C capacitor between CSD and V
.
F
SD
CCA
Disable Input, PECL or CMOS Compatible. Data outputs are held to a static logic ꢀ when DIS is
asserted high. The LOS function remains active when the outputs are disabled. When
connected to the LOS pin, an automatic squelch function is enabled.
8
JAM
DIS
Positive Loss-of-Signal Output, PECL. LOS is high when the level of the input signal drops
below the threshold set by the TH input. LOS is low when the signal level is above the
threshold. LOS can be connected directly to DIS for automatic squelch.
9
ST
LOS
Negative Loss-of-Signal Output, PECL. LOS is low when the level of the input signal drops
below the threshold set by the TH input. LOS is high when the signal level is above the
threshold.
1ꢀ
ST
LOS
11
12
13
14
15
GNDE
GNDE
DOUT-
DOUT+
Digital Supply Ground. Must be at the same potential as the GNDA pin.
Negative Data Output, PECL. A high at DIS forces DOUT- high.
Positive Data Output, PECL. A high at DIS forces DOUT+ low.
D
OUT
D
OUT
V
CCE
V
+2.97V to +5.5V Digital Supply Voltage. Must be at the same potential as the V
pin.
CCA
CCE
NC
N.C.
No Connection
Loss-of-Signal Threshold Pin. Resistor (R ) to ground sets the LOS threshold. This pin cannot
TH
be left open.
16
V
SET
TH
tance variation (3.3kΩ to 6.4kΩ) must be considered to
Detailed Description
The MAX3645 consists of gain stages, offset correction,
power detector, LOS indicators, and PECL output buffers.
See Figure 2 for the functional diagram.
accurately calculate the -3dB frequency. Capacitor val-
ues should be chosen that set the -3dB frequency at
least a factor of 1ꢀ below the lowest frequency of inter-
est. A capacitor value of ꢀ.1µF is recommended.
Data Input
Gain Stage and Offset Correction
The data inputs have a single-ended input resistance of
The limiting amplifier provides approximately 74dB
TH
4.8kΩ and are internally DC-biased to V
- ꢀ.87V (see
CC
(R = 1ꢀꢀΩ) of gain. This large gain makes the ampli-
Figure 3). External capacitors are required to AC-cou-
ple the data signals. Pattern-dependent jitter is mini-
mized by using coupling capacitor values large enough
to pass the lowest frequencies of interest (consecutive
ones and zeros) with the given input resistance.
fier susceptible to small DC offsets in the signal path.
To correct DC offsets, the amplifier has an internal feed-
back loop that acts as a DC autozero circuit. By cor-
recting the DC offsets, the limiting amplifier improves
receiver sensitivity and power-detector accuracy.
Typically, ꢀ.1µF coupling capacitors yield a -3dB fre-
quency of 354Hz. Capacitor tolerance and input resis-
6
_______________________________________________________________________________________
+2.97V to +5.5V, 125Mbps to 200Mbps Limiting
Amplifier with Loss-of-Signal Detector
V
CC
TH
CSD
V
CC
V
- 0.87V
CC
LOS
LOS
4.8kΩ
4.8kΩ
POWER
DETECTOR
MAX3645
DIN+
DIN-
DOUT+
DOUT-
DIS
DIN+
DIN-
OFFSET
CORRECTION
ESD
STRUCTURES
C
INT
CAZ1
CAZ2
Figure 2. Functional Diagram
Figure 3. Equivalent Data Input Circuit
The external autozero capacitor (C ), in parallel with
detector time constant, which determines the LOS
assert/deassert time. With C = 1nF the assert/
deassert time is in the range of 2.3µs to 8ꢀµs. This pro-
vides a long enough time constant to avoid false trig-
gering due to variations in mark density.
AZ
internal capacitance (C ), determines the time con-
INT
SD
stant of the DC offset correction loop. With C = ꢀ.1µF
AZ
(recommended), the -3dB frequency cutoff of the signal
path is typically ꢀ.5kHz.
Power Detector and LOS Indicators
Disable Function
When the DIS input is forced high, the disable function
is enabled, which holds DOUT+ low and DOUT- high.
The disable function is used to prevent the data outputs
from toggling due to noise when no signal is present.
The LOS output can be connected to the DIS input for
automatic squelch.
The external resistor R sets the gain of the first limit-
TH
ing stage. This gain setting controls the threshold at
which the power detector indicates an LOS condition.
Power detection is accomplished by rectifying and low-
pass filtering the data signal, then comparing it to the
programmed threshold voltage. A hysteresis of 2dB
prevents the LOS output from chattering when the input
signal is near the threshold.
PECL Output Terminations
The proper termination for a PECL output is 5ꢀΩ to
PECL Output Buffer
The data outputs (DOUT+, DOUT-) and the loss-of-sig-
nal outputs (LOS+, LOS-) are PECL outputs. The equiv-
alent PECL output circuit is shown in Figure 4.
(V
- 2V), but other standard termination techniques
CC
can be used. For more information on PECL termina-
tions and how to interface with other logic families, refer
to Maxim Application Note HFAN-01.0: Introduction to
LVDS, PECL, and CML.
Applications Information
Layout Considerations
For best performance, use good high-frequency layout
techniques. Filter power supplies, keep ground con-
nections short, and use multiple vias where possible.
Power-supply decoupling should be placed close to
Programming LOS Assert/Deassert Levels
The appropriate value of R
is determined by using
TH
the Loss-Of-Signal Threshold vs. R
graph in the
TH
Typical Operating Characteristics.
the V
pins. Minimize the distance from the preampli-
CC
LOS Time Constant
fier and use controlled-impedance transmission lines to
interface with the outputs when possible.
The lowpass filter of the power detector comprises a
2ꢀkΩ on-chip resistor (R ) and an external capacitor
SD
(C ). The C
capacitor value determines the power-
SD
SD
_______________________________________________________________________________________
7
+2.97V to +5.5V, 125Mbps to 200Mbps Limiting
Amplifier with Loss-of-Signal Detector
Chip Information
TRANSISTOR COUNT: 1ꢀ26
V
CC
PROCESS: Silicon bipolar
DOUT+/LOS
DOUT+/LOS
ESD
STRUCTURES
Figure 4. Equivalent PECL Output Circuit
8
_______________________________________________________________________________________
+2.97V to +5.5V, 125Mbps to 200Mbps Limiting
Amplifier with Loss-of-Signal Detector
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
INCHES
MILLIMETERS
DIM
A
MIN
MAX
0.069
0.010
0.019
0.010
MIN
1.35
0.10
0.35
0.19
MAX
1.75
0.25
0.49
0.25
0.053
0.004
0.014
0.007
N
A1
B
C
e
0.050 BSC
1.27 BSC
E
0.150
0.228
0.016
0.157
0.244
0.050
3.80
5.80
0.40
4.00
6.20
1.27
E
H
H
L
VARIATIONS:
INCHES
1
MILLIMETERS
DIM
D
MIN
MAX
0.197
0.344
0.394
MIN
4.80
8.55
9.80
MAX
5.00
N
8
MS012
AA
TOP VIEW
0.189
0.337
0.386
D
8.75 14
10.00 16
AB
D
AC
D
C
A
B
0 -8
e
A1
L
FRONT VIEW
SIDE VIEW
PROPRIETARY INFORMATION
TITLE:
PACKAGE OUTLINE, .150" SOIC
APPROVAL
DOCUMENT CONTROL NO.
REV.
1
21-0041
B
1
_______________________________________________________________________________________
9
+2.97V to +5.5V, 125Mbps to 200Mbps Limiting
Amplifier with Loss-of-Signal Detector
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
PACKAGE OUTLINE, QSOP .150", .025" LEAD PITCH
1
21-0055
E
1
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
10 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2ꢀꢀ3 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
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MAX3645ESE
+2.97V to +5.5V, 125Mbps to 200Mbps Limiting Amplifier with Loss-of-Signal Detector
MAXIM
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