MAX3640UCM+T [MAXIM]

Cross Point Switch, 1 Func, 8 Channel, PQFP48, 7 X 7 X 1.40 MM, TQFP-48;
MAX3640UCM+T
型号: MAX3640UCM+T
厂家: MAXIM INTEGRATED PRODUCTS    MAXIM INTEGRATED PRODUCTS
描述:

Cross Point Switch, 1 Func, 8 Channel, PQFP48, 7 X 7 X 1.40 MM, TQFP-48

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19-4800; Rev 0; 3/00  
3.3V, 622Mbps LVDS,  
Dual 4:2 Crosspoint Switch  
General Description  
Features  
The MAX3640 is a dual-path crosspoint switch for use  
at OC-12 data rates. The MAX3640 can be used to  
receive and transmit 622Mbps low-voltage differential  
signals (LVDS) across a backplane with minimum jitter  
accumulation. Each path incorporates input buffers,  
multiplexers, a crosspoint switch, and output drivers.  
The four output channels have a redundant set of out-  
puts for test or fanning purposes. The device offers sig-  
nal-path redundancy for critical data streams.  
Single +3.3V Supply  
257mW Power Consumption (four output  
channels enabled)  
2.8ps  
Output Random Jitter  
RMS  
42ps Output Deterministic Jitter  
Power-Down Feature for Deselected Outputs  
110ps Channel-to-Channel Skew  
240ps Output Edge Speed  
The MAX3640 has a unique power-saving feature.  
When a set of four output channels has been de-select-  
ed, the output drivers are powered down to reduce  
power consumption by 165mW. The fully differential  
architecture ensures low crosstalk, jitter accumulation,  
and signal skew.  
LVDS Inputs/Outputs  
LVDS Output 3-State Enable  
The MAX3640 is available in a 48-pin TQFP package  
and operates from a +3.3V supply over the 0°C to  
+85°C temperature range.  
Ordering Information  
Applications  
SONET/SDH Backplanes  
High-Speed Parallel Links  
Digital Cross-Connects  
System Interconnects  
ATM Switch Cores  
PART  
TEMP. RANGE  
PIN-PACKAGE  
MAX3640UCM  
0°C to +85°C  
48 TQFP  
Pin Configuration appears at end of data sheet.  
Typical Operating Circuit  
SONET  
SOURCE A  
MAX3869  
MAX3640  
CROSSPOINT  
SWITCH  
LASER DRIVER  
MAX3831  
4-CHANNEL  
INTERCONNECT  
MUX/DEMUX  
OPTICAL  
2.5Gbps  
TRANSCEIVER  
SONET  
SOURCE B  
622Mbps  
622Mbps  
MAX3866  
TIA AND LA  
MAX3876  
CDR  
PARALLEL DATA  
OUTPUT  
________________________________________________________________ Maxim Integrated Products  
1
For free samples and the latest literature, visit www.maxim-ic.com or phone 1-800-998-8800.  
For small orders, phone 1-800-835-8769.  
3.3V, 622Mbps LVDS,  
Dual 4:2 Crosspoint Switch  
ABSOLUTE MAXIMUM RATINGS  
Supply Voltage, V ................................................-0.5V to 5.0V  
Operating Temperature Range...............................0°C to +85°C  
Storage Temperature Range............................ -55°C to +150°C  
Lead Temperature (soldering, 10s) .................................+300°C  
CC  
Input Voltage (LVDS, TTL)..........................-0.5V to (V  
Output Voltage (LVDS)...............................-0.5V to (V  
+ 0.5V)  
+ 0.5V)  
CC  
CC  
Continuous Power Dissipation (T = +85°C)  
A
48-Pin TQFP (derate 12.5mW/°C) .................................813mW  
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional  
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to  
absolute maximum rating conditions for extended periods may affect device reliability.  
DC ELECTRICAL CHARACTERISTICS  
CC  
unless otherwise noted.)  
(V  
= +3.0V to 3.6V, LVDS differential load = 1001ꢀ, T = 0°C to +85°C. Typical values are at V  
= +3.3V, T = +25°C,  
CC A  
A
PARAMETER  
SYMBOL  
CONDITIONS  
Eight outputs enabled  
Four outputs enabled  
MIN  
TYP  
130  
78  
MAX  
UNITS  
175  
Supply Current  
I
mA  
CC  
LVDS INPUTS AND OUTPUTS  
Input Voltage Range  
V
0
2400  
100  
mV  
mV  
mV  
IN  
Differential Input Threshold  
Threshold Hysteresis  
V
IDTH  
HYST  
-100  
V
90  
Differential Input Impedance  
Input Common-Mode Current  
Output Voltage High  
R
85  
100  
245  
115  
1.475  
400  
25  
IN  
I
LVDS input, V = 1.2V  
OS  
µA  
V
OS  
V
Figure 1  
Figure 1  
Figure 1  
OH  
Output Voltage Low  
V
0.925  
250  
V
OL  
Output Voltage Swing  
|V  
OD  
|
mV  
Change in Magnitude of  
Differential Output for  
Complementary States  
|V  
|
mV  
mV  
mV  
OD  
Offset Output Voltage  
V
Figure 1  
1.125  
1.275  
25  
OS  
Change in Magnitude of  
Output Offset Voltage for  
Complementary States  
|V  
|
OS  
ENA, ENB = GND  
1
MΩ  
Differential Output Impedance  
ENA, ENB = V  
80  
120  
12  
CC  
Output Current  
Shorted together  
mA  
TTL INPUTS  
Input Voltage High  
Input Voltage Low  
Input Current High  
Input Current Low  
V
2.0  
V
V
IH  
V
0.8  
IL  
I
V
V
= 2.0V  
= 0.8V  
-250  
-550  
µA  
µA  
IH  
IH  
IL  
I
IL  
2
_______________________________________________________________________________________  
3.3V, 622Mbps LVDS,  
Dual 4:2 Crosspoint Switch  
AC ELECTRICAL CHARACTERISTICS  
CC  
unless otherwise noted.) (Note 1)  
(V  
= +3.0V to 3.6V, LVDS differential load = 1001ꢀ, T = 0°C to +85°C. Typical values are at V  
= +3.3V, T = +25°C,  
CC A  
A
PARAMETER  
SYMBOL  
CONDITIONS  
MIN  
TYP  
622  
240  
2.8  
42  
MAX  
UNITS  
Mbps  
ps  
Parallel Input/Output Data Rate  
Output Rise/Fall Time  
t , t  
r
20ꢀ to 80ꢀ  
(Note 2)  
150  
350  
4
f
Output Random Jitter  
RJ  
DJ  
ps  
RMS  
Output Deterministic Jitter  
LVDS Output Differential Skew  
200  
50  
ps  
ps  
t
t
24  
SKEW1  
LVDS Output Channel-to-  
Channel Skew  
110  
ps  
SKEW2  
LVDS Output Enable Time  
LVDS Output Disable Time  
266  
66  
ns  
ns  
LVDS Propagation Delay from  
Input to Output  
t
2.5  
ns  
D
Note 1: AC characteristics are guaranteed by design and characterization.  
Note 2: Deterministic jitter (DJ) is the arithmetic sum of pattern-dependent jitter and pulse-width distortion. DJ is measured while  
applying 100mVp-p noise (f 2MHz) to the power supply.  
V
OH  
125mV MIN  
200mV MAX  
250mV MIN  
400mV MAX  
LVDS+  
SINGLE ENDED  
V
= 1.2V ±±5mV  
OS  
V
OL  
V
OH  
250mV MIN  
400mV MAX  
V
OS  
= 1.2V ±±5mV  
125mV MIN  
200mV MAX  
LVDS-  
SINGLE ENDED  
V
OL  
V
OD  
250mV MIN  
400mV MAX  
500mV MIN  
800mV MAX  
0
(LVDS+) - (LVDS-)  
DIFFERENTIAL OUTPUT  
VOLTAGE  
Figure 1. LVDS Output Levels  
_______________________________________________________________________________________  
3
3.3V, 622Mbps LVDS,  
Dual 4:2 Crosspoint Switch  
Typical Operating Characteristics  
(V  
= +3.3V, T = +25°C, unless otherwise noted.)  
CC  
A
DIFFERENTIAL OUTPUT VOLTAGE  
SUPPLY CURRENT vs. TEMPERATURE  
vs. TEMPERATURE  
150  
640  
140  
130  
630  
620  
610  
600  
590  
580  
570  
560  
8 OUTPUTS ENABLED  
4 OUTPUTS ENABLED  
120  
110  
100  
90  
80  
±0  
60  
50  
0
10 20 30 40 50 60 ±0 80  
TEMPERATURE (°C)  
0
20  
40  
60  
80  
TEMPERATURE (°C)  
622Mbps EYE DIAGRAM  
1.25Gbps EYE DIAGRAM  
13  
13  
INPUT = 2 - 1 PRBS  
INPUT = 2 - 1 PRBS  
CONTAINS 100 ZEROS  
CONTAINS 100 ZEROS  
100mV/div  
100mV/div  
200ps/div  
100ps/div  
4
_______________________________________________________________________________________  
3.3V, 622Mbps LVDS,  
Dual 4:2 Crosspoint Switch  
Pin Description  
PIN  
NAME  
FUNCTION  
1, 12, 25, 36,  
41  
V
Positive Supply Voltage  
CC  
2, 11, 26, 35  
3, 5, 45, 47  
GND  
Supply Ground  
DIA3+, DIA4+, DIA1+,  
DIA2+  
Positive LVDS, Channel-A Data Input  
DIA3-, DIA4-, DIA1-,  
DIA2-  
4, 6, 46, 48  
7, 9, 13, 15  
Negative LVDS, Channel-A Data Input  
Positive LVDS, Channel-B Data Input  
DIB1+, DIB2+, DIB3+,  
DIB4+  
DIB1-, DIB2-, DIB3-,  
DIB4-  
8, 10, 14, 16  
1720  
Negative LVDS, Channel-B Data Input  
Crosspoint Switch Select, TTL Input. (Table 1)  
Negative LVDS, Channel-B Data Output  
SEL1SEL4  
DOB4-, DOB3-, DOB2-,  
DOB1-  
21, 23, 27, 29  
DOB4+, DOB3+,  
DOB2+, DOB1+  
22, 24, 28, 30  
Positive LVDS, Channel-B Data Output  
Negative LVDS, Channel-A Data Output  
Positive LVDS, Channel-A Data Output  
DOA4-, DOA3-, DOA2-,  
DOA1-  
31, 33, 37, 39  
DOA4+, DOA3+,  
DOA2+, DOA1+  
32, 34, 38, 40  
Channel-B Output Enable, TTL Input. ENB = high enables DOB1DOB4.  
ENB = low powers down DOB1DOB4 and sets them to a high-impedance state.  
42  
43  
44  
ENB  
ENA  
Channel-A Output Enable, TTL Input. ENA = high enables DOA1DOA4.  
ENA = low powers down DOA1DOA4 and sets them to a high-impedance state.  
Input Select Pin, TTL Input. Connect to logic high (or V ) to select DIA1DIA4.  
CC  
IN_SEL  
Connect to logic low (or GND) to select DIB1DIB4.  
LVDS Inputs and Outputs  
Detailed Description  
The MAX3640 features LVDS inputs and outputs for  
interfacing with high-speed digital circuitry. The LVDS  
standard is based on the IEEE 1596.3 LVDS specifica-  
tion. This technology uses 500mV to 800mV differential  
low-voltage swings to achieve fast transition times, low  
power dissipation, and improved noise immunity.  
Figure 2 shows the MAX3640s architecture. It consists  
of two data paths; each data path begins with four dif-  
ferential input buffers. The IN_SEL pin selects whether  
the A or B channels are passed to the 2x2 crosspoint  
switch that follows. The SEL_ pins control the routing of  
the crosspoint switch. Each crosspoint switch output  
drives a pair of LVDS output drivers. This provides a  
redundant set of outputs that can be used for fan-out  
or test purposes. Each set of outputs, DOA_ and  
DOB_, is enabled or disabled by the ENA and ENB  
pins. See Table 1 for routing controls.  
For proper operation, the data outputs require 100dif-  
ferential termination between the inverting and nonin-  
verting pins. Do not terminate these outputs to ground.  
See Figure 1 for LVDS output voltage specifications.  
The data inputs are internally terminated with 100dif-  
ferential and therefore do not require external termina-  
tion.  
_______________________________________________________________________________________  
5
3.3V, 622Mbps LVDS,  
Dual 4:2 Crosspoint Switch  
2x2 CROSSPOINT  
SWITCH  
MAX3640  
DIA1+  
DOA1+  
DOA1-  
1
0
DIA1-  
DIB1+  
DOB1+  
1
0
DIB1-  
DIA2+  
DOB1-  
SEL1  
DOA2+  
DOA2-  
1
0
DIA2-  
DIB2+  
DOB2+  
DOB2-  
SEL2  
1
0
DIB2-  
2x2 CROSSPOINT  
SWITCH  
DIA3+  
DIA3-  
DOA3+  
DOA3-  
1
0
0
1
DIB3+  
DIB3-  
DOB3+  
DOB3-  
SEL3  
DIA4+  
DIA4-  
DOA4+  
DOA4-  
1
0
0
1
DIB4+  
DIB4-  
DOB4+  
DOB4-  
SEL4  
IN_SEL  
ENA  
ENB  
Figure 2. Functional Diagram  
6
_______________________________________________________________________________________  
3.3V, 622Mbps LVDS,  
Dual 4:2 Crosspoint Switch  
Table 1. Output Routing  
ROUTING CONTROLS  
OUTPUT SIGNALS  
IN_SEL  
SEL1  
SEL2  
Signal at DOA1/DOB1  
Signal at DOA2/DOB2  
0
0
0
0
1
DIB1  
DIB1  
0
DIB1  
DIB2  
0
1
0
DIB2  
DIB1  
0
1
1
DIB2  
DIB2  
1
0
0
DIA1  
DIA1  
1
0
1
DIA1  
DIA2  
1
1
0
DIA2  
DIA1  
1
1
1
DIA2  
DIA2  
IN_SEL  
SEL3  
0
SEL4  
0
Signal at DOA3/DOB3  
Signal at DOA4/DOB4  
0
0
0
0
1
1
1
DIB3  
DIB3  
DIB4  
DIB4  
DIA3  
DIA3  
DIA4  
DIB3  
DIB4  
DIB3  
DIB4  
DIA3  
DIA4  
DIA3  
0
1
1
0
1
1
0
0
0
1
1
0
1
1
1
DIA4  
DIA4  
Note: Disabling the outputs by using ENA or ENB will drive the DOA_ or DOB_ data outputs to a high-impedance state.  
+3.3V  
182Ω  
48Ω  
48Ω  
Z = 50Ω  
o
LVPECL  
DRIVER  
MAX3640  
Z = 50Ω  
o
48Ω  
182Ω  
48Ω  
+3.3V  
Figure 3. LVPECL to LVDS Interface  
_______________________________________________________________________________________  
7
3.3V, 622Mbps LVDS,  
Dual 4:2 Crosspoint Switch  
Layout Techniques  
Applications Information  
For best performance, use good high-frequency layout  
techniques. Filter voltage supplies, and keep ground  
connections short. Use multiple vias where possible.  
Also, use controlled-impedance transmission lines to  
interface with the MAX3640 data inputs and outputs.  
Interfacing LVPECL Outputs to  
MAX3640 LVDS Inputs  
To DC-couple between LVPECL and LVDS, use the  
resistor network shown in Figure 3. Note that the  
LVPECL output is optimized for a 50load to V  
- 2V,  
CC  
Interface Models  
Figure 4 shows the interface model for the LVDS  
inputs, while Figure 5 shows the model for the LVDS  
outputs.  
so an equivalent network is used. Also, the network  
attenuation should be such that the LVPECL output sig-  
nal after attenuation is well within the LVDS input range.  
Note that the LVDS input impedance is a true 100Ω  
between the inputs. The differential impedance does  
not contribute to the DC termination impedance, but  
does contribute to the AC termination impedance. This  
means that AC and DC impedance will always be dif-  
ferent.  
V
CC  
V
25k  
CC  
MAX3640  
1.5k  
DIA1+  
5k  
50Ω  
50Ω  
V
CC  
DIA1-  
1.5k  
Figure 4. LVDS Input Model  
8
_______________________________________________________________________________________  
3.3V, 622Mbps LVDS,  
Dual 4:2 Crosspoint Switch  
Chip Information  
V
CC  
TRANSISTOR COUNT: 2453  
V
CC  
DOA1+  
DOA1-  
45Ω  
45Ω  
V
CC  
MAX3640  
Figure 5. LVDS Output Model  
Pin Configuration  
V
V
1
2
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
CC  
CC  
GND  
GND  
DIA3+  
DIA3-  
DIA4+  
DIA4-  
DIB1+  
DIB1-  
DIB2+  
DIB2-  
GND  
DOA3+  
DOA3-  
DOA4+  
DOA4-  
DOB1+  
DOB1-  
DOB2+  
DOB2-  
GND  
3
4
5
6
MAX3640  
7
8
9
10  
11  
12  
V
V
CC  
CC  
_______________________________________________________________________________________  
9
3.3V, 622Mbps LVDS,  
Dual 4:2 Crosspoint Switch  
Package Information  
10 ______________________________________________________________________________________  
3.3V, 622Mbps LVDS,  
Dual 4:2 Crosspoint Switch  
NOTES  
______________________________________________________________________________________ 11  
3.3V, 622Mbps LVDS,  
Dual 4:2 Crosspoint Switch  
NOTES  
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are  
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.  
12 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600  
© 2000 Maxim Integrated Products  
Printed USA  
is a registered trademark of Maxim Integrated Products.  

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