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MAX3302EEBA [MAXIM]

Line Driver/Receiver, 1 Driver, BICMOS, PBGA25;
MAX3302EEBA
型号： MAX3302EEBA
厂家： MAXIM INTEGRATED PRODUCTS    MAXIM INTEGRATED PRODUCTS
描述：

Line Driver/Receiver, 1 Driver, BICMOS, PBGA25

泵
文件： 总35页 (文件大小：869K)
中文：  中文翻译
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19-3275; Rev 2; 1/06  
USB On-the-Go Transceivers and Charge Pumps  
General Description  
Features  
♦ USB 2.0-Compliant Full-/Low-Speed OTG  
The MAX3301E/MAX3302E fully integrated USB On-the-  
Go (OTG) transceivers and charge pumps allow mobile  
devices such as PDAs, cellular phones, and digital  
cameras to interface directly with USB peripherals and  
each other without the need of a host PC. Use the  
MAX3301E/MAX3302E with an embedded USB host to  
directly connect to peripherals such as printers or  
external hard drives.  
Transceivers  
♦ Ideal for USB On-the-Go, Embedded Host, or  
Peripheral Devices  
♦ ±±15k ESD Protection on IDꢀIꢁ, k  
, D+, and D-  
BUS  
Terminals  
♦ Charge Pump for k  
Signaling and Operation  
BUS  
Down to 3k  
The MAX3301E/MAX3302E integrate a USB OTG trans-  
♦ Internal k  
and ID Comparators  
BUS  
ceiver, a V  
charge pump, a linear regulator, and an  
BUS  
2
I C-compatible, 2-wire serial interface. An internal level  
shifter allows the MAX3301E/MAX3302E to interface  
with +1.65V to +3.6V logic supply voltages. The  
MAX3301E/MAX3302E’s OTG-compliant charge pump  
operates with +3V to +4.5V input supply voltages, and  
♦ Internal Switchable Pullup and Pulldown  
Resistors for Host/Peripheral Functionality  
♦ I2C Bus Interface with Command and Status  
Registers  
♦ Linear Regulator Powers Internal Circuitry and  
supplies an OTG-compatible output on V  
sourcing more than 8mA of output current.  
while  
BUS  
D+/D- Pullup Resistors  
♦ Support SRP and HꢁP  
The MAX3301E/MAX3302E enable USB OTG communi-  
cation from highly integrated digital devices that cannot  
Ordering Information  
PACKAGE  
supply or tolerate the +5V V  
levels that USB OTG  
BUS  
requires. The device supports USB OTG session-request  
protocol (SRP) and host-negotiation protocol (HNP).  
PIꢁ-  
PACKAGE  
PKG  
CODE  
PART  
SIZE  
(mm)  
The MAX3301E/MAX3302E provide built-in 15ꢀV elec-  
trostatic-discharge (ESD) protection for the V , ID_IN,  
BUS  
‡
MAX330±EEBA-T  
MAX3301EETJ  
2.5 x 2.5  
5 x 5  
25 UCSP  
B25-1  
D+, and D- terminals. The MAX3301E/MAX3302E are  
available in 25-bump chip-scale (UCSP™), 28-pin TQFN,  
and 32-pin TQFN pacꢀages and operate over the  
extended -40°C to +85°C temperature range.  
32 TQFN-EP** T3255-4  
‡
MAX3302EEBA-T*  
MAX3302EETI  
2.5 x 2.5  
4 x 4  
25 UCSP  
B25-1  
28 TQFN-EP** T2844-1  
Selector Guide  
Note: All devices specified over the -40°C to +85°C operating  
range.  
‡UCSP bumps are in a 5 x 5 array. The UCSP package size is  
2.5mm x 2.5mm x 0.62mm. Requires solder temperature profile  
described in the Absolute Maximum Ratings section. UCSP reli-  
ability is integrally linked to the user’s assembly methods, circuit  
board material and environment. See the UCSP Applications  
Information section of this data sheet for more information.  
*Future product—contact factory for availability.  
2
I C ADDRESSES FOR  
†
PART  
POWER-UP STATE  
SPECIAL-FUꢁCTIOꢁ  
REGISTER 2  
Shutdown (sdwn = 1,  
bit 0 of special-  
MAX330±E  
16h, 17h  
function register 2)  
**EP = Exposed paddle.  
Operating (sdwn = 1,  
MAX3302E bit 0 of special-  
10h, 11h, and 16h, 17h  
function register 2)  
Purchase of I2C components from Maxim Integrated Products,  
Inc. or one of its sublicensed Associated Companies, conveys a  
license under the Philips I2C Patent Rights to use these compo-  
nents in an I2C system, provided that the system conforms to the  
I2C Standard Specification as defined by Philips.  
†The MAX3301E powers up in its lowest power state and the  
MAX3302E powers up in the operational, VP/VM USB mode.  
UCSP is a trademark of Maxim Integrated Products, Inc.  
Applications  
Mobile Phones  
PDAs  
Digital Cameras  
MP3 Players  
Pin Configurations appear at end of data sheet.  
ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ Maxim Integrated Products  
±
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at  
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.  
USB On-the-Go Transceivers and Charge Pumps  
ABSOLUTE MAXIMUM RATIꢁGS  
All voltages are referenced to GND.  
Continuous Power Dissipation (T = +70°C)  
A
V
, V .....................................................................-0.3V to +6V  
5 x 5 UCSP (derate 12.2mW/°C above +70°C) ...........976mW  
32-Pin TQFN (5mm x 5mm x 0.8mm) (derate 21.3mW/°C  
above +70°C).............................................................1702mW  
28-Pin TQFN (4mm x 4mm x 0.8mm) (derate 20.8mW/°C  
above +70°C).............................................................1666mW  
Operating Temperature Range ...........................-40°C to +85°C  
Junction Temperature......................................................+150°C  
Storage Temperature Range.............................-65°C to +150°C  
Lead Temperature (soldering, 10s) .................................+300°C  
Bump Reflow Temperature (Note 1)  
CC  
L
TRM (regulator off or supplied by V  
TRM (regulator supplied by V )...............-0.3V to (V  
D+, D- (transmitter tri-stated) ...................................-0.3V to +6V  
D+, D- (transmitter functional)....................-0.3V to (V + 0.3V)  
)..-0.3V to (V  
+ 0.3V)  
BUS  
+ 0.3V)  
CC  
BUS  
CC  
CC  
V
.........................................................................-0.3V to +6V  
BUS  
ID_IN, SCL, SDA.......................................................-0.3V to +6V  
INT, SPD, RESET, ADD, OE/INT, RCV, VP,  
VM, SUS, DAT_VP, SE0_VM ......................-0.3V to (V + 0.3V)  
L
C+.............................................................-0.3V to (V  
C-................................................................-0.3V to (V  
Short-Circuit Duration, V  
+ 0.3V)  
+ 0.3V)  
BUS  
CC  
Infrared (15s) ...............................................................+200°C  
Vapor Phase (20s) .......................................................+215°C  
to GND .........................Continuous  
BUS  
ꢁote ±: The UCSP pacꢀage is constructed using a unique set of pacꢀaging techniques that impose a limit on the thermal profile the  
device can be exposed to during board-level solder attach and reworꢀ. This limit permits only the use of the solder profiles recom-  
mended in the industry-standard specification, JEDEC 020A, paragraph 7.6, Table 3 for IR/VPR and convection reflow. Preheating is  
required. Hand or wave soldering is not allowed.  
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional  
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to  
absolute maximum rating conditions for extended periods may affect device reliability.  
DC ELECTRICAL CHARACTERISTICS  
(V  
= +3V to +4.5V, V = +1.65V to +3.6V, C  
= 100nF, C  
= 1µF, ESR  
= 0.1Ω (max), T = T  
to T  
, unless  
CC  
L
FLYING  
VBUS  
CVBUS  
A
MIN  
MAX  
otherwise noted. Typical values are at V  
= +3.7V, V = +2.5V, T = +25°C.) (Note 2)  
CC  
L
A
PARAMETER  
Supply Voltage  
SYMBOL  
COꢁDITIOꢁS  
MIꢁ  
3.0  
TYP  
MAX  
4.5  
3.6  
3.60  
5
UꢁITS  
V
V
V
CC  
TRM Output Voltage  
Logic Supply Voltage  
V
3.0  
TRM  
V
1.65  
V
L
2
V Supply Current  
L
I
I C interface in steady state  
µA  
VL  
USB normal mode, C = 50pF, device  
L
switching at full speed  
V
Operating Supply Current  
I
10  
mA  
CC  
CC  
vbus_drv = 1, I  
= 0  
1.4  
0.5  
3.5  
2
VBUS  
V
Supply Current During Full-  
CC  
mA  
µA  
µA  
µA  
Speed Idle  
vbus_drv = 0, D+ = high, D- = low  
0.8  
10  
V
Shutdown Supply Current  
I
CC(SHDN)  
CC  
V
Interrupt Shutdown Supply  
CC  
I
ID_IN floating or high  
20  
30  
CC(ISHDN)  
Current  
Suspend Supply Current  
V
USB suspend mode, ID_IN floating or high  
170  
500  
CC  
LOGIC I/O  
RCV, DAT_VP, SE0_VM, INT,  
OE/INT, VP, VM Output High  
Voltage  
V
I
I
= 1mA (sourcing)  
= 1mA (sinꢀing)  
V - 0.4  
V
V
V
OH  
OUT  
L
RCV, DAT_VP, SE0_VM, INT,  
OE/INT, VP, VM Output Low  
Voltage  
V
0.4  
OL  
OUT  
OE/INT, SPD, SUS, RESET,  
DAT_VP, SE0_VM Input High  
Voltage  
V
2/3 x V  
L
IH  
2
ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ  
USB On-the-Go Transceivers and Charge Pumps  
DC ELECTRICAL CHARACTERISTICS (continued)  
(V  
= +3V to +4.5V, V = +1.65V to +3.6V, C  
= 100nF, C  
= 1µF, ESR  
= 0.1Ω (max), T = T  
to T  
, unless  
CC  
L
FLYING  
VBUS  
CVBUS  
A
MIN  
MAX  
otherwise noted. Typical values are at V  
= +3.7V, V = +2.5V, T = +25°C.) (Note 2)  
CC  
L
A
PARAMETER  
SYMBOL  
COꢁDITIOꢁS  
MIꢁ  
TYP  
MAX  
UꢁITS  
OE/INT, SPD, SUS, RESET  
DAT_VP, SE0_VM Input Low  
Voltage  
V
0.4  
V
IL  
ADD Input High Voltage  
ADD Input Low Voltage  
V
2/3 x V  
V
IHA  
L
V
1/3 x V  
V
ILA  
L
Input Leaꢀage Current  
1
µA  
TRAꢁSCEIkER SPECIFICATIOꢁS  
Differential Receiver Input  
Sensitivity  
|V - V  
D+  
|
0.2  
0.8  
V
V
V
V
D-  
Differential Receiver Common-  
Mode Voltage  
2.5  
0.8  
Single-Ended Receiver Input Low  
Voltage  
V
D+, D-  
D+, D-  
ILD  
Single-Ended Receiver Input  
High Voltage  
V
2.0  
2.8  
IHD  
Single-Ended Receiver Hysteresis  
Single-Ended Output Low Voltage  
Single-Ended Output High Voltage  
Off-State Leaꢀage Current  
0.2  
V
V
V
D+, D-, R = 1.5ꢀΩ from D+ or D- to 3.6V  
0.3  
3.6  
1
OLD  
L
V
D+, D-, R = 15ꢀΩ from D+ or D- to GND  
V
OHD  
L
D+, D-  
µA  
Low steady-state drive  
High steady-state drive  
2
2
13  
13  
D+, D-, not  
including R  
Driver Output Impedance  
Ω
EXT  
ESD PROTECTIOꢁ (k  
, IDꢀIꢁ, D+, D-)  
BUS  
Human Body Model  
15  
10  
6
ꢀV  
ꢀV  
ꢀV  
IEC 61000-4-2 Air-Gap Discharge  
IEC 61000-4-2 Contact Discharge  
THERMAL SHUTDOWꢁ  
Thermal Shutdown Low-to-High  
Thermal Shutdown High-to-Low  
+160  
+150  
oC  
oC  
CHARGE-PUMP SPECIFICATIOꢁS (vbusꢀdrv = ±)  
V
V
V
Output Voltage  
Output Current  
Output Ripple  
V
3V < V < 4.5V, C  
= 10µF, I = 8mA  
VBUS  
4.80  
8
5.25  
V
BUS  
BUS  
BUS  
BUS  
CC  
VBUS  
I
mA  
mV  
VBUS  
I
= 8mA, C  
= 10µF  
VBUS  
100  
VBUS  
ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ  
3
USB On-the-Go Transceivers and Charge Pumps  
DC ELECTRICAL CHARACTERISTICS (continued)  
(V  
= +3V to +4.5V, V = +1.65V to +3.6V, C  
= 100nF, C  
= 1µF, ESR  
= 0.1Ω (max), T = T  
to T , unless  
MAX  
CC  
L
FLYING  
VBUS  
CVBUS  
A
MIN  
otherwise noted. Typical values are at V  
= +3.7V, V = +2.5V, T = +25°C.) (Note 2)  
CC  
L
A
PARAMETER  
SYMBOL  
COꢁDITIOꢁS  
MIꢁ  
TYP  
MAX  
UꢁITS  
ꢀHz  
V
Switching Frequency  
f
390  
SW  
V
Leaꢀage Voltage  
vbus_drv = 0  
0.2  
BUS  
C
= 10µF, I  
= 8mA, measured  
VBUS  
VBUS  
V
Rise Time  
100  
ms  
BUS  
from 0 to +4.4V  
V
V
V
Pulldown Resistance  
Pullup Resistance  
Input Impedance  
vbus_dischrg = 1, vbus_drv = 0, vbus_chrg = 0  
vbus_chrg = 1, vbus_drv = 0, vbus_dischrg = 0  
vbus_dischrg = 0, vbus_drv = 0, vbus_chrg = 0  
3.8  
650  
40  
5
6.5  
1250  
100  
ꢀΩ  
Ω
BUS  
BUS  
BUS  
930  
70  
Z
ꢀΩ  
INVBUS  
COMPARATOR SPECIFICATIOꢁS  
V
V
Valid Comparator Threshold  
Valid Comparator Hysteresis  
V
4.4  
4.6  
50  
4.8  
V
BUS  
BUS  
TH-VBUS  
V
mV  
HYS-VBUS  
Session-Valid Comparator  
Threshold  
V
TH-  
SESS_VLD  
0.8  
0.2  
1.4  
0.5  
2.0  
0.8  
V
V
Session-End Comparator  
Threshold  
V
TH-  
SESS_END  
dp_hi Comparator Threshold  
dm_hi Comparator Threshold  
cr_int Pulse Width  
0.8  
0.8  
1.3  
1.3  
750  
0.5  
2.0  
2.0  
V
V
ns  
V
cr_int Comparator Threshold  
IDꢀIꢁ SPECIFICATIOꢁS  
0.4  
0.6  
0.2 x  
0.8 x  
V
CC  
ID_IN Input Voltage for Car Kit  
ID_IN Input Voltage for A Device  
ID_IN Input Voltage for B Device  
V
V
V
V
CC  
0.1 x  
V
CC  
0.9 x  
V
CC  
ID_IN Input Impedance  
Z
70  
-1  
100  
150  
130  
+1  
ꢀΩ  
µA  
Ω
ID_IN  
ID_IN Input Leaꢀage Current  
ID_IN Pulldown Resistance  
ID_IN = V  
CC  
id_pulldown = 1  
300  
TERMIꢁATIꢁG RESISTOR SPECIFICATIOꢁS (D+, D-)  
D+ Pulldown Resistor  
D- Pulldown Resistor  
D+ Pullup Resistor  
D- Pullup Resistor  
dp_pulldown = 1  
14.25  
14.25  
1.425  
1.425  
15  
15  
15.75  
15.75  
1.575  
1.575  
ꢀΩ  
ꢀΩ  
ꢀΩ  
ꢀΩ  
dm_pulldown = 1  
dp_pullup = 1  
dm_pullup = 1  
1.5  
1.5  
4
ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ  
USB On-the-Go Transceivers and Charge Pumps  
TIMIꢁG CHARACTERISTICS  
(V  
= +3V to +4.5V, V = +1.65V to +3.6V, C  
= 100nF, C  
= 1µF, ESR  
= 0.1Ω (max), T = T  
to T  
, unless  
CC  
L
FLYING  
VBUS  
CVBUS  
A
MIN  
MAX  
otherwise noted. Typical values are at V  
= +3.7V, V = +2.5V, T = +25°C.) (Note 2)  
CC  
L
A
PARAMETER  
SYMBOL  
COꢁDITIOꢁS  
MIꢁ  
TYP  
MAX  
UꢁITS  
TRAꢁSMITTER CHARACTERISTICS (FULL-SPEED MODE)  
D+, D- Rise Time  
t
Figures 2 and 5  
Figures 2 and 5  
4
4
20  
20  
ns  
ns  
%
V
R
D+, D- Fall Time  
t
F
Rise-/Fall-Time Matching  
Output-Signal Crossover Voltage  
Figures 2 and 5 (Note 3)  
90  
1.3  
110  
2.0  
V
Figures 2, 6, and 7 (Note 3)  
CRS_F  
TRAꢁSMITTER CHARACTERISTICS (LOW-SPEED MODE)  
D+, D- Rise Time  
t
Figures 2 and 5  
Figures 2 and 5  
Figures 2 and 5  
Figures 2, 6, and 7  
75  
75  
80  
1.3  
300  
300  
125  
2.0  
ns  
ns  
%
V
R
D+, D- Fall Time  
t
F
Rise-/Fall-Time Matching  
Output-Signal Crossover Voltage  
V
CRS_L  
TRAꢁSMITTER TIMIꢁG (FULL-SPEED MODE)  
t
t
Low-to-high, Figures 2 and 6  
High-to-low, Figures 2 and 6  
Figures 1 and 8  
25  
25  
25  
25  
PLH  
PHL  
PDZ  
PZD  
Driver Propagation Delay  
(DAT_VP, SE0_VM to D+, D-)  
ns  
Driver Disable Delay  
Driver Enable Delay  
t
t
ns  
ns  
Figures 2 and 8  
TRAꢁSMITTER TIMIꢁG (LOW-SPEED MODE) (Low-speed delay timing is dominated by the slow rise and fall times.)  
SPEED-IꢁDEPEꢁDEꢁT TIMIꢁG CHARACTERISTICS  
Receiver Disable Delay  
Receiver Enable Delay  
D+ Pullup Assertion Time  
RCV Rise Time  
t
t
Figure 4  
30  
30  
3
ns  
ns  
µs  
ns  
ns  
PVZ  
PZV  
Figure 4  
During HNP  
t
R
Figures 3 and 5, C = 15pF  
4
4
L
RCV Fall Time  
t
Figures 3 and 5, C = 15pF  
L
F
Figures 3 and 10, |D+ - D-| to DAT_VP  
Figures 3 and 9, |D+ - D-| to RCV  
30  
30  
Differential-Receiver Propagation  
Delay  
t
t
, t  
ns  
ns  
PHL PLH  
Single-Ended-Receiver  
Propagation Delay  
Figures 3 and 9, D+, D- to DAT_VP,  
SE0_VM  
, t  
30  
PHL PLH  
Interrupt Propagation Delay  
100  
µs  
µs  
µs  
µs  
V
Propagation Delay  
Dominated by the V  
rise time  
BUS  
0.2  
BUS_CHRG  
Time to Exit Shutdown  
Shutdown Delay  
1
10  
ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ  
1
USB On-the-Go Transceivers and Charge Pumps  
2
I C-/SMBus™-COMPATIBLE TIMIꢁG SPECIFICATIOꢁS  
(V  
= +3V to +4.5V, V = +1.65V to +3.6V, C  
= 100nF, C  
= 1µF, ESR  
= 0.1Ω (max), T = T  
to T  
, unless  
CC  
L
FLYING  
VBUS  
CVBUS  
A
MIN  
MAX  
otherwise noted. Typical values are at V  
= +3.7V, V = +2.5V, T = +25°C.) (Note 2)  
CC  
L
A
PARAMETER  
SYMBOL  
COꢁDITIOꢁS  
MIꢁ  
TYP  
MAX  
UꢁITS  
Serial Clocꢀ Frequency  
f
400  
ꢀHz  
SCL  
Bus-Free Time Between Stop and  
Start Conditions  
t
1.3  
µs  
BUF  
Start-Condition Hold Time  
Stop-Condition Setup Time  
Clocꢀ Low Period  
t
t
0.6  
0.6  
1.3  
0.6  
100  
µs  
µs  
µs  
µs  
ns  
µs  
HD_STA  
SU_STO  
t
LOW  
Clocꢀ High Period  
t
HIGH  
Data Setup Time  
t
SU_DAT  
HD_DAT  
Data Hold Time  
t
(Note 4)  
(Note 5)  
0.9  
20 +  
0.1 x  
Rise Time of SDA and SCL  
Fall Time of SDA and SCL  
t
300  
ns  
R
C
B
t
Measured from 0.3 x V to 0.7 x V (Note 5)  
300  
400  
ns  
F
L
L
Capacitive Load for each Bus  
Line  
C
pF  
B
SDA AꢁD SCL I/O STAGE CHARACTERISTICS  
0.3 x  
Input-Voltage Low  
Input-Voltage High  
V
V
V
IL  
V
L
0.7 x  
V
IH  
V
L
SDA Output-Voltage Low  
V
I
= 3mA  
0.4  
V
OL  
SINK  
Pulse Width of Suppressed Spiꢀe  
t
SP  
(Note 6)  
50  
ns  
ꢁote 2: Parameters are 100% production tested at +25°C. Limits over temperature are guaranteed by design.  
ꢁote 3: Guaranteed by bench characterization. Limits are not production tested.  
ꢁote 4: A master device must provide a hold time of at least 300ns for the SDA signal to bridge the undefined region of SCL’s falling  
edge.  
ꢁote 1: C is the total capacitance of one bus line in pF, tested with C = 400pF.  
B
B
ꢁote 6: Input filters on SDA, SCL, and ADD suppress noise spiꢀes of less than 50ns.  
SMBus™ is a trademark of Intel Corporation.  
6
ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ  
USB On-the-Go Transceivers and Charge Pumps  
Typical Operating Characteristics  
(Typical operating circuit, V  
= +3.7V, V = +2.5V, C  
= 100nF, T = +25°C, unless otherwise noted.)  
CC  
L
FLYING A  
INPUT CURRENT (I  
)
V
vs. V  
V
OUTPUT VOLTAGE  
CC  
BUS  
BUS  
vs. V  
OUTPUT CURRENT  
vs. INPUT VOLTAGE (V )  
BUS  
CC  
50  
40  
30  
20  
10  
0
5.50  
5.25  
5.00  
4.75  
4.50  
4.25  
4.00  
5.75  
5.50  
5.25  
5.00  
4.75  
4.50  
V
V
= 3.3V  
= 4.2V  
V
V
= 3.0V  
= 4.2V  
LINEAR REGULATOR  
POWERED BY V  
CC  
CC  
CC  
CC  
CC  
LINEAR REGULATOR  
POWERED BY V  
CC  
I
= 0  
VBUS  
I
= 8mA  
VBUS  
LINEAR REGULATOR  
POWERED BY V  
CC  
0
4
8
12  
16  
20  
0
5
10  
OUTPUT CURRENT (mA)  
BUS  
15  
20  
25  
30  
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0  
V
OUTPUT CURRENT (mA)  
V
INPUT VOLTAGE (V ) (V)  
CC  
BUS  
TIME TO ENTER SHUTDOWN  
TIME TO EXIT SHUTDOWN  
VBUS DURING SRP  
MAX3301E toc04  
MAX3301E toc05  
MAX3301E toc06  
D+  
D-  
1V/div  
1V/div  
V
BUS  
1V/div  
C
> 13µF  
VBUS  
D-  
D+  
1V/div  
1V/div  
V
BUS  
1V/div  
SCL  
SCL  
2V/div  
1V/div  
C
> 96µF  
VBUS  
100ns/div  
4µs/div  
20ns/div  
DRIVER PROPAGATION DELAY HIGH-TO-LOW  
DRIVER PROPAGATION DELAY LOW-TO-HIGH  
DRIVER PROPAGATION DELAY HIGH-TO-LOW  
(LOW-SPEED MODE)  
(LOW-SPEED MODE)  
(FULL-SPEED MODE)  
MAX3301E toc07  
MAX3301E toc08  
MAX3301E toc09  
DAT_VP  
DAT_VP  
DAT_VP  
1V/div  
1V/div  
1V/div  
D+  
1V/div  
D-  
1V/div  
D-  
1V/div  
D+  
1V/div  
D-  
1V/div  
D+  
1V/div  
100ns/div  
100ns/div  
4ns/div  
_______________________________________________________________________________________  
7
USB On-the-Go Transceivers and Charge Pumps  
Typical Operating Characteristics (continued)  
(Typical operating circuit, V  
= +3.7V, V = +2.5V, C  
= 100nF, T = +25°C, unless otherwise noted.)  
CC  
L
FLYING A  
DRIVER PROPAGATION DELAY LOW-TO-HIGH  
DRIVER ENABLE DELAY  
(FULL-SPEED MODE)  
DRIVER DISABLE DELAY  
(FULL-SPEED MODE)  
MAX3301E toc12  
(FULL-SPEED MODE)  
MAX3301E toc10  
MAX3301E toc11  
OE/INT  
1V/div  
DAT_VP  
1V/div  
OE/INT  
1V/div  
D+  
1V/div  
D+  
1V/div  
D-  
1V/div  
D-  
1V/div  
D+  
1V/div  
D-  
1V/div  
4ns/div  
10ns/div  
10ns/div  
DRIVER ENABLE DELAY  
(LOW-SPEED MODE)  
DRIVER DISABLE DELAY  
(LOW-SPEED MODE)  
SUPPLY CURRENT  
vs. TEMPERATURE  
MAX3301E toc13  
MAX3301E toc14  
1.0  
0.8  
0.6  
0.4  
0.2  
0
OE/INT  
1V/div  
OE/INT  
1V/div  
V
V
= 4.2V  
= 3.3V  
CC  
CC  
D+  
1V/div  
D-  
1V/div  
D-  
1V/div  
D+  
1V/div  
V
OFF  
BUS  
FULL-SPEED IDLE  
C
= C = 400pF  
D-  
D+  
100ns/div  
10ns/div  
-40 -15 10  
35  
60  
85  
TEMPERATURE (°C)  
8
ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ  
USB On-the-Go Transceivers and Charge Pumps  
Pin Description  
PIꢁ  
ꢁAME  
FUꢁCTIOꢁ  
MAX3302E  
28-PIꢁ TQFꢁ  
MAX330±E  
32-PIꢁ TQFꢁ  
UCSP  
System-Side Data Input/Output. DAT_VP is an input if OE/INT is logic 0.  
1
2
D2  
DAT_VP DAT_VP is an output if OE/INT is logic 1. Program the function of DAT_VP  
with the dat_se0 bit (bit 2 of control register 1, see Table 7).  
Input Power Supply. Connect a +3V to +4.5V supply to V  
GND with a 1µF capacitor. The supply range enables direct powering from  
one Li+ battery.  
and bypass to  
CC  
D1,  
E3  
2, 25  
3, 29  
V
CC  
1, 4, 9, 12, 17,  
25, 28  
3, 9, 23  
4
—
N.C.  
C-  
No Connection. Not internally connected.  
5
C1  
Charge-Pump Flying-Capacitor Negative Terminal  
System-Side Data Input/Output. SE0_VM is an input if OE/INT is logic 0.  
5
6
C2  
SE0_VM SE0_VM is an output if OE/INT is logic 1. Program the function of SE0_VM  
with the dat_se0 bit (bit 2 of control register 1, see Table 7).  
B1,  
C5  
6, 18  
7, 21  
GND  
Ground  
2
7
8
8
A1  
B2  
SDA  
SCL  
I C-Compatible Serial Data Interface. Open-drain data input/output.  
2
10  
I C-Compatible Serial Clocꢀ Input  
Output Enable. OE  /INT controls the input or output status of DAT_VP/SE0_VM  
and D+/D-. When OE  /INT is logic 0, the device is in transmit mode. When  
OE  /INT is logic 1, the device is in receive mode. When in suspend mode,  
OE  /INT can be programmed to function as an interrupt output that detects the  
same interrupts as INT. The oe_int_en bit (bit 5 of control register 1, see Table  
7) enables and disables the interrupt circuitry of OE  /INT. The irq_mode bit (bit 1  
of special-function register 2, see Table 15) programs the output configuration  
of INT and OE  /INT as open-drain or push-pull.  
10  
11  
A2  
OE/INT  
D+ and D- Differential Receiver Output. In receive mode (see Table 4), when  
D+ is high and D- is low, RCV is high. In receive mode, when D+ is low and  
D- is high, RCV is low. RCV is low in suspend mode.  
11  
12  
13  
14  
A3  
B3  
RCV  
SPD  
Speed-Selector Input. Connect SPD to GND to select the low-speed data rate  
(1.5Mbps). Connect SPD to V to select the full-speed data rate (12Mbps).  
L
Disable the SPD input by writing a 1 to spd_susp_ctl (bit 1 in special-function  
register 1, see Table 14). The speed bit (bit 0 of control register 1, see Table  
7) determines the maximum data rate of the MAX3301E/MAX3302E when the  
SPD input is disabled.  
System-Side Logic-Supply Input. Connect to the system’s logic-level power  
supply, +1.65V to +3.6V. This sets the maximum output levels of the logic  
outputs and the input thresholds of the logic inputs. Bypass to GND with a  
0.1µF capacitor.  
13  
14  
15  
16  
A4  
A5  
V
L
Active-High Suspend Input. Drive SUS low for normal USB operation. Drive  
SUS high to enable suspend mode. RCV asserts low in suspend mode.  
Disable the SUS input by writing a 1 to spd_susp_ctl (bit 1 in special-function  
register 1, see Table 14). The suspend bit (bit 1 of control register 1, see  
Table 7) determines the operating mode of the MAX3301E/MAX3302E when  
the SUS input is disabled.  
SUS  
ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ  
9
USB On-the-Go Transceivers and Charge Pumps  
Pin Description (continued)  
PIꢁ  
ꢁAME  
FUꢁCTIOꢁ  
MAX3302E  
28-PIꢁ TQFꢁ  
MAX330±E  
32-PIꢁ TQFꢁ  
UCSP  
Active-Low Interrupt Source. Program the INT output as push-pull or open-  
drain with the irq_mode bit (bit 1 of special-function register 2, see Tables 15  
and 16).  
15  
18  
B4  
INT  
Active-Low Reset Input. Drive RESET low to asynchronously reset the  
MAX3301E/MAX3302E.  
16  
17  
19  
19  
20  
22  
B5  
C3  
C4  
RESET  
ADD  
2
I C-Interface Address Selection Input. (See Table 5.)  
ID Input. ID_IN is internally pulled up to V . The state of ID_IN determines  
CC  
ID bits 3 and 5 of the interrupt source register (see Table 10).  
ID_IN  
USB Differential Data Input/Output. Connect D- to the D- terminal of the USB  
connector through a 27.4Ω 1% series resistor.  
20  
21  
22  
23  
24  
26  
D5  
E5  
D4  
D-  
D+  
VM  
USB Differential Data Input/Output. Connect D+ to the D+ terminal of the USB  
connector through a 27.4Ω 1% series resistor.  
Single-Ended Receiver Output. VM functions as a receiver output in all  
operating modes. VM duplicates D-.  
USB Transceiver Regulated Output Voltage. TRM provides a regulated 3.3V  
output. Bypass TRM to GND with a 1µF ceramic capacitor installed as close  
to the device as possible. TRM normally derives power from V . TRM  
CC  
24  
27  
E4  
TRM  
VP  
provides power to internal circuitry and provides the pullup voltage for the  
internal USB pullup resistor. Do not use TRM to power external circuitry. The  
reg_sel bit (bit 3 of special-function register 2, see Table 15 and Table 16)  
controls the TRM power source with software.  
Single-Ended Receiver Output. VP functions as a receiver output in all  
operating modes. VP duplicates D+.  
26  
27  
30  
31  
D3  
E2  
USB Bus Power. Use V  
as an output to power the USB bus, or as an input  
BUS  
to power the internal linear regulator. Bits 5 to 7 of control register 2 (see  
V
BUS  
Table 8) control the charging and discharging functions of V  
.
BUS  
28  
EP  
32  
EP  
E1  
—
C+  
EP  
Charge-Pump Flying-Capacitor Positive Terminal  
Exposed Paddle. Connect to GND or leave floating  
Test Circuits and Timing Diagrams  
LOAD FOR DISABLE TIME (D+/D-) MEASUREMENT  
V = 0 FOR t  
TEST POINT  
LOAD FOR  
TEST POINT  
27.4Ω 220Ω  
.
PHZ  
V = V  
FOR t  
.
TRM  
PLZ  
27.4Ω  
1) ENABLE TIME (D+/D-) MEASUREMENT  
2) DAT_VP/SEO_VM TO D+/D- PROPAGATION DELAY  
3) D+/D- RISE/FALL TIMES  
C = 50pF FOR FULL SPEED.  
L
DUT  
DUT  
C = 200pF TO 600pF FOR LOW SPEED.  
L
D+/D-  
15kΩ  
D+/D-  
C = 50pF FOR FULL SPEED.  
L
C
C
V
L
L
C = 200pF TO 600pF FOR LOW SPEED.  
L
Figure 1. Load for Disable Time Measurement  
Figure 2. Load for Enable Time, Transmitter Propagation Delay,  
and Transmitter Rise/Fall Times  
±0 ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ  
USB On-the-Go Transceivers and Charge Pumps  
Test Circuits and Timing Diagrams (continued)  
TEST POINT  
LOAD FOR  
V
L
V / 2  
L
V / 2  
L
OE/INT  
0V  
1) D+/D- TO RCV/VP/VM/DAT_VP/SEO_VM PROPAGATION DELAYS  
DUT  
2) RCV/VP/VM/DAT_VP/SEO_VM RISE/FALL TIMES (C = 15pF)  
L
RCV, VP, VM,  
DAT_VP,  
t
t
PZD  
PDZ  
C
L
V
OH  
V
- 0.3V  
OHD  
SEO_VM  
D+ OR D-  
V
OLD  
+ 0.3V  
V
OL  
Figure 3. Load for Receiver Propagation Delay and Receiver  
Rise/Fall Times  
Figure 8. Enable and Disable Timing  
TEST POINT  
270Ω  
DUT  
3V  
0V  
D+  
D-  
DAT_VP  
SEO_VM  
V = 2/3 x V  
L
t
t
PLH  
PHL  
V
L
RCV  
Figure 4. Load for DAT_VP, SE0_VM Enable/Disable Time  
Measurements  
V / 2  
L
0V  
t
t
t
R
t
F
PHL  
PLH  
PHL  
DAT_VP  
SE0_VM  
V
L
V
OH  
90%  
10%  
V / 2  
L
0V  
t
t
PLH  
V
L
V
OL  
V / 2  
L
Figure 5. Rise and Fall Times  
0V  
D+/D- RISE/FALL TIMES ≤ 8ns, V = 1.8V, 2.5V, OR 3.3V  
L
DAT_VP  
t
t
PLH  
PHL  
Figure 9. D+/D- to RCV, DAT_VP, SE0_VM Propagation Delays  
(VP_VM Mode)  
SE0_VM  
D+  
D-  
V
OHD  
OLD  
V
, V  
V
, V  
CRS_F CRS_L  
CRS_F CRS_L  
3V  
0V  
D+  
V
Figure 6. Timing of DAT_VP, SE0_VM to D+, D- in VP_VM  
Mode (dat_se0 = 0)  
D-  
t
t
PLH  
PHL  
V
L
DAT_VP  
DAT_VP  
V / 2  
L
t
t
PLH  
PHL  
0V  
SE0_VM  
D+  
V
OHD  
SE0_VM  
V
, V  
V
, V  
CRS_F CRS_L  
CRS_F CRS_L  
D+/D- RISE/FALL TIMES ≤ 8ns, V = 1.8V, 2.5V, OR 3.3V  
L
D-  
V
OLD  
Figure 10. D+/D- to DAT_VP, SE0_VM Propagation Delays  
(DAT_SE0 Mode)  
Figure 7. Timing of DAT_VP, SE0_VM to D+/D- in DAT_SE0  
Mode (dat_se0 = 1)  
ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ ±±  
USB On-the-Go Transceivers and Charge Pumps  
Block Diagram  
ID  
ID_IN  
DETECTOR  
ADD  
INT  
C+  
C-  
V
BUS  
CHARGE PUMP  
SERIAL  
CONTROLLER  
RESET  
V
BUS  
V
BUS  
COMPARATORS  
LINEAR  
REGULATOR  
TRM  
SCL  
SDA  
PULLUP/PULLDOWN  
RESISTORS  
CAR KIT INTERRUPT  
DETECTOR  
DAT_VP  
SE0_VM  
OE/INT  
D+  
D-  
DIFF  
TX  
VP  
VM  
DIFF  
RX  
LEVEL  
TRANSLATOR  
RCV  
V
CC  
SE  
D+  
POWER  
BLOCK  
V
L
GND  
SPD  
SUS  
SE  
D-  
MAX3301E  
MAX3302E  
Figure 11. Block Diagram  
±2 ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ  
USB On-the-Go Transceivers and Charge Pumps  
accordance with USB OTG specifications. The charge  
Detailed Description  
pump can be turned off to conserve power when not  
The USB OTG specification defines a dual-role USB  
used. Control of the charge pump is set through the  
vbus_drv bit (bit 5) of control register 2 (see Table 8).  
device that acts either as an A device or as a B device.  
The A device supplies power on V  
and initially  
BUS  
serves as the USB host. The B device serves as the ini-  
tial peripheral and requires circuitry to monitor and pulse  
BUS  
Linear Regulator (TRM)  
An internal 3.3V linear regulator powers the transceiver  
and the internal 1.5ꢀΩ D+/D- pullup resistor. Under the  
control of internal register bits, the linear regulator can be  
V
. These initial roles can be reversed using HNP.  
The MAX3301E/MAX3302E combine a low- and full-  
speed USB transceiver with additional circuitry required  
by a dual-role device. The MAX3301E/MAX3302E  
employ flexible switching circuitry to enable the device  
to act as a dedicated host or peripheral USB transceiv-  
er. For example, the charge pump can be turned off and  
powered from V  
or V  
. The regulator power-supply  
CC  
BUS  
settings are controlled by the reg_sel bit (bit 3) in special-  
function register 2 (Tables 15 and 16). This flexibility  
allows the system designer to configure the MAX3301E/  
MAX3302E for virtually any USB power situation.  
the internal regulator can be powered from V  
bus-powered peripheral applications.  
for  
BUS  
The output of the TRM is not a power supply. Do not use  
as a power source for any external circuitry. Connect a  
1.0µF (or greater) ceramic or plastic capacitor from TRM  
to GND, as close to the device as possible.  
The Selector Guide shows the differences between the  
MAX3301E and MAX3302E. The MAX3301E powers up  
in its lowest power state and must be turned on by set-  
ting the sdwn bit to 0. The MAX3302E powers up in the  
operational, VP/VM USB mode. This allows a micro-  
processor (µP) to use the USB port for power-on boot-  
V
Level-Detection Comparators  
BUS  
Comparators drive interrupt source register bits 0, 1,  
and 7 (Table 10) to indicate important USB OTG V  
voltage levels:  
BUS  
2
up, without having to access I C. To put the MAX3302E  
•
•
•
V
is valid (vbus_vld)  
BUS  
into low-power shutdown, set the sdwn bit to 0. In the  
MAX3302E, special-function register 2 can be  
USB session is valid (sess_vld)  
2
addressed at I C register location 10h, 11h (as well as  
USB session has ended (sess_end)  
locations 16h, 17h) to support USB OTG serial-interface  
2
The vbus_valid comparator sets vbus_vld to 1 if V  
is  
engine (SIE) implementations that are limited to I C  
BUS  
higher than the V  
valid comparator threshold. The  
register addresses between 0h and 15h.  
BUS  
V
BUS  
valid status bit (vbus_vld) is used by the A device  
Transceiver  
The MAX3301E/MAX3302E transceiver complies with  
the USB version 2.0 specification, and operates at full-  
speed (12Mbps) and low-speed (1.5Mbps) data rates.  
Set the data rate with the SPD input. Set the direction of  
data transfer with the OE/INT input. Alternatively, control  
transceiver operation with control register 1 (Table 7)  
and special-function registers 1 and 2 (see Tables 14,  
15, and 16).  
to determine if the B device is sinꢀing too much current  
(i.e., is not supported). The session_valid comparator  
sets sess_vld to 1 if V  
is higher than the session  
BUS  
valid comparator threshold. This status bit indicates that  
a data transfer session is valid. The session_end com-  
parator sets sess_end to 1 if V  
is higher than the  
BUS  
V
BUS  
Level Shifters  
Internal level shifters allow the system-side interface to  
run at logic-supply voltages as low as +1.65V. Interface  
logic signals are referenced to the voltage applied to  
VBUS_VLD  
V
TH-VBUS  
the logic-supply voltage, V .  
L
SESS_VLD  
SESS_END  
Charge Pump  
V
TH-SESS_VLD  
The MAX3301E/MAX3302E’s OTG-compliant charge  
pump operates with +3V to +4.5V input supply voltages  
CC  
(V ) and supplies a +4.8V to +5.25V OTG-compatible  
V
TH-SESS_END  
output on V  
while sourcing the 8mA or greater out-  
BUS  
put current that an A device is required to supply.  
Connect a 0.1µF flying capacitor between C+ and C-.  
Bypass V  
to GND with a 1µF to 6.5µF capacitor, in  
Figure 12. Comparator Network Diagram  
BUS  
ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ ±3  
USB On-the-Go Transceivers and Charge Pumps  
session end comparator threshold. Figure 12 shows the  
level-detector comparators. The interrupt-enable regis-  
ters (Tables 12 and 13) determine whether a falling or  
•
•
•
Discharge V  
through a resistor  
BUS  
Provide power-on or receive power from V  
BUS  
Charge V  
through a resistor  
BUS  
rising edge of V  
asserts these status bits.  
BUS  
The OTG supplement allows an A device to turn V  
BUS  
ID_IN  
off when the bus is not being used to conserve power.  
The USB OTG specification defines an ID input that  
determines which dual-role device is the default host.  
An OTG cable connects ID to ground in the connector  
of one end and is left unconnected in the other end.  
Whichever dual-role device receives the grounded end  
becomes the A device. The MAX3301E/MAX3302E pro-  
vide an internal pullup resistor on ID_IN. Internal com-  
parators detect if ID_IN is grounded or left floating.  
The B device can issue a request that a new session be  
started using SRP. The B device must discharge V  
BUS  
to a level below the session-end threshold (0.8V) to  
ensure that no session is in progress before initiating  
SRP. Setting bit 6 of control register 2 to 1, discharges  
V
to GND through a 5ꢀΩ current-limiting resistor.  
BUS  
When V  
has discharged, the resistor is removed  
BUS  
from the circuit by resetting bit 6 of control register 2.  
An OTG A device is required to supply power on V  
.
Interrupt Logic  
When OTG events require action, the MAX3301E/  
MAX3302E provide an interrupt output signal on INT.  
Alternatively, OE/INT can be configured to act as an  
interrupt output while the device operates in USB sus-  
pend mode. Program INT and OE/INT as open-drain or  
push-pull interrupts with irq_mode (bit 1 of special-func-  
tion register 2, see Tables 15 and 16).  
BUS  
from  
The MAX3301E/MAX3302E provide power to V  
BUS  
V
or from the internal charge pump. Set bit 5 in control  
CC  
register 2 to 1 in both cases. Bit 5 in control register 2  
controls a current-limited switch, preventing damage to  
the device in the event of a V  
short circuit.  
BUS  
An OTG B device (peripheral mode) can request a ses-  
sion using SRP. One of the steps in implementing SRP  
requires pulsing V  
high for a controlled time. A 930Ω  
BUS  
V
Power Control  
BUS  
resistor limits the current according to the OTG specifi-  
cation. Pulse V through the pullup resistor by assert-  
V
is a dual-function port that powers the USB bus  
BUS  
BUS  
and/or provides a power source for the internal linear reg-  
ulator. The V power-control blocꢀ performs the various  
ing bit 7 of control register 2. Prior to pulsing V  
(bit  
BUS  
BUS  
7), a B device first connects an internal pulldown resis-  
switching functions required by an OTG dual-role device.  
These actions are programmed by the system logic using  
bits 5 to 7 of control register 2 (see Table 8) to:  
tor to discharge V  
below the session-end threshold.  
BUS  
The discharge current is limited by the 5ꢀΩ resistor and  
set by bit 6 of control register 2. An OTG A device must  
Table ±. Functional Bloc5s Enabled During Specific Operating Modes  
sessꢀend  
COMP  
sess ꢀvld  
COMP  
vbusꢀ vld  
COMP  
crꢀint  
COMP  
dpꢀhi  
COMP COMP  
dmꢀhi  
DIFF  
RX  
SE  
RX  
2
MODE  
I C IDꢀIꢁ  
TRM  
X
TX  
X
Shutdown1  
✓
✓
✓
✓
X
✓
✓
✓
X
X
✓
✓
✓
X
X
X
✓
✓
✓
X
✓
✓
✓
X
X
X
✓
X
Interrupt  
X
X
X
X
X
X
Shutdown2  
Suspend3  
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
Normal  
Operating  
✓
✓ = Enabled.  
X = Disabled.  
1. For the MAX3301E, enter shutdown mode by writing a 1 to sdwn (bit 0 of special-function register 2). For the MAX3302E, enter  
shutdown mode by writing a 0 to sdwn (bit 0 of special-function register 2).  
2. Enter interrupt shutdown mode by writing a 1 to int_sdwn (bit 0 of special-function register 1).  
3. Enter suspend mode by writing a 1 to spd_susp_ctl (bit 1 of special-function register 1) and suspend (bit 1 of control register 1), or  
by writing a 0 to spd_susp_ctl (bit 1 of special-function register 1) and driving SUS high.  
±4 ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ  
USB On-the-Go Transceivers and Charge Pumps  
supply 5V power and at least 8mA on V  
. Setting bit  
this mode, OE/INT detects the same interrupts as INT.  
Set irq_mode (bit 1 in special-function register 2, see  
Tables 15 and 16) to 0 to program OE/INT as an open-  
drain interrupt output. Set irq_mode to 1 to configure  
OE/INT as a push-pull interrupt output.  
BUS  
charge pump.  
5 of control register 2 turns on the V  
BUS  
Operating Modes  
The MAX3301E/MAX3302E have four operating modes to  
2
optimize power consumption. Only the I C interface  
remains active in shutdown mode, reducing supply cur-  
RCV  
RCV monitors D+ and D- when receiving data. RCV is a  
logic 1 for D+ high and D- low. RCV is a logic 0 for D+  
low and D- high. RCV retains its last valid state when D+  
and D- are both low (single-ended zero, or SE0). RCV  
asserts low in suspend mode. Table 4 shows the state  
of RCV.  
2
rent to 1µA. The I C interface, the ID_IN port, and the  
session-valid comparator all remain active in interrupt  
shutdown mode. RCV asserts low in suspend mode; how-  
ever, all other circuitry remains active. Table 1 lists the  
active blocꢀs’ power in each of the operating modes.  
Applications Information  
SPD  
Use hardware or software to control the slew rate of the  
D+ and D- terminals. The SPD input sets the slew rate of  
the MAX3301E/MAX3302E when spd_susp_ctl (bit 1 in  
special-function register 1, see Table 14) is 0. Drive SPD  
low to select low-speed mode (1.5Mbps). Drive SPD  
high to select full-speed mode (12Mbps). Alternatively,  
when spd_susp_ctl (bit 1 of special-function register 1)  
is 1, software controls the slew rate. The SPD input is  
ignored when using software to control the data rate.  
The speed bit (bit 0 of control register 1, see Table 7)  
sets the slew rate when spd_susp_ctl = 1.  
Data Transfer  
Transmitting Data to the USB  
The MAX3301E/MAX3302E transceiver features two  
modes of transmission: DAT_SE0 or VP_VM (see Table 3).  
Set the transmitting mode with dat_se0 (bit 2 in control  
register 1, see Table 7). In DAT_SE0 mode with OE/INT  
low, DAT_VP specifies data for the differential transceiv-  
er, and SE0_VM forces D+/D- to the single-ended zero  
(SE0) state. In VP_VM mode with OE/INT low, DAT_VP  
drives D+, and SE0_VM drives D-. The differential  
receiver determines the state of RCV.  
Receiving Data from the USB  
The MAX3301E/MAX3302E transceiver features two  
modes of receiving data: DAT_SE0 or VP_VM (see  
Table 4). Set the receiving mode with dat_se0 (bit 2 in  
control register 1, see Table 7). In DAT_SE0 mode with  
OE/INT high, DAT_VP is the output of the differential  
receiver and SE0_VM indicates that D+ and D- are both  
logic-low. In VP_VM mode with OE/INT high, DAT_VP  
provides the input logic level of D+ and SE0_VM pro-  
vides the input logic level of D-. The differential receiver  
determines the state of RCV. VP and VM echo D+ and  
D-, respectively.  
SUS  
Use hardware or software to control the suspend mode  
of the MAX3301E/MAX3302E. Set spd_susp_ctl (bit 1 of  
special-function register 1, see Table 14) to 0 to allow  
the SUS input to enable and disable the suspend mode  
of the MAX3301E/MAX3302E. Drive SUS low for normal  
operation. Drive SUS high to enable suspend mode.  
RCV asserts low in suspend mode while all other circuit-  
ry remains active.  
Alternatively, when the spd_susp_ctl bit (bit 1 of special-  
function register 1) is set to 1, software controls the sus-  
pend mode. Set the suspend bit (bit 1 of control register  
1, see Table 7) to 1 to enable suspend mode. Set the  
suspend bit to 0 to resume normal operation. The SUS  
input is ignored when using software to control suspend  
mode. The MAX3301E/MAX3302E must be in full-speed  
mode (SPD = high or speed = 1) to issue a remote  
waꢀe-up from the device when in suspend mode.  
OE/INT  
OE/INT controls the direction of communication. OE/INT  
can also be programmed to act as an interrupt output  
when in suspend mode. The output-enable portion con-  
trols the input or output status of DAT_VP/SE0_VM and  
D+/D-. When OE/INT is a logic 0, DAT_VP and SE0_VM  
function as inputs to the D+ and D- outputs in a method  
depending on the status of dat_se0 (bit 2 in control reg-  
ister 1). When OE/INT is a logic 1, DAT_VP and SE0_VM  
indicate the activity of D+ and D-.  
RESET  
The active-low RESET input allows the MAX3301E/  
MAX3302E to be asynchronously reset without cycling  
the power supply. Drive RESET low to reset the internal  
registers (see Tables 7–16 for the default power-up  
states). Drive RESET high for normal operation.  
OE/INT functions as an interrupt output when the  
MAX3301E/MAX3302E is in suspend mode and  
oe_int_en = 1 (bit 5 in control register 1, see Table 7). In  
ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ ±1  
USB On-the-Go Transceivers and Charge Pumps  
2-Wire I2C-Compatible Serial Interface  
Table 2. Setting the Direction of Data  
A register file controls the various internal switches and  
Transfer in General-Purpose Buffer Mode  
operating modes of the MAX3301E/MAX3302E through  
a simple 2-wire interface operating at clocꢀ rates up to  
400ꢀHz. This interface supports data bursting, where  
multiple data phases can follow a single address phase.  
DIRECTIOꢁ OF DATA  
dplusꢀdir  
dminusꢀ dir  
TRAꢁSFER  
DAT_VP → D+  
SE0_VM → D-  
0
0
1
1
0
1
0
1
UART Mode  
Set uart_en (bit 6 in control register 1) to 1 to place the  
MAX3301E/MAX3302E in UART mode. D+ transfers  
data to DAT_VP and SE0_VM transfers data to D- in  
UART mode.  
DAT_VP → D+  
SE0_VM ← D-  
DAT_VP ← D+  
SE0_VM → D-  
General-Purpose Buffer Mode  
Set gp_en (bit 7 in special-function register 1) and  
dat_se0 (bit 2 in control register 1) to 1, set uart_en (bit 6  
in control register 1) to 0, and drive OE/INT low to place  
the MAX3301E/MAX3302E in general-purpose buffer  
mode. Control the direction of data transfer with dmi-  
nus_dir and dplus_dir (bits 3 and 4 of special-function  
register 1, see Tables 2 and 14).  
DAT_VP ← D+  
SE0_VM ← D-  
pullup resistor, typically 4.7ꢀΩ. The MAX3301E/  
MAX3302E SCL line only operates as an input. SCL  
requires a pullup resistor if there are multiple masters on  
the 2-wire interface, or if the master in a single-master  
system has an open-drain SCL output.  
Serial Addressing  
The MAX3301E/MAX3302E operate as a slave device  
that sends and receives control and status signals  
Each transmission consists of a start condition (see  
Figure 14) sent by a master device, the MAX3301E/  
MAX3302E 7-bit slave address (determined by the state  
of ADD), plus an R/W bit (see Figure 15), a register  
address byte, one or more data bytes, and a stop condi-  
tion (see Figure 14).  
2
through an I C-compatible 2-wire interface. The inter-  
face uses a serial data line (SDA) and a serial clocꢀ line  
(SCL) to achieve bidirectional communication between  
master(s) and slave(s). A master (typically a microcon-  
troller) initiates all data transfers to and from the  
MAX3301E/MAX3302E and generates the SCL clocꢀ  
that synchronizes the data transfer (Figure 13).  
The MAX3301E/MAX3302E SDA line operates as both an  
input and as an open-drain output. SDA requires a  
SDA  
t
BUF  
t
SU: STA  
t
SU: DAT  
t
t
HD: DAT  
LOW  
t
t
SU: STO  
HD: STA  
SCL  
t
HIGH  
t
HD: STA  
t
R
t
F
REPEATED START  
CONDITION  
START  
CONDITION  
STOP  
START  
CONDITION CONDITION  
Figure 13. 2-Wire Serial-Interface Timing Details  
±6 ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ  
USB On-the-Go Transceivers and Charge Pumps  
Table 3. Transmit Mode  
COꢁTROL PIꢁ/BIT  
IꢁPUT  
OUTPUT  
D+  
MODE  
DESCRIPTIOꢁ  
SUS  
0
GPꢀEꢁ  
DATꢀSE0  
DATꢀkP SE0ꢀkM  
D-  
1
0
0
0
0
0
1
1
1
0
0
0
0
0
1
1
OE/INT  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
0
0
1
0
1
0
1
0
0
0
1
0
1
0
Functional  
DAT_SE0  
0
USB functional mode  
0
2
transceiver and I C interface  
0
are fully functional  
0
Functional  
VP_VM  
0
0
1
1
1
1
1
Suspend  
USB suspend mode  
1
1
1
Driver is Driver is  
Hi-Z Hi-Z  
1
0
0
0
1
1
X
X
X
X
X
X
Driver is Driver is  
Receiving  
See Table 4  
Hi-Z  
Hi-Z  
General-  
purpose  
buffer  
General-purpose buffer  
mode  
X
1
0
1
See Table 2  
SDA  
S
P
SCL  
START  
STOP  
CONDITION  
CONDITION  
Figure 14. Start and Stop Conditions  
R/W  
ACK  
1
0
0
A0  
1
0
0
SDA  
START  
MSB  
LSB  
SCL  
Figure 15. Slave Address  
ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ ±7  
USB On-the-Go Transceivers and Charge Pumps  
Table 4. Receive Mode  
COꢁTROL PIꢁ/BIT  
IꢁPUTS  
OUTPUTS  
MODE  
SUS  
(ꢁOTE 7)  
GPꢀEꢁ OE/IꢁT DATꢀSE0 BIꢀDI D+ D-  
DATꢀkP  
SE0ꢀkM  
RCk  
kP  
kM  
Last value  
of DAT_VP  
Last value  
of RCV  
0
0
1
1
1
0
0
1
0
0
0
1
1
1
1
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
0
1
0
1
0
1
1
0
0
1
1
1
0
0
0
1
0
0
0
1
0
0
Functional  
DAT_SE0  
Undefined  
Undefined  
0
1
0
1
0
0
0
0
Last value  
of RCV  
0
0
1
0
1
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
1
0
1
0
1
0
1
1
0
0
1
1
1
0
1
0
1
0
1
0
1
1
0
0
1
1
1
Echo Echo  
D+ D-  
0
Functional  
VP_VM  
Undefined  
0
0
0
0
General-  
X
X
X
1
X
X
X
0
X
X
X
X
X
X
0
See Table 2  
0
0
0
purpose buffer  
Transmitting  
(see Table 3)  
—
—
Unidirectional  
(transmitter  
only)  
ꢁote 7: Enter suspend mode by driving SUS high or by writing a 1 to suspend (bit 1 in control register 1), depending on the status of  
spd_susp_ctl in special-function register 1.  
X = Don’t care.  
±8 ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ  
USB On-the-Go Transceivers and Charge Pumps  
Start and Stop Conditions  
Both SCL and SDA assert high when the interface is not  
busy. A master device signals the beginning of a trans-  
mission with a start (S) condition by transitioning SDA  
from high to low while SCL is high. The master issues a  
stop (P) condition by transitioning SDA from low to high  
while SCL is high. The bus is then free for another trans-  
mission (see Figure 14).  
an ACK when receiving an address or data by pulling  
SDA low during the ninth clocꢀ period. When transmit-  
ting data, the MAX3301E/MAX3302E wait for the receiv-  
ing device to generate an ACK. Monitoring ACK allows  
for detection of unsuccessful data transfers. An unsuc-  
cessful data transfer occurs if a receiving device is busy  
or if a system fault has occurred. In the event of an  
unsuccessful data transfer, the bus master should reat-  
tempt communication at a later time.  
Bit Transfer  
One data bit is transferred during each clocꢀ pulse. The  
data on SDA must remain stable while SCL is high (see  
Figure 16).  
Slave Address  
A bus master initiates communication with a slave  
device by issuing a START condition followed by the 7-  
bit slave address (see Figure 15). When idle, the  
MAX3301E/MAX3302E wait for a START condition fol-  
lowed by its slave address. The LSB of the address  
word is the read/write (R/W) bit. R/W indicates whether  
the master is writing to or reading from the  
MAX3301E/MAX3302E (R/W = 0 selects the write con-  
dition, R/W = 1 selects the read condition). After  
receiving the proper address, the MAX3301E/  
MAX3302E issue an ACK.  
Acknowledge  
The acꢀnowledge bit (ACK) is the 9th bit attached to  
any 8-bit data word. ACK is always generated by the  
receiving device. The MAX3301E/MAX3302E generate  
SDA  
The MAX3301E/MAX3302E have two possible addresses  
(see Table 5). Address bits A6 through A1 are preset,  
while a reset condition or an I2C general call address  
loads the value of A0 from ADD. Connect ADD to GND to  
SCL  
set A0 to 0. Connect ADD to V to set A0 to 1. This allows  
L
up to two MAX3301E’s or two MAX3302E’s to share the  
same bus.  
DATA LINE STABLE, CHANGE OF DATA  
DATA VALID  
ALLOWED  
Write Byte Format  
Writing data to the MAX3301E/MAX3302E requires the  
transmission of at least 3 bytes. The first byte consists of  
the MAX3301E/MAX3302E’s 7-bit slave address, fol-  
lowed by a 0 (R/W bit). The second byte determines  
which register is to be written to. The third byte is the  
new data for the selected register. Subsequent bytes  
are data for sequential registers. Figure 18 shows the  
typical write byte format.  
Figure 16. Bit Transfer  
START  
CONDITION  
CLOCK PULSE FOR ACKNOWLEDGEMENT  
1
2
8
9
SCL  
SDA BY  
TRANSMITTER  
Read Byte Format  
Reading data from the MAX3301E/MAX3302E requires  
the transmission of at least 3 bytes. The first byte con-  
sists of the MAX3301E/MAX3302E’s slave address, fol-  
lowed by a 0 (R/W bit). The second byte selects the  
register from which data is read. The third byte consists  
S
SDA BY  
RECEIVER  
Figure 17. Acknowledge  
SLAVE ADDRESS  
(7 BITS)  
REGISTER ADDRESS  
(8 BITS)  
DATA  
(8 BITS)  
S
R/W  
0
A
A
A
P
A6 A5 A4 A3 A2 A1 A0  
MSB  
LSB  
MSB  
LSB  
Figure 18. Write Byte Format  
ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ ±9  
USB On-the-Go Transceivers and Charge Pumps  
SLAVE ADDRESS  
(7 BITS)  
REGISTER ADDRESS  
(8 BITS)  
S
R/W  
0
A
0
A
0
A6  
A5  
A4  
A3  
A2  
A1  
A0  
MSB  
LSB  
SLAVE ADDRESS  
(7 BITS)  
DATA  
(8 BITS)  
RS  
NA  
P
0
R/W  
A
0
A6 A5 A4 A3 A2 A1 A0  
1
MSB  
LSB  
1
Figure 19. Read Byte Format  
R/W: Read/write (R/W = 1: read; R/W = 0: write)  
S: Start condition  
A: Acꢀnowledge bit from the slave  
NA: Not-acꢀnowledged bit from the master  
Blanꢀ: Master transmission  
RS: Repeated start condition  
P: Stop condition  
SLAVE ADDRESS  
REGISTER ADDRESS (K)  
(8 BITS)  
DATA (K)  
(8 BITS)  
S
R/W  
0
A
A
A
P
(7 BITS)  
A6  
A5  
A4  
A3  
A2  
A1  
A0  
MSB  
LSB  
A
MSB  
LSB  
A
DATA (K+1)  
(8 BITS)  
DATA (K+2)  
(8 BITS)  
DATA (K+N)  
(8 BITS)  
A
MSB  
LSB  
MSB  
LSB  
MSB  
LSB  
MAX3301E/MAX3302E RECOGNIZES  
ITS ADDRESS  
MAX3301E/MAX3302E SENDS  
AN ACK  
SLAVE ADDRESS  
(7 BITS)  
UNSUPPORTED REGISTER ADDRESS (K)  
(8 BITS)  
DATA (K)  
(8 BITS)  
S
A
NA  
R/W  
0
A
A6  
A5 A4 A3  
A2 A1 A0  
MSB  
LSB  
MSB  
LSB  
MAX3301E/MAX3302E RECOGNIZES A WRITE TO AN  
UNSUPPORTED LOCATION, THEN SENDS A NACK  
Figure 20. Burst-Mode Write Byte Format  
of the MAX3301E/MAX3302E’s slave address, followed  
by a 1 (R/W bit). The master then reads one or more  
bytes of data. Figure 19 shows the typical read byte  
format.  
address and the MAX3301E/MAX3302E return an  
acꢀnowledge bit. The master writes a data byte to the  
selected register and receives an acꢀnowledge bit if a  
supported register address has been chosen. The reg-  
ister address increments and is ready for the master to  
send the next data byte. The MAX3301E/MAX3302E  
send an acꢀnowledge bit after each data byte. If an  
unsupported register is selected, the MAX3301E/  
MAX3302E send a NACK to the master and the register  
index does not increment (see Figure 20).  
Burst-Mode Write Byte Format  
The MAX3301E/MAX3302E allow a master device to  
write to sequential registers without repeatedly sending  
the slave address and register address each time. The  
master first sends the slave address, followed by a 0 to  
write data to the MAX3301E/MAX3302E. The  
MAX3301E/MAX3302E send an acꢀnowledge bit bacꢀ  
to the master. The master sends the 8-bit register  
20 ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ  
USB On-the-Go Transceivers and Charge Pumps  
SLAVE ADDRESS  
(7 BITS)  
REGISTER ADDRESS (K)  
(8 BITS)  
S
R/W  
0
A
A
P
A6 A5 A4 A3 A2 A1 A0  
MSB  
MSB  
LSB  
SLAVE ADDRESS  
(7 BITS)  
DATA (K)  
(8 BITS)  
DATA (K+1)  
(8 BITS)  
S
R/W  
1
A
A
A
P
A6 A5 A4 A3 A2 A1 A0  
LSB  
A
MSB  
LSB  
NA  
DATA (K+2)  
(8 BITS)  
DATA (K+3)  
(8 BITS)  
DATA (K+N)  
(8 BITS)  
A
MSB  
LSB  
MSB  
LSB  
MSB  
LSB  
MAX3301E/MAX3302E RECOGNIZE  
THEIR ADDRESS  
MAX3301E/MAX3302E SENDS  
AN ACK  
SLAVE ADDRESS  
(7 BITS)  
UNSUPPORTED REGISTER ADDRESS (K)  
(8 BITS)  
S
S
R/W  
0
A
A
A
A
P
A6 A5 A4 A3 A2 A1 A0  
MSB  
MSB  
LSB  
LSB  
SLAVE ADDRESS  
(7 BITS)  
UNSUPPORTED REGISTER ADDRESS (K)  
(8 BITS) — ALL 0's RETURNED  
R/W  
1
A6 A5 A4 A3 A2 A1 A0  
ACK FROM MASTER  
Figure 21. Burst-Mode Read Byte Format  
2
Table 1. I C Slave Address Map  
ADDRESS BITS  
ADD IꢁPUT  
A
6
A
5
A
4
A
3
A
2
A
1
A
0
GND (0)  
V (1)  
0
1
0
1
1
0
0
0
1
0
1
1
0
1
L
ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ 2±  
USB On-the-Go Transceivers and Charge Pumps  
Table 6. Register Map  
REGISTER  
Vendor ID  
Product ID  
MEMORY ADDRESS  
00h, 01h  
DESCRIPTIOꢁ  
Read only. The contents of registers 00h and 01h are 6Ah and 0Bh, respectively.  
Read only. The contents of registers 02h and 03h are 01h and 33h, respectively.  
02h, 03h  
04h (set)  
05h (clear)  
Control 1  
Control 2  
Sets operating modes, maximum data rate, and direction of data transfer.  
06h (set)  
07h (clear)  
Controls D+/D- pullup/pulldown resistor connections, ID_IN state, and V  
behavior.  
BUS  
Interrupt source  
Unused*  
08h (read)  
09h  
Read only.  
Not used.  
0Ah (set)  
0Bh (clear)  
Interrupt latch  
Indicates which interrupts have occurred.  
Enables interrupts for high-to-low transitions.  
Interrupt-enable  
Falling edge  
0Ch (set)  
0Dh (clear)  
Interrupt-enable  
Rising edge  
0Eh (set)  
0Fh (clear)  
Enables interrupts for low-to-high transitions.  
MAX3301E: Not used.  
MAX3302E: Alternate register addresses for special-function register 2. This  
register is also accessible from 16h and 17h.  
Unused*/Special  
Function 2  
10h (set)  
11h (clear)  
12h (set)  
13h (clear)  
Enables hardware/software control of the MAX3301E's behavior, interrupt activity,  
and operating modes.  
Special function 1  
Revision ID  
14h, 15h  
Read only. The contents of registers 14h and 15h are 77h and 41h, respectively.  
16h (set)  
17h (clear)  
Sets operating modes, INT output configuration, D+/D- behavior in audio mode,  
and TRM source.  
Special function 2  
Unused*  
18h–Fh  
Not used.  
*When writing to an unused register, the device generates a NACK and the register index does not increment.  
an unsupported register address is encountered, the  
MAX3301E/MAX3302E send a byte of zeros.  
Burst-Mode Read Byte Format  
The MAX3301E/MAX3302E allow a master device to read  
data from sequential registers with the burst-mode read  
byte protocol (see Figure 21). The master device first  
sends the slave address, followed by a 0. The  
MAX3301E/MAX3302E then sends an acꢀnowledge bit.  
Next, the master sends the register address to the  
MAX3301E/MAX3302E, which then generates another  
acꢀnowledge bit. The master then sends a stop (P) con-  
dition to the MAX3301E/MAX3302E. Next, the master  
sends a start condition, followed by the MAX3301E/  
MAX3302E’s slave address, and then a 1 to indicate a  
read command. The MAX3301E/MAX3302E then sends  
data to the master device, one byte at a time. The master  
sends an acꢀnowledge bit to the MAX3301E/ MAX3302E  
after each data byte, and the register address of the  
MAX3301E/MAX3302E increments after each byte. This  
continues until the master sends a stop (P) condition. If  
Registers  
Control Registers  
There are two read/write control registers. Control regis-  
ter 1 (Table 7) sets operating modes, sets the data rate,  
and controls the direction of data transfer. Control regis-  
ter 2 (Table 8) connects the D+/D- pullup or pulldown  
resistors, sets the V  
charge/discharge conditions,  
BUS  
and grounds ID_IN. The control registers have two  
addresses that implement write-one-set and write-one-  
clear features for each of these registers. Writing a 1 to  
the set address sets that bit to 1. Writing a 1 to the clear  
address resets that bit to 0. Writing a 0 to either address  
has no effect on the bits.  
22 ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ  
USB On-the-Go Transceivers and Charge Pumps  
Table 7. Control Register ± Description (Write to Address 04h to Set, Write to Address  
01h to Clear)  
kALUE AT  
POWER-UP  
BIT ꢁUMBER  
SYMBOL  
OPERATIOꢁ  
Set to 0 for low-speed (1.5Mbps) mode. Set to 1 for full-speed (12Mbps) mode. This  
bit changes the data rate only if spd_susp_ctl = 1 in special-function register 1.  
0
1
speed  
0
Set to 0 for normal operating mode. Set to 1 for suspend mode. This bit changes  
the operating mode only if spd_susp_ctl = 1 in special-function register 1.  
suspend  
0
2
3
dat_se0  
—
Set to 0 for VP_VM USB mode. Set to 1 for DAT_SE0 USB mode.  
Not used.  
0
0
Enables the transceiver (when configured as an A device) to connect its pullup  
resistor if the B device disconnect is detected during HNP. Set to 0 to disable this  
feature. Set to 1 to enable this feature.  
4
5
bdis_acon_en  
oe_int_en  
0
0
Set to 0 to disable the interrupt output circuitry of OE/INT. Set to 1 to enable the  
interrupt output circuitry of OE/INT.  
Set to 0 to disable UART mode. Set to 1 to enable UART mode. This bit overrides  
the settings of dminus_dir, dplus_dir, and gp_en bits.  
6
7
uart_en  
—
0
0
Not used.  
Table 8. Control Register 2 Description (Write to Address 06h to Set, Write to Address  
07h to Clear)  
kALUE AT  
POWER-UP  
BIT ꢁUMBER  
SYMBOL  
OPERATIOꢁ  
0
1
dp_pullup  
dm_pullup  
Set to 0 to disconnect the pullup resistor to D+. Set to 1 to connect the pullup resistor to D+.  
Set to 0 to disconnect the pullup resistor to D-. Set to 1 to connect the pullup resistor to D-.  
0
0
Set to 0 to disconnect the pulldown resistor to D+. Set to 1 to connect the pulldown  
resistor to D+.  
2
3
dp_pulldown  
dm_pulldown  
1
1
Set to 0 to disconnect the pulldown resistor to D-. Set to 1 to connect the pulldown  
resistor to D-.  
4
5
id_pulldown Set to 0 to allow ID_IN to float. Set to 1 to connect ID_IN to GND.  
0
0
vbus_drv  
Set to 0 to turn V  
off. Set to 1 to drive V  
through a low impedance (see Note 8).  
BUS  
BUS  
Set to 0 to disconnect the V  
discharge resistor (see Note 8).  
discharge resistor. Set to 1 to connect the V  
BUS  
BUS  
6
7
vbus_dischrg  
0
0
Set to 0 to disconnect the V  
charge resistor (see Note 8).  
charge resistor. Set to 1 to connect the V  
BUS  
BUS  
vbus_chrg  
ꢁote 8: To prevent a high-current state where the transceiver is both sourcing current to V  
and sinꢀing current from V , the fol-  
BUS  
BUS  
lowing logic is used to set bits 5, 6, and 7 of control register 2:  
•
•
Setting vbus_drv clears vbus_dischrg and vbus_chrg  
Setting vbus_dischrg clears vbus_drv and vbus_chrg, unless vbus_drv is set with the same command, in which case vbus_drv  
clears the other bits  
•
Setting vbus_chrg clears vbus_drv and vbus_dischrg, unless either of these bits are set with the same command, as shown in Table 9  
ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ 23  
USB On-the-Go Transceivers and Charge Pumps  
Table 9. k  
Control Logic  
BUS  
SET COMMAꢁD (ADDRESS 06h)  
BEHAkIOR OF MAX330±E/MAX3302E  
vbusꢀdrv  
vbusꢀdischrg  
vbusꢀchrg  
vbusꢀdrv  
vbusꢀdischrg  
vbusꢀchrg  
1
X
1
0
0
X
X
1
0
1
0
0
0
0
1
0
0
0
0
0
1
Not affected  
Not affected  
Not affected  
X = Don’t care.  
Table ±0. Interrupt Source Register (Address 08h is Read Only)  
BIT ꢁUMBER  
SYMBOL  
vbus_vld  
sess_vld  
COꢁTEꢁTS  
valid comparator threshold.  
0
1
Logic 1 if V  
Logic 1 if V  
> V  
BUS  
BUS  
BUS  
> session valid comparator threshold.  
Logic 1 if V > dp_hi comparator threshold (D+ assertion during data line pulsing through  
D+  
SRP method).  
2
3
4
5
6
dp_hi  
id_gnd  
Logic 1 if V  
< 0.1 x V  
.
CC  
ID_IN  
Logic 1 if V > dm_hi comparator threshold (D- assertion during data line pulsing through SRP  
D-  
method).  
dm_hi  
id_float  
bdis_acon  
Logic 1 if V  
> 0.9 x V  
.
CC  
ID_IN  
Logic 1 if bdis_acon_en = 1 and the MAX3301E/MAX3302E assert dp_pullup after detecting a  
B device disconnect during HNP.  
Logic 1 if V  
< sess_end comparator threshold, or if V > cr_int comparator threshold (0.4V to  
D+  
BUS  
7
cr_int_sess_end  
0.6V), depending on the value of int_source (bit 5 of special-function register 1, see Table 14).  
Interrupt Registers  
the set address sets that bit to 1. Writing a 1 to the clear  
address resets that bit to 0. Writing a 0 to either  
address has no effect on the bits. Special-function reg-  
ister 1 determines whether hardware or software con-  
trols the maximum data rate and suspend behavior,  
sets the direction of data transfer, and toggles general-  
purpose buffer mode. Special-function register 2  
enables shutdown mode, configures the interrupt out-  
put as open-drain or push-pull, sets the TRM power  
source, and controls the D+/D- connections for audio  
mode. Table 15 depicts the special-function register 2  
for the MAX3301E and Table 16 depicts the special-  
function register 2 for the MAX3302E.  
Four registers control all interrupt behavior of the  
MAX3301E/MAX3302E. A source register (Table 10)  
indicates the current status of the various interrupt  
sources. An interrupt latch register (Table 11) indicates  
which interrupts have occurred. An interrupt-enable low  
and interrupt-enable high register enable interrupts on  
rising or falling (or both) transitions. Tables 10–13 pro-  
vide the bit configurations for the various interrupt regis-  
ters. The interrupt latch, interrupt-enable low, and  
interrupt-enable high registers have two addresses that  
implement write- one-set and write-one-clear features for  
each of these registers. Writing a 1 to the set address  
sets that bit to 1. Writing a 1 to the clear address resets  
that bit to 0. Writing a 0 to either address has no effect  
on the bits.  
The MAX3301E powers up in its lowest power state and  
must be turned on by setting the sdwn bit to 0. The  
MAX3302E powers up in the operational, VP/VM USB  
mode. This allows a µP to use the USB port for power-  
on boot-up, without having to access I2C. To put the  
MAX3302E into low-power shutdown, set the sdwn bit  
to 0. The MAX3302E also has special-function register  
2 mapped to two I2C register addresses. In the  
MAX3302E, special-function register 2 can be  
Special-Function Registers  
Tables 14, 15, and 16 describe the special-function  
registers. The special-function registers have two  
addresses that implement write-one-set and write-one-  
clear features for each of these registers. Writing a 1 to  
24 ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ  
USB On-the-Go Transceivers and Charge Pumps  
Table ±±. Interrupt Latch Register Description (Write to Address 0Ah to Set, Write to  
Address 0Bh to Clear)  
kALUE AT  
POWER-UP  
BIT ꢁUMBER  
SYMBOL  
vbus_vld  
sess_vld  
dp_hi  
COꢁTEꢁTS  
vbus_vld asserts if a transition occurs on this condition and the appropriate  
interrupt-high or interrupt-low enable bit is set. See Tables 10, 12, and 13.  
0
1
2
3
4
5
6
7
0
sess_vld asserts if a transition occurs on this condition and the appropriate  
interrupt-high or interrupt-low enable bit is set. See Tables 10, 12, and 13.  
0
0
0
0
0
0
0
dp_hi asserts if a transition occurs on this condition and the appropriate interrupt-  
high or interrupt-low enable bit is set. See Tables 10, 12, and 13.  
id_gnd asserts if a transition occurs on this condition and the appropriate interrupt-  
high or interrupt-low enable bit is set. See Tables 10, 12, and 13.  
id_gnd  
dm_hi asserts if a transition occurs on this condition and the appropriate interrupt-  
high or interrupt-low enable bit is set. See Tables 10, 12, and 13.  
dm_hi  
id_float asserts if a transition occurs on this condition and the appropriate interrupt-  
high or interrupt-low enable bit is set. See Tables 10, 12, and 13.  
id_float  
bdis_acon asserts if a transition occurs on this condition and the appropriate  
interrupt-high or interrupt-low enable bit is set. See Tables 10, 12, and 13.  
bdis_acon  
cr_int_sess_end  
cr_int_sess_end asserts if a transition occurs on this condition and the appropriate  
interrupt-high or interrupt-low enable bit is set. See Tables 10, 12, and 13.  
Table ±2. Interrupt-Enable Low Register (Write to Address 0Ch to Set, Write to Address  
0Dh to Clear)  
kALUE AT  
POWER-UP  
BIT ꢁUMBER  
SYMBOL  
vbus_vld  
sess_vld  
dp_hi  
COꢁTEꢁTS  
Set to 0 to disable the vbus_vld interrupt for a high-to-low transition. Set to 1 to  
enable the vbus_vld interrupt for a high-to-low transition. See Tables 10 and 11.  
0
1
2
3
4
5
6
0
Set to 0 to disable the sess_vld interrupt for a high-to-low transition. Set to 1 to  
enable the sess_vld interrupt for a high-to-low transition. See Tables 10 and 11.  
0
0
0
0
0
0
Set to 0 to disable the dp_hi interrupt for a high-to-low transition. Set to 1 to  
enable the dp_hi interrupt for a high-to-low transition. See Tables 10 and 11.  
Set to 0 to disable the id_gnd interrupt for a high-to-low transition. Set to 1 to  
enable the id_gnd interrupt for a high-to-low transition. See Tables 10 and 11.  
id_gnd  
Set to 0 to disable the dm_hi interrupt for a high-to-low transition. Set to 1 to  
enable the dm_hi interrupt for a high-to-low transition. See Tables 10 and 11.  
dm_hi  
Set to 0 to disable the id_float interrupt for a high-to-low transition. Set to 1 to  
enable the id_float interrupt for a high-to-low transition. See Tables 10 and 11.  
id_float  
Set to 0 to disable the bdis_acon interrupt for a high-to-low transition. Set to 1 to  
enable the bdis_acon interrupt for a high-to-low transition. See Tables 10 and 11.  
bdis_acon  
Set to 0 to disable the cr_int_sess_end interrupt for a high-to-low transition.  
Set to 1 to enable the cr_int_sess_end interrupt for a high-to-low transition.  
See Tables 10 and 11.  
7
cr_int_sess_end  
0
ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ 21  
USB On-the-Go Transceivers and Charge Pumps  
Table ±3. Interrupt-Enable High Register (Write to Address 0Eh to Set, Write to Address  
0Fh to Clear)  
kALUE AT  
POWER-UP  
BIT ꢁUMBER  
SYMBOL  
vbus_vld  
sess_vld  
dp_hi  
COꢁTEꢁTS  
Set to 0 to disable the vbus_vld interrupt for a low-to-high transition. Set to 1 to  
enable the vbus_vld interrupt for a low-to-high transition. See Tables 10 and 11.  
0
1
2
3
4
5
6
0
Set to 0 to disable the sess_vld interrupt for a low-to-high transition. Set to 1 to  
enable the sess_vld interrupt for a low-to-high transition. See Tables 10 and 11.  
0
0
0
0
0
0
Set to 0 to disable the dp_hi interrupt for a low-to-high transition. Set to 1 to  
enable the dp_hi interrupt for a low-to-high transition. See Tables 10 and 11.  
Set to 0 to disable the id_gnd interrupt for a low-to-high transition. Set to 1 to  
enable the id_gnd interrupt for a low-to-high transition. See Tables 10 and 11.  
id_gnd  
Set to 0 to disable the dm_hi interrupt for a low-to-high transition. Set to 1 to  
enable the dm_hi interrupt for a low-to-high transition. See Tables 10 and 11.  
dm_hi  
Set to 0 to disable the id_float interrupt for a low-to-high transition. Set to 1 to  
enable the id_float interrupt for a low-to-high transition. See Tables 10 and 11.  
id_float  
Set to 0 to disable the bdis_acon interrupt for a low-to-high transition. Set to 1 to  
enable the bdis_acon interrupt for a low-to-high transition. See Tables 10 and 11.  
bdis_acon  
Set to 0 to disable the cr_int_sess_end interrupt for a low-to-high transition.  
Set to 1 to enable the cr_int_sess_end interrupt for a low-to-high transition.  
See Tables 10 and 11.  
7
cr_int_sess_end  
0
addressed at I2C register location 10h, 11h (as well as  
locations 16h, 17h) to support USB OTG SIE implemen-  
tations that are limited to I2C register addresses  
between 0h and 15h.  
External Components  
External Resistors  
Two external resistors (27.4Ω 1%) are required for  
USB connection. Install one resistor in series between  
D+ of the MAX3301E/MAX3302E and D+ of the USB  
connector. Install the other resistor in series between D-  
of the MAX3301E/MAX3302E and D- of the USB con-  
nector (see the Typical Operating Circuit).  
ID and Manufacturer Register Address Map  
Table 17 provides the contents of the ID registers of the  
MAX3301E/MAX3302E. Addresses 00h and 01h com-  
prise the vendor ID registers. Addresses 02h and 03h  
comprise the product ID registers. Addresses 14h and  
15h comprise the revision ID registers.  
External Capacitors  
Five external capacitors are recommended for proper  
operation. Install all capacitors as close to the device as  
Audio Car Kit  
Many cell phones are required to interface to car ꢀits.  
Depending upon the car ꢀit, the interface to the phone  
may be required to support any or all of the following  
functions:  
possible. Decouple V to GND with a 0.1µF ceramic  
L
CC  
capacitor. Bypass V  
to GND with a 1µF ceramic  
capacitor. Bypass TRM to GND with a 1µF (or greater)  
ceramic or plastic capacitor. Connect a 100nF flying  
capacitor between C+ and C- for the charge pump (see  
•
•
•
•
Audio input  
the Typical Operating Circuit). Bypass V  
to GND  
BUS  
Audio output  
Charging  
with a 1µF to 6.5µF ceramic capacitor in accordance  
with USB OTG specifications.  
Control and status  
ESD Protection  
To protect the MAX3301E/MAX3302E against ESD, D+,  
D+ and D- of the MAX3301E/MAX3302E go to a high-  
impedance state when in shutdown mode, allowing  
external signals (including audio) to be multiplexed onto  
these lines.  
D-, ID_IN, and V  
, have extra protection against stat-  
BUS  
ic electricity to protect the device up to 15ꢀV. The ESD  
structures withstand high ESD in all states; normal oper-  
26 ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ  
USB On-the-Go Transceivers and Charge Pumps  
Table ±4. Special-Function Register ± (Write to Address ±2h to Set, Write to Address ±3h  
to Clear)  
kALUE AT  
POWER-UP  
BIT ꢁUMBER  
SYMBOL  
COꢁTEꢁTS  
2
Set to 0 for normal operation. Set to 1 to enter interrupt shutdown mode. The I C  
interface and interrupt sources remain active, while all other circuitry is off.  
0
int_sdwn  
0
Set to 0 to control the MAX3301E/MAX3302E behavior with SPD and SUS. Set to 1 to  
control the MAX3301E/MAX3302E behavior with the speed and suspend bits in control  
register 1 (see Table 7).  
1
2
3
4
5
spd_susp_ctl  
bi_di  
0
1
0
0
0
Set to 0 to transfer data from DAT_VP and SE0_VM to D+ and D-, respectively.  
DAT_VP and SE0_VM are always inputs when this bit is 0. Set to 1 to control the  
direction of data transfer with OE/INT.  
Set to 0 to transfer data from SE0_VM to D-. Set to 1 to transfer data from D- to  
SE0_VM. Ensure that gp_en = 1, dat_se0 = 1, uart_en = 0, and OE/INT = low to  
activate this function.  
dminus_dir  
dplus_dir  
int_source  
Set to 0 to transfer data from DAT_VP to D+. Set to 1 to transfer data from D+ to  
DAT_VP. Ensure that gp_en = 1, dat_se0 = 1, uart_en = 0, and OE/INT = low to  
activate this function.  
Set to 0 to use cr_int as the interrupt source for bit 7 of the interrupt source  
register. Set to 1 to use sess_end as the interrupt source for bit 7 of the interrupt  
source register (see Table 10).  
Session end comparator status (read only). Sess_end = 0 when V  
>
BUS  
6
7
sess_end  
gp_en  
—
0
sess_end threshold. Sess_end = 1 when V  
< sess_end threshold.  
BUS  
Set to 0 to disable general-purpose buffer mode. Set to 1 to enable general-  
purpose buffer mode.  
ꢁote: sess_end value at power-up is dependent on the voltage at V  
.
BUS  
Table ±1. MAX330±E Special-Function Register 2 (Write to Address ±6h to Set, Write to  
Address ±7h to Clear)  
kALUE AT  
POWER-UP  
BIT ꢁUMBER  
SYMBOL  
sdwn  
COꢁTEꢁTS  
2
Set to 0 for normal operation. Set to 1 to enable shutdown mode. Only the I C  
interface remains active in shutdown.  
0
1
2
1
Set to 0 to set INT and OE/INT as open-drain outputs. Set to 1 to set INT and  
OE/INT as push-pull outputs.  
irq_mode  
0
0
Set to 0 to leave the D+/D- single-ended receiver inputs connected. Set to 1 to  
disconnect the D+/D- receiver inputs to reduce power consumption in audio mode.  
xcvr_input_disc  
3
reg_sel  
—
Set to 0 to power TRM from V . Set to 1 to power TRM from V  
CC  
.
0
BUS  
4–7  
Reserved. Set to 0 for normal operation.  
0000  
ation, suspend mode, interrupt shutdown, and shut-  
down. For the ESD structures to worꢀ correctly, connect  
a 1µF or greater capacitor from TRM to GND and from  
•
•
15ꢀV using the Human Body Model  
6ꢀV using the IEC 61000-4-2 Contact Discharge  
Method  
V
to GND. ESD protection can be tested in various  
BUS  
•
10ꢀV using the IEC 61000-4-2 Air-Gap Discharge  
Method  
ways; the D+, D-, ID_IN, and V  
inputs/outputs are  
BUS  
characterized for protection to the following limits:  
ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ 27  
USB On-the-Go Transceivers and Charge Pumps  
Table ±6. MAX3302E Special-Function Register 2 (Write to Address ±0h or ±6h to Set,  
Write to Address ±±h or ±7h to Clear)  
kALUE AT  
POWER-UP  
BIT ꢁUMBER  
SYMBOL  
COꢁTEꢁTS  
2
Set to 0 to enable shutdown mode. Set to 1 for normal operation. Only the I C  
interface remains active in shutdown.  
0
1
2
sdwn  
1
Set to 0 to set INT and OE/INT as open-drain outputs. Set to 1 to set INT and  
OE/INT as push-pull outputs.  
irq_mode  
0
0
Set to 0 to leave the D+/D- single-ended receiver inputs connected. Set to 1 to  
disconnect the D+/D- receiver inputs to reduce power consumption in audio mode.  
xcvr_input_disc  
3
reg_sel  
—
Set to 0 to power TRM from V . Set to 1 to power TRM from V  
CC  
.
0
BUS  
4–7  
Reserved. Set to 0 for normal operation.  
0000  
test involves approaching the device with a charged  
probe. The contact discharge method connects the  
probe to the device before the probe is energized.  
Figure 25 shows the IEC 61000-4-2 current waveform.  
Table ±7. ID Registers  
REGISTER  
ADDRESS  
COꢁTEꢁTS  
6Ah  
00h  
01h  
02h  
03h  
14h  
15h  
Vendor ID  
0Bh  
Layout Considerations  
The MAX3301E/MAX3302E high operating frequency  
maꢀes proper layout important to ensure stability and  
maintain the output voltage under all loads. For best  
performance, minimize the distance between the  
bypass capacitors and the MAX3301E/MAX3302E. Use  
symmetric trace geometry from D+ and D- to the USB  
connector.  
01h  
Product ID  
Revision ID  
33h  
77h  
41h  
ESD performance depends on a variety of conditions.  
Contact Maxim for a reliability report that documents  
test setup, methodology, and results.  
UCSP Applications Information  
For the latest application details on UCSP construction,  
dimensions, tape carrier information, PC board tech-  
niques, bump-pad layout, and the recommended reflow  
temperature profile, as well as the latest information on  
reliability testing results, refer to the Application Note:  
UCSP—A Wafer-Level Chip-Scale Package available on  
Maxim’s website at www.maxim-ic.com/ucsp.  
Human Body Model  
Figure 22 shows the Human Body Model and Figure 23  
shows the current waveform it generates when dis-  
charged into a low impedance. This model consists of a  
100pF capacitor charged to the ESD voltage of interest,  
which is then discharged into the test device through a  
1.5ꢀΩ resistor.  
IEC 61000-4-2  
The IEC 61000-4-2 standard covers ESD testing and  
performance of finished equipment; it does not specifi-  
cally refer to integrated circuits. The MAX3301E/  
MAX3302E helps the user design equipment that meets  
level 3 of IEC 61000-4-2, without the need for additional  
ESD-protection components. The major difference  
between tests done using the Human Body Model and  
IEC 61000-4-2 is a higher peaꢀ current in IEC 61000-4-2,  
due to the fact that series resistance is lower in the IEC  
61000-4-2 model. Hence, the ESD-withstand voltage  
measured to IEC 61000-4-2 is generally lower than that  
measured using the Human Body Model. Figure 24  
shows the IEC 61000-4-2 model. The Air-Gap Discharge  
28 ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ  
USB On-the-Go Transceivers and Charge Pumps  
R
R
1MΩ  
D
C
I
1.5kΩ  
100%  
DISCHARGE  
RESISTANCE  
CHARGE-CURRENT-  
LIMIT RESISTOR  
90%  
HIGH-  
VOLTAGE  
DC  
DEVICE  
UNDER  
TEST  
C
100pF  
STORAGE  
CAPACITOR  
s
SOURCE  
Figure 22. Human Body ESD Test Modes  
10%  
t
t
R
= 0.7ns TO 1ns  
I 100%  
P
90%  
PEAK-TO-PEAK RINGING  
(NOT DRAWN TO SCALE)  
I
r
30ns  
60ns  
AMPERES  
Figure 25. IEC 61000-4-2 Current Waveform  
36.8%  
10%  
0
Chip Information  
TIME  
0
t
RL  
PROCESS: BiCMOS  
t
DL  
CURRENT WAVEFORM  
Figure 23. Human Body Model Current Waveform  
R
C
R
D
50MΩ to 100MΩ  
330Ω  
DISCHARGE  
RESISTANCE  
CHARGE-CURRENT-  
LIMIT RESISTOR  
HIGH-  
VOLTAGE  
DC  
DEVICE  
UNDER  
TEST  
C
s
150pF  
STORAGE  
CAPACITOR  
SOURCE  
Figure 24. IEC 61000-4-2 ESD Test Model  
ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ 29  
USB On-the-Go Transceivers and Charge Pumps  
Pin Configurations  
TOP VIEW  
BOTTOM VIEW  
MAX3301E/MAX3302E  
24 23 22 21 20 19 18 17  
SDA  
GND  
V
SUS  
OE/INT  
RCV  
SPD  
L
25  
26  
27  
28  
29  
N.C.  
VM  
16 SUS  
A
B
V
L
15  
RESET  
SCL  
INT  
TRM  
N.C.  
SPD  
14  
13  
12  
11  
10  
9
RCV  
C-  
ID_IN  
VM  
GND  
D-  
SE0_VM  
DAT_VP  
ADD  
VP  
MAX3301E  
V
CC  
C
D
E
N.C.  
VP 30  
BUS 31  
C+ 32  
OE/INT  
SCL  
V
CC  
V
EXPOSED PADDLE  
N.C.  
C+  
1
TRM  
D+  
V
V
CC  
BUS  
2
1
2
3
4
5
6
7
8
3
4
5
UCSP  
(2.5mm x 2.5mm)  
TQFꢁ  
(5mm x 5mm)  
TOP VIEW  
21 20 19 18 17 16 15  
14  
13  
VM 22  
SUS  
V
L
N.C. 23  
12 SPD  
24  
25  
26  
27  
28  
TRM  
RCV  
11  
10  
9
V
CC  
MAX3302E  
VP  
OE/INT  
N.C.  
V
BUS  
C+  
EXPOSED PADDLE  
8
SCL  
1
2
3
4
5
6
7
TQFꢁ  
(4mm x 4mm)  
30 ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ  
USB On-the-Go Transceivers and Charge Pumps  
Typical Operating Circuit  
V
V
V
V
L
CC  
1µF  
0.1µF  
*USB OTG SPECIFICATIONS LIMIT  
THE TOTAL CAPACITANCE ON V  
FROM 1µF (MIN) TO 6.5µF (MAX)  
FOR A DUAL-ROLE DEVICE.  
V
L(I/O)  
L
BUS  
CC  
V
DAT_VP  
SE0_VM  
RCV  
BUS  
C
VBUS  
*
4.7µF  
27.4Ω  
27.4Ω  
V
BUS  
D+  
D-  
VP  
D+  
D-  
MAX3301E  
MAX3302E  
VM  
OEV/INT  
INT  
ID_IN  
ID  
ASIC  
GND  
C+  
RESET  
SUS  
OTG  
CONNECTOR  
C
0.1µF  
FLYING  
SPD  
C-  
SDA  
SCL  
ADD  
TRM  
GND  
1µF  
ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ 3±  
USB On-the-Go Transceivers and Charge Pumps  
Package Information  
(The pacꢀage drawing(s) in this data sheet may not reflect the most current specifications. For the latest pacꢀage outline information,  
go to www.maxim-ic.com/pac5ages.)  
D2  
D
b
0.10 M  
C A B  
C
L
D2/2  
D/2  
k
L
MARKING  
AAAAA  
E/2  
E2/2  
C
(NE-1) X  
e
L
E2  
E
PIN # 1 I.D.  
0.35x45°  
DETAIL A  
e/2  
PIN # 1  
I.D.  
e
(ND-1) X  
e
DETAIL B  
e
L
C
L
C
L
L1  
L
L
e
e
0.10  
C
A
0.08  
C
C
A3  
A1  
PACKAGE OUTLINE,  
16, 20, 28, 32, 40L THIN QFN, 5x5x0.8mm  
1
-DRAWING NOT TO SCALE-  
I
21-0140  
2
32 ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ  
USB On-the-Go Transceivers and Charge Pumps  
Package Information (continued)  
(The pacꢀage drawing(s) in this data sheet may not reflect the most current specifications. For the latest pacꢀage outline information,  
go to www.maxim-ic.com/pac5ages.)  
COMMON DIMENSIONS  
EXPOSED PAD VARIATIONS  
PKG.  
16L 5x5  
20L 5x5  
28L 5x5  
32L 5x5  
40L 5x5  
L
DOWN  
BONDS  
ALLOWED  
D2  
E2  
exceptions  
PKG.  
SYMBOL MIN. NOM. MAX. MIN. NOM. MAX. MIN. NOM. MAX. MIN. NOM. MAX. MIN. NOM. MAX.  
CODES  
±0.15  
MIN. NOM. MAX. MIN. NOM. MAX.  
3.00 3.10 3.20 3.00 3.10 3.20  
3.00 3.10 3.20 3.00 3.10 3.20  
A
0.70 0.75 0.80 0.70 0.75 0.80 0.70 0.75 0.80 0.70 0.75 0.80 0.70 0.75 0.80  
0.02 0.05 0.02 0.05 0.02 0.05 0.02 0.05 0.02 0.05  
0.20 REF. 0.20 REF. 0.20 REF. 0.20 REF. 0.20 REF.  
T1655-2  
T1655-3  
YES  
NO  
NO  
**  
**  
**  
**  
A1  
0
0
0
0
0
A3  
b
T1655N-1 3.00 3.10 3.20 3.00 3.10 3.20  
0.25 0.30 0.35 0.25 0.30 0.35 0.20 0.25 0.30 0.20 0.25 0.30 0.15 0.20 0.25  
4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10  
4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10  
T2055-3  
T2055-4  
T2055-5  
T2855-3  
3.00 3.10 3.20 3.00 3.10 3.20  
3.00 3.10 3.20 3.00 3.10 3.20  
YES  
NO  
D
E
**  
YES  
3.15 3.25 3.35 3.15 3.25 3.35 0.40  
e
0.80 BSC.  
0.25  
0.65 BSC.  
0.25  
0.50 BSC.  
0.25  
0.50 BSC.  
0.25  
0.40 BSC.  
3.15 3.25 3.35 3.15 3.25 3.35  
YES  
YES  
NO  
**  
**  
**  
k
-
-
-
-
-
-
-
-
0.25 0.35 0.45  
T2855-4  
T2855-5  
2.60 2.70 2.80 2.60 2.70 2.80  
2.60 2.70 2.80 2.60 2.70 2.80  
3.15 3.25 3.35 3.15 3.25 3.35  
L
0.30 0.40 0.50 0.45 0.55 0.65 0.45 0.55 0.65 0.30 0.40 0.50 0.40 0.50 0.60  
L1  
-
-
-
-
-
-
-
-
-
-
-
-
0.30 0.40 0.50  
NO  
YES  
YES  
T2855-6  
T2855-7  
**  
**  
N
ND  
NE  
16  
4
4
20  
5
5
28  
7
7
32  
8
8
40  
10  
10  
2.80  
2.60 2.70  
2.60 2.70 2.80  
T2855-8  
3.15 3.25 3.35 3.15 3.25 3.35 0.40  
WHHB  
WHHC  
WHHD-1  
WHHD-2  
-----  
JEDEC  
T2855N-1 3.15 3.25 3.35 3.15 3.25 3.35  
NO  
YES  
NO  
YES  
NO  
**  
**  
**  
**  
**  
**  
3.20  
3.00 3.10 3.20  
T3255-3  
T3255-4  
T3255-5  
3.00 3.10  
3.00 3.10 3.20 3.00 3.10 3.20  
3.20  
NOTES:  
3.00 3.10  
3.00 3.10 3.20  
1. DIMENSIONING & TOLERANCING CONFORM TO ASME Y14.5M-1994.  
2. ALL DIMENSIONS ARE IN MILLIMETERS. ANGLES ARE IN DEGREES.  
3. N IS THE TOTAL NUMBER OF TERMINALS.  
T3255N-1 3.00 3.10 3.20 3.00 3.10 3.20  
T4055-1 3.20 3.30 3.40 3.20 3.30 3.40  
YES  
**SEE COMMON DIMENSIONS TABLE  
4. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL  
CONFORM TO JESD 95-1 SPP-012. DETAILS OF TERMINAL #1 IDENTIFIER ARE  
OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE TERMINAL #1  
IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE.  
5. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN  
0.25 mm AND 0.30 mm FROM TERMINAL TIP.  
6. ND AND NE REFER TO THE NUMBER OF TERMINALS ON EACH D AND E SIDE RESPECTIVELY.  
7. DEPOPULATION IS POSSIBLE IN A SYMMETRICAL FASHION.  
8. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS.  
9. DRAWING CONFORMS TO JEDEC MO220, EXCEPT EXPOSED PAD DIMENSION FOR  
T2855-3 AND T2855-6.  
10. WARPAGE SHALL NOT EXCEED 0.10 mm.  
11. MARKING IS FOR PACKAGE ORIENTATION REFERENCE ONLY.  
12. NUMBER OF LEADS SHOWN ARE FOR REFERENCE ONLY.  
13. LEAD CENTERLINES TO BE AT TRUE POSITION AS DEFINED BY BASIC DIMENSION "e", ±0.05.  
PACKAGE OUTLINE,  
16, 20, 28, 32, 40L THIN QFN, 5x5x0.8mm  
2
-DRAWING NOT TO SCALE-  
21-0140  
I
2
ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ 33  
USB On-the-Go Transceivers and Charge Pumps  
Package Information (continued)  
(The pacꢀage drawing(s) in this data sheet may not reflect the most current specifications. For the latest pacꢀage outline information,  
go to www.maxim-ic.com/pac5ages.)  
PACKAGE OUTLINE,  
12, 16, 20, 24, 28L THIN QFN, 4x4x0.8mm  
1
E
21-0139  
2
PACKAGE OUTLINE,  
12, 16, 20, 24, 28L THIN QFN, 4x4x0.8mm  
2
E
21-0139  
2
34 ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ  
USB On-the-Go Transceivers and Charge Pumps  
Package Information (continued)  
(The pacꢀage drawing(s) in this data sheet may not reflect the most current specifications. For the latest pacꢀage outline information,  
go to www.maxim-ic.com/pac5ages.)  
PACKAGE OUTLINE, 5x5 UCSP  
1
21-0096  
H
1
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are  
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.  
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 31  
© 2006 Maxim Integrated Products  
Printed USA  
is a registered trademarꢀ of Maxim Integrated Products, Inc.  

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