MAX3111EEWI+G36 [MAXIM]
Serial I/O Controller, 1 Channel(s), CMOS, PDSO28, 0.300 INCH, ROHS COMPLIANT, MS-013AE, SOIC-28;
| 型号： | MAX3111EEWI+G36 |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Serial I/O Controller, 1 Channel(s), CMOS, PDSO28, 0.300 INCH, ROHS COMPLIANT, MS-013AE, SOIC-28 光电二极管 |
| 文件： | 总32页 (文件大小：409K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-1494; Rev 0; 7/99
SPI/MICROWIRE-Compatible UART and ±15kV ESD-
Protected RS-232 Transceivers with Internal Capacitors
0/MAX31E
General Description
Features
The MAX3110E/MAX3111E combine a full-featured uni-
versal asynchronous receiver/transmitter (UART) with
±15kV ESD-protected RS-232 transceivers and inte-
grated charge-pump capacitors into a single 28-pin
package for use in space-, cost-, and power-con-
strained applications. The MAX3110E/MAX3111E also
feature an SPI™/QSPI™/MICROWIRE™-compatible
serial interface to save additional board space and
microcontroller (µC) I/O pins.
♦ Integrated RS-232 Transceiver and UART in a
Single 28-Pin Package
♦ SPI/QSPI/MICROWIRE-Compatible µC Interface
♦ Internal Charge-Pump Capacitors—
No External Components Required!
♦ True RS-232 Operation Down to V
= +3V
CC
(MAX3111E)
♦ ESD Protection for RS-232 I/O Pins
A proprietary low-dropout output stage enables the
2-driver/2-receiver interface to deliver true RS-232 per-
±15kV—Human Body Model
±8kV—IEC 1000-4-2, Contact Discharge
±15kV—IEC 1000-4-2, Air-Gap Discharge
formance down to V
= +3V (+4.5V for MAX3110E)
CC
while consuming only 600µA. The receivers remain
active in a hardware/software-invoked shutdown, allow-
ing external devices to be monitored while consuming
only 10µA. Each device is guaranteed to operate at up
to 230kbps while maintaining true EIA/TIA-232 output
voltage levels.
♦ Single-Supply Operation
+5V (MAX3110E)
+3.3V (MAX3111E)
♦ Low Power
600µA Supply Current
10µA Shutdown Supply Current with
Receiver Interrupt Active
The MAX3110E/MAX3111E’s UART includes a crystal
oscillator and baud-rate generator with software-pro-
grammable divider ratios for all common baud rates
from 300baud to 230kbaud. The UART features an 8-
word-deep receive FIFO that minimizes processor over-
head and provides a flexible interrupt with four
maskable sources. Two control lines (one input and
one output) are included for hardware handshaking.
♦ Guaranteed 230kbps Data Rate
♦ Hardware/Software-Compatible with MAX3100
and MAX3222E
Ordering Information
The UART and RS-232 functions can be used together
or independently since the two functions share only
supply and ground connections (the MAX3110E/
MAX3111E are hardware- and software-compatible
with the MAX3100 and MAX3222E).
TEMP.
RANGE
PIN-
PACKAGE
V
CC
(V)
PART
MAX3110ECWI 0°C to +70°C
MAX3110ECNI 0°C to +70°C
28 Wide SO
5
5
28 Plastic DIP
Ordering Information continued at end of data sheet.
________________________Applications
Point-of-Sale (POS) Devices
Typical Application Circuit
Handy-Terminals
MAX3110E
MAX3111E
Telecom/Networking Diagnostic Ports
Industrial Front-Panel Interfaces
Hand-Held/Battery-Powered Equipment
SPI
RS-232
DB-9
CS
U
A
R
T
SCLK
DIN
1
2
3
4
5
µP
DOUT
Pin Configuration appears at end of data sheet.
6
7
8
9
†
Covered by U.S. Patent numbers 4,636,930; 4,679,134;
IRQ
4,777,577; 4,797,899; 4,809,152; 4,897,774; 4,999,761; and
other patents pending.
SPI and QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corp.
________________________________________________________________ Maxim Integrated Products
1
For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800.
For small orders, phone 1-800-835-8769.
SPI/MICROWIRE-Compatible UART and ±15kV ESD-
Protected RS-232 Transceivers with Internal Capacitors
ABSOLUTE MAXIMUM RATINGS
V
V
to GND (MAX3110E) ........................................-0.3V to +6V
to GND (MAX3111E).........................................-0.3V to +4V
TX, RTS Output Current ....................................................100mA
Short-Circuit Duration
CC
CC
V+ to GND (Note 1)..................................................-0.3V to +7V
V- to GND (Note 1) ...................................................+0.3V to -7V
V+ to V- (Note 1)..................................................................+13V
Input Voltages to GND
X2, DOUT, IRQ (to V
T_OUT (to GND) .....................................................Continuous
Continuous Power Dissipation (T = +70°C)
28-pin Wide SO (derate 12.5mW/°C above +70°C) ...........1W
28-pin Plastic DIP (derate 14.3mW/°C above +70°C) ....1.14W
Operating Temperature Ranges
MAX311_EC_ _ .................................................. 0°C to +70°C
MAX311_EE_ _ ................................................-40°C to +85°C
Storage Temperature Range ............................-65°C to +150°C
Lead Temperature (soldering, 10sec) .............................+300°C
or GND).............................Continuous
CC
A
CS, X1, CTS, RX, DIN, SCLK.................. -0.3V to (V + 0.3V)
CC
T_IN, SHDN ...........................................................-0.3V to +6V
R_IN ..................................................................................±25V
Output Voltage to GND
DOUT, RTS, TX, X2 .................................-0.3V to (V + 0.3V)
CC
IRQ .......................................................................-0.3V to +6V
T_OUT ...........................................................................±13.2V
R_OUT.....................................................-0.3V to (V
+ 0.3V)
CC
Note 1: V+ and V- can have maximum magnitudes of 7V, but their absolute difference should not exceed 13V.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and function-
al operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure
to absolute maximum rating conditions for extended periods may affect device reliability.
0/MAX31E
ELECTRICAL CHARACTERISTICS—MAX3110E
(V
= +4.5V to +5.5V, T = T
to T , unless otherwise noted. Typical values are measured for baud rate set to 9600baud at
MAX
CC
A
MIN
V
= +5V, T = +25°C.) (Note 2)
CC
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DC CHARACTERISTICS (V
= +5V, T = +25°C)
A
CC
Supply Current
I
0.6
2
1
mA
mA
SHDN = V , no load
CC
CC
Supply Current with Hardware
Shutdown
I
0.48
SHDN = GND (Note 3)
CCSHDN(H)
Supply Current with Hardware
and Software Shutdown
I
3
20
µA
SHDN = GND, SHDNi bit = 1 (Note 4)
CCSHDN(H+ S)
UART OSCILLATOR INPUT (X1)
Input High Voltage
V
V
V
0.7V
CC
IH1
Input Low Voltage
V
0.2V
CC
IL1
SHDNi bit = 0
25
2
Input Current
I
V
= 0 or 5.5V
µA
pF
IN1
X1
SHDNi bit = 1
Input Capacitance
C
IN1
5
UART LOGIC INPUTS (DIN, SCLK, CS, CTS, RX)
Input High Voltage
V
0.7V
V
V
IH2
CC
Input Low Voltage
V
0.3V
CC
IL2
Input Hysteresis
V
250
5
mV
µA
pF
HYST2
Input Leakage Current
Input Capacitance
I
±1
LKG1
C
IN2
RS-232 LOGIC INPUTS (T_IN, SHDN)
Input High Voltage
V
V
= 5V
2.4
IH3
CC
Input Low Voltage
V
0.8
±1
V
IL3
Transmitter Input Hysteresis
Input Leakage Current
V
500
mV
µA
HYST3
I
±0.01
IN3
2
_______________________________________________________________________________________
SPI/MICROWIRE-Compatible UART and ±15kV ESD-
Protected RS-232 Transceivers with Internal Capacitors
0/MAX31E
ELECTRICAL CHARACTERISTICS—MAX3110E (continued)
(V
= +4.5V to +5.5V, T = T
to T
, unless otherwise noted. Typical values are measured for baud rate set to 9600baud at
MAX
CC
A
MIN
V
= +5V, T = +25°C.) (Note 2)
CC
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
+25
0.8
7
UNITS
RS-232 RECEIVER INPUTS (R_IN)
Input Voltage Range
Input High Voltage
-25
2.4
V
V
V
IH4
T
T
= +25°C, V
= +25°C, V
= 5V
= 5V
A
CC
Input Low Voltage
V
V
IL4
A
CC
Input Hysteresis
V
500
5
mV
kΩ
HYST4
Input Resistance
R
T
A
= +25°C
3
IN
RS-232 ESD PROTECTION (R_IN, T_OUT)
Human Body Model
±15
±15
±8
ESD Protection
IEC 1000-4-2 Air Discharge
IEC 1000-4-2 Contact Discharge
kV
RS-232 RECEIVER OUTPUTS (R_OUT)
Output High Voltage
Output Low Voltage
Receiversdisabled
±0.05
±10
0.4
µA
V
V
I
= 1.6mA
SINK
OL1
RS-232 TRANSMITTER OUTPUTS (T_OUT)
Output Voltage Swing
3kΩ load on all transmitter outputs
= V+ = V- = 0, V = ±2V
5
±5.4
V
Ω
Output Resistance
R
V
300
10M
OUT
O
CC
Output Short-Circuit Current
±60
mA
V
= 0 or 5.5V, V
= ±12V,
CC
OUT
Output Leakage Current
I
I
±25
µA
LKG2
transmitters disabled
UART OUTPUTS (DOUT, TX, RTS)
Output Leakage Current
±1
µA
V
DOUT only, CS = V
LKG3
CC
V
V
- 0.5
I
= 5mA; DOUT, RTS
CC
SOURCE
SOURCE
Output High Voltage
V
OH2
I
= 10mA; TX only
= 4mA; DOUT, RTS
= 25mA; TX only
- 0.5
CC
0.4
0.9
I
SINK
Output Low Voltage
Output Capacitance
V
V
OL2
I
SINK
C
5
5
pF
OUT1
UART IRQ OUTPUTS (IRQ = open drain)
Output Leakage Current
Output Low Voltage
I
V
= 5.5V
= 4mA
±1
µA
V
LKG4
IRQ
V
I
0.4
OL3
SINK
Output Capacitance
C
pF
OUT2
UART AC TIMING
t
C
= 100pF
LOAD
100
100
ns
ns
ns
ns
ns
CS Low to DOUT Valid
CS High to DOUT Tri-State
CS to SCLK Setup Time
CS to SCLK Hold Time
SCLK Fall to DOUT Valid
DV
t
C
LOAD
= 100pF, R
= 10kΩ
CS
TR
t
t
100
CSS
0
CSH
t
C
LOAD
= 100pF
100
DO
_______________________________________________________________________________________
3
SPI/MICROWIRE-Compatible UART and ±15kV ESD-
Protected RS-232 Transceivers with Internal Capacitors
ELECTRICAL CHARACTERISTICS—MAX3110E (continued)
(V
= +4.5V to +5.5V, T = T
to T
, unless otherwise noted. Typical values are measured for baud rate set to 9600baud at
MAX
CC
A
MIN
V
= +5V, T = +25°C.) (Note 2)
CC
A
PARAMETER
SYMBOL
CONDITIONS
MIN
100
0
TYP
MAX
UNITS
ns
DIN to SCLK Setup Time
DIN to SCLK Hold Time
SCLK Period
t
DS
t
ns
DH
t
238
100
100
100
ns
CP
SCLK High Time
t
ns
CH
SCLK Low Time
t
ns
CL
t
ns
SCLK Rising Edge to CS Falling
CS0
CS Rising Edge to SCLK Rising
Edge
t
200
200
ns
CS1
CS High Pulse Width
Output Rise Time
Output Fall Time
t
ns
ns
ns
CSW
t
r
10
10
TX, RTS, DOUT; C = 100pF
L
t
f
TX, RTS, DOUT, IRQ; C = 100pF
L
RS-232 AC TIMING
R = 3kΩ, C = 1000pF,
one transmitter switching
L
L
Maximum Data Rate
250
kbps
ns
0/MAX31E
t
Receiver input to receiver output
150
150
100
50
PHL
Receiver Propagation Delay
t
C = 150pF
L
PLH
Transmitter Skew
Receiver Skew
|t
|t
- t
|
|
(Note 5)
ns
ns
PHL PLH
- t
PHL PLH
V
= 5V,
CC
L
C = 150pF to
L
1000pF
6
4
30
30
R = 3kΩ to 7kΩ,
T
= +25°C,
A
Transition-Region Slew Rate
V/µs
measured from
+3V to -3V or
-3V to +3V
C = 150pF to
L
2500pF
4
_______________________________________________________________________________________
SPI/MICROWIRE-Compatible UART and ±15kV ESD-
Protected RS-232 Transceivers with Internal Capacitors
0/MAX31E
ELECTRICAL CHARACTERISTICS—MAX3111E
(V
= +3.0V to +3.6V, V = T
to T
, unless otherwise noted. Typical values are measured for baud rate set to 9600baud at
MAX
CC
CC
A
MIN
V
= +3.3V, T = +25°C.) (Note 2)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DC CHARACTERISTICS (V
= 3.3V, T = +25°C)
A
CC
Supply Current
I
0.45
0.18
1.4
0.4
mA
mA
SHDN = V , no load
CC
CC
Supply Current with Hardware
Shutdown
I
SHDN = GND (Note 3)
CCSHDN(H)
Supply Current with Hardware
and Software Shutdown
I
1
5
20
µA
SHDN = GND SHDNi bit = 1 (Note 4)
CCSHDN(H+ S)
UART OSCILLATOR INPUT (X1)
Input High Voltage
V
V
V
0.7V
CC
IH1
Input Low Voltage
V
0.2V
IL1
CC
25
2
SHDNi bit = 0
Input Current
I
V
= 0 or 3.6V
µA
pF
IN1
X1
SHDNi bit = 1
Input Capacitance
C
IN1
UART LOGIC INPUTS (DIN, SCLK, CS, RX)
Input High Voltage
Input Low Voltage
Input Hysteresis
V
0.7V
V
V
IH2
CC
V
0.3V
CC
IL2
V
165
5
mV
µA
pF
HYST2
Input Leakage Current
Input Capacitance
I
±1
LKG1
C
IN2
RS-232 LOGIC INPUTS (T_IN, SHDN)
Input High Voltage
V
V
= 3.3V
2.0
V
V
IH3
CC
Input Low Voltage
V
0.8
±1
+25
0.6
7
IL3
Transmitter Input Hysteresis
Input Leakage Current
RS-232 RECEIVER INPUTS (R_IN)
Input Voltage Range
Input High Voltage
V
500
mV
µA
HYST3
I
±0.01
IN3
-25
2.4
V
V
V
IH4
T
T
= +25°C, V
= +25°C, V
= 3.3V
A
CC
Input Low Voltage
V
= 3.3V
V
IL4
A
CC
Input Hysteresis
V
500
5
mV
kΩ
HYST4
Input Resistance
R
T
A
= +25°C
3
IN
RS-232 ESD PROTECTION (R_IN, T_OUT)
Human Body Model
±15
±15
±8
ESD Protection
IEC 1000-4-2 Air Discharge
IEC 1000-4-2 Contact Discharge
kV
_______________________________________________________________________________________
5
SPI/MICROWIRE-Compatible UART and ±15kV ESD-
Protected RS-232 Transceivers with Internal Capacitors
ELECTRICAL CHARACTERISTICS—MAX3111E (continued)
(V
= +3.0V to +3.6V, V = T
to T
, unless otherwise noted. Typical values are measured for baud rate set to 9600baud at
CC
A
MIN
MAX
V
= +3.3V, T = +25°C.) (Note 2)
CC
A
PARAMETER
SYMBOL
CONDITION
MIN
TYP
MAX
UNITS
RS-232 RECEIVER OUTPUTS (R_OUT)
Output High Voltage
Output Low Voltage
V
I
I
= 1mA
V
- 0.6
CC
V
V
OH1
SOURCE
V
= 1.6mA
SINK
0.4
OL1
RS-232 TRANSMITTER OUTPUTS (T_OUT)
Output Voltage Swing
3kΩ load on all transmitter outputs
±5
300
±5.4
10M
V
Ω
Output Resistance
R
V
= V+ = V- = 0, V
= ±2V
OUT
O
CC
Output Short-Circuit Current
±60
±25
mA
V
= 0 or 3.6V, V
= ±12V,
CC
OUT
Output Leakage Current
I
I
µA
LKG2
transmitters disabled
UART OUTPUTS (DOUT, TX, RTS)
Output Leakage Current
±1
µA
V
DOUT only; CS = V
LKG3
CC
V
V
- 0.5
I
= 5mA; DOUT, RTS
CC
CC
SOURCE
SOURCE
Output High Voltage
V
OH2
I
= 10mA, TX only
= 4mA; DOUT, RTS
= 25mA, TX only
- 0.5
0.4
0.9
I
0/MAX31E
SINK
Output Low Voltage
Output Capacitance
V
V
OL2
I
SINK
C
5
5
pF
OUT1
UART IRQ OUTPUT (IRQ = open drain)
Output Leakage Current
Output Low Voltage
I
V
= 3.6V
= 4mA
±1
µA
V
LKG4
IRQ
V
I
0.4
OL3
SINK
Output Capacitance
UART AC TIMING
C
pF
OUT2
t
C
C
= 100pF
LOAD
100
100
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CS Low to DOUT Valid
CS High to DOUT Tri-State
CS to SCLK Setup Time
CS to SCLK Hold Time
SCLK Fall to DOUT Valid
DIN to SCLK Setup Time
DIN to SCLK Hold Time
SCLK Period
DV
t
= 100pF, R
= 10kΩ
CS
TR
LOAD
t
t
100
CSS
0
CSH
t
C
= 100pF
100
DO
LOAD
t
100
0
DS
t
DH
t
238
100
100
100
CP
SCLK High Time
t
CH
SCLK Low Time
t
CL
t
SCLK Rising Edge to CS Falling
CS0
CS Rising Edge to SCLK Rising
Edge
t
200
200
ns
CS1
t
ns
ns
ns
CS High Pulse Width
Output Rise Time
Output Fall Time
CSW
t
r
10
10
TX, RTS, DOUT; C
= 100pF
LOAD
t
f
TX, RTS, DOUT, IRQ; C
= 100pF
LOAD
6
_______________________________________________________________________________________
SPI/MICROWIRE-Compatible UART and ±15kV ESD-
Protected RS-232 Transceivers with Internal Capacitors
0/MAX31E
ELECTRICAL CHARACTERISTICS—MAX3111E (continued)
(V
= +3.0V to +3.6V, V = T
to T
, unless otherwise noted. Typical values are measured for baud rate set to 9600baud at
CC
A
MIN
MAX
V
= +3.3V, T = +25°C.) (Note 2)
CC
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
RS-232 AC TIMING
R = 3kΩ, C = 1000pF,
one-transmitter switching
L
L
Maximum Data Rate
250
kbps
t
t
Receiver input to receiver output
150
150
200
100
ns
PHL
Receiver Propagation Delay
C = 150pF
L
PLH
Transmitter Skew
Receiver Skew
|t
|t
- t
|
|
(Note 5)
ns
ns
PHL PLH
- t
PHL PLH
V
= 3.3V,
CC
L
C = 150pF to
L
1000pF
6
4
30
30
R = 3kΩ to 7kΩ,
T
A
= +25°C,
Transition-Region Slew Rate
V/µs
measured from
+3V to -3V or
-3V to +3V
C = 150pF to
L
2500pF
Note 2: All currents into the device are positive; all currents out of the device are negative. All voltages are referred to device
ground unless otherwise noted.
Note 3: I
represents a hardware-only shutdown. In hardware shutdown, the UART is in normal operation and the charge
CCSHDN(H)
pumps for the RS-232 transmitters are shut down.
Note 4: I
represents a simultaneous software and hardware shutdown in which the UART and charge pumps are
CCSHDN(H+S)
shut down.
Note 5: Transmitter skew is measured at the transmitter zero cross points.
_______________________________________________________________________________________
7
SPI/MICROWIRE-Compatible UART and ±15kV ESD-
Protected RS-232 Transceivers with Internal Capacitors
Typical Operating Characteristics
(T = +25°C, unless otherwise noted.)
A
UART SUPPLY CURRENT
vs. BAUD RATE
UART SHUTDOWN CURRENT
vs. TEMPERATURE
UART SUPPLY CURRENT vs. TEMPERATURE
1000
10
400
350
1.8432MHz CRYSTAL
TRANSMITTING AT 115.2kbps
1.8432MHz CRYSTAL
1.8432MHz
CRYSTAL
+5V
900
9
8
7
6
TRANSMITTING
800
700
600
500
300
250
200
150
100
50
+5V
STANDBY
MAX3110E
5
4
3
MAX3110E, V = +5V
CC
400
300
200
100
0
+3V
TRANSMITTING
MAX3111E, V = +3.3V
CC
MAX3110E, V = +5V
CC
MAX3111E, V = +3.3V
CC
2
1
0
MAX3111E
+3V
STANDBY
-40 -20
0
20
40
60
80 100
-40 -20
0
20
40
60
80 100
100
1000
10k
100k
1M
TEMPERATURE (°C)
TEMPERATURE (°C)
BAUD RATE (bps)
MAX3110E
MAX3111E
TX, RTS, DOUT OUTPUT CURRENT
TX, RTS, DOUT OUTPUT CURRENT
UART SUPPLY CURRENT vs.
EXTERNAL CLOCK FREQUENCY
0/MAX31E
vs. OUTPUT LOW VOLTAGE (V = +5V)
vs. OUTPUT LOW VOLTAGE (V = +3.3V)
CC
CC
90
80
70
60
50
70
700
600
60
50
40
30
20
10
0
RTS
TX
RTS
TX
500
MAX3110E
V
CC
= +5V
400
300
200
100
0
DOUT
40
30
20
10
0
DOUT
MAX3111E
= +3.3V
V
CC
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
VOLTAGE (V)
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
VOLTAGE (V)
0
1
2
3
4
5
EXTERNAL CLOCK FREQUENCY (MHz)
RS-232 TRANSCEIVER SUPPLY CURRENT
vs. LOAD CAPACITANCE
RS-232 TRANSMITTER OUTPUT VOLTAGE
vs. LOAD CAPACITANCE
RS-232 TRANSMITTER SLEW RATE
vs. LOAD CAPACITANCE
50
10.0
16
TRANSMITTER 1 AT DATA RATE
TRANSMITTER 2 AT DATA RATE
3kΩ + C
TRANSMITTER 1 AT 250kbps
TRANSMITTER 2 AT 15.6kbps
TRANSMITTER 1 AT 250kbps
45
40
35
30
25
20
15
10
5
3kΩ + C
L
7.5
5.0
14
12
10
8
3kΩ + C
16
L
L
V
OUT+
250kbps
2.5
-SLEW
0
+SLEW
2000
120kbps
-2.5
-5.0
-7.5
-10.0
6
4
2
V
OUT-
20kbps
4000
0
0
0
1000
2000
3000
5000
0
1000
2000
3000
4000
5000
0
1000
3000
4000
5000
LOAD CAPACITANCE (pF)
LOAD CAPACITANCE (pF)
LOAD CAPACITANCE (pF)
8
_______________________________________________________________________________________
SPI/MICROWIRE-Compatible UART and ±15kV ESD-
Protected RS-232 Transceivers with Internal Capacitors
0/MAX31E
Pin Description
PIN
1
NAME
R2IN
FUNCTION
RS-232 Receiver Input 2
2
R2OUT
T2IN
RS-232 Receiver Output 2, TTL/CMOS
RS-232 Transmitter lnput 2, TTL/CMOS
RS-232 Transmitter lnput 1, TTL/CMOS
RS-232 Receiver Output 1, TTL/CMOS
RS-232 Receiver Input 1
3
4
T1IN
5
R1OUT
R1IN
6
7
T1OUT
RS-232 Transmitter Output 1
8
V
CC
Positive Supply Voltage
UART Crystal Connection. Leave X2 unconnected when using an external CMOS clock. See the Crystals,
Oscillators, and Ceramic Resonators section.
9
X2
UART Crystal Connection. X1 also serves as an external CMOS clock input. See the Crystals, Oscillators,
and Ceramic Resonators section.
10
11
12
X1
UART Clear-to-Send Active-Low Input. Read via the CTS bit.
CTS
RTS
UART Request-to-Send Active-Low Output. Controlled by the RTS bit. Also used to control the driver enable
in RS-485 networks.
UART Asynchronous Serial-Data (receiver) Input. The serial information received from the RS-232 receiver.
A transition on RX while in shutdown generates an interrupt (Table 1).
13
14
RX
TX
UART Asynchronous Serial-Data (transmitter) Output
15
16
17
DIN
SPI/MICROWIRE Serial-Data Input. Schmitt-trigger Input.
SPI/MICROWIRE Serial-Data Output. High impedance when CS is high.
SPI/MICROWIRE Serial-Clock Input. Schmitt-trigger input.
DOUT
SCLK
UART Active-Low Chip-Select Input. DOUT goes high impedance when CS is high. IRQ, TX, and RTS are
always active. Schmitt-trigger input.
18
19
20
CS
IRQ
UART Active-Low Interrupt Output. Open-drain interrupt output to microprocessor.
Hardware Shutdown Input. Drive SHDN low to shut down the RS-232 transmitters and charge pump. Drive
high for normal operation.
SHDN
V+
21
22
+5.5V generated by the internal charge pump. Do not make any connection to this terminal.
Positive terminal of the internal voltage-doubler charge-pump capacitor. Do not make any connection to
this terminal.
C1+
C1-
Negative terminal of the internal voltage-doubler charge-pump capacitor. Do not make any connection to
this terminal.
23
24
25
26
27
28
C2+
C2-
Positive terminal of internal inverting charge-pump capacitor. Do not make any connection to this terminal.
Negative terminal of internal inverting charge-pump capacitor. Do not make any connection to this terminal.
-5.5V generated by the internal charge pump. Do not make any connection to this terminal.
Ground
V-
GND
T2OUT
RS-232 Transmitter Output 2
_______________________________________________________________________________________
9
SPI/MICROWIRE-Compatible UART and ±15kV ESD-
Protected RS-232 Transceivers with Internal Capacitors
T2IN
T2OUT
T1OUT
R2IN
T1IN
R2OUT
R1OUT
C1+
R1IN
V+
INTERNAL
INTERNAL
5k
5k
INTERNAL
INTERNAL
C1-
C2+
CHARGE
PUMP
GND
C2-
V-
V
CC
SHDN
Pr
RX BUFFER
9
MAX3110E/MAX3111E
0/MAX31E
9
9
INTERRUPT
LOGIC
Pr
RX FIFO
IRQ
9
Pr
RX SHIFT REGISTER
DOUT
RX
9
X2
X1
BAUD-RATE
GENERATOR
4
SPI
INTERFACE
SCLK
CS
Pt
Pt
TX SHIFT REGISTER
TX
9
DIN
TX BUFFER
9
CTS
RTS
I/O
Figure 1. MAX3110E/MAX3111E Functional Diagram
tions for V
down to the minimum supply voltage and
CC
Detailed Description
are guaranteed to operate for data rates up to 250kbps.
The MAX3110E/MAX3111E contain an SPI/QSPI/MICROWIRE-
compatible UART and an RS-232 transceiver with two
drivers and two receivers. The UART is compatible with
SPI and QSPI for CPOL = 0 and CPHA = 0. The UART
supports data rates up to 230kbaud for standard UART
bit streams as well as IrDA and includes an 8-word
receive FIFO. Also included is a 9-bit-address recogni-
tion interrupt.
The UART and RS-232 functions operate as one device
or independently since the two functions share only
supply and ground connections.
UART
The universal asynchronous receiver transmitter
(UART) interfaces the SPI/QSPI/MICROWIRE-compati-
ble synchronous serial data from a microprocessor (µP)
to asynchronous, serial-data communication ports (RS-
232, IrDA). Figure 1 shows the MAX3110E/MAX3111E
functional diagram. Included in the UART function is an
SPI/QSPI/MICROWIRE interface, a baud-rate generator,
and an interrupt generator.
The RS-232 transceiver has electrostatic discharge
(ESD) protection on the transmitter outputs and the
receiver inputs. The internal charge-pump capacitors
minimize the number of external components required.
The RS-232 transceivers meet EIA/TIA-232 specifica-
10 ______________________________________________________________________________________
SPI/MICROWIRE-Compatible UART and ±15kV ESD-
Protected RS-232 Transceivers with Internal Capacitors
0/MAX31E
SPI Interface
The MAX3110E/MAX3111E are compatible with SPI,
QSPI (CPOL = 0, CPHA = 0), and MICROWIRE serial-
interface standards (Figure 2). The MAX3110E/
MAX3111E have a unique full-duplex-only architecture
that expects a 16-bit word for DIN and simultaneously
produces a 16-bit word for DOUT regardless of which
read/write register is used. The DIN stream is moni-
tored for its first two bits to tell the UART the type of
data transfer being executed (see the Write
Configuration Register, Read Configuration Register,
Write Data Register, and Read Data Register sections).
DIN (MOSI) is latched on SCLK’s rising edge. DOUT
(MISO) should be read into the µP on SCLK’s rising
edge. The first bit (bit 15) of DOUT transitions on CS’s
falling edge, and bits 14–0 transition on SCLK’s falling
edge. Figure 3 shows the detailed serial timing specifi-
cations for the synchronous SPI port.
Only 16-bit words are expected. If CS goes high in the
middle of a transmission (any time before the 16th bit),
the sequence is aborted (i.e., data does not get written
to individual registers). Most operations, such as the
clearing of internal registers, are executed only on CS’s
rising edge. Every time CS goes low, a new 16-bit
stream is expected. An example of using the Write
Configuration Register is shown in Figure 4.
Table 1 describes the bits located in the Write Config-
uration, Read Configuration, Write Data, and Read
Data Registers. This table also describes whether the
bit is a read or a write bit and the power-on reset state
(POR) of the bits. Figure 5 shows an example of parity
and word-length control.
MSB 14
MSB 14
13
13
12
12
11
11
10
10
9
8
7
6
5
4
3
2
1
LSB
LSB
DIN
9
8
7
6
5
4
3
2
1
DOUT
CS
SCLK
COMPATIBLE
WITH MAX3110E/MAX3111E
(CPOL = 0, CPHA = 0)
(CPOL = 0, CPHA = 1)
(CPOL = 1, CPHA = 0)
(CPOL = 1, CPHA = 1)
SCLK
NOT COMPATIBLE
WITH MAX3110E/MAX3111E
SCLK
SCLK
Figure 2. Compatible CPOL and CPHA Timing Modes
CS
• • •
• • •
t
t
t
t
CS1
CSS
CH
CSH
t
t
CL
CSO
SCLK
t
DS
t
DH
DIN
• • •
• • •
t
DV
t
t
TR
DO
DOUT
Figure 3. Detailed Serial Timing Specifications for the Synchronous SPI Port
______________________________________________________________________________________ 11
SPI/MICROWIRE-Compatible UART and ±15kV ESD-
Protected RS-232 Transceivers with Internal Capacitors
DATA
UPDATED
CS
SCLK
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
1
1
T
FEN SHDN
TM
RM
PM
0
RAM
0
IR
0
ST
0
PE
0
L
0
B3
0
B2
0
B1
0
B0
0
DIN
DOUT
R
0
0
0
0
Figure 4. Write Configuration Register Example
0/MAX31E
PE = 0, L = 0
START D0
D1
D2
D2
D2
D2
D3
D3
D3
D3
D4
D4
D4
D4
D5
D5
D5
D5
D6
D6
D6
D6
D7
STOP STOP IDLE
IDLE
IDLE
IDLE
PE = 0, L = 1
START D0
START D0
D1
STOP STOP IDLE
PE = 1, L = 0
D1
D7
Pt
STOP STOP IDLE
PE = 1, L = 1
START D0
D1
Pt
STOP STOP IDLE
IDLE
TIME
SECOND STOP BIT IS OMITTED IF ST = 0.
Figure 5. Parity and Word-Length Control
12 ______________________________________________________________________________________
SPI/MICROWIRE-Compatible UART and ±15kV ESD-
Protected RS-232 Transceivers with Internal Capacitors
0/MAX31E
Table 1. Bit Descriptions
BIT
NAME
BIT
TYPE
POR
STATE
DESCRIPTION
B0–B3
B0–B3
write
read
0000
0000
Baud-Rate Divisor Select Bits. Sets the baud clock’s value (Table 6).
Baud-Rate Divisor Select Bits. Reads the 4-bit baud clock value assigned to these registers.
No
change
Clear-to-Send-Input. Records the state of the CTS pin (CTS bit = 0 implies CTS pin = logic
high).
CTS
read
write
read
Transmit-Buffer Register. Eight data bits written into the transmit-buffer register. D7t is ignored
when L = 1.
D0t–D7t
D0r–D7r
XXXXXXXX
00000000
Eight data bits read from the receive FIFO or the receive-buffer register. When L = 1, D7r is
always 0.
write
read
write
read
0
0
0
0
FEN
FEN
IR
FIFO Enable. Enables the receive FIFO when FEN = 0. When FEN = 1, FIFO is disabled.
FIFO-Enable Readback. FEN’s state is read.
Enables the IrDA timing mode when IR = 1.
IR
Reads the value of the IR bit.
Bit to set the word length of the transmitted or received data. L = 0 results in 8-bit words
(9-bit words if PE = 1) (see Figure 5). L = 1 results in 7-bit words (8-bit words if PE = 1).
L
L
write
read
0
0
Reads the value of the L bit.
Transmit-Parity Bit. This bit is treated as an extra bit that is transmitted if PE = 1. In 9-bit net-
works, the MAX3110E/MAX3111E do not calculate parity. If PE = 0, then this bit (Pt) is ignored
in transmit mode (see the 9-Bit Networks section).
Pt
Pr
write
read
X
X
Receive-Parity Bit. This bit is the extra bit received if PE = 1. Therefore, PE = 1 results in 9-bit
transmissions (L = 0). If PE = 0, then Pr is set to 0. Pr is stored in the FIFO with the receive data
(see the 9-Bit Networks section).
Parity-Enable Bit. Appends the Pt bit to the transmitted data when PE = 1, and sends the Pt bit
as written. No parity bit is transmitted when PE = 0. With PE = 1, an extra bit is expected to be
received. This data is put into the Pr register. Pr = 0 when PE = 0. The MAX3110E/MAX3111E
do not calculate parity.
PE
write
0
PE
PM
PM
read
write
read
0
0
0
Reads the value of the Parity-Enable bit.
Mask for Pr bit. IRQ is asserted if PM = 1 and Pr = 1 (Table 7).
Reads the value of the PM bit (Table 7).
Receive Bit or FIFO Not Empty Flag. R = 1 means new data is available to be read or is being
read from the receive register or FIFO. If performing a Read Data or Write Data operation, the R
bit will clear on the falling edge of SCLK's 16th pulse if no new data is available.
R
read
0
write
read
write
read
0
0
0
0
RM
RM
Mask for R bit. IRQ is asserted if RM = 1 and R = 1 (Table 7).
Reads the value of the RM bit (Table 7).
RAM
RAM
Mask for RA/FE bit. IRQ is asserted if RAM = 1 and RA/FE = 1 (Table 7).
Reads the value of the RAM bit (Table 7).
Request-to-Send Bit. Controls the state of the RTS output. This bit is reset on power-up (RTS
bit = 0 sets the RTS pin = logic high).
RTS
write
0
______________________________________________________________________________________ 13
SPI/MICROWIRE-Compatible UART and ±15kV ESD-
Protected RS-232 Transceivers with Internal Capacitors
Table 1. Bit Descriptions (continued)
BIT
NAME
BIT
TYPE
POR
STATE
DESCRIPTION
Receiver-Activity/Framing-Error Bit. In shutdown mode, this is the RA bit. In normal operation,
this is the FE bit. In shutdown mode, a transition on RX sets RA = 1. In normal mode, a fram-
ing error sets FE = 1. A framing error occurs if a zero is received when the first stop bit is
expected. FE is set when a framing error occurs, and cleared upon receipt of the next proper-
ly framed character independent of the FIFO being enabled. When the device wakes up, it is
likely that a framing error will occur. This error is cleared with a Write Configuration. The FE bit
is not cleared on a Read Data operation. When an FE is encountered, the UART resets itself
to the state where it is looking for a start bit.
RA/FE
read
0
Software-Shutdown Bit. Enter software shutdown with a Write Configuration where SHDNi = 1.
Software shutdown takes effect after CS goes high, and causes the oscillator to stop as soon
as the transmitter becomes idle. Software shutdown also clears R, T, RA/FE, D0r–D7r,
D0t–D7t, Pr, Pt, and all data in the receive FIFO. RTS and CTS can be read and updated
while in shutdown. Exit software shutdown with a Write Configuration where SHDNi = 0. The
oscillator restarts typically within 50ms of CS going high. RTS and CTS are unaffected. Refer
to the Pin Description for hardware shutdown (SHDN input).
SHDNi
write
read
0
0
Shutdown Read-Back Bit. The Read Configuration register outputs SHDNo = 1 when the
UART is in shutdown. Note that this bit is not sent until the current byte in the transmitter is
sent (T = 1). This tells the processor when it may shut down the RS-485/RS-422 driver. This bit
is also set immediately when the device is shut down through the SHDN pin.
SHDNo
0/MAX31E
Transmit-Stop Bit. One stop bit will be transmitted when ST = 0. Two stop bits will be transmit-
ted when ST = 1. The receiver only requires one stop bit.
ST
ST
T
write
read
read
0
0
1
Reads the value of the ST bit.
Transmit-Buffer-Empty Flag. T = 1 means that the transmit buffer is empty and ready to
accept another data word.
Transmit-Enable Bit. If TE = 1, then only the RTS pin is updated on CS’s rising edge. The con-
tents of RTS, Pt, and D0t–D7t transmit on CS’s rising edge when TE = 0.
write
0
TE
write
read
0
0
TM
TM
Mask for T Bit. IRQ is asserted if TM = 1 and T = 1 (Table 7).
Reads the value of the TM bit (Table 7).
Notice to High-Level Programmers: The UART follows
the SPI convention of providing a bidirectional data path
for writes and reads. Whenever the data is written, data
is also read back. This speeds operation over the SPI
bus, and the UART needs this speed advantage when
operating at high baud rates. In most high-level lan-
guages, such as C, there are commands for writing and
reading stream I/O devices such as the console or serial
port. In C specifically, there is a “PUTCHAR” command
that transmits a character and a “GETCHAR” command
that receives a character. If programmers were to write
direct write and read commands in C with no underlying
driver code, they would notice that a PUTCHAR com-
mand is really a PUTGETCHAR command. These C
commands assume some form of BIOS-level support for
these commands. The proper way to implement these
commands is to write driver code, usually in the form of
an assembly-language interrupt-service routine and a
callable routine used by high-level routines. This driver
handles the interrupts and manages the receive and
transmit buffers for the MAX3110E/MAX3111E. When a
PUTCHAR executes, this driver is called and it safely
buffers any characters received when the current
character is transmitted. When a GETCHAR executes, it
checks its own receive buffer before getting data from
the UART. See the C-language Outline of a MAX3110E/
MAX3111E Software Driver in Listing 1, which appears at
the end of this data sheet.
Listing 1 is a C-language outline of an interrupt-driven
software driver that interfaces to a MAX3110E/
MAX3111E, providing an intermediate layer between
the bit-manipulation subroutine and the familiar
PUTCHAR/GETCHAR subroutines.
The user must supply code for managing the transmit
and receive queues as well as the low-level hardware
interface itself. The interrupt control hardware must be
initialized before this driver is called.
14 ______________________________________________________________________________________
SPI/MICROWIRE-Compatible UART and ±15kV ESD-
Protected RS-232 Transceivers with Internal Capacitors
0/MAX31E
Write Configuration Register (D15, D14 = 1, 1)
Configure the UART by writing a 16-bit word to the write
configuration register, which programs the baud rate,
data word length, parity enable, and enable of the 8-
word receive FIFO. In this mode, bits 15 and 14 of the
DIN configuration word are both required to be 1 in
order to enable the write configuration mode. Bits 13–0
of the DIN configuration word set the configuration of
the UART. Table 2 shows the bit assignment for the
write configuration register. The write configuration reg-
ister allows selection between normal UART timing and
IrDA timing, provides shutdown control, and contains
four interrupt mask bits.
tion mode. Bits 13–1 of the DIN word should be zeros,
and bit 0 is the test bit to put the UART in test mode
(see the Test Mode section). Table 3 shows the bit
assignment for the read configuration register.
Test Mode
The device enters a test mode if bit 0 of the DIN config-
uration word equals one when doing a read configura-
tion. In this mode, if CS = 0, the RTS pin transmits a
clock that is 16-times the baud rate. The TX pin is low
as long as CS remains low while in test mode. Table 3
shows the bit assignment for the read configuration
register.
Using the write configuration register clears the receive
FIFO and the R, T, RA/FE, D0r–D7r, D0t–D7t, Pr, and Pt
registers. RTS and CTS remain unchanged. The new
configuration is valid on CS’s rising edge if the transmit
buffer is empty (T = 1) and transmission is over. If the
latest transmission has not been completed (T = 0), the
registers are updated when the transmission is over.
Write Data Register (D15, D14 = 1, 0)
Use the write data register for transmitting to the TX-
buffer and receiving from the RX buffer (and RX FIFO
when enabled). When using this register, the DIN and
DOUT write data words are used simultaneously, and
bits 13–11 for both the DIN and DOUT write data words
are meaningless zeros. The DIN write data word con-
tains the data that is being transmitted, and the DOUT
write data word contains the data that is being received
from the RX FIFO. Table 4 shows the bit assignment for
the write data mode. To change the RTS pin’s output
state without transmitting data, set the TE bit high. If
performing a write data operation, the R bit will clear on
the falling edge of SCLK’s 16th clock pulse if no new
data is available.
The write configuration register bits (FEN, SHDNi, IR,
ST, PE, L, B3–B0) take effect after the current transmis-
sion is over. The mask bits (TM, RM, PM, RAM) take
effect immediately after SCLK’s 16th rising edge.
Bits 15 and 14 of the DOUT write configuration (R and
T) are sent out of the MAX3110E/MAX3111E along with
14 trailing zeros. The use of the R and T bits is optional,
but ignore the 14 trailing zeros.
Read Data Register (D15, D14 = 0, 0)
Use the read data register for receiving data from the
RX FIFO. When using this register, bits 15 and 14 of
DIN are both required to be 0. Bits 13–0 of the DIN
read-data word should be zeros. Table 5 shows the bit
assignments for the read data mode. Reading data
clears the R bit and interrupt IRQ. If performing a read
data operation, the R bit will clear on the falling edge of
SCLKs 16th clock pulse if no new data is available.
Warning! The UART requires stable crystal oscillator
operation before configuration (typically ~25ms after
power-up). Upon power-up, compare the write configu-
ration bits with the read configuration bits in a software
loop until both match. This ensures that the oscillator is
stable and that the UART is configured correctly.
Read Configuration Mode (D15, D14 = 0, 1)
The read configuration mode is used to read back the
last configuration written to the UART. In this mode, bits
15 and 14 of the DIN configuration word are required to
be 0 and 1, respectively, to enable the read configura-
______________________________________________________________________________________ 15
SPI/MICROWIRE-Compatible UART and ±15kV ESD-
Protected RS-232 Transceivers with Internal Capacitors
Table 2. Write Configuration (D15, D14 = 1, 1)
BIT
15
14
13
FEN
0
12
SHDNi
0
11
TM
0
10
RM
0
9
PM
0
8
RAM
0
7
IR
0
6
ST
0
5
PE
0
4
L
0
3
B3
0
2
B2
0
1
B1
0
0
B0
0
DIN
1
1
DOUT
R
T
D15 is present at DOUT on CS’s falling edge. Consecutive bits are clocked out on SCLK’s falling edge.
Notes:
bits 15, 14: DIN
1,1 = Write Configuration
bit 13: DIN
bit 15: DOUT
R = 1, Data is available to be read or is being read from the
receive register or FIFO.
R = 0, Receive register and FIFO are empty.
FEN = 0, FIFO is enabled.
FEN = 1, FIFO is disabled.
bit 12: DIN
bit 14: DOUT
T = 1, Transmit buffer is empty.
T = 0, Transmit buffer is full.
bits 13–0: DOUT
SHDNi = 1, Enter software shutdown.
SHDNi = 0, Exit software shutdown.
bit 11: DIN
Zeros
TM = 1, Transmit buffer empty interrupt is enabled.
TM = 0, Transmit buffer empty interrupt is disabled.
bit 10: DIN
0/MAX31E
RM = 1, Data available in the receive register or FIFO interrupt
is enabled.
RM = 0, Data available in the receive register or FIFO interrupt
is disabled.
bit 9: DIN
PM = 1, Parity bit high received interrupt is enabled.
PM = 0, Parity bit received interrupt is disabled.
bit 8: DIN
RAM = 1, Receiver-activity (shutdown mode)/Framing-error
(normal operation) interrupt is enabled.
RAM = 0, Receiver-activity (shutdown mode)/Framing-error
(normal operation) interrupt is disabled.
bit 7: DIN
IR = 1, IrDA mode is enabled.
IR = 0, IrDA mode is disabled.
bit 6: DIN
ST = 1, Transmit two stop-bits.
ST = 0, Transmit one stop-bit.
bit 5: DIN
PE = 1, Parity is enabled for both transmit (state of Pt) and
receive.
PE = 0, Parity is disabled for both transmit and receive.
bit 4: DIN
L = 1, 7-bit words (8-bit words if PE = 1)
L = 0, 8-bit words (9-bit words if PE = 1)
bits 3–0: DIN
B3–B0 = XXXX, Baud-Rate Divisor Select Bits (see Table 6)
16 ______________________________________________________________________________________
SPI/MICROWIRE-Compatible UART and ±15kV ESD-
Protected RS-232 Transceivers with Internal Capacitors
0/MAX31E
Table 3. Read Configuration (D15, D14 = 0, 1)
BIT
15
14
13
12
11
10
9
8
7
0
6
0
5
0
4
0
L
3
0
2
0
1
0
0
DIN
0
1
0
0
0
0
0
0
TEST
B0
DOUT
R
T
SHDNo
IR
ST
PE
B3
B2
B1
FEN
TM
RM
PM
RAM
D15 is present at DOUT on CS’s falling edge. Consecutive bits are clocked out on SCLK’s falling edge.
Notes:
bit 15, 14: DIN
0,1 = Read Configuration
bit 15: DOUT
R = 1, Data is available to be read or is being read from the
bits 13–1: DIN
Zeros
receive register or FIFO.
R = 0, Receive register and FIFO are empty.
bit 14: DOUT
T = 1, Transmit buffer is empty.
T = 0, Transmit buffer is full.
bit 13: DOUT
bit 0: DIN
If TEST = 1 and CS = 0, then RTS =16xBaudCLK
TEST = 0, Disables test mode
FEN = 0, FIFO is enabled.
FEN = 1, FIFO is disabled.
bit 12: DOUT
SHDNo = 1, Software shutdown is enabled.
SHDNo = 0, Software shutdown is disabled.
bit 11: DOUT
TM = 1, Transmit buffer empty interrupt is enabled.
TM = 0, Transmit buffer empty interrupt is disabled.
bit 10: DOUT
RM = 1, Data available in the receive register or FIFO interrupt
is enabled.
RM = 0, Data available in the receive register or FIFO interrupt
is disabled.
bit 9: DOUT
PM = 1, Parity bit high received interrupt is enabled.
PM = 0, Parity bit received interrupt is disabled.
bit 8: DOUT
RAM = 1, Receiver-activity (shutdown mode)/Framing-error
(normal operation) interrupt is enabled.
RAM = 0, Receiver-activity (shutdown mode)/Framing-error
(normal operation) interrupt is disabled.
bit 7: DOUT
IR = 1, IrDA mode is enabled.
IR = 0, IrDA mode is disabled.
bit 6: DOUT
ST = 1, Transmit two stop-bits.
ST = 0, Transmit one stop-bit.
bit 5: DOUT
PE = 1, Parity is enabled for both transmit (state of Pt) and
receive.
PE = 0, Parity is disabled for both transmit and receive.
bit 4: DOUT
L = 1, 7-bit words (8-bit words if PE = 1)
L = 0, 8-bit words (9-bit words if PE = 1)
bits 3–0: DOUT
B3–B0 = XXXX Baud-Rate Divisor Select Bits (see Table 6)
______________________________________________________________________________________ 17
SPI/MICROWIRE-Compatible UART and ±15kV ESD-
Protected RS-232 Transceivers with Internal Capacitors
Table 4. Write Data (D15, D14 = 1, 0)
BIT
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
DIN
1
0
0
0
0
RTS
CTS
Pt
Pr
D7t
D7r
D6t
D6r
D5t
D5r
D4t
D4r
D3t
D3r
D2t
D2r
D1t
D1r
D0t
D0r
TE
DOUT
R
T
0
0
0
RA/FE
D15 is present at DOUT on CS’s falling edge. Consecutive bits are clocked out on SCLK’s falling edge.
Notes:
bits 15, 14: DIN
1, 0 = Write Data
bit 15: DOUT
R = 1, Data is available to be read or is being read from the
receive register or FIFO.
bits 13–11: DIN
Zeros
R = 0, Receive register and FIFO are empty.
bit 10: DIN
bit 14: DOUT
TE = 1, Disables transmit and only RTS will be updated.
TE = 0, Enables transmit.
T = 1, Transmit buffer is empty.
T = 0, Transmit buffer is full.
bit 9: DIN
bits 13–11: DOUT
RTS = 1, Configures RTS = 0 (logic low).
RTS = 0, Configures RTS = 1 (logic high).
Zeros
0/MAX31E
bit 10: DOUT
bit 8: DIN
RA/FE = Receive-Activity (Uart shutdown)/Framing-Error
(Normal Operation) bit
Pt = 1, Transmit parity bit is high. If PE = 1, a high parity bit will
be transmitted. If PE = 0, then no parity bit will be transmitted.
bit 9: DOUT
Pt = 0, Transmit parity bit is low. If PE = 1, a low parity bit will be
transmitted. If PE = 0, then no parity bit will be transmitted.
CTS = CTS input state. If CTS = 0, then CTS = 1 and vice versa.
bit 8: DOUT
bits 7–0: DIN
Pr = Received Parity Bit. This is only valid if PE = 1.
D7t–D0t = Transmitting Data Bits. D7t is ignored when L = 1.
bits 7–0: DOUT
D7t–D0t = Received Data Bits. D7r = 0 for L = 1.
18 ______________________________________________________________________________________
SPI/MICROWIRE-Compatible UART and ±15kV ESD-
Protected RS-232 Transceivers with Internal Capacitors
0/MAX31E
Table 5. Read Data (D15, D14 = 0, 0)
BIT
DIN
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
DOUT
R
T
0
0
0
RA/FE
CTS
Pr
D7r
D6r
D5r
D4r
D3r
D2r
D1r
D0r
D15 is present at DOUT on CS’s falling edge. Consecutive bits are clocked out on SCLK’s falling edge.
Notes:
bits 15, 14: DIN
0, 0 = Read Data
bits 15: DOUT
R = 1, Data is available to be read or is being read from the
receive register or FIFO.
bits 13–0: DIN
Zeros
R = 0, Receive register and FIFO are empty.
bit 14: DOUT
T = 1, Transmit buffer is empty.
T = 0, Transmit buffer is full.
bits 13–11: DOUT
Zeros
bit 10: DOUT
RA/FE = Receive-Activity (UART shutdown)/Framing-Error
(Normal Operation) Bit
bit 9: DOUT
CTS = CTS input state. If CTS = 0, then CTS = 1 and vice versa.
bit 8: DOUT
Pr = Received parity bit. This is only valid if PE = 1.
bits 7–0: DOUT
D7t–D0t = Received Data Bits. D7r = 0 for L = 1.
______________________________________________________________________________________ 19
SPI/MICROWIRE-Compatible UART and ±15kV ESD-
Protected RS-232 Transceivers with Internal Capacitors
Baud-Rate Generator
The baud-rate generator determines the rate at which
Table 6. Baud-Rate Selection*
BAUD
RATE
BAUD
RATE
the transmitter and receiver operate. Bits B3–B0 in the
write configuration register determine the baud-rate
divisor (BRD), which divides the X1 oscillator frequen-
cy. The on-board oscillator operates with either a
1.8432MHz or a 3.6864MHz crystal or is driven at X1
with a 45% to 55% duty-cycle square wave. Table 6
shows baud-rate divisors for given input codes as well
as the baud rate for 1.8432MHz and 3.684MHz crystals.
The generator’s clock is 16-times the baud rate.
BAUD
B3 B2 B1 B0
DIVISION
RATIO
(f
OSC
=
(f
OSC
=
1.8432MHz) 3.6864MHz)
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0**
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
2
115.2k**
57.6k
28.8k
14.4k
7200
3600
1800
900
230.4k**
115.2k
57.6k
28.8k
14.4k
7200
3600
1800
76.8k
38.4k
19.2k
9600
4800
2400
1200
600
4
8
16
32
64
128
3
Interrupt Sources and Masks
Using the Read Data or Write Data register clears the
interrupt IRQ, assuming the conditions that initiated the
interrupt no longer exist. Table 7 gives the details for
each interrupt source. Figure 6 shows the functional
diagram for the interrupt sources and mask blocks.
38.4k
19.2k
9600
4800
2400
1200
600
6
Following are two examples of setting up an IRQ for the
MAX3110E/MAX3111E:
12
24
48
96
192
384
Example 1. Set up only the transmit buffer-empty inter-
rupt. Send the 16-bit word below into DIN of the
MAX3110E/MAX3111E using the Write Configuration
register. This 16-bit word configures the MAX3110E/
MAX3111E for 9600bps, 8-bit words, no parity, and one
stop bit with a 1.8432MHz crystal.
0/MAX31E
300
*Standard baud rates shown in bold
**Default baud rate
binary 1100100000001010
HEX C80A
Example 2. Set up only the data-available (or data-
being-read) interrupt.
S
R
NEW DATA AVAILABLE
DATA READ
Q
Send the 16-bit word below into DIN of the
MAX3110E/MAX3111E using the Write Configuration
register. This 16-bit word configures the MAX3110E/
MAX3111E for 9600bps, 8-bit words, no parity, and one
stop bit with a 1.8432MHz crystal.
RM MASK
S
TRANSMIT BUFFER EMPTY
DATA READ
Q
R
TM MASK
IRQ
PE = 1 AND RECEIVED
PARITY BIT = 1
PE = 0 OR RECEIVED
PARITY BIT = 0
S
binary 1100010000001010
HEX C40A
Q
R
N
PM MASK
TRANSITION ON RX
Receive FIFO
The MAX3110E/MAX3111E contain an 8-word receive
FIFO for data received by the UART to minimize
processor overhead. Using the UART-software shut-
down clears the receive FIFO. Upon power-up, the
receive FIFO is enabled. To disable the receive FIFO,
set the FEN bit high when writing to the Write
Configuration register. To check whether the FIFO is
enabled or disabled, read back the FEN bit using the
Read Configuration.
SHUTDOWN
RAM MASK
FRAMING ERROR
RAM MASK
SHUTDOWN
Figure 6. Functional Diagram for Interrupt Sources and Mask
Blocks
20 ______________________________________________________________________________________
SPI/MICROWIRE-Compatible UART and ±15kV ESD-
Protected RS-232 Transceivers with Internal Capacitors
0/MAX31E
Table 7. Interrupt Sources and Masks—Bit Descriptions
BIT
NAME
MASK
BIT
MEANING
WHEN SET
DESCRIPTION
The Pr bit reflects the value in the word currently in the receive-buffer register
(oldest data available). The Pr bit is set when parity is enabled (PE = 1) and the
received parity bit is 1. The Pr bit is cleared either when parity is not enabled (PE
= 0) or when parity is enabled and the received bit is 0. An interrupt is issued
based on the oldest Pr value in the receiver FIFO. The oldest Pr value is the next
value read by a Read Data operation.
Pr
R
Received parity bit = 1
Data available
PM
RM
The R bit is set when new data is available to be read or when data is being read
from the receive register/FIFO. FIFO is cleared when all data has been read. An
interrupt is asserted as long as R = 1 and RM = 1.
This is the RA (RX-transition) bit in shutdown, and the framing-error (FE) bit in
operating mode. RA is set if there has been a transition on RX since entering
shutdown. RA is cleared when the MAX3110E/MAX3111E exits shutdown. IRQ is
asserted when RA is set and RAM = 1.
Transition on RX when
in shutdown; framing
error when not in
shutdown
RA/FE
RAM
FE is determined solely by the currently received data and is not stored in FIFO.
The FE bit is set if a zero is received when the first stop bit is expected. FE is
cleared upon receipt of the next properly framed character. IRQ is asserted
when FE is set and RAM = 1.
The T bit is set when the transmit buffer is ready to accept data. IRQ is asserted
low if TM = 1 and the transmit buffer becomes empty. This source is cleared on
the rising edge of SCLK’s 16th clock pulse when using a Read Data or Write
Data operation. CS’s rising edge during a Read Data operation. Although the
interrupt is cleared, poll T to determine transmit-buffer status.
Transmit buffer is
empty
T
TM
UART Software Shutdown
CS goes high, the oscillator typically takes about 25ms
to stabilize. Configure the UART after the oscillator has
stabilized by using a write configuration that clears all
registers but RTS and CTS. If a framing error occurs,
you may have not waited long enough for the oscillator
to stabilize.
When in software shutdown, the UART’s oscillator turns
off to reduce power dissipation. The UART enters shut-
down by a software command (SHDNi bit = 1). The
software shutdown is entered upon completing the
transmission of the data in both the Transmit register
and the Transmit-Buffer register. The SHDNo bit is set
when the UART enters shutdown. The microcontroller
(µC) monitors the SHDNo bit to determine when the
UART is shut down and then shuts down the
RS-232 transceivers.
The hardware shutdown affects only the RS-232 trans-
ceiver, and the software shutdown affects only the
UART. See the RS-232 Transceiver Hardware
Shutdown section.
Dual Charge-Pump Voltage Converter
The internal power supply consists of a regulated dual
charge pump that provides output voltages of +5.5V
(doubling charge pump) and -5.5V (inverting charge
pump), using a +3.3V supply (MAX3111E) or a +5V sup-
ply (MAX3110E). The charge pump operates in discontin-
uous mode; if the output voltages are less than 5.5V, the
charge pump is enabled, and if the output voltages
exceed 5.5V, the charge pump is disabled. Each charge
pump includes internal flying capacitors and reservoir
capacitors to generate the V+ and V- supplies.
Software shutdown clears the receive FIFO, R, RA/FE,
D0r–D7r, Pr, and Pt registers and sets the T bit high.
Configuration bits (RM, TM, PM, RAM, IR, ST, PE, L,
B0–B3, and RTS) are programmable when SHDNo = 1
and CTS is also readable. Although RA is reset upon
entering shutdown, it goes high when any transitions
are detected on the RX pin. This allows the UART to
monitor activity on the receiver when in shutdown.
When taking the part out of software shutdown (SHDNi
= 0), the oscillator turns on when CS goes high. After
______________________________________________________________________________________ 21
SPI/MICROWIRE-Compatible UART and ±15kV ESD-
Protected RS-232 Transceivers with Internal Capacitors
RS-232 Transmitters
The transmitters are inverting-level translators that con-
vert CMOS-logic levels to ±5.0V EIA/TIA-232 levels. The
transmitters guarantee a 230kbps data rate with worst-
case loads of 3kΩ in parallel with 1000pF, providing
compatibility with PC-to-PC communication software
(such as LapLink™). Transmitters can be paralleled
because the outputs are forced into a high-impedance
state when the device is in hardware shutdown
(SHDN = GND). The MAX3110E/MAX3111E permit the
outputs to be driven up to ±12V while in shutdown.
The transmitter inputs do not have pull-up resistors.
5V/div
0
SHDN
T2OUT
2V/div
0
T1OUT
Connect unused inputs to GND or V
.
CC
V
CC
= 3.3V
RS-232 Receivers
The receivers convert RS-232 signals to CMOS-logic
output levels. The MAX3110E/MAX3111E receivers
have inverting outputs and are always active, even
when the part is in hardware (or software) shutdown.
40µs/div
Figure 7. MAX3111E Transmitter Outputs Exiting Shutdown or
Powering Up
ESD Test Conditions
ESD performance depends on a variety of conditions.
Contact Maxim’s Quality Assurance (QA) group for a
reliability report that documents test setup, methodolo-
gy, and results.
RS-232 Transceiver Hardware Shutdown
Supply current falls to I
when in hardware
CCSHDN(H)
0/MAX31E
shutdown mode (SHDN = low). When shut down, the
device’s charge pumps are turned off, V+ is pulled
down to V , V- is pulled to ground, and the transmitter
CC
outputs are disabled (high impedance). The time
required to exit shutdown is typically 100µs, as shown
Human Body Model
Figure 8a shows the Human Body Model, and Figure
8b shows the current waveform it generates when dis-
charged into a low impedance. This model consists of a
100pF capacitor charged to the ESD voltage of inter-
est, which is then discharged into the test device
through a 1.5kΩ resistor.
in Figure 7. Connect SHDN to V
if the shutdown
CC
mode is not used. The UART software shutdown does
not affect the RS-232 transceiver.
±15kV ESD Protection
As with all Maxim devices, ESD-protection structures
are incorporated on all pins to protect against electro-
static discharges encountered during handling and
assembly. The driver outputs and receiver inputs of the
MAX3110E/MAX3111E have extra protection against
static electricity. Maxim’s engineers have developed
state-of-the-art structures to protect these pins against
ESD of ±15kV without damage. The ESD structures
withstand high ESD in all states: normal operation, shut-
down, and powered down. After an ESD event, the
MAX3110E/MAX3111E keep working without latchup,
whereas competing RS-232 products can latch and
must be powered down to remove latchup.
IEC 1000-4-2
The IEC 1000-4-2 standard covers ESD testing and
performance of finished equipment; it does not specifi-
cally refer to integrated circuits. The MAX3110E/
MAX3111E help you design equipment that meets
Level 4 (the highest level) of IEC 1000-4-2 without the
need for additional ESD-protection components.
The major difference between tests done using the
Human Body Model and IEC1000-4-2 is higher peak
current in IEC 1000-4-2, because series resistance is
lower in the IEC 1000-4-2 model. Hence, the ESD that
withstands voltage measured to IEC 1000-4-2 is gener-
ally lower than that measured using the Human Body
Model. Figure 9a shows the IEC 1000-4-2 model, and
Figure 9b shows the current waveform for the ±8kV
IEC 1000-4-2 Level 4 ESD contact-discharge test.
ESD protection is tested in various ways; the transmitter
outputs and receiver inputs devices are characterized
for protection to the following limits:
•
•
±15kV using the Human Body Model
±8kV using the Contact-Discharge Method specified
in IEC 1000-4-2
•
±15kV using the Air-Gap Method specified in IEC
1000-4-2
LapLink is a trademark of Traveling Software.
22 ______________________________________________________________________________________
SPI/MICROWIRE-Compatible UART and ±15kV ESD-
Protected RS-232 Transceivers with Internal Capacitors
0/MAX31E
R
R
C
1M
D
1500Ω
I
100%
90%
PEAK-TO-PEAK RINGING
(NOT DRAWN TO SCALE)
I
P
r
DISCHARGE
RESISTANCE
CHARGE-CURRENT
LIMIT RESISTOR
AMPERES
HIGH-
VOLTAGE
DC
DEVICE
UNDER
TEST
C
STORAGE
CAPACITOR
s
36.8%
100pF
SOURCE
10%
0
TIME
0
t
RL
t
DL
CURRENT WAVEFORM
Figure 8a. Human Body ESD Test Model
Figure 8b. Human Body Model Current Waveform
I
100%
90%
R
R
D
330Ω
C
50M to 100M
DISCHARGE
RESISTANCE
CHARGE-CURRENT
LIMIT RESISTOR
HIGH-
VOLTAGE
DC
DEVICE
UNDER
TEST
C
s
150pF
STORAGE
CAPACITOR
SOURCE
10%
t
t = 0.7ns to 1ns
r
30ns
60ns
Figure 9b. IEC 1000-4-2 ESD Generator Current Waveform
Figure 9a. IEC 1000-4-2 ESD Test Model
The air-gap test involves approaching the device with a
charged probe. The contact-discharge method connects
the probe to the device before the probe is energized.
Applications Information
Crystals, Oscillators, and
Ceramic Resonators
Machine Model
The Machine Model for ESD tests all pins using a
200pF storage capacitor and zero discharge resis-
tance. Its objective is to emulate the stress caused by
contact that occurs with handling and assembly during
manufacturing. Of course, all pins require this protec-
tion during manufacturing, not just RS-232 inputs and
outputs. Therefore, after PC board assembly, the
Machine Model is less relevant to I/O ports.
The MAX3110E/MAX3111E include an oscillator circuit
derived from an external crystal oscillator for baud-rate
generation. For standard baud rates, use a 1.8432MHz
or 3.6864MHz crystal. The 1.8432MHz crystal results
in lower operating current; however, the 3.6864MHz
crystal may be more readily available in surface
mount.
______________________________________________________________________________________ 23
SPI/MICROWIRE-Compatible UART and ±15kV ESD-
Protected RS-232 Transceivers with Internal Capacitors
Ceramic resonators are low-cost alternatives to crystals
and operate similarly, although the Q and accuracy are
lower. Some ceramic resonators are available with inte-
gral load capacitors, which can further reduce cost. The
tradeoff between crystals and ceramic resonators is in
initial-frequency accuracy and temperature drift. Keep
the total error in the baud-rate generator below 1% for
reliable operation with other systems. This is accom-
plished easily with a crystal and, in most cases, is
achieved with ceramic resonators. Table 8 lists different
types of crystals and resonators and their suppliers.
specified series-resonant frequency when operated in
parallel mode.
Note: It is very important to keep crystal, resonator, and
load-capacitor leads and traces as short and direct as
possible. Make the X1 and X2 trace lengths and ground
tracks short, with no intervening traces. This helps mini-
mize parasitic capacitance and noise pickup in the
oscillator, and reduces EMI. Minimize capacitive load-
ing on X2 to minimize supply current. The MAX3110E/
MAX3111E’s X1 input can be driven directly by an
external CMOS clock source. The trip level is approxi-
The MAX3110E/MAX3111E’s oscillator supports paral-
lel-resonant mode crystals and ceramic resonators or
can be driven from an external clock source. Internally,
the oscillator consists of an inverting amplifier with its
input, X1, tied to its output, X2, by a bias network that
mately equal to V /2. Make no connection to X2 in this
CC
mode. If a TTL or non-CMOS clock source is used, AC-
couple it with a 10nF capacitor to X1. A 2V peak-to-
peak swing on the input is required for reliable
operation.
self-biases the inverter at approximately V /2. The
CC
RS-232 Transmitter Outputs
Exiting Shutdown
external feedback circuit, usually a crystal from X2 to X1,
provides 180° of phase shift, causing the circuit to oscil-
late. As shown in the Standard Application Circuit, the
crystal or resonator is connected between X1 and X2,
with the load capacitance for the crystal being the
series combination of C1 and C2. For example, for a
1.8432MHz crystal with a specified load capacitance of
11pF, use capacitors of 22pF on either side of the crystal
to ground. Series-resonant mode crystals have a slight
frequency error, typically oscillating 0.03% higher than
Figure 7 shows two RS-232 transmitter outputs exiting
shutdown mode. As they become active, the two trans-
mitter outputs are shown going to opposite RS-232 lev-
els (one transmitter input is high; the other is low). Each
transmitter is loaded with 3kΩ in parallel with 2500pF.
The transmitter outputs display no ringing or undesir-
able transients as they come out of shutdown. Note that
the transmitters are enabled only when the magnitude
of V- exceeds approximately 3V.
0/MAX31E
Table 8. Component and Supplier List
FREQUENCY
(MHz)
TYPICAL
C1, C2 (pF)
PART
NUMBER
PHONE
NUMBER
DESCRIPTION
SUPPLIER
Through-Hole Crystal
(HC-49/U)
1.8432
1.8432
25
47
ECS International, Inc.
Murata North America
ECS-18-13-1
CSA1.84MG
913-782-7787
800-831-9172
Through-Hole
Ceramic Resonator
Through-Hole Crystal
(HC-49/US)
3.6864
3.6864
3.6864
33
39
ECS International, Inc.
ECS International, Inc.
AVX/Kyocera
ECS-36-18-4
ECS-36-20-5P
PBRC-3.68B
913-782-7787
913-782-7787
803-448-9411
SMT Crystal
SMT Ceramic
Resonator
None
(integral)
24 ______________________________________________________________________________________
SPI/MICROWIRE-Compatible UART and ±15kV ESD-
Protected RS-232 Transceivers with Internal Capacitors
0/MAX31E
High Data Rates
The MAX3110E/MAX3111E maintain the RS-232 ±5.0V
minimum transmitter output-voltage specification even
at the highest guaranteed data rate. Figure 10 shows a
transmitter loopback test circuit. Figure 11 shows a
loopback test result at 120kbps, and Figure 12 shows
the same test at 250kbps. For Figure 11, both transmit-
ters are driven simultaneously at 120kbps into an RS-
232 receiver in parallel with 1000pF. For Figure 12, a
single transmitter is driven at 250kbps, and both trans-
mitters are loaded with an RS-232 receiver in parallel
with 1000pF.
Interconnection with 3.3V and 5V Logic
The MAX3110E/MAX3111E can directly interface with
various 3.3V and 5V logic families, including ACT and
HCT CMOS. See Table 9 for more information on possi-
ble combinations of interconnections.
Typical Applications
The MAX3110E/MAX3111E each contain a UART, two
RS-232 drivers, and two RS-232 receivers in one pack-
age. The standard RS-232 typical operating circuit is
shown in Figure 13.
V
CC
0.1µF
5V/div
5V/div
5V/div
T1IN
T1OUT
R1OUT
V
CC
C1+
V+
V-
C1-
C2+
MAX3110E
MAX3111E
C2-
T_ OUT
T_ IN
2µs/div
= 3.3V (MAX3111E), V = 5.0V (MAX3110E)
R_ IN
5k
R_ OUT
SHDN
V
CC
CC
Figure 12. Loopback Test Result at 250kbps
1000pF
V
CC
GND
V
CC
X1
X2
232 ACTIVE
232 SHUTDOWN
SHDN
V
CC
Figure 10. Loopback Test Circuit
100k
V+
V-
IRQ
C1+
C1-
C2+
C2-
DIN
DOUT
SCLK
CS
µP
MAX3110E
MAX3111E
5V/div
T1IN
TX
T1IN
T1OUT
5V/div
5V/div
RTS
T2IN
T1OUT
T2OUT
R1IN
RX
RS-232 I/O
R1OUT
R1OUT
CTS
R2OUT
R2IN
2µs/div
GND
V
CC
= 3.3V (MAX3111E), V = 5.0V (MAX3110E)
CC
Figure 11. Loopback Test Result at 120kbps
Figure 13. RS-232 Typical Operating Circuit
______________________________________________________________________________________ 25
SPI/MICROWIRE-Compatible UART and ±15kV ESD-
Protected RS-232 Transceivers with Internal Capacitors
An IR and RS-232 typical operating circuit is shown in
Table 9. Logic-Family Compatibility with
Various Supply Voltages
Figure 14. Since the MAX3110E/MAX3111E’s internal
UART has IrDA capability, a standard IR transceiver
(the MAX3120) can be used to provide the IrDA com-
munication. The two-driver/two-receiver RS-232 trans-
ceiver can be used with a software UART to provide
RS-232 communication.
LOGIC
POWER-SUPPLY
VOLTAGE
(V)
V
SUPPLY
VOLTAGE
(V)
CC
COMPATIBILITY
Compatible with all
TTL and CMOS fami-
lies
9-Bit Networks
The MAX3110E/MAX3111E support a common multi-
drop communication technique referred to as 9-bit
mode. In this mode, the parity bit is set to indicate a
message that contains a header with a destination
address. The MAX3110E/MAX3111E’s parity mask can
be set to generate interrupts for this condition.
Operating a network in this mode reduces the process-
ing overhead of all nodes by enabling the slave con-
trollers to ignore most message traffic. This relieves the
remote processor to handle more useful tasks.
5
5
(MAX3110E)
3.3
Compatible with all
CMOS families
3.3
(MAX3111E)
Compatible with ACT
and HCT CMOS, and
with AC, HC, or
5
3.3
(MAX3111E)
CD4000 CMOS
0/MAX31E
V
CC
232 ACTIVE
SHDN
232 SHUTDOWN
V
CC
MAX3120
100k
TX
TXD
UART
IN
IrDA
MODE
IRQ
DIN
DOUT
SCLK
IrDA
I/O
RX
X1
µP
RXD
CS
MAX3110E
MAX3111E
X2
T1IN
T1OUT
NON-IrDA
UART
TX
RX
R1OUT
R1IN
RS-232 I/O
R2OUT
T2IN
R2IN
CTS
RTS
T2OUT
C1+
C1-
V+
V-
C2+
C2-
GND
Figure 14. IR and RS-232 Typical Operating Circuit
26 ______________________________________________________________________________________
SPI/MICROWIRE-Compatible UART and ±15kV ESD-
Protected RS-232 Transceivers with Internal Capacitors
0/MAX31E
In 9-bit mode, the MAX3110E/MAX3111E is set up with
eight bits plus parity. The parity bit in all normal mes-
sages is clear but is set in an address-type message.
NORMAL UART
TX
1
0
1
0
0
1
1
0
1
The MAX3110E/MAX3111E’s parity-interrupt mask gen-
erates an interrupt on high parity when enabled. When
the master sends an address message with the parity
bit set, all MAX3110E/MAX3111E nodes issue an inter-
rupt. All nodes then retrieve the received byte to com-
pare to their assigned address. Once addressed, the
node continues to process each received byte. If the
node was not addressed, it ignores all message traffic
until a new address is sent out by the master.
IrDA
TX
IrDA
RX
NORMAL
RX
0
1
0
1
0
0
1
1
0
1
The parity/9th-bit interrupt is controlled only by the data
in the receive register and is not affected by data in the
FIFO, so the most effective use of the parity/9th-bit
interrupt is with FIFO disabled. With the FIFO disabled,
received non-address words can be ignored and not
even read from the UART. For more detailed informa-
tion on 9-bit mode, refer to the MAX3100 data sheet.
DATA BITS
UART FRAME
Figure 15. IrDA Timing
Layout and Power-Supply
_____________________Considerations
SIR IrDA Mode
The MAX3110E/MAX3111E’s IrDA mode can be used
to communicate with other IrDA SIR-compatible
devices or to reduce power consumption in opto-isolat-
ed applications.
The MAX3110E/MAX3111E require basic layout tech-
niques and fundamental power supply considerations.
The minimum requirements include: (1) placing a 1µF
ceramic bypass capacitor as close as possible to V
,
CC
In IrDA mode, a bit period is shortened to 3/16 of a
baud period (1.61µs at 115,200 baud). A data zero is
transmitted as a pulse of light (TX pin = logic low, RX
pin = logic high), as shown in Figure 15.
preferably right next to the V
lead or on the opposite
CC
side of the PCB directly below the V
lead; (2) using
CC
an internal ground plane within the PCB, returning all
circuit grounds to this ground plane, or using a ‘star’
ground technique where all circuit grounds are
returned to a common ground point at the ‘GND’ lead
of the IC; 3) ensuring that the power source to the IC
has a low inductive path and is high-frequency
bypassed to absorb ESD events with significant
changes in the supply voltage.
In receive mode, the RX signal’s sampling is done
halfway into the transmission of a high level. The sam-
pling is done once (instead of three times, as in normal
mode). The MAX3110E/MAX3111E ignore pulses short-
er than approximately 1/16 of the baud period. The
IrDA device that is communicating with the MAX3110E/
MAX3111E must be set to transmit pulses at 3/16 of the
baud period. For compatibility with other IrDA devices,
set the format to 8-bit data, one stop, no parity. For
more detailed information on SIR IrDA mode, refer to
the MAX3100 data sheet.
______________________________________________________________________________________ 27
SPI/MICROWIRE-Compatible UART and ±15kV ESD-
Protected RS-232 Transceivers with Internal Capacitors
Listing 1. Outline for a MAX3110E/MAX3111E Software Driver
This is a C-language outline of an interrupt-driven software driver that interfaces
to a MAX3110E/MAX3111E, providing an intermediate layer between the bit-manipulation
subroutine and the familiar PutChar / GetChar subroutines.
User must supply code for managing the transmit and receive queues, as well as the
low-level hardware interface itself. The interrupt control hardware must be
initialized before this driver is called.
char is an 8 bit character.
& is the bitwise Boolean AND operator.
int is a 16 bit unsigned integer.
| is the bitwise Boolean OR operator.
/* High level interface routine to put a character to the MAX3110E/MAX3111E. */
PutChar ( char c )
{
EnQueue ( txqueue, c );
/* enable the transmit-buffer-empty interrupt */
config = config | 0x0800; /* set the TM bit */
config = config | 0xC000; /* set bits 15 and 14 */
MAX3110E/MAX3111E ( config );
}
/* High level interface routine to get a character from the MAX3110E/MAX3111E.
0/MAX31E
** Wait for a character to be received, if necessary.
*/
char GetChar ( )
{
while ( IsQueueEmpty ( rxqueue ) )
/* wait for data to be received */ ;
return DeQueue ( rxqueue );
}
/* Configure the MAX3110E/MAX3111E with the specified baud rate. */
ConfigureMAX3110E/MAX3111E ( int baud_rate_index )
{
baud_rate_index = baud_rate_index & 0x000F; /* restrict to a 4 bit field */
config = 0xC400 + baud_rate_index; /* enable received data interrupt */
MAX3110E/MAX3111E ( config );
}
/* private variable that stores the configuration settings for the MAX3110E/MAX3111E
*/
int config;
/* Low level communication routine between the computer and the MAX3110E/MAX3111E.
** This is a PRIVATE routine to be used only within the driver software.
*/
int MAX3110E/MAX3111E ( int mosi )
{
int miso;
/* this is interface-specific.
** Transmit 16 bits of master-out, slave-in data, MSB first,
** while simultaneously receiving 16 bits of master-in, slave-out data.
** If and SPI hardware interface is available, use (CPOL=0,CPHA=0) mode.
** Lacking specialized hardware, just set and clear I/O bits to generate
** the waveform in figures 2 and 3 in the MAX3110E/MAX311E data sheet.
*/
return miso; /* return 16 bits of master-in, slave-out data, MSB first */
}
28 ______________________________________________________________________________________
SPI/MICROWIRE-Compatible UART and ±15kV ESD-
Protected RS-232 Transceivers with Internal Capacitors
0/MAX31E
Listing 1. Outline for a MAX3110E/MAX3111E Software Driver (continued)
/* This driver needs a txqueue transmit-data queue and a rxqueue receive-data queue.
** These can be ring buffers or any other kind of first-in, first-out data queue.
*/
EnQueue ( queue , char )
char DeQueue ( queue )
true/false IsQueueEmpty ( queue )
/* Interrupt service routine called when the MAX3110EMAX3111E’s INT pin falls to a
low level.
** This is a PRIVATE routine to be used only within the driver software.
*/
ServiceMAX3110E/MAX3111Eint ( )
{
int rxdata;
int txdata;
char c;
/* issue a READ DATA command to discover the cause of the interrupt */
rxdata = MAX3110E/MAX3111E ( 0 );
if ( rxdata & 0x8000 ) /* the R bit = 1 */
{
c = rxdata & 0x00FF; /* get the received character data */
EnQueue ( rxqueue, c );
}
if ( rxdata & 0x4000 ) /* the T bit = 1 */
{
if ( IsQueueEmpty ( txqueue ) )
{
/* mask the transmit-buffer-empty interrupt */
config = config & ~ 0x0800; /* clear the TM bit */
config = config | 0xC000; /* set bits 15 and 14 */
MAX3110E/MAX3111E ( config );
}
else /* transmit some data */
{
/* issue a WRITE DATA command */
txdata = DeQueue ( txqueue );
c = txdata & 0x00FF; /* get the transmit character */
MAX3110E/MAX3111E ( 0x8000 | c );
}
}
} /* end of ServiceMAX3110E/MAX3111Eint */
______________________________________________________________________________________ 29
SPI/MICROWIRE-Compatible UART and ±15kV ESD-
Protected RS-232 Transceivers with Internal Capacitors
Ordering Information
Chip Information
PIN-
PACKAGE
V
CC
(V)
TRANSISTOR COUNT: 7977
PART
TEMP. RANGE
MAX3110EEWI -40°C to +85°C
MAX3110EENI -40°C to +85°C
28 Wide SO
28 Plastic DIP
28 Wide SO
28 Plastic DIP
28 Wide SO
28 Plastic DIP
5
5
MAX3111ECWI
0°C to +70°C
0°C to +70°C
3.3
3.3
3.3
3.3
MAX3111ECNI
MAX3111EEWI -40°C to +85°C
MAX3111EENI -40°C to +85°C
Pin Configuration
TOP VIEW
R2IN
R2OUT
T2IN
1
2
3
4
5
6
7
8
9
28 T2OUT
27 GND
26 V-
0/MAX31E
T1IN
25 C2-
24 C2+
R1OUT
R1IN
MAX3110E
MAX3111E
23 C1-
22 C1+
21 V+
T1OUT
V
CC
X2
20 SHDN
19 IRQ
18 CS
X1 10
CTS 11
RTS 12
RX 13
TX 14
17 SCLK
16 DOUT
15 DIN
Narrow DIP/Wide SO
30 ______________________________________________________________________________________
SPI/MICROWIRE-Compatible UART and ±15kV ESD-
Protected RS-232 Transceivers with Internal Capacitors
0/MAX31E
Package Information
______________________________________________________________________________________ 31
SPI/MICROWIRE-Compatible UART and ±15kV ESD-
Protected RS-232 Transceivers with Internal Capacitors
Package Information (continued)
0/MAX31E
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
32 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 1999 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
相关型号：
MAX3111EEWI-T
Serial I/O Controller, 1 Channel(s), CMOS, PDSO28, 0.300 INCH, MS-013AE, SOIC-28
MAXIM
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