MAX3062EEKA+T [MAXIM]
Line Transceiver,;
| 型号： | MAX3062EEKA+T |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Line Transceiver, |
| 文件： | 总17页 (文件大小：350K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-2536; Rev 1; 7/07
1ꢀ5kVEꢁSD-Potected,VFailDꢁafe,V20Mbps,VꢁlewDRateD
LimitedVRꢁD48ꢀ/RꢁD422VTPansceivePsVinVaVꢁOT
GenePalVSescPiption
FeatuPes
The MAX3060E/MAX3061E/MAX3062E high-speed
transceivers for RS-485/RS-422 communication contain
one driver and one receiver. These devices feature fail-
safe circuitry, which guarantees a logic-high receiver
output when the receiver inputs are open or shorted.
This means that the receiver output is a logic high if all
transmitters on a terminated bus are disabled (high
impedance). These devices also feature hot-swap cir-
cuitry that eliminates data glitches during hot insertion.
♦ True Fail-Safe Receiver While Maintaining
EIA/TIA-485 Compatibility
♦ Enhanced Slew-Rate Limiting Facilitates
Error-Free Data Transmission (MAX3060E and
MAX3061E)
♦ 1nA Low-Current Shutdown Mode
♦ Hot-Swappable for Telecom Applications
♦ ESD Protection: 15ꢀk Human ꢁody Model
♦ Allow Up to 256 Transceivers on the ꢁus
♦ Space-Saving 8-Pin SOT23 Pacꢀage
The MAX3060E features slew-rate-limited drivers that
minimize EMI and reduce reflections caused by
improperly terminated cables, allowing error-free data
transmission up to 115kbps. The MAX3061E, also slew-
rate limited, transmits up to 500kbps. The MAX3062E
driver is not slew-rate limited, allowing transmit speeds
up to 20Mbps. All transmitter outputs are protected to
15kꢀ using the ꢁuman ꢂody Model.
OPdePingVInfoPmation
PIN-
PACKAGE
TOP
MARK
PART
TEMP RANGE
These transceivers typically draw 910µA of supply
current when unloaded, or 790µA when fully loaded
with the drivers disabled.
MAX3060EEKA-T
MAX3060EEKA#T
MAX3061EEKA-T
MAX3061EEKA#T
MAX3062EEKA-T
MAX3062EEKA#T
-40°C to +85°C 8 SOT23-8
-40°C to +85°C 8 SOT23-8
-40°C to +85°C 8 SOT23-8
-40°C to +85°C 8 SOT23-8
-40°C to +85°C 8 SOT23-8
-40°C to +85°C 8 SOT23-8
AAKI
AEPA*
AAKJ
All devices have a 1/8-unit-load receiver input imped-
ance that allows up to 256 transceivers on the bus. These
devices are intended for half-duplex communication.
AEPꢂ*
AAKK
AEPC*
Applications
RS-422/RS-485 Communications
Level Translators
*Indicates an RoHS-compliant part
T = Tape and Reel
ꢁelectoPVGuide
Transceivers for EMI-Sensitive Applications
Industrial-Control Local-Area Networks
DATA
RATE
(Mbps)
SLEW-
RATE
LIMITED
TRANSCEIkERS
PART
ON ꢁUS
MAX3060E
MAX3061E
MAX3062E
0.115
0.5
Yes
Yes
No
256
256
256
20
TypicalVOpePatingVCiPcuit/-inVConfiguPation
+5V
0.1μF
MAX3060E
MAX3061E
MAX3062E
TOP VIEW
DE
DI
R
RO
RE
DE
DI
1
2
3
4
8
7
V
D
CC
Rt
B
B
A
Rt
6
A
RO
R
D
5
GND
RE
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim's website at www.maxim-ic.com.
1ꢀ5kVEꢁSD-Potected,VFailDꢁafe,V20Mbps,VꢁlewDRateD
LimitedVRꢁD48ꢀ/RꢁD422VTPansceivePsVinVaVꢁOT
AꢁSOLUTE MAXIMUM RATINGS
All ꢀoltages with Respect to GND
Operating Temperature Range
Supply ꢀoltage (ꢀ ) ............................................................+7ꢀ
MAX306_EE_ _ ................................................-40°C to +85°C
Storage Temperature Range.............................-65°C to +150°C
Junction Temperature......................................................+150°C
Lead Temperature (soldering, 10s) .................................+300°C
CC
Input ꢀoltage (RE, DE, DI)..........................-0.3ꢀ to (ꢀ
+ 0.3ꢀ)
CC
Driver Output/Receiver Input ꢀoltage (A, ꢂ) .......-7.5ꢀ to +12.5ꢀ
Receiver Output ꢀoltage (RO)....................-0.3ꢀ to (ꢀ + 0.3ꢀ)
CC
Continuous Power Dissipation (T = +70°C)
A
8-Pin SOT23 (derate 8.9mW/°C above +70°C)............714mW
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(ꢀ
= +5ꢀ 5%, T = T
A
to T
, unless otherwise noted. Typical values are at ꢀ
= +5ꢀ and T = +25°C.) (Notes 1, 2)
CC A
CC
MIN
MAX
PARAMETER
SYMꢁOL
CONDITIONS
MIN
TYP
MAX
UNITS
DRIkER
Differential Driver Output
(No Load)
ꢀ
ꢀ
ꢀ
= 5ꢀ
CC
5
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
OD1
OD2
Figure 1, R = 50Ω (RS-422)
Figure 1, R = 27Ω (RS-485)
2.0
1.5
Differential Driver Output
Change in Magnitude of
Differential Output ꢀoltage
Δꢀ
Figure 1, R = 50Ω or R = 27Ω (Note 3)
Figure 1, R = 50Ω or R = 27Ω
0.2
3
OD
Driver Common-Mode Output
ꢀoltage
ꢀ
OC
Change in Magnitude of
Common-Mode ꢀoltage
Δꢀ
Figure 1, R = 50Ω or R = 27Ω (Note 3)
0.2
OC
Input ꢁigh ꢀoltage
Input Low ꢀoltage
DI Input ꢁysteresis
Input Current
ꢀ
DE, DI, RE
DE, DI, RE
2.0
ꢀ
ꢀ
Iꢁ
ꢀ
0.8
IL
ꢀ
100
mꢀ
µA
µA
ꢁYS
IN1
I
DE, DI, RE
1
ꢁot-Swap Driver Input Current
I
DE, RE (Note 4)
200
125
ꢁOTSWAP
ꢀ
ꢀ
= +12ꢀ
= -7ꢀ
IN
IN
DE = GND,
= GND or 5.25ꢀ
Input Current (A and ꢂ)
I
µA
IN2
ꢀ
CC
-100
15
Driver Short-Circuit Output
Current
ꢀ
-7ꢀ ≤ ꢀ
≤ +12ꢀ, T = +25°C (Note 5)
250
mA
OD1
OUT
A
IEC 1000-4-2 Air-Gap Discharge
IEC 1000-4-2 Contact Discharge
ꢁuman ꢂody Model
7
7
ESD Protection for A, ꢂ
kꢀ
15
2
_______________________________________________________________________________________
1ꢀ5kVEꢁSD-Potected,VFailDꢁafe,V20Mbps,VꢁlewDRateD
LimitedVRꢁD48ꢀ/RꢁD422VTPansceivePsVinVaVꢁOT
DC ELECTRICAL CHARACTERISTICS (continued)
(ꢀ
= +5ꢀ 5%, T = T
A
to T
, unless otherwise noted. Typical values are at ꢀ
= +5ꢀ and T = +25°C.) (Notes 1, 2)
CC A
CC
MIN
MAX
PARAMETER
SYMꢁOL
CONDITIONS
MIN
TYP
MAX
UNITS
RECEIkER
Receiver Differential Threshold
ꢀoltage
ꢀ
-7ꢀ ≤ ꢀCM ≤ +12ꢀ
-200
-125
25
-50
mꢀ
Tꢁ
Receiver Input ꢁysteresis
Δꢀ
mꢀ
ꢀ
Tꢁ
Receiver Output ꢁigh ꢀoltage
Receiver Output Low ꢀoltage
ꢀ
I
I
= -4mA, ꢀ = -50mꢀ
ꢀ
- 1.5
CC
Oꢁ
O
ID
ꢀ
= 4mA, ꢀ = -200mꢀ
0.4
1
ꢀ
OL
O
ID
Three-State Output Current at
Receiver
I
0ꢀ ≤ ꢀ ≤ ꢀ
CC
0.01
µA
kΩ
mA
OZR
O
Receiver Input Resistance
R
-7ꢀ ≤ ꢀ
≤ +12ꢀ
96
8
IN
CM
Receiver Output Short-Circuit
Current
I
0ꢀ ≤ ꢀ
≤ ꢀ
CC
80
OSR
RO
SUPPLY CURRENT
DE = RE = GND
790
910
1400
1500
No load,
DI = GND or ꢀ
Supply Current
I
µA
µA
CC
CC
DE = RE = ꢀ
CC
Supply Current in Shutdown
Mode
I
DE = GND, RE = ꢀ
0.001
1
SꢁDN
CC
_______________________________________________________________________________________
3
1ꢀ5kVEꢁSD-Potected,VFailDꢁafe,V20Mbps,VꢁlewDRateD
LimitedVRꢁD48ꢀ/RꢁD422VTPansceivePsVinVaVꢁOT
SWITCHING CHARACTERISTICS—MAX3060E
(ꢀ
= +5ꢀ 5%, T = T
A
to T
, unless otherwise noted. Typical values are at ꢀ
= +5ꢀ and T = +25°C.) (Notes 1, 2)
CC A
CC
MIN
MAX
PARAMETER
SYMꢁOL
, t
CONDITIONS
MIN
TYP
MAX
UNITS
Figures 3 and 5, R
= 54Ω,
= 54Ω,
= 54Ω,
DIFF
DIFF
DIFF
Driver Input to Output
t
1.0
1.7
2.4
µs
DPLꢁ DPꢁL
C
= 50pF
DIFF
Driver Output Skew
Figures 3 and 5, R
C = 50pF
DIFF
t
-200
-7
+200
2.5
ns
µs
DSKEW
(t
- t
)
DPLꢁ DPꢁL
Figures 3 and 5, R
= 50pF
Driver Rise or Fall Time
Maximum Data Rate
t , t
DR DF
1.3
1.85
C
DIFF
f
115
kbps
µs
MAX
Driver Enable to Output ꢁigh
Driver Enable to Output Low
Driver Disable Time from Low
Driver Disable Time from ꢁigh
t
Figures 4 and 6, C = 100pF, S2 closed
0.6
0.5
60
1.5
1.5
DZꢁ
L
t
Figures 4 and 6, C = 100pF, S1 closed
µs
DZL
DLZ
DꢁZ
L
t
Figures 4 and 6, C = 15pF, S1 closed
200
200
ns
L
t
Figures 4 and 6, C = 15pF, S2 closed
85
ns
L
t
t
,
Figures 7 and 9; | ꢀ | ≥ 2.0ꢀ;
ID
RPLꢁ
Receiver Input to Output
47
-3
80
ns
ns
rise and fall time of ꢀ ≤ 4ns, C = 15pF
RPꢁL
ID L
Differential Receiver Skew
Figures 7 and 9; | ꢀ | ≥ 2.0ꢀ;
ID
t
-10
50
+10
RSKD
(t
- t
)
rise and fall time of ꢀ ≤ 4ns, C = 15pF
RPLꢁ RPꢁL
ID L
Receiver Enable to Output Low
Receiver Enable to Output ꢁigh
t
Figures 2 and 8, C = 15pF, S1 closed
50
50
ns
ns
ns
ns
ns
RZL
L
t
Figures 2 and 8, C = 15pF, S2 closed
L
RZꢁ
Receiver Disable Time from Low
Receiver Disable Time from ꢁigh
Time to Shutdown
t
Figures 2 and 8, C = 15pF, S1 closed
50
RLZ
RꢁZ
L
t
Figures 2 and 8, C = 15pF, S2 closed
L
50
t
(Note 6)
180
600
SꢁDN
Driver Enable from Shutdown to
Output ꢁigh
t
t
Figures 4 and 6, C = 100pF, S2 closed
2
µs
µs
µs
µs
DZꢁ(SꢁDN)
L
Driver Enable from Shutdown to
Output Low
t
Figures 4 and 6, C = 100pF, S1 closed
2
DZL(SꢁDN)
L
Receiver Enable from Shutdown
to Output ꢁigh
Figures 2 and 8, C = 15pF, S2 closed
1.5
1.5
RZꢁ(SꢁDN)
L
Receiver Enable from Shutdown
to Output Low
t
Figures 2 and 8, C = 15pF, S1 closed
L
RZL(SꢁDN)
4
_______________________________________________________________________________________
1ꢀ5kVEꢁSD-Potected,VFailDꢁafe,V20Mbps,VꢁlewDRateD
LimitedVRꢁD48ꢀ/RꢁD422VTPansceivePsVinVaVꢁOT
SWITCHING CHARACTERISTICS—MAX3061E
(ꢀ
= +5ꢀ 5%, T = T
to T
, unless otherwise noted. Typical values are at ꢀ
= +5ꢀ and T = +25°C.) (Notes 1, 2)
CC A
CC
A
MIN
MAX
PARAMETER
SYMꢁOL
CONDITIONS
MIN
TYP
MAX
UNITS
t
t
,
Figures 3 and 5, R
= 54Ω,
= 54Ω,
= 54Ω,
DPLꢁ
DIFF
DIFF
DIFF
Driver Input to Output
250
470
800
ns
C
= 50pF
DIFF
DPꢁL
Driver Output Skew
Figures 3 and 5, R
C = 50pF
DIFF
t
-100
-4
+100
750
ns
ns
DSKEW
(t
- t
)
DPLꢁ DPꢁL
Figures 3 and 5, R
= 50pF
Driver Rise or Fall Time
Maximum Data Rate
t
, t
200
500
530
DR DF
C
DIFF
f
kbps
ns
MAX
Driver Enable to Output ꢁigh
Driver Enable to Output Low
Driver Disable Time from Low
Driver Disable Time from ꢁigh
t
Figures 4 and 6, C = 100pF, S2 closed
330
200
60
1000
1000
200
DZꢁ
L
t
t
Figures 4 and 6, C = 100pF, S1 closed
ns
DZL
DLZ
DꢁZ
L
Figures 4 and 6, C = 15pF, S1 closed
ns
L
t
Figures 4 and 6, C = 15pF, S2 closed
80
200
ns
L
t
t
,
Figures 7 and 9; | ꢀ | ≥ 2.0ꢀ;
ID
RPLꢁ
Receiver Input to Output
47
-3
80
ns
ns
rise and fall time of ꢀ ≤ 4ns, C = 15pF
RPꢁL
ID L
Differential Receiver Skew
Figures 7 and 9; | ꢀ | ≥ 2.0ꢀ;
ID
t
-10
50
+10
RSKD
(t
- t
)
rise and fall time of ꢀ ≤ 4ns, C = 15pF
RPLꢁ RPꢁL
ID L
Receiver Enable to Output Low
Receiver Enable to Output ꢁigh
t
Figures 2 and 8, C = 15pF, S1 closed
50
50
ns
ns
ns
ns
ns
RZL
L
t
Figures 2 and 8, C = 15pF, S2 closed
L
RZꢁ
Receiver Disable Time from Low
Receiver Disable Time from ꢁigh
Time to Shutdown
t
Figures 2 and 8, C = 15pF, S1 closed
50
RLZ
L
t
Figures 2 and 8, C = 15pF, S2 closed
L
50
RꢁZ
t
(Note 6)
180
600
SꢁDN
Driver Enable from Shutdown to
Output ꢁigh
t
Figures 4 and 6, C = 100pF, S2 closed
1.5
1.5
1.5
1.5
µs
µs
µs
µs
DZꢁ(SꢁDN
DZL(SꢁDN)
RZꢁ(SꢁDN)
L
Driver Enable from Shutdown to
Output Low
t
Figures 4 and 6, C = 100pF, S1 closed
L
Receiver Enable from Shutdown
to Output ꢁigh
t
Figures 2 and 8, C = 15pF, S2 closed
L
Receiver Enable from Shutdown
to Output Low
t
Figures 2 and 8, C = 15pF, S1 closed
L
RZL(SꢁDN)
_______________________________________________________________________________________
5
1ꢀ5kVEꢁSD-Potected,VFailDꢁafe,V20Mbps,VꢁlewDRateD
LimitedVRꢁD48ꢀ/RꢁD422VTPansceivePsVinVaVꢁOT
SWITCHING CHARACTERISTICS—MAX3062E
(ꢀ
= +5ꢀ 5%, T = T
A
to T
, unless otherwise noted. Typical values are at ꢀ
= +5ꢀ and T = +25°C.) (Notes 1, 2)
CC A
CC
MIN
MAX
PARAMETER
SYMꢁOL
CONDITIONS
MIN
-10
20
TYP
MAX
UNITS
t
,
Figures 3 and 5, R
= 54Ω,
= 54Ω,
= 54Ω,
DPLꢁ
DIFF
DIFF
DIFF
Driver Input to Output
20
30
ns
t
C
= 50pF
DIFF
DPꢁL
Driver Output Skew
Figures 3 and 5, R
C = 50pF
DIFF
t
+1
8
+10
15
ns
ns
DSKEW
(t
- t
)
DPLꢁ DPꢁL
Figures 3 and 5, R
= 50pF
Driver Rise or Fall Time
Maximum Data Rate
t , t
DR DF
C
DIFF
f
Mbps
ns
MAX
Driver Enable to Output ꢁigh
Driver Enable to Output Low
Driver Disable Time from Low
Driver Disable Time from ꢁigh
t
Figures 4 and 6, C = 100pF, S2 closed
250
250
100
100
500
500
200
200
DZꢁ
L
t
Figures 4 and 6, C = 100pF, S1 closed
ns
DZL
DLZ
DꢁZ
L
t
Figures 4 and 6, C = 15pF, S1 closed
ns
L
t
Figures 4 and 6, C = 15pF, S2 closed
ns
L
t
t
,
Figures 7 and 9; | ꢀ | ≥ 2.0ꢀ;
ID
rise and fall time of ꢀ ≤ 4ns, C = 15pF
ID L
RPLꢁ
Receiver Input to Output
45
-4
80
ns
ns
RPꢁL
Differential Receiver Skew
Figures 7 and 9; | ꢀ | ≥ 2.0ꢀ;
ID
t
-10
50
+10
RSKD
(t
- t
)
rise and fall time of ꢀ ≤ 4ns, C = 15pF
ID L
RPLꢁ RPꢁL
Receiver Enable to Output Low
Receiver Enable to Output ꢁigh
t
Figures 2 and 8, C = 15pF, S1 closed
50
50
ns
ns
ns
ns
ns
RZL
L
t
Figures 2 and 8, C = 15pF, S2 closed
L
RZꢁ
Receiver Disable Time from Low
Receiver Disable Time from ꢁigh
Time to Shutdown
t
Figures 2 and 8, C = 15pF, S1 closed
50
RLZ
RꢁZ
L
t
Figures 2 and 8, C = 15pF, S2 closed
L
50
t
(Note 6)
180
600
SꢁDN
Driver Enable from Shutdown to
Output ꢁigh
t
t
Figures 4 and 6, C = 100pF, S2 closed
100
100
1.5
ns
ns
µs
µs
DZꢁ(SꢁDN)
L
Driver Enable from Shutdown to
Output Low
t
Figures 4 and 6, C = 100pF, S1 closed
L
DZL(SꢁDN)
Receiver Enable from Shutdown
to Output ꢁigh
Figures 2 and 8, C = 15pF, S2 closed
RZꢁ(SꢁDN)
L
Receiver Enable from Shutdown
to Output Low
t
Figures 2 and 8, C = 15pF, S1 closed
1.5
RZL(SꢁDN)
L
Note 1: Overtemperature limits are guaranteed by design and are not production tested. Devices are tested at T = +25°C.
A
Note 2: All currents into the device are positive; all currents out of the device are negative. All voltages are referred to device
ground, unless otherwise noted.
Note 3: Δꢀ
and Δꢀ
are the changes in ꢀ
and ꢀ , respectively, when the DI input changes state.
OD OC
OD
OC
Note 4: This input current level is for the hot-swap enable (DE, RE) inputs and is present until the first transition only. After the first
transition, the input reverts to a standard high-impedance CMOS input with input current I . For the first 10µs, the input
IN1
current can be as high as 1mA. During this period the input is disabled.
Note 5: Maximum current level applies to peak current just prior to foldback-current limiting; minimum current level applies during
current limiting.
Note 6: The device is put into shutdown by bringing RE high and DE low. If the enable inputs are in this state for less than 50ns, the
device is guaranteed not to enter shutdown. If the enable inputs are in this state for at least 600ns, the device is guaranteed
to have entered shutdown.
6
_______________________________________________________________________________________
1ꢀ5kVEꢁSD-Potected,VFailDꢁafe,V20Mbps,VꢁlewDRateD
LimitedVRꢁD48ꢀ/RꢁD422VTPansceivePsVinVaVꢁOT
A
1kΩ
TEST POINT
R
RECEIVER
OUTPUT
V
CC
S1
S2
C
L
1kΩ
V
OD2
15pF
R
V
OC
B
Figure 1. Driver DC Test Load
Figure 2. Receiver Enable/Disable Timing Test Load
5V
DE
V
CC
A
S1
500Ω
DI
OUTPUT
UNDER TEST
V
OD2
R
DIFF
C
DIFF
B
C
L
S2
Figure 3. Driver Timing Test Circuit
Figure 4. Driver Enable/Disable Timing Test Load
5V
5V
DI
1.5V
1.5V
DE
1.5V
1.5V
0
t
t
0
DPLH
DPHL
t
t
, t
DLZ
DZL(SHDN) DZL
B
A
A, B
2.3V
V
V
+ 0.5V
- 0.5V
OUTPUT NORMALLY LOW
OUTPUT NORMALLY HIGH
OL
V
OL
V
= V (A) - V (B)
DIFF
V
O
0
A, B
V
DIFF
90%
90%
2.3V
OH
10%
10%
-V
0
O
t
DR
t
DF
t
, t
t
DHZ
DZH(SHDN) DZH
t
t
- t
DSKEW = | DPLH DPHL |
Figure 5. Driver Propagation Delays
Figure 6. Driver Enable and Disable Times
_______________________________________________________________________________________
7
1ꢀ5kVEꢁSD-Potected,VFailDꢁafe,V20Mbps,VꢁlewDRateD
LimitedVRꢁD48ꢀ/RꢁD422VTPansceivePsVinVaVꢁOT
5V
RE
1.5V
1.5V
0
V
t
t
, t
OH
RLZ
RZL(SHDN) RZL
RO
V
RO
CC
1.5V
1.5V
V
OUTPUT
OL
1.5V
V
V
+ 0.5V
- 0.5V
OUTPUT NORMALLY LOW
OUTPUT NORMALLY HIGH
OL
t
t
RPLH
RPHL
A
B
1V
-1V
INPUT
RO
1.5V
OH
0
t
, t
t
RHZ
RZH(SHDN) RZH
Figure 7. Receiver Propagation Delays
Figure 8. Receiver Enable and Disable Times
B
RECEIVER
OUTPUT
V
R
ID
ATE
A
Figure 9. Receiver Propagation Delay Test Circuit
TypicalVOpePatingVChaPactePistics
(ꢀ
= +5ꢀ, T = +25°C, unless otherwise noted.)
A
CC
NO-LOAD SUPPLY CURRENT
vs. TEMPERATURE
RECEIVER OUTPUT CURRENT
vs. RECEIVER OUTPUT LOW VOLTAGE
RECEIVER OUTPUT CURRENT
vs. RECEIVER OUTPUT HIGH VOLTAGE
950
900
60
50
40
30
20
10
0
20
18
16
14
12
10
8
DE = RE = V
CC
850
800
750
700
650
DE = RE = GND
6
4
2
0
-40
-15
10
35
60
85
0
1
2
3
4
5
0
1
2
3
4
5
TEMPERATURE (°C)
OUTPUT LOW VOLTAGE (V)
OUTPUT HIGH VOLTAGE (V)
8
_______________________________________________________________________________________
1ꢀ5kVEꢁSD-Potected,VFailDꢁafe,V20Mbps,VꢁlewDRateD
LimitedVRꢁD48ꢀ/RꢁD422VTPansceivePsVinVaVꢁOT
TypicalVOpePatingVChaPactePisticsV(continued)
(ꢀ
= +5ꢀ, T = +25°C, unless otherwise noted.)
A
CC
RECEIVER OUTPUT HIGH VOLTAGE
vs. TEMPERATURE
SHUTDOWN CURRENT
vs. TEMPERATURE
RECEIVER OUTPUT LOW VOLTAGE
vs. TEMPERATURE
5.0
0.50
0.45
0.40
0.35
0.30
0.25
0.20
0.15
0.10
I
= -8mA
RO
I
= 8mA
RO
4.2
4.0
3.8
3.6
3.4
3.2
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
-40
-15
10
35
60
85
-40
-15
10
35
60
85
-40
-15
10
35
60
85
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
RECEIVER PROPAGATION DELAY
(MAX3060E/MAX3061E) vs. TEMPERATURE
RECEIVER PROPAGATION DELAY
(MAX3062E) vs. TEMPERATURE
DRIVER PROPAGATION DELAY
(MAX3060E) vs. TEMPERATURE
70
70
65
60
55
50
45
40
35
30
25
20
1.80
1.78
1.76
1.74
1.72
1.70
1.68
1.66
1.64
1.62
1.60
R = 54Ω
t
C = 15pF
L
C = 15pF
L
65
60
55
50
45
40
35
30
25
20
-40
-15
10
35
60
85
-40
-15
10
35
60
85
-40
-15
10
35
60
85
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
DRIVER DIFFERENTIAL OUTPUT VOLTAGE
vs. TEMPERATURE
DRIVER PROPAGATION DELAY
(MAX3062E) vs. TEMPERATURE
DRIVER PROPAGATION DELAY
(MAX3061E) vs. TEMPERATURE
30
25
20
15
10
5
3.4
3.2
3.0
2.8
2.6
2.4
2.2
2.0
540
520
500
480
460
440
420
400
R = 54Ω
t
R = 54Ω
R = 54Ω
t
t
0
-40
-15
10
35
60
85
-40
-15
10
35
60
85
-40
-15
10
35
60
85
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
_______________________________________________________________________________________
9
1ꢀ5kVEꢁSD-Potected,VFailDꢁafe,V20Mbps,VꢁlewDRateD
LimitedVRꢁD48ꢀ/RꢁD422VTPansceivePsVinVaVꢁOT
TypicalVOpePatingVChaPactePisticsV(continued)
(ꢀ
= +5ꢀ, T = +25°C, unless otherwise noted.)
A
CC
DRIVER OUTPUT CURRENT
vs. DIFFERENTIAL OUTPUT VOLTAGE
DRIVER OUTPUT CURRENT
vs. OUTPUT LOW VOLTAGE
DRIVER OUTPUT CURRENT
vs. OUTPUT HIGH VOLTAGE
100
10
120
100
80
60
40
20
0
90
80
70
60
50
40
30
20
10
0
1
0.1
0.01
0
1
2
3
4
5
6
0
2
4
6
8
10
12
-8
-6
-4
-2
0
2
4
6
DIFFERENTIAL OUTPUT VOLTAGE (V)
OUTPUT LOW VOLTAGE (V)
OUTPUT HIGH VOLTAGE (V)
RECEIVER PROPAGATION DELAY
(MAX3060E/MAX3061E)
DRIVER PROPAGATION DELAY
(MAX3061E)
RECEIVER PROPAGATION DELAY
(MAX3062E)
MAX3060E toc16
MAX3060E toc18
MAX3060E toc17
DI
5V/div
V
- V
B
A
V
- V
B
A
1V/div
1V/div
RO
5V/div
RO
5V/div
V
A
- V
B
2V/div
20ns/div
1μs/div
20ns/div
DRIVER PROPAGATION DELAY
(MAX3061E)
DRIVER PROPAGATION DELAY
(MAX3060E)
DRIVER PROPAGATION DELAY
(MAX3062E)
MAX3060E toc20
MAX3060E toc21
MAX3060E toc19
DI
5V/div
DI
5V/div
V
- V
B
A
2V/div
V
A
- V
B
2V/div
10ns/div
20ns/div
2μs/div
10 ______________________________________________________________________________________
1ꢀ5kVEꢁSD-Potected,VFailDꢁafe,V20Mbps,VꢁlewDRateD
LimitedVRꢁD48ꢀ/RꢁD422VTPansceivePsVinVaVꢁOT
-inVSescPiption
PIN
NAME
FUNCTION
Receiver Output. When RE is low and when A - ꢂ ≥ -50mꢀ, RO is high; if A - ꢂ ≤ -200mꢀ, RO is low. RO
is high impedance when RE is high.
1
RO
Receiver Output Enable. Drive RE low to enable RO; RO is high impedance when RE is high. Drive RE
high and DE low to enter low-power shutdown mode. RE is a hot-swap input and reverts to a standard
CMOS input after the first low transition.
2
RE
Driver Output Enable. Drive DE high to enable driver outputs. Driver outputs are high impedance when
DE is low. Drive RE high and DE low to enter low-power shutdown mode. DE is a hot-swap input and
reverts to a standard CMOS input after the first high transition.
3
4
DE
DI
Driver Input. With DE high, a low on DI forces the noninverting output low and the inverting output high.
Similarly, a high on DI forces the noninverting output high and the inverting output low.
5
6
7
8
GND
A
Ground
Noninverting Receiver Input and Noninverting Driver Output
Inverting Receiver Input and Inverting Driver Output
Positive Supply. ꢂypass with a 0.1µF capacitor to GND.
ꢂ
ꢀ
CC
ReceivePVInputVFiltePing
The receivers of the MAX3060E and MAX3061E incorpo-
SetailedVSescPiption
The MAX3060E/MAX3061E/MAX3062E high-speed trans-
ceivers for RS-485/RS-422 communication contain one
driver and one receiver. These devices feature fail-safe
circuitry, which guarantees a logic-high receiver output
when the receiver inputs are open or shorted, or when
they are connected to a terminated transmission line with
all drivers disabled (see the Fail Safe section). All devices
have a hot-swap input structure that prevents distur-
bances on the differential signal lines when a circuit
board is plugged into a hot backplane (see the Hot-Swap
Capability section). The MAX3060E features a reduced
slew-rate driver that minimizes EMI and reduces reflec-
tions caused by improperly terminated cables, allowing
error-free data transmission up to 115kbps (see the
Reduced EMI and Reflections section). The MAX3061E is
also slew-rate limited, transmitting up to 500kbps. The
MAX3062E driver is not slew-rate limited, allowing trans-
mit speeds up to 20Mbps. The MAX3060E/MAX3061E/
MAX3062E are half-duplex transceivers.
rate input filtering in addition to input hysteresis. This fil-
tering enhances noise immunity with differential signals
that have very slow rise and fall times. Receiver propa-
gation delay increases by 2ns due to this filtering.
FailDꢁafe
The MAX3060E family of devices guarantee a logic-high
receiver output when the receiver inputs are shorted or
open, or when they are connected to a terminated trans-
mission line with all drivers disabled. This is done by set-
ting the receiver threshold between -50mꢀ and
-200mꢀ. If the differential receiver input voltage (A - ꢂ) is
greater than or equal to -50mꢀ, RO is logic high. If
A - ꢂ is less than or equal to -200mꢀ, RO is logic low. In
the case of a terminated bus with all transmitters dis-
abled, the receiver’s differential input voltage is pulled to
0ꢀ by the termination. In the case of an unterminated bus
with all transmitters disabled, the receiver’s differential
input voltage is pulled to 0ꢀ by the receiver’s input resis-
tors. With the receiver thresholds of the MAX3060E fami-
ly, this results in a logic high output with a 50mꢀ
minimum input noise margin. Unlike previous fail-safe
devices, the -50mꢀ to -200mꢀ threshold complies with
the 200mꢀ EIA/TIA-485 standard.
All of these parts operate from a single +5ꢀ supply.
Drivers are output short-circuit current limited. Thermal-
shutdown circuitry protects drivers against excessive
power dissipation. When activated, the thermal-shut-
down circuitry places the driver outputs into a high-
impedance state.
______________________________________________________________________________________ 11
1ꢀ5kVEꢁSD-Potected,VFailDꢁafe,V20Mbps,VꢁlewDRateD
LimitedVRꢁD48ꢀ/RꢁD422VTPansceivePsVinVaVꢁOT
FunctionalVTables
Table 2. Receiver Functional Table
Table 1. Transmitter Functional Table
TRANSMITTING
RECEIkING
INPUTS
INPUTS
OUTPUTS
OUTPUT
RO
1
RE
X
DE
1
DI
1
ꢂ
0
1
A
RE
0
DE
X
A-ꢂ
≥ -0.05ꢀ
≤ -0.2ꢀ
Open/shorted
X
1
0
0
X
1
0
0
X
1
0
0
X
X
ꢁigh-Z
ꢁigh-Z
0
X
1
0
Shutdown*
1
1
ꢁigh-Z
1
0
X
Shutdown
X = Don’t care.
*Shutdown mode, driver and receiver outputs are high impedance.
until an external source overcomes the required input
current. At this time, the SR latch resets and M1 turns off.
When M1 turns off, DE reverts to a standard, high-
HotDꢁwapVCapability
Hot-Swap Input
When circuit boards are inserted into a hot or powered
backplane, differential disturbances to the data bus can
lead to data errors. Upon initial circuit board insertion, the
data communication processor undergoes its own power-
up sequence. During this period, the processor’s logic-
output drivers are high impedance and are unable to
drive the DE and RE inputs of the MAX306_E to a defined
logic level. Leakage currents up to 10µA from the high-
impedance state of the processor’s logic drivers could
cause standard CMOS enable inputs of a transceiver to
drift to an incorrect logic level. Additionally, parasitic cir-
impedance CMOS input. Whenever ꢀ
1ꢀ, the hot-swap input is reset.
drops below
CC
For RE, there is a complementary circuit employing two
PMOS devices pulling RE to ꢀ
.
CC
cuit board capacitance could cause coupling of ꢀ
or
CC
V
CC
GND to the enable inputs. Without the hot-swap capabili-
ty, these factors could improperly enable the transceiver’s
driver or receiver.
10μs
TIMER
SR LATCH
When ꢀ
rises, an internal pulldown circuit holds DE
CC
TIMER
low for at least 10µs and until the current into DE
exceeds 200µA. After the initial positive transition, the
pulldown circuit becomes transparent, resetting the
hot-swap tolerable input.
Hot-Swap Input Circuitry
These devices’ enable inputs feature hot-swap capabili-
ty. At the input there are two NMOS devices, M1 and M2
8kΩ
DE
DE
(HOT SWAP)
(Figure 10). When ꢀ
ramps from zero, an internal 10µs
CC
300μA
timer turns on M2 and sets the SR latch, which also turns
on M1. Transistors M2, a 300µA current sink, and M1, a
30µA current sink, pull DE to GND through an 8kΩ resis-
tor. M2 is designed to pull DE to the disabled state
against an external parasitic capacitance up to 100pF
that can drive DE high. After 10µs, the timer deactivates
M2 while M1 remains on, holding DE low against three-
state leakages that can drive DE high. M1 remains on
30μA
M1
M2
Figure 10. Simplified Structure of the Driver Enable Input (DE)
12 ______________________________________________________________________________________
1ꢀ5kVEꢁSD-Potected,VFailDꢁafe,V20Mbps,VꢁlewDRateD
LimitedVRꢁD48ꢀ/RꢁD422VTPansceivePsVinVaVꢁOT
Hot-Swap Line Transient
The circuit of Figure 11 shows a typical offset termina-
5V
tion used to guarantee a greater than 200mꢀ offset
when a line is not driven (the 50pF represents the mini-
V
0
CC
A
mum parasitic capacitance that would exist in a typical
application). During a hot-swap event when the driver
is connected to the line and is powered up, the driver
must not cause the differential signal to drop below
200mꢀ. Figures 12, 13, and 14 show the results of the
200mV/div
B
200mV/div
MAX3060E during power-up for three different ꢀ
CC
ramp rates (0.1ꢀ/µs, 1ꢀ/µs, and 10ꢀ/µs). The photos
238mV
20mV/div
A - B
show the ꢀ
ramp, the single-ended signal on each
CC
side of the 100Ω termination, as well as the differential
signal across the termination.
40μs/div
1ꢀ5kVEꢁSV-Potection
As with all Maxim devices, ESD-protection structures
are incorporated on all pins to protect against ESD
encountered during handling and assembly. The
MAX3060E family’s receiver inputs/driver outputs (A, ꢂ)
have extra protection against static electricity found in
normal operation. Maxim’s engineers developed state-
of-the-art structures to protect these pins against
15kꢀ ESD without damage. After an ESD event, the
devices continue working without latchup.
Figure 12. Differential Power-Up Glitch (0.1V/µs)
5V
V
CC
A
0
20mV/div
ESD protection can be tested in several ways. The
receiver inputs are characterized for protection to the
following:
B
20mV/div
•
•
15kꢀ using the ꢁuman ꢂody Model
238mV
20mV/div
A - B
7kꢀ using the Contact Discharge method specified
in IEC 1000-4-2 (formerly IEC 801-2)
2μs/div
•
7kꢀ using the Air-Gap Discharge method specified
in IEC 1000-4-2 (formerly IEC 801-2)
Figure 13. Differential Power-Up Glitch (1V/µs)
5.0V
5V
0
V
CC
A
1kΩ
V
CC
A
B
50mV/div
50mV/div
DI
50pF
0.1kΩ
1kΩ
B
V
OR GND
CC
238mV
20mV/div
A - B
200ns/div
Figure 11. Typical Offset Termination
Figure 14. Differential Power-Up Glitch (10V/µs)
______________________________________________________________________________________ 13
1ꢀ5kVEꢁSD-Potected,VFailDꢁafe,V20Mbps,VꢁlewDRateD
LimitedVRꢁD48ꢀ/RꢁD422VTPansceivePsVinVaVꢁOT
ESD Test Conditions
R
1MΩ
R
C
ESD performance depends on a number of conditions.
Contact Maxim for a reliability report that documents
test setup, methodology, and results.
D
1.5kΩ
DISCHARGE
RESISTANCE
CHARGE-CURRENT
LIMIT RESISTOR
Human Body Model
Figure 15a shows the ꢁuman ꢂody Model, and Figure
15b shows the current waveform it generates when dis-
charged into a low impedance. This model consists of
a 100pF capacitor charged to the ESD voltage of inter-
est, which is then discharged into the device through a
1.5kΩ resistor.
HIGH-
VOLTAGE
DC
DEVICE
UNDER
TEST
C
100pF
STORAGE
CAPACITOR
s
SOURCE
IEC 1000-4-2
The IEC 1000-4-2 standard covers ESD testing and per-
formance of finished equipment; it does not specifically
refer to integrated circuits.
Figure 15a. Human Body ESD Test Model
The main difference between tests done using the
ꢁuman ꢂody Model and IEC 1000-4-2 is higher peak
current in IEC 1000-4-2. ꢂecause series resistance is
lower in the IEC 1000-4-2 ESD test model (Figure 16), the
ESD withstand voltage measured to this standard is gen-
erally lower than that measured using the ꢁuman ꢂody
Model. The Air-Gap test involves approaching the
device with a charged probe. The Contact Discharge
method connects the probe to the device before the
probe is energized.
I 100%
P
90%
PEAK-TO-PEAK RINGING
(NOT DRAWN TO SCALE)
I
r
AMPERES
36.8%
10%
0
TIME
0
t
RL
t
DL
CURRENT WAVEFORM
Machine Model
The Machine Model for ESD testing uses a 200pF stor-
age capacitor and zero-discharge resistance. It mimics
the stress caused by handling during manufacturing
and assembly. All pins (not just RS-485 inputs) require
this protection during manufacturing. Therefore, the
Machine Model is less relevant to the I/O ports than are
the ꢁuman ꢂody Model and IEC 1000-4-2.
Figure 15b. Human Body Current Waveform
R
R
D
C
50MΩ to 100MΩ
330Ω
DISCHARGE
RESISTANCE
CHARGE-CURRENT
LIMIT RESISTOR
ApplicationsVInfoPmation
HIGH-
VOLTAGE
DC
DEVICE
UNDER
TEST
C
s
150pF
STORAGE
CAPACITOR
2ꢀ6VTPansceivePsVonVtheVBus
The standard RS-485 receiver input impedance is 12kΩ
(one-unit load), and the standard driver can drive up to
32-unit loads. The MAX3060E family of transceivers have
a 1/8-unit-load receiver input impedance (96kΩ), allow-
ing up to 256 transceivers to be connected in parallel on
one communication line. Any combination of these
devices and/or other RS-485 transceivers with a total of
32 unit loads or less can be connected to the line.
SOURCE
Figure 16. IEC 1000-4-2 ESD Test Model
ReducedVEMIVandVReflections
The MAX3060E and MAX3061E are slew-rate limited,
minimizing EMI and reducing reflections caused by
improperly terminated cables. Figure 17 shows the dri-
ver output waveform and its Fourier analysis of a 25kꢁz
signal transmitted by a MAX3062E. ꢁigh-frequency
harmonic components with large amplitudes are evi-
dent. Figure 18 shows the same signal displayed for a
MAX3061E transmitting under the same conditions.
14 ______________________________________________________________________________________
1ꢀ5kVEꢁSD-Potected,VFailDꢁafe,V20Mbps,VꢁlewDRateD
LimitedVRꢁD48ꢀ/RꢁD422VTPansceivePsVinVaVꢁOT
Figure 18’s high-frequency harmonic components are
much lower in amplitude, compared with Figure 17’s,
and the potential for EMI is significantly reduced. Figure
19 shows the same signal displayed for a MAX3060E
transmitting under the same conditions. Figure 19’s
high-frequency harmonic components are even lower.
In general, a transmitter’s rise time relates directly to the
20dB/div
length of an unterminated stub, which can be driven with
only minor waveform reflections. The following equation
expresses this relationship conservatively:
Length = t
/ (10 x 1.5ns/ft)
RISE
where t
is the transmitter’s rise time.
RISE
0
125kHz/div
1.25MHz
For example, the MAX3060E’s rise time is typically
1850ns, which results in excellent waveforms with a stub
length up to 123ft. A system can work well with longer
unterminated stubs, even with severe reflections, if the
waveform settles out before the UART samples them.
Figure 17. Driver Output Waveform and FFT Plot of MAX3062E
Transmitting a 25kHz Signal
LowD-owePVꢁhutdownVModeV
Low-power shutdown mode is initiated by bringing both
RE high and DE low. In shutdown, the devices typically
draw only 1nA of supply current.
RE and DE can be driven simultaneously. The parts are
guaranteed not to enter shutdown if RE is high and DE is
low for less than 50ns. If the inputs are in this state for at
least 600ns, the parts are guaranteed to enter shutdown.
20dB/div
Enable times t_
and t_
in the Switching Char-
ZL
Zꢁ
acteristics tables assume the part was not in a low-
power shutdown state. Enable times t_ and
Zꢁ(SꢁDN)
t_
assume the parts were shut down. It takes
ZL(SꢁDN)
0
125kHz/div
1.25MHz
drivers and receivers longer to become enabled from
low-power shutdown mode (t_ , t_
)
ZL(SꢁDN)
Zꢁ(SꢁDN)
Figure 18. Driver Output Waveform and FFT Plot of MAX3061E
Transmitting a 25kHz Signal
than from driver/receiver-disable mode (t_ , t_ ).
Zꢁ
ZL
SPivePVOutputV-Potection
Two mechanisms prevent excessive output current and
power dissipation caused by faults or by bus con-
tention. The first, a foldback current limit on the output
stage, provides protection after a 20µs delay against
short circuits over the whole common-mode voltage
range (see Typical Operating Characteristics). The sec-
ond, a thermal shutdown circuit, forces the driver out-
puts into a high-impedance state if the die temperature
becomes excessive.
20dB/div
0
125kHz/div
1.25MHz
Figure 19. Driver Output Waveform and FFT Plot of MAX3060E
Transmitting a 25kHz Signal
______________________________________________________________________________________ 15
1ꢀ5kVEꢁSD-Potected,VFailDꢁafe,V20Mbps,VꢁlewDRateD
LimitedVRꢁD48ꢀ/RꢁD422VTPansceivePsVinVaVꢁOT
120Ω
120Ω
DE
B
B
DI
D
D
DI
DE
B
A
A
B
A
A
RO
RE
RO
RE
R
R
R
R
D
D
MAX3060E/MAX3061E/
MAX3062E
(HALF-DUPLEX)
DI
DE
RO RE
DI
DE RO RE
Figure 20. Typical Half-Duplex RS-485 Network
TypicalVApplications
The MAX3060E family of transceivers are designed for
bidirectional data communications on multipoint bus
transmission lines. Figure 20 shows a typical network
application circuit.
ChipVInfoPmation
PROCESS: CMOS
To minimize reflections, the line should be terminated at
both ends in its characteristic impedance, and stub
lengths off the main line should be kept as short as
possible. The slew-rate-limited MAX3060E and
MAX3061E are more tolerant of imperfect termination.
16 ______________________________________________________________________________________
1ꢀ5kVEꢁSD-Potected,VFailDꢁafe,V20Mbps,VꢁlewDRateD
LimitedVRꢁD48ꢀ/RꢁD422VTPansceivePsVinVaVꢁOT
-ac5ageVInfoPmation
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/pacꢀages.)
MARKING
0
0
PACKAGE OUTLINE, SOT-23, 8L BODY
1
21-0078
G
1
RevisionVHistoPy
Pages changed at Rev 1: 1, 16, 17
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
MaximVIntegPatedV-Poducts,V120VꢁanVGabPielVSPive,Vꢁunnyvale,VCAVV94086V408D737D7600V ____________________ 17
© 2007 Maxim Integrated Products
is a registered trademark of Maxim Integrated Products, Inc.
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