MAX2741ETI [MAXIM]
Integrated L1-Band GPS Receiver; 集成L1波段GPS接收机
| 型号： | MAX2741ETI |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Integrated L1-Band GPS Receiver |
| 文件： | 总12页 (文件大小：238K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-3559; Rev 0; 1/05
Integrated L1-Band GPS Receiver
General Description
Features
The MAX2741 L1-band GPS receiver IC offers a high-
performance, compact solution for mobile handsets,
PDAs, and automotive applications. Total voltage gain
of 80dB and a 4.7dB cascaded noise figure can pro-
vide receiver sensitivity for applications requiring
-185dBW for indoor tracking solutions.
♦ Supports All Popular Handset Reference
Frequencies Up to 26MHz
♦ 4.7dB Cascaded Noise Figure
♦ 80dB Cascaded Gain
♦ Tolerates -90dBm In-Band Jammer
This dual-conversion receiver downconverts the
1575.42MHz GPS signal to a 37.38MHz first IF, and then
a 3.78MHz second IF. An integrated 2- or 3-bit ADC (1-
bit SIGN, 1- or 2-bit MAG selectable) samples the sec-
ond IF and outputs the digitized signals to the baseband
processor.
♦ Tolerates +13dBm CDMA Out-of-Band Jammer at
Device Input
♦ Integrated Synthesizer and VCO
♦ Integrated 2- or 3-Bit ADC
♦ 50dB IF AGC Range
The integrated synthesizer offers the flexibility in fre-
quency planning to allow a single board design to be
employed for reference frequencies from 2MHz to
26MHz. The integrated reference oscillator allows either
TCXO or crystal operation.
♦ Small 28-Pin Thin QFN Package
♦ SPI™ Control Interface
♦ Clock Output for Baseband Processor
The receiver runs from a 2.7V to 3.0V supply, and draws
only 30mA when active. It is offered in a 28-pin thin QFN
package, and is specified for -40°C to +85°C at 3V.
SPI is a trademark of Motorola, Inc.
Ordering Information
PART
TEMP RANGE
PIN-PACKAGE
MAX2741ETI
-40°C to +85°C
28 Thin QFN
x
Pin Configuration/
Functional Diagram
Applications
In-Vehicle Navigation Systems (IVNS)
Telematics (Vehicle and Asset Tracking,
Inventory Management)
28
27
26
25
24
23
22
Automotive Security
MAX2741
V
1
1
2
3
4
5
6
7
21 SDO
20 N.C.
CC
Emergency Response Systems
Emergency Road-Side Assistance
Location-Based Services/Internet (PDAs)
Digital Cameras/Camcorders
N.C.
33.6MHz
LNA
RFIN
19
V 5
CC
90
0
/96
1612.8MHz
/2
V
2
CC
3
CC
4
CC
18 GPSIF0
17 GPSIF1
16 GPSIF2
15 GPSCLK
/16128
ADC
Recreational Handhelds/Walkie-Talkies
Geographical Information Systems (GIS)
Consumer Electronics (Location-Based Games)
Precision Timing
P.D.
200kHz
V
V
VCO
3225.6MHz
/R
/192
MUX
16.8MHz
REF
OSC
SPI INTERFACE
10
GND
8
9
11
12
13
14
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
Integrated L1-Band GPS Receiver
ABSOLUTE MAXIMUM RATINGS
V
V
Pins to GND ...................................................-0.3V to +3.3V
Pins to Each Other.........................................-0.3V to +0.3V
Crystal Inputs to GND (XTAL, REFCLK).....-0.3V to (V
Maximum RF Input Power...................................................0dBm
+ 0.3V)
CC
CC
CC
FILT to GND................................................-0.3V to (V
CMOS Inputs to GND (SHDN, SCLK,
CS, SDI).................................................+0.3V to (V
CMOS Outputs to GND (CLKOUT,
GPSIF_, SDO).........................................-0.3V to (V
RFIN to GND...............................................-0.3V to (V
First IF Filter I/O to GND (IFOUT , IFIN ).....-0.3V to (V
+ 0.3V)
Continuous Power Dissipation (T = +85°C)
CC
A
28-Pin Thin QFN (derate 20.8mW/°C above +70°C) .1000mW
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range.............................-65°C to +160°C
Lead Temperature (soldering, 10s) .................................+300°C
+ 0.3V)
CC
+ 0.3V)
+ 0.3V)
+ 0.3V)
CC
CC
CC
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
CAUTION! ESD SENSITIVE DEVICE
DC ELECTRICAL CHARACTERISTICS
(Operating conditions (unless otherwise specified): V
= 2.7V to 3.0V; REFCLK driven with 10MHz sinusoid, 1.2V ; registers set
P-P
CC
according to mode; no RF input signal; digital baseband outputs left open; T = -40°C to +85°C. Typical values are measured at V
=
A
CC
2.75V, T = +25°C.)
A
PARAMETER
CONDITIONS
MIN
TYP
MAX
3.0
UNITS
Supply Voltage
2.7
V
Normal operation (T = +25°C)
30
42
A
Supply Current
mA
V
Standby (V
= V , SYNTH:D8 = 0)
0.7
SHDN
IL
V
0.1
-
-
CC
Input-Logic High Threshold
Input-Logic Low Threshold
0.1
V
Input-Logic High/Low Current
-10
+10
µA
V
0.3
CC
Output-Logic High
Output-Logic Low
I
I
= 100µA
V
V
LOAD
LOAD
= 100µA
0.3
AC ELECTRICAL CHARACTERISTICS
(Operating conditions (unless otherwise specified): V
= 2.7V to 3.0V for T = -40°C to +85°C; REFCLK driven at 10MHz sinusoid,
CC
A
1.2V ; registers set according to mode; using the Typical Application Circuit; CW RF signal at 1575.42MHz. Typical values are mea-
P-P
sured at V = 2.75V, T = +25°C.)
CC
A
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
1st CONVERSION STAGE (RF TO 1st IF)
RF Frequency
L1-band
(Note 1)
1575.42
21
MHz
dB
RF Conversion Gain
Noise Figure
15
32
Mid-gain (CONFIG1:D4–D0 = 10000)
(Note 2)
4.7
dB
Input IP3
-30
dBm
dB
RF Image Rejection
LO Leakage at RF
(Notes 3, 4)
20
35
LO to RFIN pin
-90
dBm
2
_______________________________________________________________________________________
Integrated L1-Band GPS Receiver
AC ELECTRICAL CHARACTERISTICS (continued)
(Operating conditions (unless otherwise specified): V
= 2.7V to 3.0V for T = -40°C to +85°C; REFCLK driven at 10MHz sinusoid,
CC
A
1.2V ; registers set according to mode; using the Typical Application Circuit; CW RF signal at 1575.42MHz. Typical values are mea-
P-P
sured at V = 2.75V, T = +25°C.)
CC
A
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
2nd CONVERSION STAGE (1st IF TO ADC INPUT)
1st IF Frequency
At IFOUT
37.38
61
MHz
dB
Max gain (CONFIG1:D4–D0 = 11111) (Note 1)
Min gain (CONFIG1:D4–D0 = 00000) (Note 1)
1st conversion (Note 5)
Max gain (CONFIG1:D4–D0 = 11111)
Real
48
74
Conversion Gain
10
dB
Input IP3
-36
12
dBm
dB
Noise Figure
0.40
1.5
mS
pF
IF Output Port Admittance
IF Input Port Admittance
Imaginary
Real
0.40
0.15
2.9
mS
pF
Imaginary
(SYNTH:D13–D10 = 1111)
(SYNTH:D13–D10 = 0000)
LPF -3dB Corner Frequency
MHz
7.7
SYNTHESIZER
I
I
PLL charge-pump source current
PLL charge-pump sink current
At 1kHz offset
75
-100
-55
-44
10
µA
µA
CP_OH
CP_OL
Closed-Loop Phase Noise
Comparison Spurs
dBc/Hz
dBc/Hz
MHz
At 200kHz offset
Reference Oscillator Frequency
REF Input Voltage Level
Sinusoid (Note 1)
2
26
Sinusoid (Note 1)
0.6
2.2
V
P-P
Programmable (CONFIG1:D7 to D5 = 000 to 111)
(Note 1)
VCO Coarse Tune Range
240
1
MHz
MHz
DIGITAL I/O
SPI Clock Frequency
Note 1: Production tested for +25°C and +85°C, guaranteed by design and characterization for -40°C.
Note 2: Test tones at 1575.8MHz and 1576.8MHz at -60dBm/tone.
Note 3: Guaranteed by design and characterization.
Note 4: Image frequency is 1575.42MHz + 2(f ) = 1650.18MHz
IF
Note 5: Test tones at 37.38MHz and 36.88MHz at -50dBm/tone.
_______________________________________________________________________________________
3
Integrated L1-Band GPS Receiver
Pin Description
PIN
1
NAME
FUNCTION
LNA Supply Connection. External RF bypass capacitor to ground required.
Reserved. Make no connections to this pin.
V
1
CC
2, 20, 22, 23
N.C.
LNA Input. Connect to GPS antenna through a bandpass filter. This input requires an external
matching network to match to 50 . AC-couple to this pin.
3
RFIN
4
5
6
7
V
V
V
2
3
4
VCO Supply Connection. External RF bypass capacitor to ground required.
CML Supply Connection. External RF bypass capacitor to ground required.
Digital Logic and PLL Supply Connection. External RF bypass capacitor to digital ground required.
Ground. Connect to PC board digital ground plane.
CC
CC
CC
GND
PLL Loop Filter Connection. This is the output of the phase detector’s charge pump. Use the
recommended filter on EV kit for optimal phase noise and lock time.
8
FILT
9
SCLK
CS
SPI Clock Input (CMOS)
10
11
SPI Chip-Select Input (CMOS, Active Low)
SPI Data Input (CMOS)
SDI
Full IC Power-Down. This shutdown pin disables the on-chip oscillator and the rest of the IC. To keep
the oscillator running, use the software shutdown (SYNTH:D8); (CMOS, active high).
12
SHDN
13
14
15
16
17
18
19
21
24
XTAL
Crystal Oscillator Feedback Capacitor Connection
REFCLK
GPSCLK
GPSIF2
GPSIF1
GPSIF0
Reference Clock Input for PLL. Drive with 1.2V
when using TCXO module.
P-P
GPS Clock Output to Baseband. This is the clock used by the ADC to sample the GPS data (CMOS).
Sampled IF Output, Bit 2 (CMOS). See Table 5.
Sampled IF Output, Bit 1 (CMOS). See Table 5.
Sampled IF Output, Bit 0 (CMOS). See Table 5.
V
5
CC
IF Supply Connection. External RF bypass capacitor to ground required.
SPI Data Output (CMOS)
SDO
IFIN-
1st IF Input (Inverting). Connect this 2.5k differentially terminated input to the 1st IF filter’s (-) output.
1st IF Input (Noninverting). Connect this 2.5k differentially terminated input to the 1st IF filter’s (+)
output.
25
IFIN+
26
27
IFOUT-
1st IF Output (Inverting). Connect this 2.4k differential output to the 1st IF filter’s (-) input.
1st IF Output (Noninverting). Connect this 2.4k differential output to the 1st IF filter’s (+) input.
RF Image-Reject Mixer Supply. External RF bypass capacitor to ground required.
IFOUT+
28
V
6
CC
Exposed
GND
RF Ground. Ultra-low inductance connection to ground. Place several vias to PC board ground plane.
4
_______________________________________________________________________________________
Integrated L1-Band GPS Receiver
DC offset compensation at the ADC input is performed by
Detailed Description
an on-chip 4-bit DAC. This compensates for any DC error
introduced by transistor mismatch in the differential stage
driving the ADC input, allowing the downconverted GPS
signal’s DC level to be centered within the threshold volt-
ages of the ADC.
The MAX2741 GPS offers a high-performance super-
heterodyne receiver solution for low-power mobile
devices, with the benefit of using the system’s existing
clock reference. This receiver is ideal for integration into
mobile phone handsets using common reference fre-
quencies such as 10.0, 13.0, 14.4, 19.2, 20.0, and
26.0MHz. The only external components required are the
GPS RF filter, an IF filter (typically designed from inexpen-
sive discretes), a three-component PLL loop filter, and a
few other resistors and capacitors. The MAX2741 inte-
grates the reference oscillator core, the VCO and its tank,
the synthesizer, a 1- to 3-bit ADC, and all signal path
blocks except for the 1st IF filter. The typical application
area for the receiver is less than 2cm2.
ADC
The on-chip ADC samples the down-converted GPS
signal at the 2nd IF (3.78MHz). Sampled output is pro-
vided in either 2-bit (1-bit magnitude, 1-bit sign) or 3-bit
(2-bit magnitude, 1-bit sign) formats, as determined by
the ADC mode configuration bit (CONFIG1:D15); see
Table 5 for details. The ADC sample clock (system GPS
clock) is derived either directly from the reference clock
(SYNTH:D9 = 1), or from an RFLO divide-by-96 block to
provide a 16.8MHz sample clock (SYNTH:D9 = 0). The
clock is available to the baseband processor at
GPSCLK (pin 15). The sampled ADC data bits are
available on pins 16, 17, and 18 (GPSIF2, GPSIF1, and
GPSIF0). The functionality of the pins is different in
each mode (2-bit vs. 3-bit)—see Table 5 in determining
the interface connection for the application circuit.
RF/1st Conversion Stage (Front-End)
The MAX2741 RF front-end LNA and mixer are the most
important in the signal path. This stage sets the noise
figure for the receiver, defining the sensitivity, and mixes
the 1575.42MHz L1-band GPS signal down to a 1st IF of
37.38MHz. The LNA itself has an NF of approximately
1.5dB; the cascaded NF of the front-end (including the
mixer) is approximately 4.7dB, and the cascaded gain
is typically 21dB.
Synthesizer
The MAX2741 integrates an integer-N synthesizer; all
blocks except the loop filter are on-chip. The reference
can be either a crystal (driven by the internal oscillator),
or a TCXO module. The oscillator provides a 5pF load
to the crystal. A TCXO module should provide a swing
The image-reject mixer is set up for a high-side injected
RFLO (1612.80MHz), and offers typically better than 30dB
rejection of the image noise (1650.18MHz). The -30dBm
input 3rd-order intercept (IIP3) of the RF strip, in conjunc-
tion with the GPS IF filter, provides excellent out-of-band
interferer immunity.
in the 0.6V
to 2.2V
range.
P-P
P-P
The reference divider (/R) is programmable (SYNTH:
D7–D0), and can accommodate reference frequencies
up to 26MHz. The reference divider needs to be set so
The 1st IF outputs (IFOUT ) are internally biased to
approximately 2V, and have a differential source
impedance of approximately 2.5k . The IF filter can be
implemented as a discrete L/C filter, or as a monolithic
SAW or ceramic if one is available.
the comparison frequency (f
) at the frequency/
COMP
phase detector is 200kHz. The VCO runs at twice the fre-
quency of the RFLO; the RFLO is therefore generated
from the VCO using a quadrature divide-by-2 block. The
IF/2nd Conversion Stage
The 2nd conversion stage consists of an active mixer, a
variable-gain amplifier (VGA), and a tunable lowpass
filter. The IF mixer is configured for low-side LO injec-
tion for a 2nd IF of 3.78MHz. Total gain in this stage is
62dB, and the VGA offers 51dB of gain adjustment. The
VGA is typically controlled by the baseband IC through
the SPI interface to optimize the signal swing for digiti-
zation by the ADC.
RF LO is f
x 8064 (typically 1612.80MHz), and the
COMP
COMP
1st IF LO is f
x 168 (typically 33.6MHz); the RF and
IF LO division ratios are not adjustable. This configuration
allows for the use of reference frequencies common to
GSM, CDMA, TDMA, TD-SCDMA, and UMTS handsets:
9.6MHz (R = 48), 13.0MHz (R = 65), 14.4MHz (R = 72),
19.2MHz (R = 96), 26.0MHz (R = 130), etc.
The on-chip lowpass filter has an adjustable cutoff fre-
quency, programmable from 2.9MHz to 7.7MHz in 16
steps. This LPF further reduces out-of-band noise and
band-limits the signal to the ADC, ensuring that the
sampling process does not generate alias components.
_______________________________________________________________________________________
5
Integrated L1-Band GPS Receiver
SPI Bus, Address and Bit Assignments
An SPI-compatible serial interface is used to program the
MAX2741 for configuring the different operating modes.
In addition, data can be read out of the MAX2741 for sta-
tus and diagnostic use. The serial interface is controlled
by four signals: SCLK (serial clock), CS (chip-select), SDI
(data input), and SDO (data output).
MAX2741
V
4
CC
6
7
GND
8
9
The control of the PLL, AGC, test, offset management,
and block selection is performed through the SPI bus
from the baseband controller. A 20-bit word, with the MSB
(D15) being sent first, is clocked into a serial shift register
when the chip-select signal is asserted low.
22nF
36k
100pF
The SPI bus has four control lines: serial clock (SCLK),
chip-select (CS), data in (SDI), and data out (SDO).
Enable SDO functionality by setting the digital test bus
bits: CONFIG1:D9 to D8 = 01. The timing of the inter-
face signals is shown in Figure 2 and Table 1 along
with typical values for setup and hold time require-
ments.
Figure 1. Recommended 3rd-Order PLL Filter
The VCO offers a bank of tuning capacitors that can be
latched in/out to adjust the center frequency. Because
the system does not require any RF LO frequency
change (i.e., changing channels), the VCO varactor tun-
ing gain is very low by design, which means the tuning
range of the VCO is narrow. The coarse-tune capacitors
in the tank circuit allow the system to adjust the VCO
center frequency as needed to guarantee that the syn-
thesizer can lock. In practice, process and temperature
effects on VCO centering are negligible, and a coarse-
tune setting of 110 (CONFIG:D7 to D5) will center the
VCO tuning range correctly in virtually all cases. To aid in
bench and prototype testing, the PFD offers out-of-lock-
high and out-of-lock-low indicators, available in the SPI
STATUS register (STATUS:D9 to D8). Use these flags to
determine if the VCO tuning range needs to be adjusted
higher or lower in the case where the PLL cannot lock.
For best performance, the SPI bus should be configured
during the startup initialization and then left with the opti-
mum values in the registers. Any changes to the ADC
and VGA bits during GPS signal processing may cause
glitches and corrupt the analog signal path. Reading
from the SPI bus does not interrupt GPS operation.
t
SETUPSS
CS
t
END
t
SETUPD
SCLK
SDI
t
HDATA
t
PERIOD
MSB
LSB
The PLL filter is the only external block of the synthesizer.
The typical filter is a classic C-R-C two-pole shunt network
on the tune line. Low phase noise is preferred at the
expense of longer PLL settling times, so a low 10kHz to
20kHz loop bandwidth is used. The recommended PLL
10kHz filter implementation, with charge pump set to
200µA (CONFIG1:D10 = 1), is shown in Figure 1.
Figure 2. SPI Timing Diagram
Table 1. SPI Timing Requirements
TYP
VALUE
SYMBOL
PARAMETER
UNITS
t
t
t
t
t
Data to SCLK setup
SCLK period
20
100
20
ns
ns
ns
ns
ns
SETUPD
PERIOD
HDATA
SETUPSS
END
The system/GPS clock is derived either directly from
the reference oscillator, or synthesized from the RFLO
(see the ADC section). This clock is used as the sam-
pling clock for the on-chip ADC, and is seen at pin 15,
GPSCLK.
Data hold to SCLK
CS to SCLK disable
Falling SCLK to CS inactive
20
20
6
_______________________________________________________________________________________
Integrated L1-Band GPS Receiver
Table 2. Register Address and Data Bit Assigments (Write)
DATA
D8 D7
ADDRESS
REGISTER
NAME
D15 D14 D13 D12 D11 D10 D9
D6
D5
D4
D3
D2
D1
D0 A3 A2 A1 A0
SYNTH
0
0
0
1
1
1
0
0
1
0
1
0
CONFIG 1
CONFIG 2
Table 3. Register Address and Data Bit Assigments (Read)
DATA
D8 D7
ADDRESS
D0 A3 A2 A1 A0
REGISTER
NAME
D15 D14 D13 D12 D11 D10 D9
D6
D5
D4
D3
D2
D1
STATUS
0
1
1
1
_______________________________________________________________________________________
7
Integrated L1-Band GPS Receiver
Detailed Register Definitions
Table 4. Detailed Register Definition for Write Address 0100: SYNTH
DATA BIT
D15
DEFAULT
DESCRIPTION
1
1
Reserved
D14
LPF Autotune Initiate: I = Initiate autotune, 0 = Manual tuning.
D13–D10
D9
0100
1
LPF Tuning Word: 0000 ~ 7.7MHz, 1111 ~ 2.9MHz.
XTAL Clock Select: 1 = External reference, 0 = Synthesized 16.8MHz.
Standby: 0 = Normal operating mode, 1 = Standby (oscillator remains active), but only if D9 = 1.
D8
0
D7–D0
01100000 Reference Division Ratio. Default 19.2MHz external reference (R = 96dec). R = f
/ 200kHz.
REF
Table 5. Detailed Register Definition for Write Address 0101: CONFIG 1
DATA BIT
DEFAULT
DESCRIPTION
ADC Mode. Select 1 for 1-bit magnitude and sign, select 0 for 2-bit magnitude and sign.
1: GPSIF2 = sign, GPSIF1 = magnitude, GPSIF0 = X
D15
1
0: GPSIF2 = MSB magnitude, GPSIF1 = LSB magnitude, GPSIF0 = sign
D14–D11
D10
0000
0
ADC Offset Control (approx 4mV/step): D14 = LSB, D12 = MSB, D11 = sign.
Double Charge-Pump Current: 0 = 100µA, 1 = 200µA.
D9 to D8
D7 to D5
00
Digital Test Bus Mode Select. See Table 9 for test-mode descriptions.
VCO Coarse Tuning Range. 000 = Lowest frequency, 111 = Highest frequency.
001
AGC Gain. Digital control of the AGC amplifier in the 2nd IF section. 00000 => min gain, 11111 =>
max gain (linear gain ~2.5dB per unit SPI word).
D4–D0
11111
Table 6. Detailed Register Definition for Write Address 0110: CONFIG 2
DATA BIT
DEFAULT
DESCRIPTION
D15
1
Reset CMOS: 0 = Hold CMOS dividers in reset and PFD is tri-stated, 1 = Inactive.
Drive VCO Low: 0 = Active, forces VCO to lowest frequency.
N.B. do not activate both D14 and D13 at the same time.
D14
D13
1
1
Drive VCO High: <forces LCP low FET on, driving V
low, forcing VCO to highest extreme> 0 =
TUNE
Active, forces VCO to highest frequency. N.B. do not activate both D14 and D13 at the same time.
D12–D7
D6 to D5
D4–D0
100000
11
Reserved
Must be programmed to 11
Analog Test Mode Select: Reserved
11111
8
_______________________________________________________________________________________
Integrated L1-Band GPS Receiver
Table 7. Detailed Register Definition for Read Address 0111: STATUS
DATA BIT
DEFAULT
DESCRIPTION
D15–D10
XXXXXX
Reserved
Out-of-Lock (High Frequency): 1 = PLL is out of lock, VCO free-running at its highest frequency,
0 = Locked.
D9
D8
X
X
Out-of-Lock (Low Frequency): 1 = PLL is out of lock, VCO free-running at its lowest frequency,
0 = Locked high.
D7
D6
1
X
XTAL Clock Selected: 1 = Synthesized 16.8MHz reference, 0 = External clock.
Parity: 1 = Even, 0 = Odd.
D5
X
Reserved
D4
X
LPF Autotune End: 0 = Autotune run ended; 1 = Calibrating or manual tuning.
LPF Autotune: 0000 ~ 7.7MHz; 1111 = 2.9MHz.
D3–D0
XXXX
Applications Information
Table 8. MAX2741 S11
Fundamentally, the only application areas that require
careful consideration are the LNA input match and the
1st IF filter. Of course, proper supply bypassing,
grounding, and layout is required for reliable perfor-
mance from any RF circuit.
FREQ (MHz)
1100
1200
1300
1400
1500
1550
1560
1570
1575
1580
1590
1600
1650
1700
1800
1900
2000
S11 (MAG)
S11 (°)
-50.9
-56.1
-61.5
-66.9
-72.3
-74.9
-75.4
-75.9
-76.2
-76.4
-77.0
-77.5
-80.0
-82.5
-87.4
-92.3
-96.8
0.874
0.867
0.859
0.842
0.821
0.809
0.806
0.804
0.803
0.801
0.799
0.796
0.783
0.768
0.739
0.708
0.677
LNA Input Matching
Input matching is critical for optimum noise figure and
system sensitivity. Optimum source impedance (as seen
from the LNA input) for lowest noise figure is 29 + j47 .
Remember that optimum noise match and optimum gain
match (return loss) do not occur simultaneously, so a
good application circuit will sacrifice gain slightly in favor
of reduced noise figure. Gain and noise circles are pro-
vided in Figure 3; S11 tabular data is provided in Table 8.
G = Gmax - 1dB
NF = NFmin + 0.2dB
1st IF Interface and Filtering
The typical application uses a 37.38MHz 1st IF, and
employs an IF filter. The order of the filter should be tai-
lored to suit the application—stand-alone GPS
receivers will not require the channel-selection and
stopband attenuation of GPS receivers that are inte-
grated into other wireless handsets. Be sure that the fil-
ter topology provides DC-blocking for the IF I/O ports.
Figure 3. Gain and Noise Circles for MAX2741 LNA Input
_______________________________________________________________________________________
9
Integrated L1-Band GPS Receiver
Typical Interface Diagram
28 27 26 25 24 23 22
BASEBAND IC
SDO
V
1
SDO
N.C.
CC
1
2
3
4
5
6
7
21
20
19
18
17
16
15
N.C.
SD1
RFIN
V 5
CC
CS
V
V
V
2
CC
3
CC
4
CC
GPSIF0
GPSIF1
GPSIF2
GPSCLK
SCLK
MAX2741
GPSIF0
GPSIF1
GPSIF2
GPSCLK
REFCLK
GND
8
9
10 11 12 13 14
Interface Summary
All I/O connections are DC-coupled. Supply voltages as specified in the electrical specifications.
RF
I/O CONNECTION
RECEIVER
RF BPF
RFIN
LNA Input
RF BPF Output
IF
RECEIVER
I/O CONNECTION
IFOUT+
IF FILTER
1st IF Output from Mixer (+)
1st IF Output from Mixer (-)
1st IF Input (+)
IF BPF Input, 2.5k Differential
IF BPF Input, 2.5k Differential
IF BPF Input, 2.5k Differential
IF BPF Input, 2.5k Differential
IFOUT-
IFIN+
IFIN-
1st IF Input (-)
BASEBAND
RECEIVER
I/O CONNECTION
SCLK
BB IC/MAC
CMOS Output
CMOS Output
CMOS Output
CMOS Input
CMOS Input
CMOS Input
CMOS Input
CMOS Output
CMOS Input
CMOS Output
CMOS Output
CMOS Output
CMOS Output
CS
SDI
SDO
SHDN
CMOS Output
CMOS Input
GPSCLK
GPSIF0
GPSIF1
GPSIF2
CMOS Input
CMOS Input
CMOS Input
SYNTHESIZER
RECEIVER
I/O CONNECTION
FILT
EXTERNAL COMPONENTS
PLL Phase-Detector Charge-Pump
Crystal Oscillator Feedback
External TCXO or Crystal
PLL Loop Filter
XTAL
Feedback Capacitors
REFCLK
Analog (also connected to REFCLK input to MAC)
10 ______________________________________________________________________________________
Integrated L1-Band GPS Receiver
Typical Application Circuit
680pF
5.6pF
470
680pF
V
CC
39pF
470
H
H
39pF
100pF
22pF
680pF
5.6pF
680pF
28
27
26
25
24
23
22
V
1
SDO
N.C.
CC
SPI DATA OUT
MAX2741
V
1
2
3
4
5
6
7
21
20
19
18
17
16
15
CC
TO BASEBAND PROCESSOR
100pF
22pF
N.C.
33.6MHz
/96
100pF
6.2nH
RFIN
LNA
V 5
CC
GPS RF INPUT
FROM GPS BPF
V
CC
90
0
2.2pF
100pF
1nF
1612.8MHz
/2
V
CC
V
CC
V
CC
2
3
4
GPSIF0
GPSIF1
GPSIF2
GPSCLK
V
CC
/16128
200kHz
ADC
100pF
100nF
22pF
P.D.
/R
V
CC
CC
VCO
3225.6MHz
GPS DATA AND CLOCK
TO BASEBAND PROCESSOR
1nF
100pF
/192
MUX
16.8MHz
V
100pF
GND
REF
OSC
SPI INTERFACE
10
8
9
11
12
13
14
22nF
220pF
100pF
36k
SPI CLOCK AND DATA INTO
BASEBAND PROCESSOR
SYSTEM TCXO
(2MHz TO 26MHz)
H/W SHUTDOWN LINE
FROM BASEBAND PROCESSOR
Table 9. Digital Test-Mode-Select Description
DIGITAL OUTPUT FUNCTION
GPSIF1
REGISTER SETTING
MODE
CONFIG1:D9 to D8
GPSIF2
SIGN
GPSIF0
3
2
1
0
11
10
01
00
LSB
MSB
M COUNTER
CHARGE PUMP UP
CML CLOCK
R COUNTER
HANDSHAKE STATUS
SDO
CHARGE PUMP DOWN
CALIBRATE LPF END
XTL CLOCK SELECTED
Digital Test Bus
The digital test bus (DTB) is provided to allow for easy
bench analysis of the digital workings of the receiver.
______________________________________________________________________________________ 11
Integrated L1-Band GPS Receiver
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
D2
D
b
0.10 M
C A B
C
L
D2/2
D/2
k
L
MARKING
XXXXX
E/2
E2/2
C
(NE-1) X
e
L
E2
E
PIN # 1 I.D.
0.35x45∞
DETAIL A
e
PIN # 1
I.D.
(ND-1) X
e
DETAIL B
e
L
C
C
L
L1
L
L
L
e
e
0.10
C
A
0.08
C
C
A3
A1
PACKAGE OUTLINE,
16, 20, 28, 32L THIN QFN, 5x5x0.8mm
1
-DRAWING NOT TO SCALE-
21-0140
G
2
COMMON DIMENSIONS
20L 5x5 28L 5x5
EXPOSED PAD VARIATIONS
D2 E2
MIN. NOM. MAX. MIN. NOM. MAX. ±0.15
DOWN
BONDS
ALLOWED
L
PKG.
SYMBOL MIN. NOM. MAX. MIN. NOM. MAX. MIN. NOM. MAX. MIN. NOM. MAX.
16L 5x5
32L 5x5
PKG.
CODES
T1655-1
T1655-2
3.00 3.10 3.20 3.00 3.10 3.20
3.00 3.10 3.20 3.00 3.10 3.20
NO
YES
NO
A
**
**
**
**
0.70 0.75 0.80 0.70 0.75 0.80 0.70 0.75 0.80 0.70 0.75 0.80
0.02 0.05 0.02 0.05 0.02 0.05 0.02 0.05
0.20 REF. 0.20 REF. 0.20 REF. 0.20 REF.
A1
0
0
0
0
T1655N-1 3.00 3.10 3.20 3.00 3.10 3.20
A3
b
T2055-2
T2055-3
T2055-4
T2055-5
3.00 3.10 3.20 3.00 3.10 3.20
3.00 3.10 3.20 3.00 3.10 3.20
3.00 3.10 3.20 3.00 3.10 3.20
NO
YES
NO
Y
0.25 0.30 0.35 0.25 0.30 0.35 0.20 0.25 0.30 0.20 0.25 0.30
4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10
4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10
**
**
D
E
3.15 3.25 3.35 3.15 3.25 3.35 0.40
e
0.80 BSC.
0.25
0.30 0.40 0.50 0.45 0.55 0.65 0.45 0.55 0.65 0.30 0.40 0.50
0.65 BSC.
0.50 BSC.
0.50 BSC.
T2855-1
T2855-2
3.15 3.25 3.35 3.15 3.25 3.35
2.60 2.70 2.80 2.60 2.70 2.80
NO
NO
**
**
**
**
k
-
-
0.25
-
-
0.25
-
-
0.25
-
-
L
T2855-3
T2855-4
3.15 3.25 3.35 3.15 3.25 3.35
2.60 2.70 2.80 2.60 2.70 2.80
2.60 2.70 2.80 2.60 2.70 2.80
3.15 3.25 3.35 3.15 3.25 3.35
YES
YES
NO
L1
-
-
-
-
-
-
-
-
-
-
-
-
N
ND
16
4
20
5
28
7
32
8
T2855-5
T2855-6
T2855-7
T2855-8
**
**
**
NO
YES
4
5
7
8
NE
2.80
3.35
3.35
3.20
2.60 2.70
3.15 3.25
2.60 2.70 2.80
3.15 3.25 3.35
3.15 3.25 3.35
3.00 3.10 3.20
WHHB
WHHC
WHHD-1
WHHD-2
JEDEC
0.40
Y
N
NO
T2855N-1 3.15 3.25
**
**
**
NOTES:
T3255-2
T3255-3
T3255-4
3.00 3.10
1. DIMENSIONING & TOLERANCING CONFORM TO ASME Y14.5M-1994.
2. ALL DIMENSIONS ARE IN MILLIMETERS. ANGLES ARE IN DEGREES.
3. N IS THE TOTAL NUMBER OF TERMINALS.
3.00 3.10 3.20 3.00 3.10 3.20
3.00 3.10 3.20 3.00 3.10 3.20
YES
NO
**
**
NO
T3255N-1 3.00 3.10 3.20 3.00 3.10 3.20
4. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL
CONFORM TO JESD 95-1 SPP-012. DETAILS OF TERMINAL #1 IDENTIFIER ARE
OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE TERMINAL #1
IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE.
**SEE COMMON DIMENSIONS TABLE
5. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.25 mm AND 0.30 mm
FROM TERMINAL TIP.
6. ND AND NE REFER TO THE NUMBER OF TERMINALS ON EACH D AND E SIDE RESPECTIVELY.
7. DEPOPULATION IS POSSIBLE IN A SYMMETRICAL FASHION.
8. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS.
9. DRAWING CONFORMS TO JEDEC MO220, EXCEPT EXPOSED PAD DIMENSION FOR T2855-1,
T2855-3 AND T2855-6.
10. WARPAGE SHALL NOT EXCEED 0.10 mm.
11. MARKING IS FOR PACKAGE ORIENTATION REFERENCE ONLY.
12. NUMBER OF LEADS SHOWN ARE FOR REFERENCE ONLY.
PACKAGE OUTLINE,
16, 20, 28, 32L THIN QFN, 5x5x0.8mm
2
-DRAWING NOT TO SCALE-
21-0140
G
2
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
12 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2005 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products, Inc.
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