MAX2316EEI [MAXIM]
CDMA IF VGAs and I/Q Demodulators with VCO and Synthesizer; CDMA IF VGA及I / Q解调器，带有VCO及合成器
| 型号： | MAX2316EEI |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | CDMA IF VGAs and I/Q Demodulators with VCO and Synthesizer |
| 文件： | 总22页 (文件大小：334K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-1507; Rev 1; 3/03
CDMA IF VGAs and I/Q Demodulators
with VCO and Synthesizer
General Description
Features
The MAX2310/MAX2312/MAX2314/MAX2316 are IF
receivers designed for dual-band, dual-mode, and sin-
gle-mode N-CDMA and W-CDMA cellular phone sys-
tems. The signal path consists of a variable gain
amplifier (VGA) and I/Q demodulator. The devices fea-
ture guaranteed +2.7V operation, a dynamic range of
over 110dB, and high input IP3 (-33dBm at 35dB gain,
1.7dBm at -35dB).
ꢀ Complete IF Subsystem Includes VCO and
Synthesizer
ꢀ Supports Dual-Band, Triple-Mode Operation
ꢀ VGA with >110dB Gain Control
ꢀ Quadrature Demodulator
ꢀ High Output Level (2.7V)
Unlike similar devices, the MAX2310 family of receivers
includes dual oscillators and synthesizers to form a
self-contained IF subsystem. The synthesizer’s refer-
ence and RF dividers are fully programmable through a
3-wire serial bus, enabling dual-band system architec-
tures using any common reference and IF frequency.
The differential baseband outputs have enough band-
width to suit both N-CDMA and W-CDMA systems, and
offer saturated output levels of 2.7Vp-p at a low +2.75V
supply voltage. Including the low-noise voltage-con-
trolled oscillator (VCO) and synthesizer, the MAX2310
draws only 26mA from a +2.75V supply in CDMA (dif-
ferential IF) mode.
ꢀ Programmable Charge-Pump Current
ꢀ Supports Any IF Frequency Between 40MHz and
300MHz
ꢀ 3-Wire Programmable Interface
ꢀ Low Supply Voltage (+2.7V)
Ordering Information
PART
TEMP RANGE
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
PIN-PACKAGE
28 QSOP
The MAX2310/MAX2312/MAX2314/MAX2316 are avail-
able in 28-pin QSOP packages.
MAX2310EEI
MAX2312EEI
MAX2314EEI
MAX2316EEI
28 QSOP
28 QSOP
Applications
Single/Dual/Triple-Mode CDMA Handsets
Globalstar Dual-Mode Handsets
Wireless Data Links
28 QSOP
Pin Configurations appear at end of data sheet.
Block Diagram appears at end of data sheet.
Tetra Direct-Conversion Receivers
Wireless Local Loop (WLL)
Selector Guide
PART
MODE
DESCRIPTION
INPUT RANGE
AMPS,
MAX2310
Cellular CDMA,
PCS CDMA
Dual Band, Triple Mode
40MHz to 300MHz
MAX2312
MAX2314
PCS CDMA
Single Band, Single Mode
Single Band, Dual Mode
67MHz to 300MHz
40MHz to 150MHz
AMPS,
Cellular CDMA
Single Band, Single Mode or
Single Band, Dual Mode with
External Discriminator
MAX2316
Cellular CDMA
40MHz to 150MHz
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
CDMA IF VGAs and I/Q Demodulators
with VCO and Synthesizer
ABSOLUTE MAXIMUM RATINGS
CC
SHDN to GND.............................................-0.3V to (V + 0.3V)
STBY, BUFEN, MODE, EN, DATA,
V
to GND..............................................................-0.3V, +6.0V
Digital Input Current SHDN, MODE, DIVSEL,
BUFEN, DATA, CLK, EN, STBY..................................... 10mA
CC
Continuous Power Dissipation (T = +70°C)
A
CLK, DIVSEL ...........................................-0.3V to (V
VGC to GND...............-0.3V, the lesser of +4.2V or (V
+ 0.3V)
+ 0.3V)
28-pin QSOP (derate 10mW/°C above T = +70°C) ....800mW
A
CC
CC
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range.............................-65°C to +160°C
Lead Temperature (soldering, 10s) .................................+300°C
AC Signals TankH , TankL
,
REF, FM , CDMA .................................................1.0V peak
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
CC
registers set to default power-up settings. Typical values are at V
(V
= +2.7V to +5.5V, MODE = DIVSEL = SHDN = STBY = BUFEN = high, differential output load = 10kΩ, T = -40°C to +85°C,
A
= +2.75V and T = +25°C, unless otherwise noted.)
A
CC
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
37.5
41.5
36.7
40.6
35.7
39.5
18.8
20.7
18.4
20.3
UNITS
T
A
T
A
T
A
T
A
T
A
T
A
T
A
T
A
T
A
T
A
= +25°C
25.9
CDMA mode
= -40°C to +85°C
= +25°C
25.4
24.7
12.3
11.5
FM IQ mode
= -40°C to +85°C
= +25°C
FM I mode
Supply Current (Note 1)
I
= -40°C to +85°C
= +25°C
mA
CC
STANDBY (VCO_H)
STANDBY (VCO_L)
= -40°C to +85°C
= +25°C
= -40°C to +85°C
3.5
1.5
3
Addition for LO out (BUFEN = low)
SHDN = low
Shutdown Current
I
I
10
µA
mA
V
CC
Register Shutdown Current
Logic High
5.8
CC
2.0
2
Logic Low
0.5
V
Logic High Input Current
Logic Low Input Current
VGC Control Input Current
I
µA
µA
µA
IH
I
2
5
IL
0.5V < V
< 2.3V
-5
VGC
VGC Control Input Current
During Shutdown
1
µA
SHDN = low
Lock Indicator High (locked)
Lock Indicator Low (unlocked)
DC Offset Voltage
50kΩ load
50kΩ load
2.0
-20
V
V
0.5
I+ to I- and Q+ to Q-, PLL locked
= 2.75V
1.5
+20
mV
V
Common-Mode Output Voltage
V
CC
V
- 1.4
CC
2
_______________________________________________________________________________________
CDMA IF VGAs and I/Q Demodulators
with VCO and Synthesizer
AC ELECTRICAL CHARACTERISTICS
(MAX2310/MAX2314 or MAX2312/MAX2316 EV kit, V
= +2.75V, registers set to default power-up states, f = 210.88MHz for
IN
CC
CDMA, f = 85.88MHz for FM, f
= 19.68MHz, synthesizer locked with passive 2nd-order lead-lag loop filter, SHDN = high, VGC
IN
REF
set for +35dB voltage gain, differential output load = 10kΩ, all power levels referred to 50Ω, T = +25°C, unless otherwise noted.)
A
PARAMETER
Input Frequency
SYMBOL
CONDITIONS
MIN
TYP
MAX
300
39
UNITS
MHz
f
IN
(Note 2)
(Note 2)
40
Reference Frequency
f
MHz
REF
Frequency Reference Signal
Level
V
REF
0.2
Vp-p
SIGNAL PATH, CDMA MODE
Gain = -35dB (Note 3)
Gain = +35dB (Note 4)
Gain = -35dB
1.7
-33.2
-6.4
Input Third-Order Intercept
IIP3
dBm
dBm
dBm
-9
Input 1dB Compression
P
1dB
Gain = +35dB
-44
-38.3
-14.8
-49
Gain = -35dB
Gain = +35dB
Input 0.25dB Desensitization
(Note 5)
Minimum Voltage Gain
Maximum Voltage Gain
A
A
V
V
= 0.5V (Note 6)
= 2.3V (Note 6)
-54.8
61.3
62.9
6.36
-49
dB
dB
V
GC
56
V
GC
Gain = -35dB
Gain = +35dB
DSB Noise Figure
NF
dB
SIGNAL PATH, FM_IQ MODE
Input Third-Order Intercept
Gain = -35dB
Gain = +35dB
Gain = -35dB
Gain = +35dB
-6.0
-31
IIP3
(Note 7)
dBm
dBm
-20
-44
-16.2
-38.4
-50.2
63.4
Input 1dB Compression
P
1dB
(Notes 6, 8)
Minimum Voltage Gain
Maximum Voltage Gain
A
A
V
V
= 0.5V (Note 6)
= 2.3V (Note 6)
-47.4
dB
dB
V
GC
58.5
V
GC
SIGNAL PATH, CDMA and FM_IQ MODE
Maximum Gain Variation
Over Temperature
Normalized to +25°C
2.5
dB
Baseband 0.5dB Bandwidth
Quadrature Suppression
LO to Baseband Leakage
4.2
+35
1
MHz
dB
T
= T
to T
(Note 6)
MAX
+28
A
MIN
mVp-p
Vp-p
Saturated Output Level
V
SAT
Differential
2.7
PHASE-LOCKED LOOP
f
80
300
600
VCO_L
VCO Tune Range
(Note 2)
MHz
dBm
f
135
VCO_H
LOOUT Output Power
P
LO
-13.7
R = 50Ω, BUFEN = low
L
_______________________________________________________________________________________
3
CDMA IF VGAs and I/Q Demodulators
with VCO and Synthesizer
AC ELECTRICAL CHARACTERISTICS (continued)
(MAX2310/MAX2314 or MAX2312/MAX2316 EV kit, V
= +2.75V, registers set to default power-up states, f = 210.88MHz for
CC
IN
CDMA, f = 85.88MHz for FM, f
= 19.68MHz, synthesizer locked with passive 2nd-order lead-lag loop filter, SHDN = high, VGC
IN
REF
set for +35dB voltage gain, differential output load = 10kΩ, all power levels referred to 50Ω, T = +25°C, unless otherwise noted.)
A
PARAMETER
SYMBOL
M1, M2
M1, M2
R1, R2
CONDITIONS
MIN
16383
2047
TYP
MAX
UNITS
VCO Minimum Divide Ratio
VCO Maximum Divide Ratio
REF Minimum Divide Ratio
REF Maximum Divide Ratio
256
2
R1, R2
Minimum Phase Detector
Comparison Frequency
(Note 6)
(Note 6)
20
kHz
Maximum Phase Detector
Comparison Frequency
1500
kHz
dBc
Base Band Spurious due to PLL
-50
1kHz offset
-72
-100
-110
-119
-125
-64
12.5kHz offset
30kHz offset
120kHz offset
900kHz offset
1kHz offset
LOOUT at 85MHz,
VCO_L Enabled (Note 9)
dBc/Hz
dBc/Hz
12.5kHz offset
30kHz offset
120kHz offset
900kHz offset
-91
LOOUT at 210MHz,
VCO_H Enabled (Note 9)
-105
-115
-125
TURBO LOCK
Acquisition, CPX = XX, TC = 1
Locked, CPX = 00
1480
105
150
210
300
2100
150
210
300
425
2650
190
265
380
530
Charge-Pump Source/Sink
Current
Locked, CPX = 01
µA
%
Locked, CPX = 10
Locked, CPX = 11
Charge-Pump Source/Sink
Matching
Locked, all values of CPX,
0.2
10
0.5V < V < V - 0.5V
CP
CC
Note 1: FM_IQ and FM_I modes are not available on MAX2312 and MAX2316.
Note 2: Recommended operating frequency range.
Note 3: f = 210.88MHz, f = 210.89MHz, P = P = -15dBm.
1
2
f1
f2
Note 4: f = 210.88MHz, f = 210.89MHz, P = P = -50dBm.
1
2
f1
f2
Note 5: Small-signal gain at 200kHz below the LO frequency will be reduced by less than 0.25dB when an interfering signal at
1.25MHz below the LO frequency is applied at the specified level.
Note 6: Guaranteed by design and characterization.
Note 7: f = 85.88MHz, f = 85.98MHz, P = P = -15dBm.
1
2
f1
f2
Note 8: f = 85.88MHz, f = 85.98MHz, P = P = -50dBm.
1
2
f1
f2
Note 9: Measured at LOOUT with BD = 0 (÷2 selected).
4
_______________________________________________________________________________________
CDMA IF VGAs and I/Q Demodulators
with VCO and Synthesizer
Typical Operating Characteristics
(MAX2310/MAX2314 or MAX2312/MAX2316 EV kit, V
= +2.75V, registers set to default power-up states, f = 210.88MHz for
IN
CC
CDMA, f = 85.88MHz for FM, f
= 19.68MHz, synthesizer locked with passive 2nd-order lead-lag loop filter, SHDN = high, VGC
IN
REF
set for +35dB voltage gain, differential output load = 10kΩ, all power levels referred to 50Ω, T = +25°C, unless otherwise noted.)
A
RECEIVE SUPPLY CURRENT
vs. SUPPLY VOLTAGE
RECEIVE SHUTDOWN CURRENT vs.
SUPPLY VOLTAGE
GAIN vs. V
GC
35.00
32.50
30.00
27.50
25.00
22.50
20.00
80
60
0.014
0.012
0.010
0.008
0.006
0.004
0.002
0
T
= +85°C
= +25°C
A
40
T
= +85°C
A
20
T
A
T
= +25°C
A
0
T
= +25°C
A
T
= -40°C
A
-20
-40
-60
-80
T
= -40°C
A
T
= +85°C
A
T
= -40°C
A
2.5
3.0
3.5
4.0
4.5
5.0
5.5
0.5
1.0
1.5
2.0
(V)
2.5
3.0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
V
GC
THIRD-ORDER INPUT
INTERCEPT vs. GAIN
GAIN vs. INPUT FREQUENCY
GAIN vs. BASEBAND FREQUENCY
10
0
60
60.0
59.5
59.0
58.5
58.0
57.5
57.0
56.5
56.0
T
= -40°C
A
55
50
45
40
35
30
25
20
15
V
= 2.5V
GC
-10
-20
-30
-40
-50
-60
T
= +85°C
A
T
= +25°C
A
-60 -40 -20
0
20
40
60
80
0
100
200
300
400
500
0
2
4
6
8
10 12 14 16 18 20
GAIN (dB)
FREQUENCY (MHz)
FREQUENCY (MHz)
NOISE FIGURE vs. TEMPERATURE
NOISE FIGURE vs. GAIN
VCO VOLTAGE vs. TIME
MAX2310 toc09
7.4
7.2
7.0
6.8
6.6
6.4
6.2
6.0
70
60
50
SHDN
VCO
VOLTAGE
40
30
LOCK
20
10
0
LOCK TIME
1.83ms
-40 -20
0
20
40
60
80 100
TIME (500µs/div)
-40 -30 -20 -10
0
10 20 30 40 50 60 70
GAIN (dB)
TEMPERATURE (°C)
_______________________________________________________________________________________
5
CDMA IF VGAs and I/Q Demodulators
with VCO and Synthesizer
Typical Operating Characteristics (continued)
(MAX2310/MAX2314 or MAX2312/MAX2316 EV kit, V
= +2.75V, registers set to default power-up states, f = 210.88MHz for
IN
CC
CDMA, f = 85.88MHz for FM, f
= 19.68MHz, synthesizer locked with passive 2nd-order lead-lag loop filter, SHDN = high, VGC
IN
REF
set for +35dB voltage gain, differential output load = 10kΩ, all power levels referred to 50Ω, T = +25°C, unless otherwise noted.)
A
FM PORT
S11 vs. FREQUENCY
TANKL PORT
1/S11 vs. FREQUENCY
TANKH PORT
1/S11 vs. FREQUENCY
4
4
3
2
1
3
2
1
1
2
3
4
1: 641 - j428 10MHz
2: 27 - j162 85MHz
3: 4 - j73 210MHz
4: 1.8 - j39 600MHz
1: 1.98ms + j437µs, 100MHz
2: 2.18ms + j853µs, 160MHz
3: 2.11ms +j 2.53ms, 420MHz
4: 2.17ms +j 3.71ms, 600MHz
1: -3.06ms + j349µs, 100MHz
2: -3.01ms + j853µs, 160MHz
3: -3.11ms + j1.45ms, 240MHz
4: -3.04ms + j1.85ms, 300MHz
CDMA PORT
S11 vs. FREQUENCY
LOOUT PORT
S22 vs. FREQUENCY
1
2
1: 108.63Ω (Re)
10.266Ω (1m)
40MHz
3
2: 134.99Ω (Re)
13.71Ω (1m)
150MHz
3: 158.83Ω (Re)
39.58Ω (1m)
300MHz
4
1: 10MHz, 375Ω - j56Ω
2: 85MHz, 285Ω - j200Ω
3: 210MHz, 73Ω - j169Ω
4: 600MHz, 2.1Ω - j34Ω
Pin Description
PIN
NAME
FUNCTION
MAX2310
MAX2312
MAX2314
MAX2316
Bypass Node. Must be capacitively decoupled (bypassed)
to analog ground.
1
1
1, 8
1
BYP
2
3
2
3
2
3
2
3
CP_OUT
GND
Charge-Pump Output
Analog Ground Reference
TANKL+,
TANKL-
4, 5
—
—
4
4, 5
—
5, 6
4
Differential Tank Input for Low-Frequency Oscillator
High selects M1/R1; low selects M2/R2.
DIVSEL
6
_______________________________________________________________________________________
CDMA IF VGAs and I/Q Demodulators
with VCO and Synthesizer
Pin Description (continued)
PIN
NAME
FUNCTION
MAX2310
MAX2312
MAX2314
MAX2316
TANKH+,
TANKH-
6, 7
5, 6
—
—
Differential Tank Input for High-Frequency Oscillator
—
—
7
—
7
LO Buffer Amplifier—active low
BUFEN
—
6, 7
—
N.C.
No Connection. Must be left open-circuit.
Mode Select. High selects CDMA mode; low selects FM
mode.
8
—
—
—
MODE
Internal VCO Output. Depending on setting of BD bit, LOOUT
is either the VCO frequency (twice the IF frequency) or one-
half the VCO frequency (equal to the IF frequency).
—
8
—
8
LOOUT
V
9
9
9
9
+2.7V to +5.5V Supply for Digital Circuits
Digital Ground
CC
10
11
10
11
10
11
10
11
GND
REF
Reference Frequency Input
Shutdown Input—active low. Low powers down entire device,
including registers and serial interface.
12
12
12
12
SHDN
IOUT+,
IOUT-
Differential In-Phase Baseband Output, or FM signal output
FM_I mode is selected.
13, 14
15
13, 14
15
13, 14
15
13, 14
15
Lock Output—open-collector pin. Logic high indicates phase-
locked condition.
LOCK
QOUT-,
QOUT+
Differential Quadrature-Phase Baseband Output. Disabled if
FM_I mode is selected.
16, 17
16, 17
16, 17
16, 17
18
19
20
21
22
18
19
20
21
22
18
19
20
21
22
18
19
20
21
22
CLK
EN
Clock input of the 3-wire serial bus
Enable Input. When low, input shift register is enabled.
Data input of the 3-wire serial bus.
DATA
V
2.7V to 5.5V Supply for Analog Circuits
CC
VGC
VGA Gain Control Input. Control voltage range is 0.5V to 2.3V.
CDMA-,
CDMA+
23, 24
23, 24
23, 24
23, 24
Differential CDMA Input. Active in CDMA mode.
25
—
—
25
—
—
FM+
N.C.
Differential Positive Input. Active in FM mode.
No Connection.
25
25
Differential Negative Input for FM signal. Bypass to GND for
single-ended operation.
26
—
—
26
26
—
—
26
FM-
STBY
BYP
Standby Input—active low. Low powers down VGA and demod-
ulator while keeping VCO, PLL, and serial bus on.
Bypass Node. Must be capacitively decoupled (bypassed) to
27, 28
27, 28
27, 28
27, 28
analog V
.
CC
_______________________________________________________________________________________
7
CDMA IF VGAs and I/Q Demodulators
with VCO and Synthesizer
47pF
0.01µF
V
CC
10kΩ
0.01µF
0.1µF
BYP
BYP
BYP
FM-
3.3nF
18pF
0.033µF
0.01µF
CPOUT
GND
10kΩ
FM
FM+
TANKL+
CDMA+
5pF
68nH
18nH
18pF
CDMA
MAX2310
680Ω
10kΩ
10kΩ
TANKL-
CDMA-
VGC
12pF
TANKH+
DAC
47pF
1.5pF
12pF
V
CC
10kΩ
TANKH-
MODE
V
CC
DATA
EN
V
CC
V
CC
47pF
3-WIRE
GND
REF
CLK
SHDN
IOUT+
QOUT+
10kΩ
47kΩ
10kΩ
I
Q
IOUT-
QOUT-
LOCK
V
CC
Figure 1. MAX2310 Typical Operating Circuit
configured for conversion to the I channel, or it may be
converted in quadrature to both the I and Q channels.
The MAX2310’s operation modes are described in
Table 1. These modes are set by programming the con-
trol register and setting logic levels on control pins. If
MODE is left floating, the internal register controls the
operation. If driven high or low, mode will override cer-
tain register bits, as shown in Table 1.
_______________Detailed Description
MAX2310
The MAX2310 is intended for dual-band (PCS and cel-
lular) and dual-mode code division multiple access
(CDMA) and FM applications (Figure 1). The device
includes an IF variable-gain amplifier, quadrature
demodulator, dual VCOs, and dual-frequency synthe-
sizers (Figure 7). Dual VCOs are provided for applica-
tions using different IF frequencies for each mode or
band of operation. The analog FM output signal can be
8
_______________________________________________________________________________________
CDMA IF VGAs and I/Q Demodulators
with VCO and Synthesizer
Table 1. MAX2310 Control Register States
M
S
B
L
S
B
PINS
CONTROLREGISTER
OPERATIONAL
MODE
ACTION
RESULT
Shutdown pin completely
powers down the chip
SHUTDOWN
SHUTDOWN
STANDBY
CDMA
L
X
X
X
H
F
L
F
L
F
X
X
X
X
X
X
X
X
0
0
0
0
0
0
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
1
1
1
1
1
1
X
0 in shutdown register bit leaves
serial port active
H
H
H
H
H
H
H
0
1
1
1
1
1
1
1
0 in standby register bit turns off
VGA and modulator only
Mode pin overrides VCO_SEL,
DIVSEL, and IN_SEL to high
X
1
X
X
1
X
X
X
0
0
1
1
X
1
X
0
X
0
Floating mode pin returns control
to register
CDMA
Mode pin overrides VCO_SEL,
DIVSEL, and IN_SEL to low
FM_IQ
Floating mode pin returns control
to register
FM_IQ
Mode pin overrides VCO_SEL,
DIVSEL, and IN_SEL to low
FM_I
X
X
Floating pins return control to
register
H
L
FM_I
Note: H = high, L = low, F = floating pin, X = don’t care, Blank = independent parameter, 1 = logic high, 0 = logic low.
be configured for the VCO frequency (twice the IF fre-
quency) or one-half the VCO frequency (IF frequency).
The BUFEN pin enables this feature. A standby mode,
in which only the VCO and synthesizer are operational,
can be selected through the serial interface or the
STBY pin. The MAX2312/MAX2316s’ operational modes
are described in Table 2. These modes are set by pro-
gramming the control register and/or setting logic lev-
els on control pins. If the control pins (STBY, BUFEN,
DIVSEL) are left floating, the internal register controls
the operational mode. If driven high or low, the control
pins will override certain register bits, as shown in
Table 2.
MAX2312/MAX2316
The MAX2312/MAX2316 quadrature demodulators are
simplified versions of the MAX2310 that can be used in
single-mode CDMA or dual mode using an external FM
discriminator (Figures 2a and 2b). The MAX2312 VCO
is optimized for the 67MHz to 300MHz IF frequency
range, while the MAX2316 VCO is optimized for the
40MHz to 150MHz IF frequency range.
Both devices include a buffered output for the VCO.
The buffered VCO output can be used to support sys-
tems implementing traditional limiting IF stages for FM
demodulation in dual-mode phones as well as for the
transmit LO in TDD systems. This buffered output can
_______________________________________________________________________________________
9
CDMA IF VGAs and I/Q Demodulators
with VCO and Synthesizer
47pF
10kΩ
0.01µF
0.01µF
0.01µF
BYP
BYP
V
V
CC
CC
3300pF
12pF
0.033µF
CPOUT
GND
BYP
STBY
DIVSEL
TANKH+
10kΩ
10kΩ
CDMA+
1.5pF
12pF
18nH
CDMA
680Ω
MAX2312
TANKH-
BUFEN
LOOUT
CDMA-
VGC
DAC
47pF
V
CC
V
V
CC
CC
47pF
DATA
EN
V
CC
GND
3-WIRE
REF
CLK
SHDN
IOUT+
QOUT+
10kΩ
47kΩ
I
10kΩ
Q
IOUT-
QOUT-
LOCK
V
CC
Figure 2a. MAX2312 Typical Operating Circuit
10 ______________________________________________________________________________________
CDMA IF VGAs and I/Q Demodulators
with VCO and Synthesizer
47pF
0.033µF
0.01µF
0.01µF
0.01µF
10kΩ
BYP
BYP
V
V
CC
CC
3300pF
17pF
CP_OUT
GND
BYP
STBY
DIVSEL
TANKL+
10kΩ
CDMA+
5pF
18pF
68nH
CDMA
680Ω
MAX2316
10kΩ
TANKL-
BUFEN
LOOUT
CDMA-
VGC
DAC
DISCRIMINATOR
47pF
V
CC
455kHz
V
V
CC
CC
47pF
DATA
EN
V
CC
GND
3-WIRE
REF
CLK
SHDN
IOUT+
QOUT+
LIMITER
FM
10kΩ
47kΩ
I
10kΩ
Q
IOUT-
QOUT-
LOCK
V
CC
Figure 2b. MAX2316 Typical Operating Circuit
______________________________________________________________________________________ 11
CDMA IF VGAs and I/Q Demodulators
with VCO and Synthesizer
Table 2. MAX2312/MAX2316 Control Register States
M
S
B
L
S
B
PINS
CONTROLREGISTER
OPERATIONAL
MODE
ACTION
RESULT
Shutdown pin com-
pletely powers down
the chip
SHUTDOWN
SHUTDOWN
STANDBY
L
H
H
X
X
X
X
X
L
X
X
X
X
X
X
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
X
0 in shutdown register
bit leaves serial bus
active
X
0
1
0 in standby pin turns
off VGA and modulator
only
0 in standby register bit
turns off VGA and mod-
ulator only
H/
L
STANDBY
H
H
H
H
0
0
0
X
X
X
1
1
1
DIVIDER
SELECT
DIV_SEL pin overrides
DIV_SEL register bit
H/
L
H
H
X
If DIV_SEL pin is float-
ed, then register bit
selects divider
DIVIDER
SELECT
1/
0
F
BUFEN pin controls the
LO buffer and overrides
the bit
LO BUFFER
ENABLE
H/
L
H
F
0
0
X
X
X
1
1
If pin is floated, then
BUFEN register bit
controls buffer
LO BUFFER
ENABLE
1/
0
H
Note: H = high, L = low, 1 = logic high, 0 = logic low, X = don’t care, blank = independent parameter.
12 ______________________________________________________________________________________
CDMA IF VGAs and I/Q Demodulators
with VCO and Synthesizer
47pF
10kΩ
0.01µF
0.01µF
BYP
BYP
BYP
V
V
CC
CC
0.033µF
3300pF
18pF
0.01µF
0.01µF
MAX2314
CP_OUT
GND
FM-
FM+
10kΩ
10kΩ
TANKL+
FM
5pF
18pF
68nH
CDMA+
TANKL-
BYP
CDMA
680Ω
1000pF
CDMA-
VGC
DAC
47pF
V
V
V
CC
CC
CC
47pF
GND
DATA
EN
V
CC
REF
3-WIRE
CLK
SHDN
I_OUT+
Q_OUT+
10kΩ
47kΩ
10kΩ
Q
I_OUT-
Q_OUT-
LOCK
V
CC
Figure 3. MAX2314 Typical Operating Circuit
MAX2314
__________Applications Information
The MAX2314 supports CDMA cellular-band, dual-
mode operation. As with the MAX2310, the FM mode
can be configured for conversion to the I port or quad-
rature conversion to both the I and Q ports (Figure 3).
The MAX2314’s operational modes are described in
Table 3. These modes are set by programming the
control register and setting logic levels on control pins.
Variable-Gain Amplifier and Demodulator
The MAX2310 family provides a Variable-Gain Amplifier
(VGA) with exceptional gain range. The MAX2310/
MAX2314 support multimode applications with dual dif-
ferential inputs, selectable with the IN_SEL (IS) control
bit. On the MAX2310 this function can be controlled
with the MODE pin, which overrides the IS control bit.
The VGA’s gain is controlled over a 110dB range with
______________________________________________________________________________________ 13
CDMA IF VGAs and I/Q Demodulators
with VCO and Synthesizer
Table 3. MAX2314 Control Register States
P
I
N
M
S
B
L
S
B
CONTROLREGISTER
ACTION
RESULT
OPERATIONAL
MODE
Shutdown pin completely shuts down
chip
L
H
H
X
X
X
X
X
X
0
X
X
X
X
X
X
X
X
0
X
X
X
X
X
X
X
X
X
X
X
X
0
X
SHUTDOWN
SHUTDOWN
STANDBY
0 in shutdown register bit leaves seri-
al port active
L
1
0 in standby pin turns off VGA and
modulator only
CDMA
FM_IQ
FM_I
CDMA operation
H
H
H
0
0
0
0
0
0
X
X
X
X
X
X
X
0
1
1
0
0
1
1
1
1
1
1
FM IQ quadrature operation
FM I operation
Note: H = high, L = low, 1 = logic high, 0 = logic low, X = don’t care, blank = independent parameter
the VGC pin. The output of the VGA drives the RF ports
of a quadrature demodulator. The MAX2310/MAX2314
provide two types of FM demodulation, controlled by
the FM_TYPE (FT) control bit. When FM_TYPE is “1,”
the signal is passed through both the I and Q signal
paths for subsequent lowpass filtering and A/D conver-
sion at baseband. If FM_TYPE is “0,” the FM signal is
passed through the I mixer only.
control bit. They oscillate at twice the desired LO fre-
quency. For applications requiring an external LO, the
VCOs can be bypassed with the VCO_BYP (VB) control
bit.
The MAX2312/MAX2316 buffer the output of the VCO
and provide this signal at the LOOUT pin. This signal is
enabled by the BUFEN (BE) control bit or by the
BUFEN control pin. The frequency of this signal is
selected by the BUF_DIV (BD) control bit, and can be
either the VCO frequency or half the VCO frequency.
Voltage-Controlled Oscillator,
Buffers, and Quadrature Generation
Quadrature downconversion is realized by providing in-
phase (I) and quadrature-phase (Q) components of the
LO signal to the LO ports of the demodulator described
above. The quadrature LO signals are generated by
dividing the VCO output frequency using two latches.
The appropriate latch outputs provide I and Q signals
at the desired LO frequency.
The LO signal for downconversion is provided by a
voltage-controlled oscillator (VCO) consisting of an on-
chip differential oscillator, and an off-chip high-Q reso-
nant network. Figure 4 shows a simplified schematic of
the VCO oscillator. Multiband operation is supported by
the MAX2310 with dual VCOs. VCO_H and VCO_L are
selectable with the MODE pin or the VCO_SEL (VS)
14 ______________________________________________________________________________________
CDMA IF VGAs and I/Q Demodulators
with VCO and Synthesizer
When the part initially powers up or changes state, the
synthesizer acquisition time can be reduced by using
the Turbo feature, enabled by the TURBOCHARGE
(TC) control bit. Turbo functionality provides a larger
charge-pump current during acquisition mode. Once
the VCO frequency is acquired, the charge-pump out-
put current magnitude automatically returns to the pre-
programmed state to maintain loop stability and
minimize spurs in the VCO output signal.
Synthesizer
The VCO’s output frequency is controlled by an internal
phase-locked-loop (PLL) dual-modulus synthesizer.
The loop filter is off-chip to simplify loop design for
emerging applications. The tunable resonant network is
also off-chip for maximum Q and for system design
flexibility. The VCO output frequency is divided down to
the desired comparison frequency with the M counter.
The M counter consists of a 4-bit A swallow counter
and a 10-bit P counter. A reference signal is provided
from an external source and is divided down to the
comparison frequency with the R counter. The two
divided signals are compared with a three-state digital
phase-frequency detector. The phase-detector output
drives a charge pump as well as lock-detect logic and
turbocharge control logic. The charge pump output
(CP_OUT) pin is processed by the loop filter and drives
the tunable resonant network, altering the VCO fre-
quency and closing the loop.
The lock detect output indicates when the PLL is
locked with a logic high.
3-Wire Interface and Registers
The MAX2310 family incorporates a 3-wire interface for
synthesizer programming and device configuration
(Figure 5). The 3-wire interface consists of a clock,
data, and ENABLE. It controls the VCO dividers (M1
and M2), reference frequency dividers (R1 and R2),
and a 13-bit control register. The control register is
used to set up the operational modes (Table 4). The
input shift is 17 data bits long and requires a total of 18
clock bits (Figure 6). A single clock pulse is required
before enable drops low to initialize the data bus.
Multimode applications are supported by two indepen-
dent programmable registers each for the M counter
(M1, M2), the R counter (R1, R2), and the charge-pump
output current magnitude (CP1, CP2). The DIVSEL (DS)
bit selects which set of registers is used. It can be over-
ridden by the MAX2310’s MODE pin or the MAX2312/
MAX2316’s DIVSEL pin. Programming these registers is
discussed in the 3-Wire Interface and Registers sec-
tion.
Whenever the M or R divide register value is pro-
grammed and downloaded, the control register must
also be subsequently updated. This prevents turbolock
from going active when not desired.
The SHDN control bit is notable because it differs from
the SHDN pin. When the SHDN control bit is low, the
registers and serial interface are left active, retaining
the values stored in the latches, while the rest of the
device is shut off. In contrast, the SHDN pin, when low,
shuts down everything, including the registers and seri-
al interface. See the functional diagram in Figure 7.
800µA
D1
R1
Registers
Figure 8 shows the programming logic. The 17-bit shift
register is programmed by clocking in data at the rising
edge of CLK. Before the shift register is able to accept
data, it must be initialized by driving it with at least one
full clock cycle at the CLK input with EN high (see
Figure 6). Pulling enable low will allow data to be
clocked into the shift register; pulling enable high loads
the register addressed by A0, A1, and A2, respectively
(Figure 8). Table 5 lists the power-on default values of
all registers. Table 6 lists the charge-pump current,
depending on CP0 and CP1.
TANK-
TANK+
R
L
R
L
R
R
B
B
C
C
F
F
R
R
E
E
Figure 4. Voltage-Controlled Oscillators
______________________________________________________________________________________ 15
CDMA IF VGAs and I/Q Demodulators
with VCO and Synthesizer
VCO1
14-BIT M1
COUNTER
(00)
DATA
CLK
EN
CPI
START BIT
16-BIT
DATA/ADDRESS
REGISTER
2-BIT
CP1
11-BIT R1
COUNTER
(010)
(011)
M
U
X
CPOUT
F
REF
2-BIT
CP2
11-BIT R2
COUNTER
(11X)
13-BIT CONTROL
REGISTER
CP2
(01)
VCO2
14-BIT M2
COUNTER
Figure 5. 3-Wire Control Block Diagram
MSB
*SB
LSB
DATA
*START BIT MUST BE LOGIC HIGH.
*
CLOCK
*RISE AND FALL REQUIRED PRIOR TO EN GOING LOW.
ENABLE
Figure 6. 3-Wire Interface Timing Diagram
16 ______________________________________________________________________________________
CDMA IF VGAs and I/Q Demodulators
with VCO and Synthesizer
MAX2310
MAX2312
MAX2314
MAX2316
VGC
IOUT+
CDMA+
IOUT-
CDMA-
EN
CLK
DATA
LOGIC
(MAX2310/14)
SB
1
÷2
SHIFT REGISTER
FM+
FM-
QOUT+
QOUT-
14
14
00
01
M1 REGISTER
M2 REGISTER
R1 REGISTER
R2 REGISTER
FT
2
2
010
011
11
CP1
MODE
(MAX2310)
11
IS
CP2
VS
DS
TM POL TE TC
VB
BD
FT IS
11
110
VS
BE
SB
SD
DS
VCO_L
CONTROL
14
14
2
11
2
TANKL+
TANKL-
2
14
11
R COUNTER
VB
M COUNTER
LOCK DET
REF
Ø
DET
POL
TANKH+
TANKH-
VCO_H
TURBO
CONTROL
TC
CHARGE
PUMP
2
LOCK
LO_OUT
BUFEN
÷2
BIAS
SHDN
STBY
CP_OUT
BD
BE
(MAX2312/16)
(MAX2312/16)
SB
SD
Figure 7. Functional Diagram
______________________________________________________________________________________ 17
CDMA IF VGAs and I/Q Demodulators
with VCO and Synthesizer
Table 4. Control Register, Default State: 0B57 Address: 110
h,
b
POWER-
UP
STATE
BIT
LOCATION
0 = LSB
BIT ID
BIT NAME
FUNCTION
TM
TEST_MODE
0
12
11
Must be 0 for normal operation.
Logic “1” causes the charge-pump output CP_OUT to source cur-
rent when f /R > f /M. This state is used when the VCO tune
REF
VCO
polarity is such that increasing voltage produces increasing fre-
quency. Logic “0” causes CP_OUT to source current when f
POL
CP_POL
1
/M
VCO
> f /R. This state is used when increasing tune voltage causes
REF
the VCO frequency to decrease.
TE
TC
TEST_ENABLE
0
1
10
9
Must be 0 for normal operation.
Logic “1” activates turbocharge mode, which provides rapid fre-
quency acquisition in the PLL.
TURBO_CHARGE
DS
VB
VS
DIV_SEL
VCO_BYP
VCO_SEL
1
0
1
8
7
6
Logic “1” selects M1/R1 divide ratios. Logic “0” selects M2/R2.
Logic “1” bypasses the VCO inputs for external VCO operation.
Logic “1” selects VCO_H. Logic “0” selects VCO_L.
Logic “1” selects divide-by-2 on LOOUT port. Logic “0” bypasses
divider.
BD
BE
FT
IS
BUF_DIV
BUFEN
0
1
0
1
5
4
3
2
Logic “1” disables LOOUT. Logic “0” enables LOOUT.
Active in FM mode. Logic “0” selects quadrature demodulator for
FM mode. Logic “1” selects downconversion to I port.
FM_TYPE
IN_SEL
Logic “0” selects FM input port. Logic “1” selects CDMA input.
Logic “0” enables standby mode, which shuts down the VGA and
demodulator stages, leaving the VCO locked and the registers
active.
SB
SD
1
1
1
0
STBY
Logic “0” enables register-based shutdown. This mode shuts down
everything except the M and R latches and the serial bus.
SHDN
Table 6. Charge-Pump Control Bits
Table 5. Register Defaults
CHARGE-PUMP CURRENT
REGISTER
DEFAULT
CP1
CP0
AFTER ACQUISITION
(µA)
M1
M2
10519
DEC
DEC
DEC
DEC
4269
0
0
1
1
0
1
0
1
150
210
300
425
R1
492
492
R2
CTRL
CP0
CP1
OB57
HEX
11 BIN
11 BIN
18 ______________________________________________________________________________________
CDMA IF VGAs and I/Q Demodulators
with VCO and Synthesizer
ADDRESS
DECODED
START BIT
1
A /M
2
A
A
A
A
0
0
1
1
0
0
DATA
SHIFT REGISTER
A /M
2
M1 REGISTER
M2 REGISTER
M 13
M
0
0
1
0
1
0
1
1/0
2/0
M
M 13
2
0
1
1
1
CP1 AND R1 REGISTERS
CP2 AND R2 REGISTERS
CTRL REGISTER
CP
1/1
CP
CP
R
1/10
R
R
0
1/0
2/0
1/0
2/0
0
1
CP
/1
R
2/10
2/1
TM POL TE
TC
DS
VB
VS
BD
BE
FT
IS
SB
SD
Figure 8. Programming Logic
______________________________________________________________________________________ 19
CDMA IF VGAs and I/Q Demodulators
with VCO and Synthesizer
Pin Configurations
TOP VIEW
BYP
CP_OUT
GND
1
2
3
4
5
6
7
8
9
28 BYP
BYP
CP_OUT
GND
1
2
3
4
5
6
7
8
9
28 BYP
27 BYP
27 BYP
26 FM-
26 FM-
TANKL+
TANKL-
TANKH+
TANKH-
MODE
25 FM+
24 CDMA+
23 CDMA-
22 VGC
TANKL+
TANKL-
N.C.
25 FM+
24 CDMA+
23 CDMA-
22 VGC
MAX2314
MAX2310
N.C.
21
V
CC
BYP
21 V
CC
V
20 DATA
19 EN
V
20 DATA
19 EN
CC
CC
GND 10
REF 11
GND 10
REF 11
18 CLK
18 CLK
SHDN 12
IOUT+ 13
IOUT- 14
17 QOUT+
16 QOUT-
15 LOCK
SHDN 12
IOUT+ 13
IOUT- 14
17 QOUT+
16 QOUT-
15 LOCK
QSOP
QSOP
BYP
CPOUT
GND
1
2
3
4
5
6
7
8
9
28 BYP
BYP
CP_OUT
GND
1
2
3
4
5
6
7
8
9
28 BYP
27 BYP
27 BYP
26 STBY
25 N.C.
26 STBY
25 N.C.
DIVSEL
TANKH+
TANKH-
BUFEN
LOOUT
DIVSEL
TANKL+
TANKL-
BUFEN
LOOUT
24 CDMA+
23 CDMA-
22 VGC
24 CDMA+
23 CDMA-
22 VGC
MAX2312
MAX2316
21
V
CC
21 V
CC
V
20 DATA
19 EN
V
20 DATA
19 EN
CC
CC
GND 10
REF 11
GND 10
REF 11
18 CLK
18 CLK
SHDN 12
IOUT+ 13
IOUT- 14
17 QOUT+
16 QOUT-
15 LOCK
SHDN 12
IOUT+ 13
IOUT- 14
17 QOUT+
16 QOUT-
15 LOCK
QSOP
QSOP
20 ______________________________________________________________________________________
CDMA IF VGAs and I/Q Demodulators
with VCO and Synthesizer
Chip Information
TRANSISTOR COUNT: 6422
Block Diagram
DAC
V
CC
LOCK
QOUT+ QOUT-
AVCC
V
FM- FM+
CDMA+
CC
CDMA-
DATA
EN
BYP
BYP
VGA
CLK
0
/2
90
MAX2310
/M
PHASE
CHARGE
PUMP
DETECTOR
/R
TANKL+
TANKH+
BYP
AGND
REF
TANKH-
TANKL-
SHDN IOUT+ IOUT-
MODE DV
CC
______________________________________________________________________________________ 21
CDMA IF VGAs and I/Q Demodulators
with VCO and Synthesizer
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages.)
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
22 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2003 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
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