MAX20353AEWN+ [MAXIM]
PMIC with Ultra-Low Iq Regulators, Charger, Fuel Gauge, and Haptic Driver for Small Li Systems;型号: | MAX20353AEWN+ |
厂家: | MAXIM INTEGRATED PRODUCTS |
描述: | PMIC with Ultra-Low Iq Regulators, Charger, Fuel Gauge, and Haptic Driver for Small Li Systems 仪表 集成电源管理电路 |
文件: | 总153页 (文件大小:2901K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
EVALUATION KIT AVAILABLE
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MAX20353
PMIC with Ultra-Low Iq Regulators, Charger,
Fuel Gauge, and Haptic Driver for
Small Li+ Systems
General Description
Benefits and Features
● Extend Battery Use Time Between Battery Charging
The MAX20353 is a highly integrated and programmable
power management solution designed for ultra-low-power
wearable applications. It is optimized for size and efficiency
to enhance the value of the end product by extending battery
life and shrinking the overall solution size. A flexible set
of power-optimized voltage regulators, including multiple
bucks, boost, buck-boost, and linear regulators, provides
a high level of integration and the ability to create a fully
optimized power architecture. The quiescent current of
each regulator is specifically suited for 1µA (typ) to extend
battery life in always-on applications.
• 2 x Micro-I Buck Regulators (<1µA I (typ) Each)
Q
Q
• 350mA Output
• Buck1: 0.7V to 2.275V in 25mV Steps
• Buck2: 0.7V to 3.85V in 50mV Steps
• Micro-I LV LDO/Load Switch (1µA I (typ))
Q
Q
• 1.16V to 2.0V Input Voltage
• 50mA Output
• 0.5V to 1.95V Output, 25mV Steps
• Micro-I LDO/Load Switch (1µA I (typ))
Q
Q
• 1.71V to 5.5V Input Voltage
• 100mA Output
• 0.9V to 4V, 100mV Steps
The MAX20353 includes a complete battery management
solution with battery seal, charger, power path, and fuel
gauge. Both thermal management and input protection
are built into the charger.
• Micro-I Buck-Boost Regulator (1.3µA I (typ))
Q
Q
• 250mW Output
• 2.5V to 5V in 100mV Steps
● Easy-to-Implement Li+ Battery Charging
The device also includes a factory programmable button
controller with multiple inputs that are customizable to fit
specific product UX requirements.
• Wide Fast Charge Current Range: 5mA to 500mA
• Smart Power Selector
• 28V/-5.5V Tolerant Input
Three integrated LED current sinks are included for indicator
or backlighting functions, and an ERM/LRA driver with
automatic resonance tracking is capable of providing
sophisticated haptic feedback to the user.
• Programmable JEITA Current/Voltage Profiles
● Minimize Solution Footprint Through High Integration
• Safe Output LDO
• 15mA When CHGIN Present
• 5V or 3.3V
• Haptic Driver
2
The device is configurable through an I C interface that
allows for programming various functions and reading
device status, including the ability to read temperature
and supply voltages with the integrated ADC.
• ERM/LRA Driver with Quick Start And Stored
Pattern RAM
This device is available in a 56-bump, 0.5mm pitch
3.71mm x 4.21mm, wafer-level package (WLP) and
operates over the -40°C to +85°C extended temperature
range.
• Automatic Resonance Tracking (LRA only)
• Closed Loop Automatic Braking (LRA only)
● Support Wide Variety of Display Options
• Micro-I Boost Regulator (2.4µA I (typ))
Q
Q
• 300mW Output
Applications
● Wearable Devices
● IoT
• 5V to 20V in 250mV Step
• 3 Channel Current Sinks
• 20V Tolerant
• Programmable from 0.6 to 30mA
Ordering Information appears at end of data sheet.
● Optimize System Control
• Power-On/Reset Controller
• Programmable Push-Button Controller
• Programmable Supply Sequencing
• Factory Shelf Mode
• On-Chip Voltage Monitor Multiplexer and Analog-
to-Digital Converter (ADC)
19-100568; Rev 2; 2/21
MAX20353
PMIC with Ultra-Low Iq Regulators, Charger,
Fuel Gauge, and Haptic Driver for
Small Li+ Systems
TABLE OF CONTENTS
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Benefits and Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Typical Operating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Bump Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Bump Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
Typical Application Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Detailed Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Power Regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
Dynamic Voltage Scaling (DVS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
Power Switch and Reset Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
Power Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
Current Sink . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
System Load Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Smart Power Selector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
Input Limiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
SAR ADC/Monitor MUX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
JEITA Monitoring with Charger Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
Haptic Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
ERM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
LRA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
LRA Braking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
Driver Amplitude . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
Automatic Level Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
Haptic UVLO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
Vibration Timeout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
Overcurrent/Thermal Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
Haptic Driver Lock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
Interface Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
Pure-PWM (PPWM). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
2
2
Real-Time I C (RTI C). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
External Triggered Stored Pattern (ETRG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
RAM Stored Haptic Pattern (RAMHP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
Fuel Gauge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
ModelGauge Theory of Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Maxim Integrated
│ 2
www.maximintegrated.com
MAX20353
PMIC with Ultra-Low Iq Regulators, Charger,
Fuel Gauge, and Haptic Driver for
Small Li+ Systems
(
)
TABLE OF CONTENTS CONTINUED
Fuel-Gauge Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Battery Voltage and State of Charge. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
Temperature Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
Impact of Empty-Voltage Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
Battery Insertion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
Battery Insertion Debounce. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
Battery Swap Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
Quick-Start. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
Power-On Reset (POR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
Hibernate Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
Alert Interrupt. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
Sleep Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
2
I C Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
Applications Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
2
I C Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
Start, Stop, And Repeated Start Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
Slave Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
Bit Transfer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
Single-Byte Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
Burst Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
Single Byte Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
Burst Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
Acknowledge Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
Application Processor Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
AP Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
AP Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
AP Launch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Write-Protected Commands and Fields. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
2
Direct Access I C Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
2
Direct Access I C Register Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Interrupt Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Interrupt Mask Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
AP Interface Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Buck1 DVS Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80
LDO Direct Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
MPC Direct Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Haptic Braking Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83
Maxim Integrated
│ 3
www.maximintegrated.com
MAX20353
PMIC with Ultra-Low Iq Regulators, Charger,
Fuel Gauge, and Haptic Driver for
Small Li+ Systems
(
)
TABLE OF CONTENTS CONTINUED
Haptic RAM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84
LED Direct Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
Haptic Direct Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
AP Command Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
GPIO Config Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90
Input Current Limit Commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95
Thermal Shutdown Configuration Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96
Charger Configuration Commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Boost Configuration Commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106
Buck Configuration Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
LDO Configuration Commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Charge Pump Configuration Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
SFOUT Configuration Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
MON Mux Configuration Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Buck-Boost Configuration Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Haptic Configuration Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Power and Reset Commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .141
VCELL Register (0x02) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
SOC Register (0x04). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
MODE Register (0x06) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
VERSION Register (0x08) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
2
Fuel Gauge I C Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .141
HIBRT Register (0x0A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
CONFIG Register (0x0C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
VALRT Register (0x14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
CRATE Register (0x16). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
VRESET/ID Register (0x18) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
STATUS Register (0x1A). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
Reset Indicator: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
Alert Descriptors: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
Enable or Disable VRESET Alert: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
TABLE Registers (0x40 to 0x7F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
CMD Register (0xFE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
Chip Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
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PMIC with Ultra-Low Iq Regulators, Charger,
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Small Li+ Systems
LIST OF FIGURES
Figure 1a. PwrRstCfg = 0000 or 0001. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 1b. PwrRstCfg = 0010 or 0011 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Figure 1c. PwrRstCfg = 0100 or 0101 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Figure 1d. PwrRstCfg = 0110. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Figure 1e. PwrRstCfg = 0111 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Figure 1f. PwrRstCfg = 1000 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Figure 2. The full MAX20353 Boot Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Figure 3. Reset Sequence Programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Figure 4a. Sample JEITA Pre Charge Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Figure 4b. Sample JEITA Fast Charge Profile. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Figure 4c. Sample JEITA Maintain Charge Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Figure 5. Charger State Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Figure 6. Read and Write Processes for RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Figure 7a. Sample Pattern Stored in RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Figure 7b. Haptic Driver Output of Stored Pattern. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Figure 8. I2C START, STOP and REPEATED START Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Figure 9. Write Byte Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Figure 10. Burst Write Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Figure 11. Read Byte Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Figure 12. Burst Read Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Figure 13. Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Figure 14. Executing a Write Opcode and Reading the MAX20353 Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Figure 15. Executing a Read Opcode and Reading the MAX20353 Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Figure 16. MODE Register Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
Figure 17. HIBRT Register Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
Figure 18. CONFIG Register Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
Figure 19. VALRT Register Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
Figure 20. VRESET/ID Register Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
Figure 21. STATUS Register Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
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MAX20353
PMIC with Ultra-Low Iq Regulators, Charger,
Fuel Gauge, and Haptic Driver for
Small Li+ Systems
LIST OF TABLES
Table 1. Buck1 DVS MPC Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Table 2. PwrRstCfg Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Table 3. SAR ADC Full-Scale Voltages and Conversions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Table 4. RAMHP Pattern Storage Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Table 5. HardwareID Register (0x00). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Table 6. FirmwareID Register (0x01) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Table 7. Int0 Register (0x03) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Table 8. Int1 Register (0x04) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Table 9. Int2 Register (0x05) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Table 10. Status0 Register (0x06) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Table 11. Status1 Register (0x07) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Table 12. Status2 Register (0x08) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Table 13. Status3 Register (0x09) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Table 14. SystemError Register (0x0B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
Table 15. IntMask0 Register (0x0C). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Table 16. IntMask1 Register (0x0D). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Table 17. IntMask2 Register (0x0E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Table 18. APDataOut0 Register (0x0F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Table 19. APDataOut1 Register (0x10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Table 20. APDataOut2 Register (0x11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Table 21. APDataOut3 Register (0x12) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Table 22. APDataOut4 Register (0x13) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Table 23. APDataOut5 Register (0x14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Table 24. APDataOut6 Register (0x15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Table 25. APCmdOut Register (0x17) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Table 26. APResponse Register (0x18). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Table 27. APDataIn0 Register (0x19). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Table 28. APDataIn1 Register (0x1A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Table 29. APDataIn2 Register (0x1B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Table 30. APDataIn3 Register (0x1C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Table 31. APDataIn4 Register (0x1D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Table 32. APDataIn5 Register (0x1E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Table 33. Buck1I2CDVS Register (0x1F). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Table 34. LDODirect Register (0x20). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Table 35. MPCDirectWrite Register (0x21) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
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MAX20353
PMIC with Ultra-Low Iq Regulators, Charger,
Fuel Gauge, and Haptic Driver for
Small Li+ Systems
(
)
LIST OF TABLES CONTINUED
Table 36. MPCDirectRead Register (0x22) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Table 37. DVSVlt1 Register (0x23). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Table 38. DVSVlt2 Register (0x24) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Table 39. DVSVlt3 Register (0x25) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Table 40. AutoBrkCfg0 Register (0x26) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Table 41. AutoBrkCfg1 Register (0x27) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Table 42. HptRAMAddr Register (0x28) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Table 43. HptRAMDataH Register (0x29) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Table 44. HptRAMDataM Register (0x2A). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Table 45. HptRAMDataL Register (0x2B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Table 46. LEDStepDirect Register (0x2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Table 47. LED0Direct Register (0x2D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Table 48. LED1Direct Register (0x2E). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Table 49. LED2Direct Register (0x2F). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Table 50. HptDirect0 Register (0x30). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Table 51. HptDirect1 Register (0x31) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Table 52. HptRTI2CAmp Register (0x32). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Table 53. HptPatRAMAddr Register (0x33). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Table 54. 0x01 – GPIO_Config_Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Table 55. GPIO_Config_Write Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Table 56. 0x02 – GPIO_Config_Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Table 57. GPIO_Config_Read Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Table 58. 0x03 – GPIO_Control_Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Table 59. GPIO_Control_Write Response. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Table 60. 0x04 – GPIO_Control_Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Table 61. GPIO_Control_Read Response. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Table 62. 0x06 – MPC_Config_Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Table 63. MPC_Config_Write Response. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Table 64. 0x07 – MPC_Config_Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Table 65. MPC_Config_Read Response. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Table 66. 0x10 – InputCurrent_Config_Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Table 67. InputCurrent_Config_Write Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Table 68. 0x11 – InputCurrent_Config_Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Table 69. InputCurrent_Config_Read Response. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Table 70. 0x12 – ThermalShutdown_Config_Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
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Table 71. ThermalShutdown_Config_Read Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Table 72. 0x14 – Charger_Config_Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Table 73. Charger_Config_Write Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Table 74. 0x15 – Charger_Config_Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Table 75. Charger_Config_Read Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Table 76. 0x16 – ChargerThermalLimits_Config_Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Table 77. ChargerThermalLimits_Config_Write Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Table 78. 0x17 – ChargerThermalLimits_Config_Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Table 79. ChargerThermalLimits_Config_Read Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Table 80. 0x18 – ChargerThermalReg_Config_Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Table 81. ChargerThermalReg_Config_Write Response. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Table 82. 0x19 – ChargerThermalReg_Config_Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Table 83. ChargerThermalReg_Config_Read Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Table 84. 0x1A – Charger_ControlWrite . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Table 85. Charger_ControlWrite Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Table 86. 0x1B – Charger_ControlRead . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Table 87. Charger_Control_Read Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Table 88. 0x1C – Charger_ JEITAHyst_ControlWrite . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Table 89. Charger_JEITAHyst_ControlWrite Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Table 90. Charger_JEITAHyst_ControlRead . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Table 91. Charger_JEITAHyst_ControlRead Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Table 92. 0x30 – Bst_Config_Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Table 93. Bst_Config_Write Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Table 94. 0x31 – Bst_Config_Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Table 95. Bst_Config_Read Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Table 96. 0x35 – Buck1_Config_Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Table 97. Buck1_Config_Write Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Table 98. 0x36 – Buck1_Config_Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Table 99. Buck1_Config_Read Response. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110
Table 100. 0x37 – Buck1_DVSConfig_Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110
Table 101. Buck1_DVSConfig_Write Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111
Table 102. 0x3A – Buck2_Config_Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111
Table 103. Buck2_Config_Write Response. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112
Table 104. 0x3B – Buck2_Config_Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112
Table 105. Buck2_Config_Read Response. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113
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Table 106. 0x3C – Buck2_DVSConfig_Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113
Table 107. Buck2_DVSConfig_Write Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114
Table 108. 0x40 – LDO1_Config_Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114
Table 109. LDO1_Config_Write Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115
Table 110. 0x41 – LDO1_Config_Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115
Table 111. LDO1_Config_Read Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115
Table 112. 0x42 – LDO2_Config_Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116
Table 113. LDO2_Config_Write Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117
Table 114. 0x43 – LDO2_Config_Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117
Table 115. LDO2_Config_Read Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117
Table 116. 0x46 – ChargePump_Config_Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118
Table 117. ChargePump_Config_Write Response. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118
Table 118. 0x47 – ChargePump_Config_Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118
Table 119. ChargePump_Config_Read Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119
Table 120. 0x48 – SFOUT_Config_Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119
Table 121. SFOUT_Config_Write Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Table 122. 0x49 – SFOUT_Config_Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Table 123. SFOUT_Config_Read Response. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Table 124. 0x50 – MONMux_Config_Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121
Table 125. MONMux_Config_Write Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121
Table 126. 0x51 – MONMux_Config_Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121
Table 127. MONMux_Config_Read Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Table 128. 0x53 – ADC_Measure_Launch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Table 129. ADC_Measure_Launch Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Table 130. 0x70 – BBst_Config_Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Table 131. BBst_Config_Write Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Table 132. 0x71 – BBst_Config_Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Table 133. BBst_Config_Read Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Table 134. 0xA0 – Hpt_Config_Write0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Table 135. Hpt_Config_Write0 Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Table 136. 0xA1 – Hpt_Config_Read0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Table 137. Hpt_Config_Read0 Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Table 138. 0xA2 – Hpt_Config_Write1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Table 139. Hpt_Config_Write1 Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Table 140. 0xA3 – Hpt_Config_Read1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
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Table 141. Hpt_Config_Read1 Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Table 142. 0xA4— Hpt_Config_Write2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Table 143. Hpt_Config_Write2 Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Table 144. 0xA5 – Hpt_Config_Read2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Table 145. Hpt_Config_Read2 Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Table 146. 0xA6 – Hpt_SYS_Threshold_Config_Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Table 147. Hpt_SYS_threshold_Config_Write Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Table 148. 0xA7—Hpt_SYS_threshold_Config_Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131
Table 149. Hpt_SYS_threshold_Config_Read Response. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131
Table 150. 0xA8 – Hpt_Lock_Config_Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131
Table 151. Hpt_Lock_Config_Write Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131
Table 152. 0xA9 – Hpt_Lock_Config_Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131
Table 153. Hpt_Lock_Config_Read Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131
Table 154. 0xAA – Hpt_EMF_Threshold_Config_Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Table 155. Hpt_EMF_Threshold_Config_Write Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Table 156. 0xAB – Hpt_EMF_Threshold_Config_Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Table 157. HPT_EMF_Threshold_Config_Read Response. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Table 158. 0xAC—HPT_Autotune . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Table 159. HPT_Autotune Response. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Table 160. 0xAD— HPT_SetMode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Table 161. HPT_SetMode Response. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Table 162. 0xAE— HPT_SetInitialGuess. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Table 163. HPT_SetInitialGuess Response. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Table 164. 0xAF— HPT_SetInitialDelay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
Table 165. HPT_SetInitialDelay Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
Table 166. 0xB0—HPT_SetWindow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
Table 167. HPT_SetWindow Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
Table 168. 0xB1 – HPT_SetBackEMFCycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
Table 169. HPT_SetBackEMFCycle Response. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
Table 170. 0xB2—HPT_SetFullScale. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
Table 171. HPT_SetFullScale Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
Maxim Integrated
│ 10
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MAX20353
PMIC with Ultra-Low Iq Regulators, Charger,
Fuel Gauge, and Haptic Driver for
Small Li+ Systems
(
)
LIST OF TABLES CONTINUED
Table 172. 0xB3—Hpt_SetHptPattern. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
Table 173. Hpt_SetHptPattern Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
Table 174. 0xB4—Hpt_SetGain. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
Table 175. Hpt_SetGain Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
Table 176. 0xB5—HPT_SetLock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Table 177. Hpt_SetLock Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Table 178. 0xB6—Hpt_ReadResonanceFrequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Table 179. Hpt_ReadResonanceFrequency Response. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Table 180. 0xB7—Hpt_SetTimeout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Table 181. Hpt_SetTimeout Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Table 182. 0xB8—Hpt_GetTimeout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Table 183. Hpt_GetTimeout Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Table 184. 0xB9—Hpt_SetBlankingWindow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Table 185. Hpt_SetBlankingWindow Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Table 186. 0xBA—Hpt_SetZCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Table 187. Hpt_SetZCC Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Table 188. 0x80—PowerOff_Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
Table 189. PowerOff_Command Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
Table 190. 0x81 – SoftReset_Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
Table 191. SoftReset_Command Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
Table 192. 0x82—Hard-Reset_Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Table 193. Hard-Reset_Command Response. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Table 194. 0x83—StayOn_Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Table 195. 0x83—StayOn_Command Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
Table 196. 0x84—PowerOff_Command_Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
Table 197. PowerOff_Command_Delay Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
Table 198. Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .141
Table 199. Haptic Driver Recommended Default Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
Table 200. Haptic Driver Recommended Default Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
Table 201. Register Bit Default Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .147
Table 202. Register Bit Default Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
2
Table 203. I C Direct Register Default Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
Table 204. Read Opcode Default Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
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│ 11
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MAX20353
PMIC with Ultra-Low Iq Regulators, Charger,
Fuel Gauge, and Haptic Driver for
Small Li+ Systems
Absolute Maximum Ratings
BAT, SYS, MON, PFN1, PFN2, THM, INT, RST,
SDA, SCL, CELL, ALRT, CTG, QSTRT, L2IN,
BBOUT ................................................................-0.3V to +6V
VDIG, L1IN...........................................................-0.3V to +2.2V
CHGIN......................................................................-6V to +30V
CAP, SFOUT ..........................-0.3V to min(|CHGIN| + 0.3, +6)V
TPU ...........................................................-0.3V to VDIG + 0.3V
SET..............................................................-0.3V to BAT + 0.3V
MPC0, MPC1, MPC2, MPC3, MPC4, DRP,
BSTHVLX to BSTOUT ..........................................-22V to +0.1V
BBHVLX .................................-0.3V to min (BBOUT + 0.3, +6)V
AGND, DGND, BK1GND, BK2GND, BSTGND,
HDGND, BBGND to GSUB ..............................-0.3V to +0.3V
Continuous Current into BAT,
SYS, CHGIN......................................... -1000mA to +1000mA
Continuous Current into DRP, DRN ............. -600mA to +600mA
Continuous Current into Any Other Terminal...-100mA to +100mA
Continuous Power Dissipation (multilayer board
DRN, BK1LX, BK2LX, BK1OUT, BK2OUT,
at +70°C): 7 x 8 Array 56-Ball, 3.71mm x
CPP, BSTLVLX, BBLVLX........................ -0.3V to SYS + 0.3V
L1OUT........................................................-0.3V to L1IN + 0.3V
L2OUT........................................................-0.3V to L2IN + 0.3V
CPP .................................................... CPN – 0.3V to CPN + 6V
4.21mm, 0.5mm pitch WLP (derate 29.98mW/°C)....2399mW
Operating Temperature Range........................... -40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range............................ -65°C to +150°C
CPOUT............................... CPP – 0.3V to min(CPP + 6, +12)V
BSTHVLX, BSTOUT, LED0, LED1, LED2.............-0.3V to +22V
Lead Temperature (soldering, 10s) .................................+300°C
Soldering Temperature (reflow).......................................+260°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Package Information
PACKAGE TYPE: 56 WLP
Package Code
W563A4+1
Outline Number
21-100104
Land Pattern Number
Refer to Application Note 1891
THERMAL RESISTANCE, FOUR-LAYER BOARD
Junction to Ambient (θ
)
33.35°C/W
JA
For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”,
“#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing
pertains to the package regardless of RoHS status.
Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer board.
For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.
Maxim Integrated
│ 12
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MAX20353
PMIC with Ultra-Low Iq Regulators, Charger,
Fuel Gauge, and Haptic Driver for
Small Li+ Systems
Electrical Characteristics
(V
= +3.7V, T = -20°C to +70°C, unless otherwise noted. Typical values are at T = +25°C. C
= 1µF, C
= 1µF, C
= 1µF,
= 27nF,
BAT
A
A
L2IN
SFOUT
VDIG
CAP
C
C
= 10µF, C
= 10µF, C
= 10µF, C
= 1µF, C
= 1µF, C
= 1µF, C
= 1µF, C
SYS_EFF
BK1OUT_EFF
BK2OUT_EFF
L1IN
L1OUT
L2OUT
CPP
= 10µF, C
= 10µF, L
= 2.2µH, L
= 2.2µH, L
= 4.7µH, L
= 4.7µH). (Note 1)
BSTOUT_EFF
BBOUT_EFF
BK1
BK2
BSTOUT
BBOUT
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
GLOBAL SUPPLY CURRENT
V
= +5V, On state, charger
CHGIN
Charger Input Current
I
disabled, Buck1 enabled, no LDO
1.1
mA
CHGIN
enabled
V
V
= 0V, Off state, LDO2 disabled
0.4
1.6
CHGIN
= 0V, Off state, LDO2 enabled,
CHGIN
L2IN connected to BAT
V
= 0V, On state, all blocks
CHGIN
2.4
3.4
3.9
BAT Input Current
I
disabled, Fuel Gauge off
µA
BAT
V
= 0V, On state, Buck1 enabled,
CHGIN
Fuel Gauge off
V
= 0V, On state, Buck1 and
CHGIN
Buck2 enabled, Fuel Gauge off
INTERNAL SUPPLIES, BIAS, AND UVLOS
V
Rising
V
CCINTUVLO
VCCINT_
UVLO_R
(Note 2)
(Note 2)
(Note 2)
2.25
2.2
2.45
2.4
50
2.75
2.7
V
V
Threshold
V
Falling
V
CCINTUVLO
VCCINT_
UVLO_F
Threshold
V
Threshold
V
CCINTUVLO
VCCINT_
UVLO_H
mV
Hysteresis
Internal CAP Regulator
CAPOK Rising Threshold
CAPOK Falling Threshold
V
V
V
V
= +4.3V to +28V
3.75
3.15
2.6
4.1
3.4
2.8
4.55
3.6
3
V
V
V
CAP
CAP_OK_R
CHGIN
V
= V
= V
CHGIN
CHGIN
CAP
V
CAP_OK_F
CAP
CAPOK Threshold
Hysteresis
V
600
4.15
3.3
mV
V
CAP_OK_H
V
CHGIN_
DET_R
V
Rising Threshold
4
4.3
3.4
BDET
V
CHGIN_
DET_F
V
V
Falling Threshold
Threshold
3.2
V
BDET
V
BDET
CHGIN_
DET_H
850
mV
Hysteresis
t
CHGIN insertion
28
20
CHGIN Detection
Debounce Time
CHGIN_DET_R
ms
t
CHGIN detachment
CHGIN_DET_F
SYSUVLO Rising
Threshold
V
2.65
2.6
2.75
2.7
50
2.85
2.8
V
V
SYS_UVLO_R
SYSUVLO Falling
Threshold
V
SYS_UVLO_F
SYS_UVLO_H
SYSUVLO Threshold
Hysteresis
V
mV
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│ 13
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MAX20353
PMIC with Ultra-Low Iq Regulators, Charger,
Fuel Gauge, and Haptic Driver for
Small Li+ Systems
Electrical Characteristics (continued)
(V
= +3.7V, T = -20°C to +70°C, unless otherwise noted. Typical values are at T = +25°C. C
= 1µF, C
= 1µF, C
= 1µF,
= 27nF,
BAT
A
A
L2IN
SFOUT
VDIG
CAP
C
C
= 10µF, C
= 10µF, C
= 10µF, C
= 1µF, C
= 1µF, C
= 1µF, C
= 1µF, C
SYS_EFF
BK1OUT_EFF
BK2OUT_EFF
L1IN
L1OUT
L2OUT
CPP
= 10µF, C
= 10µF, L
= 2.2µH, L
= 2.2µH, L
= 4.7µH, L
= 4.7µH). (Note 1)
BSTOUT_EFF
BBOUT_EFF
BK1
BK2
BSTOUT
BBOUT
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
From 200mA to 1.6A in 200mA steps,
Device specific (See Table 201)
BATOC Rising Threshold
I
I
t
-40
+40
%
BAT_OC_R
BATOC Threshold
Hysteresis
6
%
BAT_OC_H
BAT_OC_D
BATOC Rising Debounce
Time
9
10
11
2.0
ms
V
Internal V
Regulator
V
1.68
1.61
1.8
DIG
VDIG
V
Rising
DIGUVLO
V
1.71
V
VDIG_UVLO_R
Threshold
V
Falling
DIGUVLO
V
1.51
1.61
V
VDIG_UVLO_F
Threshold
V
Threshold
DIGUVLO
V
100
mV
VDIG_UVLO_H
Hysteresis
SFOUT
SFOUTVSet = 0 (+5V),
4.85
3.15
5
5.15
3.45
V
= +6V, I
= 0mA
CHGIN
SFOUT
SFOUTVSet = 0 (+5V),
= +5V, I
4.9
3.3
V
= 15mA
SFOUT
CHGIN
SFOUT LDO Voltage
SFOUT OVP Voltage
V
V
SFOUT
SFOUTVSet = 1 (+3.3V),
= +5V, I = 0mA
V
CHGIN
SFOUT
SFOUTVSet = 1 (+3.3V),
= +5V, I = 15mA
3.29
V
CHGIN
SFOUT
SFOUT LDO is turned off above
threshold
V
CHGIN
V
V
SFOUT_OVP
V
CHGIN_OV_R
OV_R
150
SFOUT Thermal Limit
SAR ADC AND MON
ADC Quiescent Current
T
°C
SFOUT_LIM
I
Conversion running
30
µA
ADC_Q
ADC SYS Divider
Resistance
R
ADC_SYS_
DIV
SYS conversion running
2.2
MΩ
ADC MON Divider
Resistance
R
ADC_MON_
DIV
MON conversion running
CHGIN conversion running
CPOUT conversion running
BSTOUT conversion running
2.2
1.1
MΩ
MΩ
MΩ
MΩ
mV
ADC CHGIN Divider
Resistance
R
ADC_CHGIN_
DIV
ADC CPOUT Divider
Resistance
R
R
ADC_CPOUT_
DIV
0.82
0.89
21.57
ADC BSTOUT Divider
Resistance
ADC_BSTOUT
DIV
ADC SYS Least
Significant Bit
V
ADC_SYS_
LSB
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│ 14
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MAX20353
PMIC with Ultra-Low Iq Regulators, Charger,
Fuel Gauge, and Haptic Driver for
Small Li+ Systems
Electrical Characteristics (continued)
(V
= +3.7V, T = -20°C to +70°C, unless otherwise noted. Typical values are at T = +25°C. C
= 1µF, C
= 1µF, C
= 1µF,
= 27nF,
BAT
A
A
L2IN
SFOUT
VDIG
CAP
C
C
= 10µF, C
= 10µF, C
= 10µF, C
= 1µF, C
= 1µF, C
= 1µF, C
= 1µF, C
SYS_EFF
BK1OUT_EFF
BK2OUT_EFF
L1IN
L1OUT
L2OUT
CPP
= 10µF, C
= 10µF, L
= 2.2µH, L
= 2.2µH, L
= 4.7µH, L
= 4.7µH). (Note 1)
BSTOUT_EFF
BBOUT_EFF
BK1
BK2
BSTOUT
BBOUT
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
ADC MON Least
Significant Bit
V
ADC_MON_
LSB
21.57
mV
ADC THM Least
Significant Bit
V
ADC_THM_
LSB
0.39
32.35
32.35
82.35
%V
DIG
ADC CHGIN Least
Significant Bit
V
ADC_CHGIN_
LSB
mV
ADC CPOUT Least
Significant Bit
V
ADC_CPOUT_
LSB
mV
mV
ADC BSTOUT Least
Significant Bit
V
ADC_
BSTOUT_LSB
V
= +2.6V
-55
-96
-35
-96
+55
+96
+35
+96
ADC SYS Absolute Sensing
Worst-Case Accuracy
V
SYS
SYS
MON
MON
ADC_SYS_
mV
mV
V
V
V
= +5.5V
= +1.0V
= +5.5V
ACC
ADC MON Absolute Sensing
Worst-Case Accuracy
V
ADC_MON_
ACC
ADC THM Percentage
Sensing Worst-Case
Accuracy
V
ADC_THM_
ACC
V
= (5 to 95)%V
-1.539
+1.539
%V
DIG
THM
DIG
ADC CHGIN Absolute
Sensing Worst-Case
Accuracy
V
V
V
= +3.0V
= +8.0V
= +5.0V
-70
-139
-97
+70
+139
+97
CHGIN
CHGIN
CPOUT
V
ADC_CHGIN_
ACC
mV
mV
ADC CPOUT Absolute
Sensing Worst-Case
Accuracy
V
ADC_CPOUT_
ACC
V
= +6.6V
-119
+119
CPOUT
ADC BSTOUT Absolute
Sensing Worst-Case
Accuracy
V
V
= +3.0V
-122
-359
+122
+359
BSTOUT
V
ADC_
BSTOUT_ACC
mV
µs
= +21.0V
BSTOUT
1.1ms (typ) additional delay prior to
each 1st conversion.
ADC Conversion Time
t
83
ADC_CONV
THM Input Leakage
I
-1
+1
µA
LK_THM
TPU Switch Resistance
R
1mA max load on TPU
4
Ω
TPU_SW
No load on MON
pin. Inputs: BAT,
SYS, BK1OUT,
BK2OUT, L1OUT,
L2OUT, SFOUT,
BBOUT
MonRatioCfg = 00
MonRatioCfg = 01
MonRatioCfg = 10
MonRatioCfg = 11
100
50
33.33
25
MON Multiplexer Output
Ratio
V
%
MON_DIV_RT
Maxim Integrated
│ 15
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MAX20353
PMIC with Ultra-Low Iq Regulators, Charger,
Fuel Gauge, and Haptic Driver for
Small Li+ Systems
Electrical Characteristics (continued)
(V
= +3.7V, T = -20°C to +70°C, unless otherwise noted. Typical values are at T = +25°C. C
= 1µF, C
= 1µF, C
= 1µF,
= 27nF,
BAT
A
A
L2IN
SFOUT
VDIG
CAP
C
C
= 10µF, C
= 10µF, C
= 10µF, C
= 1µF, C
= 1µF, C
= 1µF, C
= 1µF, C
SYS_EFF
BK1OUT_EFF
BK2OUT_EFF
L1IN
L1OUT
L2OUT
CPP
= 10µF, C
= 10µF, L
= 2.2µH, L
= 2.2µH, L
= 4.7µH, L
= 4.7µH). (Note 1)
BSTOUT_EFF
BBOUT_EFF
BK1
BK2
BSTOUT
BBOUT
PARAMETER
SYMBOL
CONDITIONS
100µA load on
MIN
TYP
MAX
UNITS
MON pin. Inputs:
BAT, SYS,
BK2OUT, BK1OUT, MonRatioCfg = 00
L2OUT, L1OUT,
5.5
SFOUT, BBOUT
MON Multiplexer Output
Impedance
R
MON_DIV
kΩ
kΩ
No load on MON
pin. Inputs: BAT,
SYS, BK2OUT,
BK1OUT, L2OUT,
L1OUT, SFOUT,
BBOUT
MonRatioCfg = 01
MonRatioCfg = 10
MonRatioCfg = 11
31
28
24
59
MON Multiplexer Off State
Pulldown Resistance
MON disabled, pulldown resistance
enabled
R
MON_OFF_PD
OVP AND INPUT CURRENT LIMITER
Allowed CHGIN Input
Voltage Range
V
-5.5
7.2
+28
7.8
V
V
CHGIN_RNG
CHGIN Overvoltage
Rising Threshold
SFOUT LDO is turned off above this
threshold
V
V
7.5
CHGIN_OV_R
CHGIN_OV_H
CHGIN Overvoltage
Threshold Hysteresis
200
145
275
mV
mV
mV
CHGIN Valid Trip Point
V
V
- V
SYS
30
290
CHGN-SYS_TP
CHGIN
CHGIN Valid Trip Point
Hysteresis
V
CHGIN-SYS_
TP-HYS
Input Overcurrent Max
ILimMax = 0/1, device specific
(see Table 201)
I
450/1000
mA
LIM_MAX
Limit (t < t
)
ILIM_BLANK
ILimCnt = 000
ILimCnt = 001
ILimCnt = 010
ILimCnt = 011
ILimCnt = 100
ILimCnt = 101
ILimCnt = 110
ILimCnt = 111
50
90
150
200
300
400
450
1000
Input Current Limit
(t > t
I
mA
LIM
)
ILIM_BLANK
Maxim Integrated
│ 16
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MAX20353
PMIC with Ultra-Low Iq Regulators, Charger,
Fuel Gauge, and Haptic Driver for
Small Li+ Systems
Electrical Characteristics (continued)
(V
= +3.7V, T = -20°C to +70°C, unless otherwise noted. Typical values are at T = +25°C. C
= 1µF, C
= 1µF, C
= 1µF,
= 27nF,
BAT
A
A
L2IN
SFOUT
VDIG
CAP
C
C
= 10µF, C
= 10µF, C
= 10µF, C
= 1µF, C
= 1µF, C
= 1µF, C
= 1µF, C
SYS_EFF
BK1OUT_EFF
BK2OUT_EFF
L1IN
L1OUT
L2OUT
CPP
= 10µF, C
= 10µF, L
= 2.2µH, L
= 2.2µH, L
= 4.7µH, L
= 4.7µH). (Note 1)
BSTOUT_EFF
BBOUT_EFF
BK1
BK2
BSTOUT
BBOUT
PARAMETER
SYMBOL
CONDITIONS
ILimBlank = 00
MIN
TYP
0.003
0.5
MAX
UNITS
ILimBlank = 01
ILimBlank = 10
ILimBlank = 11
Input Current Limit
Blanking Time
t
ms
ILIM_BLANK
1
10
V
V
V
BAT_
BAT_
BAT_
SYS Regulation Voltage
V
+
0.14
+
+
0.26
V
SYS_REG
REG
REG
0.2
REG
SYS Regulation Voltage
Dropout
V
R
40
mV
Ω
CHGIN-SYS
CHGIN to SYS On-
Resistance
0.37
1
0.66
CHGIN-SYS
Input Current Soft-Start
Time
I
ms
LIM_SFT
50
60
70
80
90
100
110
120
0.5
1
Thermal Shutdown
Temperature
See T
in table 201 for
CHGIN_SHDN
T
°C
CHGIN_SHDN
device specific threshold
TShdnTmo = 01
TShdnTmo = 10
TShdnTmo = 11
Thermal Shutdown
Timeout
T
CHGIN_SHDN_
TO
s
5
BATTERY CHARGER
BAT to SYS On
Resistance
V
= 4.2V,
= 300mA
BAT
R
80
140
mΩ
°C
BAT-SYS
I
BAT
Thermal Regulation
Temperature
T
CHGIN_
T
CHG_LIM
- 3
SHDN
BAT-to-SYS Switch On
Threshold
V
SYS falling
10
-3
22
35
0
mV
mV
mV
BAT-SYS_ON
BAT-to-SYS Switch Off
Threshold
V
SYS rising
-1.5
100
BAT-SYS_OFF
SYS-BAT Charge Current
Reduction Threshold
Measured as V
SysMinVlt = 000, V
- V
,
SYS
BAT
V
SYS-BAT_LIM
> 3.6V
BAT
Maxim Integrated
│ 17
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MAX20353
PMIC with Ultra-Low Iq Regulators, Charger,
Fuel Gauge, and Haptic Driver for
Small Li+ Systems
Electrical Characteristics (continued)
(V
= +3.7V, T = -20°C to +70°C, unless otherwise noted. Typical values are at T = +25°C. C
= 1µF, C
= 1µF, C
= 1µF,
= 27nF,
BAT
A
A
L2IN
SFOUT
VDIG
CAP
C
C
= 10µF, C
= 10µF, C
= 10µF, C
= 1µF, C
= 1µF, C
= 1µF, C
= 1µF, C
SYS_EFF
BK1OUT_EFF
BK2OUT_EFF
L1IN
L1OUT
L2OUT
CPP
= 10µF, C
= 10µF, L
= 2.2µH, L
= 2.2µH, L
= 4.7µH, L
= 4.7µH). (Note 1)
BSTOUT_EFF
BBOUT_EFF
BK1
BK2
BSTOUT
BBOUT
PARAMETER
SYMBOL
CONDITIONS
SysMinVlt = 000
MIN
TYP
3.6
3.7
3.8
3.9
4.0
4.1
4.2
4.3
MAX
UNITS
SysMinVlt = 001
SysMinVlt = 010
SysMinVlt = 011
SysMinVlt = 100
SysMinVlt = 101
SysMinVlt = 110
SysMinVlt = 111
Minimum SYS Voltage
V
V
SYS_LIM
V
< 3.4V
BAT
Charger Current Soft-Start
Time
t
1
ms
CHG_SOFT
IPChg = 00
5
IPChg = 01
9
10
11
Precharge Current
I
%I
FCHG
PCHG
IPChg = 10
20
IPChg = 11
30
VPChg = 000
VPChg = 001
VPChg = 010
VPChg = 011
VPChg = 100
VPChg = 101
VPChg = 110
VPChg = 111
2.1
2.25
2.4
2.55
2.7
2.85
3
Precharge Threshold
V
V
BAT_PCHG
3.15
Precharge Threshold
Hysteresis
V
BAT_PCHG_
HYS
90
mV
SET Current Gain
Factor
K
V
2000
A/A
V
SET
SET
SET Regulation Voltage
1
5
R
R
R
= 400kΩ
= 40kΩ
= 4kΩ
SET
SET
SET
BAT Charge Current
Set Range
I
45
50
500
55
mA
FCHG
Maxim Integrated
│ 18
www.maximintegrated.com
MAX20353
PMIC with Ultra-Low Iq Regulators, Charger,
Fuel Gauge, and Haptic Driver for
Small Li+ Systems
Electrical Characteristics (continued)
(V
= +3.7V, T = -20°C to +70°C, unless otherwise noted. Typical values are at T = +25°C. C
= 1µF, C
= 1µF, C
= 1µF,
= 27nF,
BAT
A
A
L2IN
SFOUT
VDIG
CAP
C
C
= 10µF, C
= 10µF, C
= 10µF, C
= 1µF, C
= 1µF, C
= 1µF, C
= 1µF, C
SYS_EFF
BK1OUT_EFF
BK2OUT_EFF
L1IN
L1OUT
L2OUT
CPP
= 10µF, C
= 10µF, L
= 2.2µH, L
= 2.2µH, L
= 4.7µH, L
= 4.7µH). (Note 1)
BSTOUT_EFF
BBOUT_EFF
BK1
BK2
BSTOUT
BBOUT
PARAMETER
SYMBOL
CONDITIONS
BatReg = 0000
MIN
TYP
4.05
4.10
4.15
4.20
4.20
4.25
4.30
4.35
4.40
4.45
4.50
4.55
4.60
70
MAX
UNITS
BatReg = 0001
BatReg = 0010
BatReg = 0011, T = 25°C
A
4.179
4.158
4.221
4.242
BatReg = 0011
BatReg = 0100
BatReg = 0101
BatReg = 0110
BatReg = 0111
BatReg = 1000
BatReg = 1001
BatReg = 1010
BatReg = 1011
BatReChg = 00
BatReChg = 01
BatReChg = 10
BatReChg = 11
PChgTmr = 00
PChgTmr = 01
PChgTmr = 10
PChgTmr = 11
FChgTmr = 00
FChgTmr = 01
FChgTmr = 10
FChgTmr = 11
ChgDone = 00
ChgDone = 01
ChgDone = 10
ChgDone = 11
Battery Regulation
Voltage
V
V
BAT_REG
120
170
220
30
Battery Recharge
Threshold
V
mV
min
min
BAT_RECHG
60
Maximum Precharge
Time
t
PCHG
120
240
75
150
300
600
5
Maximum Fast Charge
Time
t
FCHG
8.5
-10
10
11.5
10
Charge Done
Qualification
I
%I
FCHG
CHG_DONE
20
30
Timer Accuracy
t
%
CHG_ACC
Timer Extend Threshold
(1/2 Fast Charge
t
See Figure 5
50
%I
FCHG
CHG_EXT
Current Comparator)
Maxim Integrated
│ 19
www.maximintegrated.com
MAX20353
PMIC with Ultra-Low Iq Regulators, Charger,
Fuel Gauge, and Haptic Driver for
Small Li+ Systems
Electrical Characteristics (continued)
(V
= +3.7V, T = -20°C to +70°C, unless otherwise noted. Typical values are at T = +25°C. C
= 1µF, C
= 1µF, C
= 1µF,
= 27nF,
BAT
A
A
L2IN
SFOUT
VDIG
CAP
C
C
= 10µF, C
= 10µF, C
= 10µF, C
= 1µF, C
= 1µF, C
= 1µF, C
= 1µF, C
SYS_EFF
BK1OUT_EFF
BK2OUT_EFF
L1IN
L1OUT
L2OUT
CPP
= 10µF, C
= 10µF, L
= 2.2µH, L
= 2.2µH, L
= 4.7µH, L
= 4.7µH). (Note 1)
BSTOUT_EFF
BBOUT_EFF
BK1
BK2
BSTOUT
BBOUT
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Timer Suspend Threshold
(1/5 Fast Charge Current
Comparator)
t
See Figure 5
20
%I
FCHG
CHG_SUS
THM Percentage Sensing
Worst Case Accuracy
V
see ADC
section
ADC_THM_
ACC
V
= (5 to 95)%V
DIG
THM
Cool/Cold Threshold
Hysteresis
Falling, LSB = 0.39%V
0 to 31
0 to 31
LSB
LSB
DIG
DIG
Warm/Hot Threshold
Hysteresis
Rising, LSB = 0.39%V
Cold/Cool/Room/Warm/
HotBatReg = 00
BatReg
– 150mV
Cold/Cool/Room/Warm/
HotBatReg = 01
BatReg
– 100mV
Battery Regulation
Voltage Reduction Due to
Battery Pack Temperature
V
BAT_REG_
RED
V
Cold/Cool/Room/Warm/
HotBatReg = 10
BatReg
– 50mV
Cold/Cool/Room/Warm/
HotBatReg = 11
BatReg
Cold/Cool/Room/Warm/
HotFChg = 000
I
I
I
I
I
I
I
x
x
x
x
x
x
x
FCHG
0.2
Cold/Cool/Room/Warm/
HotFChg = 001
FCHG
0.3
Cold/Cool/Room/Warm/
HotFChg = 010
FCHG
0.4
Cold/Cool/Room/Warm/
HotFChg = 011
FCHG
0.5
Fast Charge Current
Reduction Due to Battery
Pack Temperature
I
mA
FCHG_FACT
Cold/Cool/Room/Warm/
HotFChg = 100
FCHG
0.6
Cold/Cool/Room/Warm/
HotFChg = 101
FCHG
0.7
Cold/Cool/Room/Warm/
HotFChg = 110
FCHG
0.8
Cold/Cool/Room/Warm/
HotFChg = 111
I
FCHG
BAT UVLO Threshold
V
1.9
2.05
50
2.2
V
BAT_UVLO
BAT UVLO Threshold
Hysteresis
V
BAT_UVLO_
HYS
mV
Maxim Integrated
│ 20
www.maximintegrated.com
MAX20353
PMIC with Ultra-Low Iq Regulators, Charger,
Fuel Gauge, and Haptic Driver for
Small Li+ Systems
Electrical Characteristics (continued)
(V
= +3.7V, T = -20°C to +70°C, unless otherwise noted. Typical values are at T = +25°C. C
= 1µF, C
= 1µF, C
= 1µF,
= 27nF,
BAT
A
A
L2IN
SFOUT
VDIG
CAP
C
C
= 10µF, C
= 10µF, C
= 10µF, C
= 1µF, C
= 1µF, C
= 1µF, C
= 1µF, C
SYS_EFF
BK1OUT_EFF
BK2OUT_EFF
L1IN
L1OUT
L2OUT
CPP
= 10µF, C
= 10µF, L
= 2.2µH, L
= 2.2µH, L
= 4.7µH, L
= 4.7µH). (Note 1)
BSTOUT_EFF
BBOUT_EFF
BK1
BK2
BSTOUT
BBOUT
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
BUCK1
Input Voltage Range
Output Voltage Range
Output Voltage UVLO
V
Input voltage = V
2.7
0.7
5.5
2.275
0.62
V
V
V
BK1IN
SYS
V
25mV step resolution
Rising edge, typical hysteresis = 70mV
= 0, V = +3.7V,
BK1OUT
V
UVLO_BK1
I
BK1OUT
SYS
Quiescent Supply Current
I
0.8
1.3
µA
µA
Q_BK1
Buck1VSet = 0b010100 (+1.2V)
Dropout Quiescent Supply
Current
I
I
= 0, V – V ≤ +0.1V
250
Q_DO_BK1
BK1OUT
SYS
BK1OUT
Shutdown Supply Current
with Active Discharge
Enabled
I
Buck 1 disabled, Buck1ActDsc = 1
60
10
µA
%
SD_BK1
Output Average Voltage
Accuracy
ACC_BK1
-2.6
+2.6
375
I
= 10mA
BK1OUT
Buck1ISet = 0100 (100mA),
= 2.2µF,
Peak-to-Peak Ripple
V
C
mV
RPP_BK1
BK1OUT_EFF
I
= 1mA
BK1OUT
25mA step resolution. The accuracy of
Peak Current Set Range
I
codes below 50mA is limited by t
0
mA
PSET_BK1
ON_
MIN_BK1
V
Buck1ISet = 0110 (150mA),
LOAD_REG_
BK1
Load Regulation Error
Line Regulation Error
-3
2
%
Buck1IAdptEn = 1, I
= 300mA
BK1OUT
V
V
= +1.2V, V
from +2.7V
LINE_REG_
BK1
BK1OUT
SYS
mV
to +5.5V
V
= +3.7V, Buck1VSet = 010100
SYS
Maximum Operative
Output Current
(+1.2V), Buck1ISet = 1111 (375mA),
Buck1IAdptEn = 1, load regulation
error = -5%
I
350
mA
BK1_MAX_1111
BK1OUT Pulldown
Current
I
Buck 1 Enabled
100
7
200
nA
PD_BK1_E
BK1OUT Pulldown
Resistance with Buck
Disabled
Buck 1 Disabled, V
Buck1VSet = 000000 (+0.7V)
= +3.6V,
SYS
I
MΩ
PD_BK1_D
R
Buck1FETScale = 0
Buck1FETScale = 1
Buck1FETScale = 0
Buck1FETScale = 1
0.35
0.7
0.49
0.98
0.4
P_ON_BK1
PMOS On-Resistance
NMOS On-Resistance
Ω
R
R
P_ON_BK1_FS
R
0.25
0.5
N_ON_BK1
Ω
Ω
0.7
N_ON_BK1_FS
Freewheeling On-
Resistance
R
V
= +3.7V,
ON_BK1_
FRWHL
SYS
7
12
Buck1VSet = 010100 (+1.2V)
Maxim Integrated
│ 21
www.maximintegrated.com
MAX20353
PMIC with Ultra-Low Iq Regulators, Charger,
Fuel Gauge, and Haptic Driver for
Small Li+ Systems
Electrical Characteristics (continued)
(V
= +3.7V, T = -20°C to +70°C, unless otherwise noted. Typical values are at T = +25°C. C
= 1µF, C
= 1µF, C
= 1µF,
= 27nF,
BAT
A
A
L2IN
SFOUT
VDIG
CAP
C
C
= 10µF, C
= 10µF, C
= 10µF, C
= 1µF, C
= 1µF, C
= 1µF, C
= 1µF, C
SYS_EFF
BK1OUT_EFF
BK2OUT_EFF
L1IN
L1OUT
L2OUT
CPP
= 10µF, C
= 10µF, L
= 2.2µH, L
= 2.2µH, L
= 4.7µH, L
= 4.7µH). (Note 1)
BSTOUT_EFF
BBOUT_EFF
BK1
BK2
BSTOUT
BBOUT
PARAMETER
Minimum t
SYMBOL
CONDITIONS
MIN
TYP
60
95
3
MAX
UNITS
ns
t
95
ON
ON_MIN_BK1
Maximum Duty Cycle
Switching Frequency
D_MAX_BK1
FREQ_BK1
Buck1IAdptEn = 1
%
Load regulation error = -5%
Buck1ISet = 0110 (150mA),
MHz
Average Current During
Short-Circuit to GND
I
I
100
mA
µA
SHRT_BK1
Buck1IAdptEn = 1, V
= 0V
BK1OUT
BK1LX Leakage
Current
I
Buck 1 disabled
1
LK_BK1LX
Active Discharge
Current
V
= +1.2V
8
19
10
58
35
mA
kΩ
ms
ACTD_BK1
BK1OUT
Passive Discharge
Resistance
R
PSV_BK1
Full Turn-On Time
t
Time from enable to full current capability
Buck1VSet = 010100 (+1.2V), I
ON_BK1
BK1OUT
Efficiency
EFFIC_BK1
= 10mA, Buck1ISet = 0111 (175mA),
88.5
%
Inductor: Murata DFE201610E-2R2M
SLW_BK1
Buck1LowEMI = 0
Buck1LowEMI = 1
2
BK1LX Rising/Falling
Slew Rate
V/ns
°C
SLW_BK1_L
0.5
Thermal Shutdown
Threshold
T
140
SHDN_BK1
BUCK2
Input Voltage Range
Output Voltage Range
Output Voltage UVLO
V
Input voltage = V
2.7
0.7
5.5
V
V
V
BK2IN
SYS
V
50mV step resolution
3.85
0.62
BK2OUT
V
Rising edge, typical hysteresis = 70mV
UVLO_BK2
I
= 0mA, V
= +3.7V,
BK2OUT
SYS
Quiescent Supply Current
I
0.9
1.4
µA
µA
Q_BK2
Buck2VSet = 001010 (+1.2V)
I = 0mA, V – V
BK2OUT
Dropout Quiescent Supply
Current
SYS
BK2OUT
I
250
Q_DO_BK2
≤ +0.1V
Shutdown Supply Current
with Active Discharge
Enabled
I
Buck 2 disabled, Buck2ActDsc = 1
60
µA
SD_BK2
Output Average Voltage
Accuracy
I
= 10mA, Buck2VSet ≤ 110100
BK2OUT
ACC_BK2
-2.6
+2.6
375
%
(+3.3V)
Buck2ISet = 0100 (100mA),
= 2.2µF, I
Peak-to-Peak Ripple
V
10
mV
RPP_BK2
C
= 1mA
BK2OUT
BK2OUT_EFF
25mA step resolution. The accuracy of
codes below 50mA is limited by t
Peak Current Set Range
I
0
mA
PSET_BK2
ON_
MIN_BK2
Maxim Integrated
│ 22
www.maximintegrated.com
MAX20353
PMIC with Ultra-Low Iq Regulators, Charger,
Fuel Gauge, and Haptic Driver for
Small Li+ Systems
Electrical Characteristics (continued)
(V
= +3.7V, T = -20°C to +70°C, unless otherwise noted. Typical values are at T = +25°C. C
= 1µF, C
= 1µF, C
= 1µF,
= 27nF,
BAT
A
A
L2IN
SFOUT
VDIG
CAP
C
C
= 10µF, C
= 10µF, C
= 10µF, C
= 1µF, C
= 1µF, C
= 1µF, C
= 1µF, C
SYS_EFF
BK1OUT_EFF
BK2OUT_EFF
L1IN
L1OUT
L2OUT
CPP
= 10µF, C
= 10µF, L
= 2.2µH, L
= 2.2µH, L
= 4.7µH, L
= 4.7µH). (Note 1)
BSTOUT_EFF
BBOUT_EFF
BK1
BK2
BSTOUT
BBOUT
PARAMETER
SYMBOL
CONDITIONS
Buck2ISet = 0110 (150mA),
Buck2IAdptEn = 1, I
MIN
TYP
MAX
UNITS
V
LOAD_REG_
BK2
Load Regulation Error
Line Regulation Error
-3
%
= 300mA
BK2OUT
V
V
= +1.2V, V
from +2.7V
LINE_REG_
BK2
BK2OUT
SYS
2
mV
mA
to +5.5V
V
= +3.7V, Buck2VSet = 001010
SYS
Maximum Operative
Output Current
(+1.2V) Buck2ISet = 1111 (375mA),
Buck2IAdptEn = 1, load regulation
error = -5%
I
350
BK2_MAX_1111
BK2OUT Pulldown
Current
I
Buck 2 enabled
200
3.5
400
nA
PD_BK2_E
BK2OUT Pulldown
Resistance with Buck
Disabled
Buck 2 disabled, V
Buck2VSet = 000000 (+0.7V)
= +3.6V,
SYS
I
MΩ
PD_BK2_D
R
Buck2FETScale = 0
Buck2FETScale = 1
Buck2FETScale = 0
Buck2FETScale = 1
0.35
0.7
0.49
0.98
0.4
P_ON_BK2
PMOS On-Resistance
NMOS On-Resistance
Ω
R
R
P_ON_BK2_FS
R
0.25
0.5
N_ON_BK2
N_ON_BK2_FS
Ω
Ω
0.7
Freewheeling
On-Resistance
R
V
= +3.7V,
ON_BK2_
FRWHL
SYS
7
12
95
Buck2VSet = 001010 (+1.2V)
Minimum t
t
60
95
3
ns
%
ON
ON_MIN_BK2
Maximum Duty Cycle
Switching Frequency
D_MAX_BK2
FREQ_BK2
Buck2IAdptEn = 1
Load regulation error = -5%
Buck2ISet = 0110 (150mA),
MHz
Average Current During
Short-Circuit to GND
I
100
mA
SHRT_BK2
Buck2IAdptEn = 1, V
= 0V
BK2OUT
BK2LX Leakage Current
Active Discharge Current
I
Buck 2 disabled
1
µA
LK_BK2LX
I
V
= +1.2V
8
19
10
35
mA
ACTD_BK2
BK2OUT
Passive Discharge
Resistance
R
kΩ
PSV_BK2
Full Turn-On Time
t
Time from enable to full current capability
Buck2VSet = 001010 (+1.2V), I
58
ms
ON_BUCK2
BK2OUT
Efficiency
EFFIC_BK2
= 10mA, Buck2ISet = 0111 (175mA),
88.5
%
Inductor: Murata DFE201610E-2R2M
SLW_BK2
Buck2LowEMI = 0
Buck2LowEMI = 1
2
BK2LX Rising/Falling
Slew Rate
V/ns
°C
SLW_BK2_L
0.5
Thermal Shutdown
Threshold
T
140
SHDN_BK2
Maxim Integrated
│ 23
www.maximintegrated.com
MAX20353
PMIC with Ultra-Low Iq Regulators, Charger,
Fuel Gauge, and Haptic Driver for
Small Li+ Systems
Electrical Characteristics (continued)
(V
= +3.7V, T = -20°C to +70°C, unless otherwise noted. Typical values are at T = +25°C. C
= 1µF, C
= 1µF, C
= 1µF,
= 27nF,
BAT
A
A
L2IN
SFOUT
VDIG
CAP
C
C
= 10µF, C
= 10µF, C
= 10µF, C
= 1µF, C
= 1µF, C
= 1µF, C
= 1µF, C
SYS_EFF
BK1OUT_EFF
BK2OUT_EFF
L1IN
L1OUT
L2OUT
CPP
= 10µF, C
= 10µF, L
= 2.2µH, L
= 2.2µH, L
= 4.7µH, L
= 4.7µH). (Note 1)
BSTOUT_EFF
BBOUT_EFF
BK1
BK2
BSTOUT
BBOUT
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
HVBOOST
Input Voltage Range
Output Voltage Range
V
Input voltage = V
2.7
5
5.5
20
V
V
BSTIN
SYS
V
250mV step resolution
BSTOUT
V
BSTOUT_
UVLO
Output Voltage UVLO
V
- V
-2.7
-2.2
2.4
-1.6
9
V
µA
%
BSTOUT
SYS
I
= 0mA, V
= +3.7V,
BSTOUT
SYS
BstVSet = 000000 (+5V), T = 25°C
A
Quiescent Supply Current
I
Q_BST
I
= 0mA, V
= +3.7V,
BSTOUT
SYS
106
+2
BstVSet = 000000 (+5V)
Output Average Voltage
Accuracy
ACC_BST
I
= 1mA
-2
BSTOUT
BstISet = 1010 (350mA),
BstVSet = 011100 (+12V),
Peak-to-Peak Ripple
V
5
mV
RPP_BST
C
= 10µF, L = 4.7µH,
BSTOUT_EFF
I
= 1mA
BSTOUT
Peak Current Set Range
DC Load Regulation Error
I
25mA step resolution
100
475
mA
%
PSET_BST
BstVSet = 011100 (+12V), I
25mA, BstISet = 1000 (300mA),
BstIAdptEn = 1
=
BSTOUT
V
LOAD_REG_
BST
0.3
V
BstVSet = 000110 (+6.5V), V
+2.7V to +5.5V
from
SYS
LINE_REG_
BST
DC Line Regulation Error
4
mV
mW
MΩ
Ω
Maximum Operative
Output Power
BstISet = 1000 (300mA),
BstIAdptEn = 1
P
300
700
10
MAX_BST
BSTOUT Pulldown
Resistance
R
-3% Load Reg Error
BSTOUT
True Shutdown PMOS
On-Resistance
R
I
I
= 100mA
= 100mA
0.15
0.45
0.22
0.7
ON_TS
BSTOUT
BSTOUT
Boost Freewheeling
NMOS On-Resistance
R
Ω
N_ONFRW_N
R
BstFETScale = 0, I
BstFETScale = 1, I
= 100mA
= 100mA
0.55
1.1
0.9
1.8
Boost NMOS On-
Resistance
ONBST_N
BSTOUT
Ω
R
ONBST_NFS
BSTOUT
Schottky Diode Forward
Voltage
V
I
V
= 100mA, V
-
BE_
SCHOTTKY
BSTOUT
BSTHVLX
0.2
0.4
0.6
80
V
BSTOUT
Freewheeling On-
Resistance
R
ONBST_
I
= 100mA
50
65
Ω
BSTOUT
FRWHL
Minimum t
t
ns
ON
ON_BST_MIN
Maxim Integrated
│ 24
www.maximintegrated.com
MAX20353
PMIC with Ultra-Low Iq Regulators, Charger,
Fuel Gauge, and Haptic Driver for
Small Li+ Systems
Electrical Characteristics (continued)
(V
= +3.7V, T = -20°C to +70°C, unless otherwise noted. Typical values are at T = +25°C. C
= 1µF, C
= 1µF, C
= 1µF,
= 27nF,
BAT
A
A
L2IN
SFOUT
VDIG
CAP
C
C
= 10µF, C
= 10µF, C
= 10µF, C
= 1µF, C
= 1µF, C
= 1µF, C
= 1µF, C
SYS_EFF
BK1OUT_EFF
BK2OUT_EFF
L1IN
L1OUT
L2OUT
CPP
= 10µF, C
= 10µF, L
= 2.2µH, L
= 2.2µH, L
= 4.7µH, L
= 4.7µH). (Note 1)
BSTOUT_EFF
BBOUT_EFF
BK1
BK2
BSTOUT
BBOUT
PARAMETER
SYMBOL
CONDITIONS
regulation error = -150mV.
MIN
TYP
MAX
UNITS
FREQ_BST_
MX
V
BSTOUT
Max Switching Frequency
1.7
3.5
5.5
MHz
BstISet = 100mA, BstIAdptEn = 0.
Max Peak Current
Setting Extra Budget with
BstIAdptEn = 1
BstIAdptEn = 1, V
error = -200mV
regulation
BSTOUT
Δ
150
250
200
450
mA
mA
IP_MAX
Short-Circuit Current
Limit Difference vs. Peak
Current Setting
Δ
BstIAdptEn = 0
130
250
IBST_SHRT
BSTHVLX Leakage
Current
I
Boost disabled
Boost disabled
1
1
µA
µA
LK_BSTHVLX
BSTLVLX Leakage
Current
I
LK_BSTLVLX
Passive Discharge
Resistance
R
10
12.5
13
kΩ
mA
mA
ms
BSTPSV
Linear BSTOUT
Precharge Current
I
L_BSTOUT_
PRCH
V
V
from 0 to V
– 0.4V
5
20
BSTOUT
SYS
Switching Precharge
Inductor Current
I
from V
– 0.4V to final
SW_BSTOUT_
PRCH
BSTOUT
SYS
regulation voltage
Time from enable to full
current capability
Full Turn-On Time
t
100
ON_BST
BstVSet = 011100 (+12V), I
=
BSTOUT
EFFIC_12
EFFIC_15
EFFIC_5
20mA, BstISet = 1000 (300mA), Inductor:
Murata DFE201610E-4R7M
85
83
76
73
BstVSet = 101000 (+15V), I
=
BSTOUT
2mA, BstISet = 1000 (300mA), Inductor:
Murata DFE201610E-4R7M
Efficiency
%
BstVSet = 000000 (+5V), I
=
BSTOUT
10µA, BstISet = 0010 (150mA), Inductor:
Murata DFE201610E-4R7M
BstVSet = 000110 (+6.5V), I
=
BSTOUT
EFFIC_6P5
10µA, BstISet = 0010 (150mA), Inductor:
Murata DFE201610E-4R7M
BHVLX Rising/Falling
Slew Rate
SLW_BST
HVLX
2
V/ns
°C
Thermal Shutdown
Threshold
T
125
SHDN_BST
Maxim Integrated
│ 25
www.maximintegrated.com
MAX20353
PMIC with Ultra-Low Iq Regulators, Charger,
Fuel Gauge, and Haptic Driver for
Small Li+ Systems
Electrical Characteristics (continued)
(V
= +3.7V, T = -20°C to +70°C, unless otherwise noted. Typical values are at T = +25°C. C
= 1µF, C
= 1µF, C
= 1µF,
= 27nF,
BAT
A
A
L2IN
SFOUT
VDIG
CAP
C
C
= 10µF, C
= 10µF, C
= 10µF, C
= 1µF, C
= 1µF, C
= 1µF, C
= 1µF, C
SYS_EFF
BK1OUT_EFF
BK2OUT_EFF
L1IN
L1OUT
L2OUT
CPP
= 10µF, C
= 10µF, L
= 2.2µH, L
= 2.2µH, L
= 4.7µH, L
= 4.7µH). (Note 1)
BSTOUT_EFF
BBOUT_EFF
BK1
BK2
BSTOUT
BBOUT
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
BUCK-BOOST
Input Voltage Range
V
Input voltage = V
2.7
5.5
2.1
V
BBIN
SYS
Quiescent Supply Current
I
I
= 0µA, V
= +4V
1.3
µA
Q_BB
BBOUT
BBOUT
Maximum Output
Operative Power
P
V
> +3V
250
2.5
-3
mW
V
MAX_BBOUT
SYS
Output Voltage Set Range
V
100mV step
= 1mA, C
5
3
BBOUT
Average Output Voltage
Accuracy
ACC_BBOUT
I
≥ 10µF
BBOUT_EFF
%
BBOUT
V
= +2.7V to +5.5V, I
= 10µA,
SYS
BBOUT
V
LINE_REG_
BB
Line Regulation Error
Load Regulation Error
Line Transient
BBstVSet = 001111 (+4V), BBstISet =
0010 (100mA)
-1
+0.3
+1
%/V
mV/A
mV
BBstVSet = 001111 (+4V), I
to 50mA, BBstISet = 0010 (100mA)
= 10µA
BBOUT
100
310
V
LOAD_REG_
BB
BBstVSet = 001111 (+4V), I = 10µA
to 100mA, BBstISet = 0010(100mA)
BBOUT
BBstVSet = 001111 (+4V), BBstISet =
V
LINE_TRAN_
BB
0010 (100mA), V
0.2µs rise time
from +2.7V to +5V,
15
9
SYS
I
= 0mA to 10mA, 200ns rise time,
BBOUT
BBstVSet = 001111 (+4V), BBstISet =
0010 (100mA)
V
LOAD_
TRAN_BB
Load Transient
mV
I
= 0mA to 100mA, 200ns rise
BBOUT
time, V
= 001111 (+4V), BBstISet
31
BBOUT
= 0010 (100mA)
Oscillator Frequency
f
1.8
2
2.2
MHz
OSC_BB
R
R
High-side PMOS Buck FET
Low-side NMOS Buck FET
High-side PMOS Boost FET
0.15
0.22
0.22
0.36
ON_PBK_BB
ON_NBK_BB
R
R
0.21
0.24
8
0.31
0.4
11
ON_PBST_BB
ON_NBST_BB
ON_FRWH_BB
(V
= +4V)
Output FETs R
ON
Ω
BBOUT
Low-side NMOS Boost FET
EMI improve FET between BBHVLX/
BBLVLX
R
Passive Discharge
Pulldown Resistance
R
BBstPasDsc = 1
10
19
kΩ
PDL_BB
Active Discharge Current
I
BBstActDsc = 1, V
= +1.5V
6
38
mA
ACTDL_BB
BBOUT
Maxim Integrated
│ 26
www.maximintegrated.com
MAX20353
PMIC with Ultra-Low Iq Regulators, Charger,
Fuel Gauge, and Haptic Driver for
Small Li+ Systems
Electrical Characteristics (continued)
(V
= +3.7V, T = -20°C to +70°C, unless otherwise noted. Typical values are at T = +25°C. C
= 1µF, C
= 1µF, C
= 1µF,
= 27nF,
BAT
A
A
L2IN
SFOUT
VDIG
CAP
C
C
= 10µF, C
= 10µF, C
= 10µF, C
= 1µF, C
= 1µF, C
= 1µF, C
= 1µF, C
SYS_EFF
BK1OUT_EFF
BK2OUT_EFF
L1IN
L1OUT
L2OUT
CPP
= 10µF, C
= 10µF, L
= 2.2µH, L
= 2.2µH, L
= 4.7µH, L
= 4.7µH). (Note 1)
BSTOUT_EFF
BBOUT_EFF
BK1
BK2
BSTOUT
BBOUT
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
100
1.75
14
MAX
UNITS
ms
Time from enable to full current
capability
Turn-On Time
t
ON_BB
UVLO On BBOUT
Precharge Current
V
1.65
6
1.9
24
V
BBOUT_UVLO
Precharge current. V
= +2.7V,
SYS
I
mA
PC_BB
V
= +1.65V
BBOUT
BBstVSet = 001111 (+4V), V
<
SYS
Pulse Mode Input Current
Limit
I
V
– 0.5V, f
= f /10,
6.6
mA
PLS_IN
BBOUT
SW
OSC_BBST
BBstISet = 0010 (100mA)
Pulse Mode Switching
Period Ratio
T_RATIO
f
/f 128 steps
10
138
1.1
OSC_BB SW
Average Current During
Short-Circuit to GND
I
V
= 0V
0.4
0.75
150
10
A
SHRT_BB
BBOUT
Thermal Shutdown
Threshold
T
T rising
°C
°C
SHDN_BB
J
Thermal Shutdown
Hysteresis
T
SHDN_
HYST_BB
LDO1 (Typical values are at V
= +1.2V, V
= +1V)
L1IN
L1OUT
LDO mode
1
2
Input Voltage Range
V
V
L1IN
Switch mode
0.7
2
I
I
= 0µA
1
2.1
0.7
L1OUT
L1OUT
= 0µA, Switch mode
0.35
Quiescent Supply Current
I
µA
Q_L1
LDO enabled, I
LDO1_MPC2CNT = 1, MPC2 high
= 0µA,
L1OUT
0.7
0.015
2.4
1.35
2.5
Output Leakage
I
V
= GND, LDO 1 disabled
µA
µA
LK_L1OUT
L1OUT
Quiescent Supply Current
in Dropout
I
= 0µA, V
= +1.2V, LDO1VSet
L1OUT
L1IN
I
4.2
Q_L1_DRP
= 0x1D (+1.225V)
Maximum Output Current
Output Voltage
I
50
mA
V
L1OUT_MAX
V
25mV step resolution
0.5
1.95
+3.9
L1OUT
(V
+ 0.2V) ≤ V
≤ +2V,
L1OUT
L1IN
Output Accuracy
ACC_LDO1
-3.4
%
I
= 1mA
L1OUT
V
= +1V, LDO1VSet = 0x14 (+1V),
= 50mA
L1IN
Dropout Voltage
V
63
mV
%/V
DRP_L1
I
L1OUT
Line Regulation Error
Load Regulation Error
V
V
= (V
+ 0.2V) to +2V
-0.5
+0.5
0.013
LINE_REG_L1
L1IN
L1OUT
+1V ≤ V
≤ +2V ,
L1IN
V
0.003
%/mA
LOAD_REG_L1
I
= 100µA to 50mA
L1OUT
V
V
I
= +1V to +2V, 200ns rise time
= +1V to +2V, 1µs rise time
= 0 to 10mA, 200ns rise time
±45
±25
80
V
L1IN
LINE_TRAN_
L1
Line Transient
Load Transient
mV
mV
L1IN
V
L1OUT
L1OUT
LOAD_TRAN_
L1
I
= 0 to 50mA, 200ns rise time
130
Maxim Integrated
│ 27
www.maximintegrated.com
MAX20353
PMIC with Ultra-Low Iq Regulators, Charger,
Fuel Gauge, and Haptic Driver for
Small Li+ Systems
Electrical Characteristics (continued)
(V
= +3.7V, T = -20°C to +70°C, unless otherwise noted. Typical values are at T = +25°C. C
= 1µF, C
= 1µF, C
= 1µF,
= 27nF,
BAT
A
A
L2IN
SFOUT
VDIG
CAP
C
C
= 10µF, C
= 10µF, C
= 10µF, C
= 1µF, C
= 1µF, C
= 1µF, C
= 1µF, C
SYS_EFF
BK1OUT_EFF
BK2OUT_EFF
L1IN
L1OUT
L2OUT
CPP
= 10µF, C
= 10µF, L
= 2.2µH, L
= 2.2µH, L
= 4.7µH, L
= 4.7µH). (Note 1)
BSTOUT_EFF
BBOUT_EFF
BK1
BK2
BSTOUT
BBOUT
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
10
MAX
UNITS
kΩ
Passive Discharge
Resistance
R
5
7
15
55
PDL_L1
Active Discharge Current
I
25
mA
ACTDL_L1
V
= +1V, I
L1OUT
L1IN
1.02
= 50mA
Switch Mode
On-Resistance
R
Switch mode
Ω
ON_L1
V
= +0.7V,
= 1mA
L1IN
2.7
I
L1OUT
I
= 0mA, time from 10% to 90%
L1OUT
0.38
of LDO1VSet
Turn-On Time
t
ms
ON_L1
I
= 0mA, time from 10% to 90%
L1OUT
0.065
310
of V
, Switch mode
L1IN
V
V
= +1.2V, V
= 0V
165
160
405
400
L1IN
L1OUT
L1OUT
Short Circuit Current
Limit
I
mA
= +1.2V, V
= 0V, Switch
SHRT_L1
L1IN
305
mode
Thermal Shutdown
Temperature
T
T rising
J
150
20
°C
°C
SHDN_L1
Thermal Shutdown
Temperature Hysteresis
T
SHDN_
HYS_L1
V
V
V
= +1.8V
= +1V
120
95
L1OUT
L1OUT
L1OUT
10Hz to 100kHz,
Output Noise
µV
RMS
V
V
= +2V
L1IN
= +0.5V
70
V
V
V
falling
rising
0.53
0.77
0.78
L1IN_UVLO_F
L1IN
UVLO
V
1
L1IN_UVLO_R
L1IN
LDO2 (Typical values at V
Input Voltage Range
= +3.7V, V
= +3V)
L2IN
L2OUT
LDO mode
1.71
1.2
5.5
5.5
1.7
0.7
V
V
L2IN
Switch mode
I
I
I
= 0µA
1
L2OUT
L2OUT
L2OUT
Quiescent Supply Current
I
µA
µA
Q_L2
= 0µA, Switch mode.
0.35
Quiescent Supply Current
in Dropout
= 0µA, V = +2.9V, LDO2VSet
L2IN
I
2.2
3.7
Q_L2_DRP
= 0x15 (+3V)
Maximum Output Current
Output Voltage
I
V
> +1.8V
100
0.9
mA
V
L2OUT_MAX
L2IN
V
100mV step resolution
(V + 0.5V) ≤ V
4
L2OUT
≤ +5.5V,
L2IN
L2OUT
Output Accuracy
ACC_LDO2
-2.9
+2.9
%
I
= 1mA
L2OUT
V
= +3V, LDO2VSet = 0x16 (+3.1V),
= 100mA
L2IN
100
130
mV
mV
I
L2OUT
Dropout Voltage
V
DRP_L2
V
= +1.85V, LDO2VSet = 0x0A
L2IN
(+1.9V), I
= 100mA
L2OUT
Maxim Integrated
│ 28
www.maximintegrated.com
MAX20353
PMIC with Ultra-Low Iq Regulators, Charger,
Fuel Gauge, and Haptic Driver for
Small Li+ Systems
Electrical Characteristics (continued)
(V
= +3.7V, T = -20°C to +70°C, unless otherwise noted. Typical values are at T = +25°C. C
= 1µF, C
= 1µF, C
= 1µF,
= 27nF,
BAT
A
A
L2IN
SFOUT
VDIG
CAP
C
C
= 10µF, C
= 10µF, C
= 10µF, C
= 1µF, C
= 1µF, C
= 1µF, C
= 1µF, C
SYS_EFF
BK1OUT_EFF
BK2OUT_EFF
L1IN
L1OUT
L2OUT
CPP
= 10µF, C
= 10µF, L
= 2.2µH, L
= 2.2µH, L
= 4.7µH, L
= 4.7µH). (Note 1)
BSTOUT_EFF
BBOUT_EFF
BK1
BK2
BSTOUT
BBOUT
PARAMETER
SYMBOL
CONDITIONS
= (V + 0.5V) to +5.5V
L2OUT
MIN
TYP
MAX
UNITS
Line Regulation Error
V
V
-0.38
+0.38
%/V
LINE_REG_L2
L2IN
V
+1.8V ≤ V
≤ +5.5V
LOAD_REG_
L2
L2IN
Load Regulation Error
0.002
0.005
%/mA
mV
I
= 100µA to 100mA
L2OUT
V
V
= +4V to +5V, 200ns rise time
= +4V to +5V, 1µs rise time
±35
±25
V
L2IN
LINE_TRAN_
L2
Line Transient
Load Transient
L2IN
I
= 0mA to 10mA, 200ns
L2OUT
100
200
rise time
V
LOAD_TRAN_
L2
mV
I
= 0mA to 100mA, 200ns
L2OUT
rise time
Passive Discharge
Resistance
R
5
8
10
22
15
40
kΩ
PDL_L2
Active Discharge Current
I
mA
ACTDL_L2
V
= +2.7V,
= 100mA
L2IN
0.7
I
L2OUT
Switch Mode
On-Resistance
V
L2IN
= +1.8V,
R
Switch mode
1
Ω
ON_L2
ON_L2
I
= 50mA
= +1.2V,
L2OUT
V
L2IN
2.3
I
= 5mA
L2OUT
I
= 0mA, time from 10% to 90%
L2OUT
1.5
of LDO2VSet
Turn-On Time
t
ms
I
= 0mA, time from 10% to 90%
. Switch mode
L2OUT
0.26
360
350
of V
L2IN
V
V
= +2.7V, V
= 0V
= 0V,
225
210
555
540
L2IN
L2OUT
L2OUT
Short Circuit Current
Limit
I
mA
= +2.7V, V
SHRT_L2
L2IN
Switch mode
Thermal Shutdown
Temperature
T
T rising
J
150
20
°C
°C
SHDN_L2
Thermal Shutdown
Temperature Hysteresis
T
SHDN_HYS_L2
V
V
V
V
= +3.3V
150
125
90
L2OUT
L2OUT
L2OUT
L2OUT
10Hz to
100kHz, V
= +5V
= +2.5V
= +1.2V
= +0.9V
Output Noise
UVLO
µV
L2IN
RMS
V
80
V
V
falling
1.05
1.35
1.36
L2IN
V
L2IN_UVLO
rising
1.69
L2IN
Maxim Integrated
│ 29
www.maximintegrated.com
MAX20353
PMIC with Ultra-Low Iq Regulators, Charger,
Fuel Gauge, and Haptic Driver for
Small Li+ Systems
Electrical Characteristics (continued)
(V
= +3.7V, T = -20°C to +70°C, unless otherwise noted. Typical values are at T = +25°C. C
= 1µF, C
= 1µF, C
= 1µF,
= 27nF,
BAT
A
A
L2IN
SFOUT
VDIG
CAP
C
C
= 10µF, C
= 10µF, C
= 10µF, C
= 1µF, C
= 1µF, C
= 1µF, C
= 1µF, C
SYS_EFF
BK1OUT_EFF
BK2OUT_EFF
L1IN
L1OUT
L2OUT
CPP
= 10µF, C
= 10µF, L
= 2.2µH, L
= 2.2µH, L
= 4.7µH, L
= 4.7µH). (Note 1)
BSTOUT_EFF
BBOUT_EFF
BK1
BK2
BSTOUT
BBOUT
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
CHARGE PUMP
Input Voltage
V
Input voltage = V
2.7
5.5
3.5
4.3
V
CPIN
SYS
I
I
I
= 0µA, CPVSet = 1 (+5V)
2
Q_CP_5V
CPOUT
CPOUT
Quiescent Supply Current
µA
I
= 0µA, CPVSet = 0 (+6.6V)
2.2
Q_CP_6.6V
CPVSet = 0, I
= 10µA,
CPOUT
6.6
5
V
> +3.3V
CPOUT Output Voltage
Output Accuracy
V
V
SYS
CPOUT
CPVSet = 1, I
= 10µA
CPOUT
ACC_CP
I
< 120µA, V
> +3.3V
-3
+3
%
CPOUT
SYS
Maximum Operative
Output Current
V
> +3.3V, -5% load
SYS
I
250
µA
CPOUT_MAX
EFF_CP
regulation error
CPVSet = 0 (+6.6V), I
= 10µA,
OUT
Efficiency
79
100
10
%
kHz
kΩ
V
= +3.7V
SYS
Max Charge Pump
Frequency
FREQ_CP
90
110
Passive Discharge
Resistance
R
PSV_CP
HAPTIC DRIVER
Input Voltage
V
Input voltage = V
2.6
5.5
V
HD_IN
SYS
Quiescent Current
I
V
/V
= 0 to V
1300
25
µA
HD_Q
DRP DRN
SYS
H-Bridge PWM Output
Frequency
f
22.5
27.5
kHz
HD_PWM_OUT
H-Bridge PWM Output
Duty Cycle Resolution
D
V
SYS
128
/
HD_PWM_
OUT
7 bits
%V
SYS
HptOffImp = 1
HptOffImp = 0
15
kΩ
H-Bridge Output
Impedance in Off State
R
HD_OFF
R
Ω
HD_ON_LS
H-Bridge Output Leakage
in High-Z State
During back EMF detection,
/V = 0 to V
I
-1
+1
0.5
µA
HD_LK_OUT
V
DRP DRN
SYS
High-side PMOS switch on,
300mA load
R
0.04
0.04
600
0.18
0.18
1000
130
HD_ON_HS
H-Bridge On-Resistance
Ω
Low-side NMOS switch on,
300mA load
R
0.5
HD_ON_LS
HD_OC_THR
HD_OC_HYS
H-Bridge Overcurrent
Protection Threshold
Rising current through high-side
or low-side
I
I
1500
mA
mA
H-Bridge Overcurrent
Protection Hysteresis
Maxim Integrated
│ 30
www.maximintegrated.com
MAX20353
PMIC with Ultra-Low Iq Regulators, Charger,
Fuel Gauge, and Haptic Driver for
Small Li+ Systems
Electrical Characteristics (continued)
(V
= +3.7V, T = -20°C to +70°C, unless otherwise noted. Typical values are at T = +25°C. C
= 1µF, C
= 1µF, C
= 1µF,
= 27nF,
BAT
A
A
L2IN
SFOUT
VDIG
CAP
C
C
= 10µF, C
= 10µF, C
= 10µF, C
= 1µF, C
= 1µF, C
= 1µF, C
= 1µF, C
SYS_EFF
BK1OUT_EFF
BK2OUT_EFF
L1IN
L1OUT
L2OUT
CPP
= 10µF, C
= 10µF, L
= 2.2µH, L
= 2.2µH, L
= 4.7µH, L
= 4.7µH). (Note 1)
BSTOUT_EFF
BBOUT_EFF
BK1
BK2
BSTOUT
BBOUT
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
H-Bridge Thermal
Shutdown Temperature
Threshold
T
HD_SHDN_
THR
Rising temperature
150
°C
H-Bridge Thermal
Shutdown Temperature
Hysteresis
T
HD_SHDN_
HYS
25
°C
PWM Input Frequency
f
10
250
kHz
HD_INPWM
max of
(200k/
IniGss
[11:0],
100)
min of
(800k/
IniGss
[11:0],
LRA Resonance
Frequency Tracking
Range
f
See Haptic Driver section
Hz
ms
HD_LRA
500
)
Time from command to vibration
response. See Haptic Driver section
Startup Latency
t
10
12
HD_START
LED CURRENT SINKS
Maximum Input Voltage
Quiescent Current
V
20
V
IN_LED_MAX
I
All LEDs on, V
= 3.7V
SYS
245
370
15
µA
Q_LED
LEDIStep = 00 (0.6mA steps)
LEDIStep = 01 (1mA steps)
LEDIStep = 10 (1.2mA steps)
0.6
1
Current Sink Setting
Range
I
25
mA
%
LED_RNG
1.2
30
I
= 13mA, T = +25°C,
A
LED_
-2
-4
-5
+2
+4
+5
V
= +0.7V to +20V
LED_
I
= 13mA, V
= +0.7V to +20V
LED_
LED_
LED Current Accuracy
ACC_LED
I
_
0.6mA to 30mA V
_ = +0.7V to
LED
=
,
LED
%
%
+20V, T = 25°C
A
I
_ = 0.6mA to 30mA, V
_ = +0.7V
LED
LED
-6
+6
to +20V
I
= 0.9 x 5mA
110
145
175
160
215
270
0.1
ILED_SET = 5mA, LED_
LED Dropout Voltage
Leakage in Shutdown
V
I
I
= 25mA, I
= 0.9 x 25mA
= 0.9 x 30mA
mV
LED_DROP
LED_SET
LED_SET
LED_
LED_
= 30mA, I
I
V
= +20V
µA
LK_LED
LED_
Open-LED Detection
Threshold
LED_ enabled, LEDIStep = 00,
falling edge
V
61
92
140
mV
LED_DET
Maxim Integrated
│ 31
www.maximintegrated.com
MAX20353
PMIC with Ultra-Low Iq Regulators, Charger,
Fuel Gauge, and Haptic Driver for
Small Li+ Systems
Electrical Characteristics (continued)
(V
= +3.7V, T = -20°C to +70°C, unless otherwise noted. Typical values are at T = +25°C. C
= 1µF, C
= 1µF, C
= 1µF,
= 27nF,
BAT
A
A
L2IN
SFOUT
VDIG
CAP
C
C
= 10µF, C
= 10µF, C
= 10µF, C
= 1µF, C
= 1µF, C
= 1µF, C
= 1µF, C
SYS_EFF
BK1OUT_EFF
BK2OUT_EFF
L1IN
L1OUT
L2OUT
CPP
= 10µF, C
= 10µF, L
= 2.2µH, L
= 2.2µH, L
= 4.7µH, L
= 4.7µH). (Note 1)
BSTOUT_EFF
BBOUT_EFF
BK1
BK2
BSTOUT
BBOUT
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
FUEL GAUGE
Supply Voltage
V
(Note 3)
2.5
4.5
3.48
3.15
2
V
V
CELL
Configuration range, in 40mV steps
Trimmed at 3V
2.28
2.85
Fuel-Gauge SOC Reset
V
RST
(V
Register)
3.0
0.5
RESET
Sleep mode
Hibernate mode, reset comparator
3
5
6
disabled (V
.Dis = 1)
I
I
RESET
DD0
Supply Current
µA
Hibernate mode, reset comparator
enabled (V .Dis = 0)
4
RESET
Active mode
23
40
DD1
ERR
Time Base Accuracy
AD Sample Period
t
Active, hibernate modes (Note 4)
Active mode
-3.5
+3.5
%
ms
s
250
45
Hibernate mode
V
= 3.6V, T = +25°C (Note 5)
-9
+6
CELL
A
Voltage Error
V
mV/cell
mV/cell
ERR
T
= -20°C to +70°C
-23
+20
A
Votlage-Measurement
Resolution
1.25
BAT-to-Cell On-Resistance
Bus Low-Detection Timeout
DIGITAL
R
t
V
= 3.7V
15
30
+1
Ω
ON_ISO
BAT
(Notes 6, 7)
2.125
s
SLEEP
SDA, SCL, MPC_,
PFN_ Input Leakage
Current
Input pullup/pulldown resistances
disabled, input voltage from 0 to +5.5V
I
-1
µA
LK_IO
SDA, SCL, MPC_ Input
Logic-High
V
1.4
V
V
IO_IH
SDA, SCL, MPC_ Input
Logic-Low
V
0.5
IO_IL
0.7 x
PFN_ Input Logic-High
PFN_ Input Logic-Low
V
(Note 2)
(Note 2)
V
PFN_IH
V
CCINT
0.3 x
V
V
PFN_IL
V
CCINT
MPC_, PFN_ Input Pullup
Resistance
R
R
Pullup resistance to V
(Note 2)
CCINT
170
kΩ
kΩ
V
IO_UP
IO_PD
IO_OH
MPC_, PFN_ Input
Pulldown Resistance
170
I
= 1mA, MPC_ configured as push-
V
BK2OU
OH
MPC_ Output Logic-High
V
pull output, pullup voltage is V
– 0.4
BK2OUT
T
Maxim Integrated
│ 32
www.maximintegrated.com
MAX20353
PMIC with Ultra-Low Iq Regulators, Charger,
Fuel Gauge, and Haptic Driver for
Small Li+ Systems
Electrical Characteristics (continued)
(V
= +3.7V, T = -20°C to +70°C, unless otherwise noted. Typical values are at T = +25°C. C
= 1µF, C
= 1µF, C
= 1µF,
= 27nF,
BAT
A
A
L2IN
SFOUT
VDIG
CAP
C
C
= 10µF, C
= 10µF, C
= 10µF, C
= 1µF, C
= 1µF, C
= 1µF, C
= 1µF, C
SYS_EFF
BK1OUT_EFF
BK2OUT_EFF
L1IN
L1OUT
L2OUT
CPP
= 10µF, C
= 10µF, L
= 2.2µH, L
= 2.2µH, L
= 4.7µH, L
= 4.7µH). (Note 1)
BSTOUT_EFF
BBOUT_EFF
BK1
BK2
BSTOUT
BBOUT
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
SDA, RST, INT, MPC_,
PFN_ Output Logic-Low
V
I
= 4mA
OL
0.4
V
IO_OL
SDA, SCL Bus Low-
Detection Current
I
V
= V = +0.4V
SCL
0.2
0.4
µA
PD
SDA
SCL Clock Frequency
f
0
400
kHz
SCL
Bus Free Time Between
a STOP and START
Condition
t
1.3
µs
BUF
START Condition
(repeated) Hold Time
t
0.6
µs
HD_STA
Low Period of SCL Clock
High Period of SCL Clock
t
1.3
0.6
µs
µs
LOW
t
HIGH
Setup Time for a
Repeated START
Condition
t
0.6
µs
SU_STA
Data Hold Time
Data Setup Time
t
0
0.9
µs
µs
HD_DAT
t
100
SU_DAT
Setup Time for a STOP
Condition
t
0.6
50
µs
ns
SU_STO
Spike Pulse Widths
Suppressed by Input Filter
t
SP
Note 1: All devices are 100% production tested at T = +25°C. Limits over the operating temperature range are guaranteed by
A
design.
Note 2: V
is an internal voltage supply generated from either V
or V
. The source is determined by the following:
CCINT
BAT
CAP
IF [(V
> V
AND V
> V
) OR V
> (V
+ V
)]
CHGIN
CHGIN_DET
CAP
CAP_OK
CAP
BAT
THSWOVER
THEN V
= V
CCINT
CAP
ELSE
V
= V
CCINT
BAT
Where V
Note 3: All voltages are referenced to GND.
Note 4: Test performed on unmounted/unsoldered parts.
Note 5: The voltage is trimmed and verified with16x averaging.
Note 6: Fuel Gauge enters shutdown mode after SCL < V and SDA < V for longer than t
= [0-300]mV
THSWOVER
.
IL
IL
SLEEP
Note 7: Guaranteed by design.
Maxim Integrated
│ 33
www.maximintegrated.com
MAX20353
PMIC with Ultra-Low Iq Regulators, Charger,
Fuel Gauge, and Haptic Driver for
Small Li+ Systems
Typical Operating Characteristics
V
= +3.7V, C
= 22µF, C
= 1µF, C
= 1µF, C
= 1µF, C
= 10µF, C
= 15µF, C
= 10µF, C
= 22µF,
L1IN
BAT
SFOUT
VDIG
= 15µF, C
CAP
SYS
= 10µF, C
BK1OUT_EFF
= 27nF, C
BK2OUT_EFF
C
= 10µF, C = 10µF, L
BBOUT_EFF BK1
= 2.2µH,
L2IN
BK2
L1OUT_EFF
L2OUT_EFF
CPP
BSTOUT_EFF
L
= 2.2µH, L
= 4.7µH, L
= 4.7µH, T = +25°C, unless otherwise noted.
BSTOUT
BBOUT
A
IBAT vs. VBAT
ICHG vs. TEMPERATURE
IBAT vs. TEMPERATURE
toc01
toc02
toc03
7
6
5
4
3
2
1
0
16
60
RSET = 40kΩ
BUCKS,
L1IN = B1OUT,
L2IN = BAT
14
50
40
30
20
10
0
BUCKS ON,
L1IN = B1OUT,
L2IN = BAT
12
VBAT = 3.7V
FAST CHARGE
BUCKS ON
10
8
ON MODE,
REGULATORS OFF
ON MODE,
REGULATORS OFF
BUCKS ON
OFF MODE,
LDO2 ON
6
VBAT = 2.7V
PRE CHARGE
4
OFF MODE
60
OFF MODE,
LDO2 ON
OFF MODE
2.7
2
0
3.2
3.7
4.2
-40
-15
10
35
85
-40
-15
10
35
60
85
TEMPERATURE (°C)
TEMPERATURE (°C)
VBAT (V)
IBAT/VBAT vs. TIME
VBAT_REG vs. TEMPERATURE
toc04
toc05
4.30
6
5
4
3
2
1
0
100
90
80
70
60
50
40
30
20
10
0
VCHGIN = 5V
VBAT
4.25
4.20
4.15
4.10
IBAT
150mAhr BATTERY
VPChg = 3.15V
IPChg = 5% IFChg
VCHGIN = 5V
RSET = 40.2kΩ
-40
-15
10
35
60
85
0
50
100
150
200
250
TIME (minutes)
TEMPERATURE (°C)
ISYS vs. VCHGIN
BUCK1 EFFICIENCY vs. LOAD
toc06
toc07
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
100
90
80
70
60
50
40
30
20
10
0
VBAT = 2.7V
VSYS = 3.3V
VSYS = 4.2V
VSYS = 3.7V
Buck1VSet = 1.2V
Buck1ISet = 200mA
Buck1IAdptEn = 1
2
3
4
5
6
7
8
0.001
0.1
10
1000
VCHGIN (V)
IBK1OUT (mA)
Maxim Integrated
│ 34
www.maximintegrated.com
MAX20353
PMIC with Ultra-Low Iq Regulators, Charger,
Fuel Gauge, and Haptic Driver for
Small Li+ Systems
Typical Operating Characteristics (continued)
V
= +3.7V, C
= 22µF, C
= 1µF, C
= 1µF, C
= 1µF, C
= 10µF, C
= 15µF, C
= 10µF, C
= 10µF, L
BBOUT_EFF BK1
= 22µF,
BAT
SFOUT
VDIG
= 15µF, C
CAP
SYS
= 10µF, C
BK1OUT_EFF
= 27nF, C
BK2OUT_EFF
= 10µF, C
L1IN
= 2.2µH,
C
L2IN
BK2
L1OUT_EFF
L2OUT_EFF
CPP
BSTOUT_EFF
L
= 2.2µH, L
= 4.7µH, L
= 4.7µH, T = +25°C, unless otherwise noted.
BSTOUT
BBOUT
A
BUCK1 EFFICIENCY
vs. Buck1ISet[3:0] SETTING
BUCK1 LOAD REGULATION
toc08
toc09
100
95
90
85
80
75
1.22
1.21
1.20
1.19
1.18
1.17
1.16
VSYS = 4.2V
VSYS = 3.7V
VSYS = 3.3V
Buck1VSet = 1.2V
Buck1IAdptEn = 0
IBK1OUT = 10mA
Buck1VSet = 1.2V
Buck1ISet = 200mA
Buck1IAdptEn = 1
1.15
1.14
70
0
0
100
200
IBK1OUT (mA)
300
400
75
150
225
300
375
Buck1ISet (mA)
BUCK1 SWITCHING FREQUENCY
vs. LOAD ADAPTIVE PEAK
CURRENT ENABLED
BUCK1 SWITCHING FREQUENCY
vs. LOAD ADPATIVE PEAK
CURRENT DISABLED
toc10
toc11
3.0
2.5
2.0
1.5
1.0
0.5
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
Buck1VSet = 1.2V
Buck1ISet = 200mA
Buck1IAdptEn = 1
Buck1VSet = 1.2V
Buck1ISet = 200mA
Buck1IAdptEn = 0
VSYS = 3.3V
VSYS = 3.3V
VSYS = 3.7V
VSYS = 4.2V
VSYS = 3.7V
VSYS = 4.2V
0.0
0
100
200
300
400
0
50
100
150
200
IBK1OUT (mA)
IBK1OUT (mA)
BUCK1 LOAD TRANSIENT
BUCK2 EFFICIENCY vs. LOAD
toc12
toc13
100
90
80
70
60
50
40
30
20
10
0
Buck1VSet = 1.2V
VBK1OUT
VSYS = 3.3V
VSYS = 3.7V
10mV/div (AC-
COUPLED)
VSYS = 4.2V
IBK1OUT
50mA/div
Buck2VSet = 1.8V
Buck2ISet = 225mA
Buck2IAdptEn = 1
10ms/div
0.001
0.1
10
1000
IBK2OUT (mA)
Maxim Integrated
│ 35
www.maximintegrated.com
MAX20353
PMIC with Ultra-Low Iq Regulators, Charger,
Fuel Gauge, and Haptic Driver for
Small Li+ Systems
Typical Operating Characteristics (continued)
V
= +3.7V, C
= 22µF, C
= 1µF, C
= 1µF, C
= 1µF, C
= 10µF, C
= 15µF, C
= 10µF, C
= 10µF, L
BBOUT_EFF BK1
= 22µF,
BAT
SFOUT
VDIG
= 15µF, C
CAP
SYS
= 10µF, C
BK1OUT_EFF
= 27nF, C
BK2OUT_EFF
= 10µF, C
L1IN
= 2.2µH,
C
L2IN
BK2
L1OUT_EFF
L2OUT_EFF
CPP
BSTOUT_EFF
L
= 2.2µH, L
= 4.7µH, L
= 4.7µH, T = +25°C, unless otherwise noted.
BSTOUT
BBOUT
A
BUCK2 EFFICIENCY vs.
Buck2ISet[3:0] SETTING
BUCK2 LOAD REGULATION
toc14
toc15
100
98
96
94
92
90
88
86
84
82
80
78
76
74
72
1.83
Buck2VSet = 1.8V
Buck2ISet = 225mA
Buck2IAdptEn = 1
1.82
1.81
1.80
1.79
1.78
1.77
1.76
1.75
VSYS = 4.2V
VSYS = 3.7V
VSYS = 3.3V
Buck2VSet = 1.8V
Buck2IAdptEn = 0
IBK2OUT = 10mA
1.74
1.73
1.72
70
0
75
150
225
300
375
0
100
200
300
400
Buck2ISet (mA)
IBK2OUT (mA)
BUCK2 SWITCHING FREQUENCY
vs. LOAD ADAPTIVE PEAK
CURRENT ENABLED
BUCK2 SWITCHING FREQUENCY
vs. LOAD ADAPTIVE PEAK
CURRENT DISABLED
toc16
toc17
2.5
2.0
1.5
1.0
0.5
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
Buck2VSet = 1.8V
Buck2ISet = 225mA
Buck2IAdptEn = 0
Buck2VSet = 1.8V
Buck2ISet = 225mA
Buck2IAdptEn = 1
VSYS = 4.2V
VSYS = 3.7V
VSYS = 3.3V
VSYS= 3.7V
VSYS = 4.2V
VSYS = 3.3V
0.0
0
100
200
IBK2OUT (mA)
300
400
0
50
100
150
200
IBK2OUT (mA)
BUCK2 LOAD TRANSIENT
BOOST EFFICIENCY vs. LOAD
toc18
toc19
100
90
80
70
60
50
40
30
20
10
0
Buck2VSet = 1.8V
VBAT = 4.2V
BstISet = 275mA
VBK2OUT
10mV/div
(AC-
VBAT = 3.7V
BstISet = 250mA
VBAT = 3.3V
BstISet = 275mA
COUPLED)
IBK2OUT
50mA/div
BoostVSet = 12V
0.001 0.01
0.1
1
10
100
10ms/div
IBSTOUT (mA)
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MAX20353
PMIC with Ultra-Low Iq Regulators, Charger,
Fuel Gauge, and Haptic Driver for
Small Li+ Systems
Typical Operating Characteristics (continued)
V
= +3.7V, C
= 22µF, C
= 1µF, C
= 1µF, C
= 1µF, C
= 10µF, C
= 15µF, C
= 10µF, C
= 22µF,
L1IN
BAT
SFOUT
VDIG
= 15µF, C
CAP
SYS
= 10µF, C
BK1OUT_EFF
= 27nF, C
BK2OUT_EFF
= 10µF, C
C
= 10µF, L
= 2.2µH,
L2IN
BK2
L1OUT_EFF
L2OUT_EFF
CPP
BSTOUT_EFF
BBOUT_EFF
BK1
L
= 2.2µH, L
= 4.7µH, L = 4.7µH, T = +25°C, unless otherwise noted.
BBOUT A
BSTOUT
OPTIMAL BstISEt[3:0] SETTING vs. VBSTOUT
(LBSTOUT = 4.7µH Murata DFE201610E-4R7M
BOOST EFFICIENCY vs. VBSTOUT
IBSTOUT = 10mA)
toc20
toc21
88
87
86
85
84
83
82
81
475
450
425
400
375
350
325
300
275
250
225
200
175
150
125
100
IBSTOUT = 10mA
LBSTOUT = Murata DFE201610E-4R7M
IBSTOUT = 10mA
BstISet = OPTIMAL (SEE TOC21)
80
5
10
15
20
5.0
7.5
10.0
12.5
15.0
17.5
20.0
VBSTOUT (V)
VBSTOUT (V)
BOOST SWITCHING FREQUENCY
vs. LOAD ADAPTIVE PEAK CURRENT ENABLED
1.6
BOOST LOAD REGULATION
toc22
toc23
12.5
12.0
11.5
11.0
10.5
10.0
9.5
VSYS = 4.2V
VSYS = 4.2V
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
VSYS = 3.3V
VSYS = 3.7V
VSYS = 3.7V
VSYS = 3.3V
BstVSet = 12V
BstIAdptEn = 1
BstVSet = 12V
9.0
0
20
40
60
80
100
0
20
40
60
80
100
IBSTOUT (mA)
IBSTOUT (mA)
BOOST SWITCHING FREQUENCY
vs. LOAD ADAPTIVE PEAK CURRENT DISABLED
3.0
BOOST LOAD TRANSIENT
toc24
toc25
Bst2VSet = 12V
VSYS = 4.2V
2.5
2.0
1.5
1.0
0.5
0.0
VBSTOUT
50mV/div
(AC-
COUPLED)
VSYS = 3.3V
VSYS = 3.7V
20mA/div
BstVSet = 12V
BstIAdptEn = 0
IBSTOUT
0
20
40
60
80
100
10ms/div
IBSTOUT (mA)
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MAX20353
PMIC with Ultra-Low Iq Regulators, Charger,
Fuel Gauge, and Haptic Driver for
Small Li+ Systems
Typical Operating Characteristics (continued)
V
= +3.7V, C
= 22µF, C
= 1µF, C
= 1µF, C
= 1µF, C
= 10µF, C
= 15µF, C
= 10µF, C
= 10µF, L
BBOUT_EFF BK1
= 22µF,
BAT
SFOUT
VDIG
= 15µF, C
CAP
SYS
= 10µF, C
BK1OUT_EFF
= 27nF, C
BK2OUT_EFF
= 10µF, C
L1IN
= 2.2µH,
C
L2IN
BK2
L1OUT_EFF
L2OUT_EFF
CPP
BSTOUT_EFF
L
= 2.2µH, L
= 4.7µH, L = 4.7µH, T = +25°C, unless otherwise noted.
BBOUT A
BSTOUT
BUCK-BOOST EFFICIENCY
vs. SYS VOLTAGE
BUCK-BOOST EFFICIENCY vs. LOAD
toc27
toc26
95
90
85
80
75
70
65
60
100
90
80
70
60
50
40
30
20
10
0
VSYS = 3.7V
VSYS = 4.2V
VSYS = 3.3V
55 BBstVSet = 4V
BBst2VSet = 4V
0.001 0.01
IBBOUT = 10mA
50
2.7
3.7
4.7
5.7
0.1
1
10
100
VSYS (V)
IBBOUT (mA)
CHARGE PUMP EFFICIENCY
vs. LOAD 5V SETTING
BUCK-BOOST LOAD TRANSIENT
toc28
toc29
80
70
60
50
40
30
20
10
0
VBBSTOUT
50mV/div
(AC-
VSYS = 3.3V
COUPLED)
VSYS = 3.7V
VSYS = 4.2V
50mA/div
IBBSTOUT
CPVSet = 5V
200 250
BBstVSet = 4V
0
50
100
150
20ms/div
ICPOUT (µA)
CHARGE PUMP EFFICIENCY
vs. LOAD 6.6V SETTING
LDO1 LOAD REGULATION
toc30
toc31
100
90
80
70
60
50
40
30
20
10
1.015
1.010
1.005
1.000
0.995
0.990
0.985
VSYS = 3.3V
VSYS = 3.7V
VSYS = 3.3V
VSYS = 3.7V
VSYS = 4.2V
VSYS = 4.2V
LDO1VSet = 1V
CPVSet = 6.6V
200 250
0
0
50
100
150
0
20
40
60
80
100
ICPOUT (µA)
IL1OUT (mA)
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MAX20353
PMIC with Ultra-Low Iq Regulators, Charger,
Fuel Gauge, and Haptic Driver for
Small Li+ Systems
Typical Operating Characteristics (continued)
V
= +3.7V, C
= 22µF, C
= 1µF, C
= 1µF, C
= 1µF, C
= 10µF, C
= 15µF, C
= 10µF, C
= 10µF, L
BBOUT_EFF BK1
= 22µF,
BAT
SFOUT
VDIG
= 15µF, C
CAP
SYS
= 10µF, C
BK1OUT_EFF
= 27nF, C
BK2OUT_EFF
= 10µF, C
L1IN
= 2.2µH,
C
L2IN
BK2
L1OUT_EFF
L2OUT_EFF
CPP
BSTOUT_EFF
L
= 2.2µH, L
BSTOUT
= 4.7µH, L
= 4.7µH, T = +25°C, unless otherwise noted.
BBOUT
A
LDO2 LOAD REGULATION
LDO1 LOAD TRANSIENT
toc32
toc33
3.015
LDO1VSet = 1V
LDO2VSet = 3V
3.010
3.005
3.000
2.995
2.990
2.985
VL1OUT
50mV/div
(AC-
VSYS = 3.7V
VSYS = 3.3V
COUPLED)
50mA/div
IL1OUT
VSYS = 4.2V
0
20
40
60
80
100
20ms/div
IL2OUT (mA)
TIME TO RESONANCE LOCK
vs. INITIAL GUESS ERROR
(ESTIMATED BY VIBRATION AMPLITUDE)
LDO2 LOAD TRANSIENT
toc34
toc35
800
700
600
500
400
300
200
100
0
LDO2VSet = 3V
LRA = Samsung DMJBRN1030BK
VL2OUT
EmfSkipCyc = 0x01,
WidLpGain = 0x04
EmfSkipCyc = 0x00,
WidLpGain = 0x02
50mV/div
(AC-
COUPLED)
EmfSkipCyc = 0x00,
WidLpGain = 0x03
50mA/div
IL2OUT
-25
-15
-5
5
15
25
20ms/div
INITIAL GUESS ERROR (%)
HAPTIC DRIVER LRA SELF-TUNING
IniGss CLOSE TO RESONANT FREQUENCY
HAPTIC DRIVER LRA SELF-TUNING
ERROR IN IniGss RESONANCE SETTING
toc36
toc37
IniGss = 200Hz
ERROR = -10%
ERROR = 3%
VIBRATION AMPLITUDE
500mV/div
(AC-
COUPLED)
ERROR = 0%
LRA VIBRATION
AMPLITUDE
ERROR = 3%
FREQUENCY = 211.8Hz
DRP
2V/div
ERROR = 10%
100ms/div
NarLpGain = 0x02
40ms/div
WidLpGain = 0x04
EmfSkipCyc = 0x01
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MAX20353
PMIC with Ultra-Low Iq Regulators, Charger,
Fuel Gauge, and Haptic Driver for
Small Li+ Systems
Bump Configuration
TOP VIEW
(BUMP SIDE DOWN)
MAX20353
1
2
3
4
5
6
7
+
DRN
SCL
DRP
HDGND
SYS
L2OUT
BK2GND
BK2LX
A
B
C
D
E
F
SDA
CPP
CPN
CPOUT
L2IN
BK2OUT
LED2
LED1
DGND
PFN1
MPC4
GSUB
MPC1
VDIG
MPC0
CTG
CELL
BBOUT
BBGND
QSTRT
LED0
PFN2
MON
SET
CAP
TPU
AGND
THM
ALRT
RST
BBHVLX
BBLVLX
BSTOUT
SFOUT
BSTGND
INT
MPC3
BAT
MPC2
L1OUT
CHGIN
L1IN
BK1OUT
BK1LX
G
H
BSTHVLX BSTLVLX
SYS
BK1GND
WLP
(3.71mm x 4.21mm)
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MAX20353
PMIC with Ultra-Low Iq Regulators, Charger,
Fuel Gauge, and Haptic Driver for
Small Li+ Systems
Bump Description
BUMP
A1
NAME
DRN
FUNCTION
ERM/LRA Haptic Driver Negative Output.
A2
DRP
ERM/LRA Haptic Driver Positive Output.
Haptic Driver Ground.
A3
HDGND
System Load Connection. Connect to the system load. Both SYS bumps should be connected
on PCB through a low-impedance trace. Bypass common node with a minimum 10µF capacitor
to GND.
A4, H4
SYS
A5
A6
A7
B1
B2
B3
B4
B5
B6
B7
C1
C2
C3
C4
C5
C6
C7
D1
D2
D3
D4
D5
D6
D7
E1
E2
E3
E4
E5
L2OUT
BK2GND
BK2LX
SCL
LDO Output. Bypass with 1µF capacitor to GND.
Buck 2 Ground.
Buck2 Regulator Switch. Connect through 2.2µH inductor to BK2OUT.
2
I C Serial Clock Input.
2
SDA
I C Serial Data Input/Open-Drain Output.
CPP
Charge Pump Capacitor Positive Terminal. Connect 22nF (min), 33nF (max) capacitor to CPN.
Charge Pump Capacitor Negative Terminal. Connect to 22nF (min), 33nF (max) capacitor to CPP.
Charge Pump Output. Bypass with 1µF capacitor to GND.
LDO2 Input. Bypass with 1µF capacitor to GND.
Buck2 Regulator Output. Bypass with 10µF capacitor to GND.
Current Sink Output 2.
CPN
CPOUT
L2IN
BK2OUT
LED2
DGND
MPC4
MPC1
MPC0
CELL
Digital Ground.
Multipurpose Control I/O 4.
Multipurpose Control I/O 1.
Multipurpose Control I/O 0.
Fuel Gauge Voltage. Bypass with 0.1µF capacitor to GND.
Buck-Boost Regulator Output. Bypass with 10µF capacitor to GND.
Current Sink Output 1.
BBOUT
LED1
PFN1
GSUB
VDIG
Configurable Power Mode Control Pin (e.g., KIN).
Substrate Connection. Connect to Ground.
Internal Reference Supply. Bypass with 1µF capacitor to GND.
Fuel Gauge. Connect to GND.
CTG
QSTRT
BBGND
LED0
Fuel Gauge Quick Start Input.
Buck-Boost Ground.
Current Sink Output 0.
PFN2
MON
Configurable Power Mode Control Pin (e.g., KOUT).
Monitor Multiplexer Output.
CAP
Internal Reference Supply. Bypass with 1µF capacitor to GND.
Analog Ground.
AGND
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MAX20353
PMIC with Ultra-Low Iq Regulators, Charger,
Fuel Gauge, and Haptic Driver for
Small Li+ Systems
Bump Description (continued)
BUMP
E6
NAME
ALRT
FUNCTION
Fuel Gauge Alert Output.
E7
BBHVLX
BSTOUT
SFOUT
Buck-Boost Regulator Switch HV side. Connect through a 3.3µH or 4.7µH inductor to BBLVLX.
Boost Regulator Output. Bypass with 10µF capacitor to GND.
F1
F2
Safe Out LDO. Bypass with 1uF capacitor to GND.
External Resistor For Battery Charge Current Level Setting. Do not connect any capacitance on
F3
F4
SET
TPU
this pin; maximum allowed capacitance (C
< 5μs/R
)pF.
SET
SET
Battery Temperature Thermistor Measurement Pullup (Internally Connected To V
During
DIG
Battery Temperature Thermistor Measurement). Do not exceed 1mA load on TPU.
Battery Temperature Thermistor Measurement Connection.
Reset Output. Active-Low, Open-Drain Output.
F5
F6
THM
RST
F7
BBLVLX
BSTGND
INT
Buck-Boost Regulator Switch LV Side. Connect through a 3.3µH or 4.7µH inductor to BBHVLX.
High-Voltage Boost Ground.
G1
G2
G3
G4
G5
G6
G7
H1
H2
Interrupt Open-Drain Output.
MPC3
Multipurpose Control I/O 3.
MPC2
Multipurpose Control I/O 2.
L1OUT
L1IN
LDO1 Output. Bypass with 1µF capacitor to GND.
LDO1 Input. Bypass with 1µF capacitor to GND.
Buck1 Regulator Output. Bypass with 10µF capacitor to GND.
Boost Regulator Switch. Connect through a 4.7µH inductor to BSTLVLX.
Boost Regulator Switch. Connect through a 4.7µH inductor to BSTHVLX.
BK1OUT
BSTHVLX
BSTLVLX
Battery Connection. Connect to positive battery terminal. Bypass with a minimum 1µF capacitor
to GND.
H3
BAT
H5
H6
H7
CHGIN
BK1GND
BK1LX
+28V/-5.5V Protected Charger Input. Bypass with 1µF capacitor to GND.
Buck 1 Ground.
Buck1 Regulator Switch. Connect through a 2.2µH inductor to BK1OUT.
Note: All capacitance values listed in this document refer to effective capacitance. Be sure to specify capacitors that will meet these
requirements under typical operating conditions taking into consideration the effects of voltage and temperature.
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MAX20353
PMIC with Ultra-Low Iq Regulators, Charger,
Fuel Gauge, and Haptic Driver for
Small Li+ Systems
Typical Application Diagram
VIO
ALRT
CTG
RST
ALRT
RST
PFN2
PFN2
FUEL
POWER
QSTRT
CELL
PFN1
VDIG
GAUGE
SWITCH
PFN1
1µF
0.1µF
CAP
TPU
THM
BAT
CHGIN
SET
Li+ BATTERY CHARGER
WITH SMART POWER
SELECTOR
1µF
1µF
1µF
1µF
V
VIO
USB
V
SYS
SFOUT
SYS
L2IN
SAFE LDO
10µF
1µF
V
LDO
HV_LDO /
L2OUT
SW
SCL
SCL
SDA
V
B1
SDA
BK1LX
BUCK 1
2.2µH
INT
BK1OUT
10µF
INT
GPIO
GPIO
GPIO
GPIO
GPIO
MPC 0
MPC 1
MPC 2
MPC 3
MPC 4
CONTROL
L1IN
V
SW
LV_LDO /
SW
L1OUT
1µF
V
B2
BK2LX
BUCK 2
2.2µH
BK2OUT
10µF
MONITOR
MUX
MON
MON
+6.6V
CPOUT
CPP
1µF
CHARGE
PUMP
SAR ADC
27nF
CPN
ERM /LRA
DRP
DRN
BSTLVLX
BSTHVLX
BSTOUT
HAPTIC
DRIVER
4.7µH
BOOST
V
SYS
LED 0
LED 1
LED 2
V
BST
10µF
CURRENT
SINKS
BBLVLX
BBHVLX
BBOUT
4.7µH
BUCK-
BOOST
BUZZER
10µF
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MAX20353
PMIC with Ultra-Low Iq Regulators, Charger,
Fuel Gauge, and Haptic Driver for
Small Li+ Systems
shows basic flow diagrams associated with each mode.
Both PFN pins have a 10ms debounce period to distin-
guish valid inputs followed by a PwrRstCfg dependent
Detailed Description
Power Regulation
The MAX20353 features two high-efficiency, low quiescent
current buck regulators, a buck-boost regulator, a high-
voltage boost regulator, a charge pump, and two low
quiescent current, low-dropout (LDO) linear regulators
that are configurable as load switches. Additionally, a
safe-output LDO is available when there is a valid voltage
present at CHGIN. This SFOUT regulator’s output is
configurable to 3.3V or 5V. Excellent light-load efficiency
allows the switching regulators to run continuously without
significant energy cost. The buck and boost regulators
can operate in a fixed peak current mode for low-current
applications, as well as an adaptive peak current mode to
improve load regulation, extend the high-efficiency range,
and minimize capacitor size when more current is required.
timing to execute the PFN function.
A soft reset sends a 10ms pulse on RST and will either
leave register settings unchanged or reset them to their
default values depending on the device version (see
Table 201 for device settings). A hard reset on any device
initiates a complete Power-On Reset sequence.
The device enters Off mode on cold boot (initial battery
2
attach, V
= 0V) in response to a power-off I C
CHGIN
command, a valid PFN signal based on the PwrRstCfg[3:0]
setting, or in the case of a UVLO condition on SYS.
When the device is in Off mode, the BAT-SYS connection
is opened and all functions are disabled except for the
power function controller and LDO2 (if configured as
always-on).
Dynamic Voltage Scaling (DVS)
The MAX20353 will exit Off mode and turn the main
power back on when there is a qualified PFN1 signal
(PwrRstCfg[3:0] = 0000, 0001, 0110, 0111, 1000) or when
a valid voltage is applied to CHGIN. In the powered-on
state, the SYS node is enabled and other functions can
The buck and LDO regulators feature the ability to change
their output voltages through the AP interface with-
out restarting. This function is called DVS. Additionally,
Buck1 features the ability to quickly change its output
voltage using a combination of MPC inputs and direct
2
be controlled through the I C registers. When the power-
2
I C registers. When this DVS mode is enabled, MPC0
on event occurs, the BAT-to-CELL switch is immediately
closed and, 30ms later, the power path to SYS is enabled.
This delay allows the fuel gauge to take an open cell
measurement before the battery is loaded. Note that there
is a relearning period to determine the state of the battery
whenever the fuel gauge is disconnected. If the typical
use case frequently switches the fuel gauge off and on,
the user may consider permanently connecting CELL-to-
BAT to avoid the relearning period. Figure 2 illustrates a
complete boot sequence coming out of the Off state.
and MPC1 select the Buck1 output voltage from a set of
values defined in registers 0x23─0x25 and by opcode
0x35 (see Table 1). This bypasses the process of writ-
ing Buck1VSet though the AP interface and allows faster
control of the Buck1 voltage. The Buck1 DVS function is
enabled using the Buck1DVSEn bit (register 0x1F[0]).
Power Switch and Reset Control
The MAX20353 features a power switch that provides the
ability to execute a reset sequence or to turn off the main
system power and enter Off mode to extend battery life.
Table 1. Buck1 DVS MPC Values
Shutdown and reset events are triggered by an external
control through the power function (PFN) control inputs,
MPC1
MPC0
Buck1 Voltage
Buck1VSet[5:0]
2
0
0
1
1
0
1
0
1
I C commands, or if other conditions are met. The behavior
of the PFN pins is preconfigured to support one of the
multiple types of wearable application cases. Table 2
describes the behavior of the PFN1 and PFN2 pins based
on the PwrRstCfg[3:0] bits, while Figure 1a thru Figure 1d
Buck1DVSVSet1[5:0]
Buck1DVSVSet2[5:0]
Buck1DVSVSet3[5:0]
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MAX20353
PMIC with Ultra-Low Iq Regulators, Charger,
Fuel Gauge, and Haptic Driver for
Small Li+ Systems
FROM POWER-ON
THROUGH PFN2
THROUGH PFN1
(10ms DEBOUNCE)
(10ms DEBOUNCE)
SHUTDOWN
HOLD RST LOW
TURN OFF RESOURCES
SOFT RESET
HOLD RST LOW
PFN2 RELEASED
+10ms DELAY
WAIT RESOURCES TURN-OFF TIME 20ms
PASSIVE DISCHARGE
OUTPUTS
10ms
OFF
GLOBAL PASSIVE
DISCHARGE OTP
THROUGH PFN1 (10ms DEBOUNCE)
OR CHGIN ATTACH
BOOT
SEQUENCE
PwrRstCfg = 0000, 0001
Figure 1a. PwrRstCfg = 0000 or 0001
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MAX20353
PMIC with Ultra-Low Iq Regulators, Charger,
Fuel Gauge, and Haptic Driver for
Small Li+ Systems
ON
2
THROUGH I C PWR_OFF_CMD
THROUGH PFN1 RISE/FALL
THROUGH PFN2 RISE/FALL
(10ms DEBOUNCE)
OR
(10ms DEBOUNCE)
I2C_PWR_OFF_DELY (30ms DELAY)
SHUTDOWN
HOLD RST LOW
10ms DELAY
HARD RESET
200ms DELAY
SOFT RESET
200ms DELAY
TURN OFF RESOURCES
WAIT RESOURCES TURN OFF TIME 20ms
PASSIVE DISCHARGE
OUTPUTS
HOLD RST LOW
TURN OFF RESOURCES
HOLD RST LOW
10ms
WAIT RESOURCES TURN OFF TIME 20ms
OFF
ACTIVE DISCHARGE
OUTPUTS
GLOBAL PASSIVE
DISCHARGE OTP
CHGIN ATTACH
50ms
BOOT
SEQUENCE
µC SOFTWARE RESET
BOOT
SEQUENCE
PwrRstCfg = 0010, 0011
Figure 1b. PwrRstCfg = 0010 or 0011
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ON
I2C PWR _OFF_CMD
OR
PFN1 HIGH (10ms DEBOUNCE )
PFN2 HIGH (10ms DEBOUNCE )
AND
AND
I2C_PWR _OFF_DLY (30ms DELAY )
CHGIN RISE /FALL (100ms DEBOUNCE )
CHGIN RISE /FALL (100ms DEBOUNCE )
HARD RESET PROCESS
INITIATED
SOFT RESET PROCESS
INITIATED
SHUTDOWN :
HOLD RST LOW,
TURN OFF RESOURCES AND
ENABLE ACTIVE DISCHARGE
15s DELAY
15s EXPIRE
15s DELAY
WAIT RESOURCE TURN -OFF
TIME (20ms)
HOLD RST LOW,
TURN RESOURCES OFF
HOLD RST LOW
WAIT RESOURCE TURN -OFF TIME
(20ms)
10ms DELAY
PFN2 LOW
(10ms DEBOUNCE )
ABORT SOFT RESET
ACTIVE DISCHARGE OUTPUTS
50ms
OFF
GLOBAL PASSIVE DISCHARGE
(OTP)
PFN1 LOW
(10ms DEBOUNCE )
ABORT HARD RESET
DISABLE ACTIVE DISCHARGE
µC SOFTWARE RESET
CHGIN
SEAL HANDLER
BOOT SEQUENCE
PwrRstCfg = 0100, 0101
Figure 1c. PwrRstCfg = 0100 or 0101
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PMIC with Ultra-Low Iq Regulators, Charger,
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ON
THROUGH PFN1 LOW
(10ms DEBOUNCE)
FOR 12sec
2
THROUGH I C PWR_OFF_CMD OR
I2C_PWR_OFF_DELY (30ms DELAY)
SHUTDOWN
HOLD RST LOW
TURN OFF RESOURCES
SHUTDOWN
TRAP
PFN1 HIGH (10ms DEBOUNCE)
WAIT RESOURCES TURN-OFF TIME 20ms
HOLD RST LOW
TURN OFF RESOURCES
PASSIVE DISCHARGE
OUTPUTS
10ms
OFF
GLOBAL PASSIVE
DISCHARGE OTP
VIA PFN1 LOW (10ms DEBOUNCE)
OR CHGIN ATTACH
BOOT
SEQUENCE
PwrRstCfg = 0110
Figure 1d. PwrRstCfg = 0110
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PMIC with Ultra-Low Iq Regulators, Charger,
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ON
2
THROUGH PFN1 LOW
THROUGH I C PWR_OFF_CMD OR
(10ms DEBOUNCE) FOR 10sec
I2C_PWR_OFF_DELY (30ms DELAY)
SHUTDOWN
HOLD RST LOW
TURN OFF RESOURCES
SOFT RESET
HOLD RST LOW
WAIT RESOURCES
TURN-OFF TIME 20ms
PFN1/2 RELEASE (10ms DEBOUNCE)
+ 10ms DELAY
PASSIVE DISCHARGE
OUTPUTS
10ms
OFF
GLOBAL PASSIVE
DISCHARGE OTP
THROUGH PFN 1 LOW 3s
OR CHGIN ATTACH (28ms DEBOUNCE)
BOOT
SEQUENCE
PwrRstCfg = 0111
Figure 1e. PwrRstCfg = 0111
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PMIC with Ultra-Low Iq Regulators, Charger,
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ON
2
THROUGH I C PWR_OFF_CMD
OR
THROUGH PFN2 LOW
FOR 12sec
I2C_PWR_OFF_DELY (30ms DELAY)
SHUTDOWN
HOLD RST LOW
TURN OFF RESOURCES
SOFT RESET
HOLD RST LOW
PFN2 RELEASE (10ms DEBOUNCE)
WAIT RESOURCES TURN-OFF TIME 20ms
+
10ms DELAY
PASSIVE DISCHARGE
OUTPUTS
10ms
OFF
GLOBAL PASSIVE
DISCHARGE IF ENABLED
THROUGH PFN1 LOW FOR 3s
OR CHGIN ATTACH (28ms DEBOUNCE)
BOOT
SEQUENCE
PwrRstCfg = 1000
Figure 1f. PwrRstCfg = 1000
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Table 2. PwrRstCfg Settings
PwrRstCfg
PFN1
PFN1 PU/PD*
PFN2
PFN2 PU/PD*
Notes
On/Off mode with 10ms debounce. Active-
high On/Off control on PFN1. Logic-low on
PFN2 generates 10ms pulse on RST.
Note: In this mode, if PFN1 is high, PWR_
OFF_CMD will cause the part to turn off,
then immediately return to the ON state.
Soft-Reset
Active-Low
0000
Enable
Pulldown
Pullup
On/Off mode with 10ms debounce. Active-
low On/Off control on PFN1. Logic-low on
PFN2 generates 10ms pulse on RST.
Note: In this mode, if PFN1 is high, PWR_
OFF_CMD will cause the part to turn off,
then immediately return to the ON state.
Soft-Reset
Active-Low
0001
Disable
Pullup
Pullup
Always-On mode (i.e., device can only be
put in Off state through PWR_OFF_CMD).
10ms hard reset off time. 10ms soft reset
pulse time. 200ms delay prior to both reset
behaviors.
Hard-Reset
Active-High
Soft-Reset
Active-High
0010
0011
0100
0101
Pulldown
Pullup
Pulldown
Pullup
Always-On mode (i.e., device can only be
put in Off state through PWR_OFF_CMD).
50ms Hard-Reset off time. 10ms Soft-Reset
pulse time. 200ms delay prior to both reset
behaviors.
Soft-Reset
Active-Low
Hard-Reset
Active-Low
Always-On mode (i.e., device can only be
put in Off state through PWR_OFF_CMD).
50ms Hard-Reset off time. 10ms Soft-Reset
pulse time. 15s delay prior to both reset
behaviors. Either reset may be aborted
Soft-Reset
Active-High Trig-
gered on CHGIN
Insertion
Hard-Reset
Active-High
Triggered on
CHGIN Insertion
Pulldown
Pullup
Pulldown
Pullup
Always-On mode (i.e., device can only be
put in Off state through PWR_OFF_CMD).
70ms Hard-Reset off time. 10ms Soft-Reset
pulse time. 15s delay prior to both reset
behaviors. Either reset may be aborted.
Hard-Reset
Active-Low
Triggered by
CHGIN Insertion
Soft-Reset
Active-Low Trig-
gered on CHGIN
Insertion
Off mode through specific long-press (12s)
or PWR_OFF_CMD. On mode through
specific short-press (400ms).
KIN
KIN
0110
0111
Pullup
Pullup
KOUT
KOUT
None
None
Off mode through PWR_OFF_CMD. On
mode through specific long-press (3s) or
CHGIN insertion soft reset through specific
long press (10s).
Custom Two Button. Off mode through
PWR_OFF_CMD. On mode through KIN
long-press (3s) or CHGIN insertion. Soft
reset through PFN2 long press (12s).
Soft-Reset
Active-Low 12s
Long Press
KIN
1000
Pullup
Pullup
1001-1111
RFU
*Note: The presence of internal pullup/pulldown resistors on PFN1 and PFN2 is device specific. Refer to Table 202 to determine if a
device has internal resistors or requires external resistors.
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FROM POWER ON
FUEL GAUGE: ON
WAIT FOR 30ms
NO
V
PRESENT?
YES
BUS
CHARGER: OFF
LIMITER: ON
CHARGER: OFF
WAIT FOR 10ms
WAIT TshdnTmo
SYS_UVLO = 0?
YES
POWER PATH: ON
BATOC ON
BATOC Irq Ena
SYS_UVLO = 0?
YES
NO
NO
CHG_ENA = ChgEn
NO
Seq BASED STARTUP
SEQUENCE
TshdnTmo = 0?
YES
LIMITER: OFF
POWER PATH: OFF
CHARGER ENABLE: OFF
NO
SYS_UVLO = 0?
YES
RST
SYS_UVLO Irq Ena
ON
ERROR MODE
(OUTPUTS AS OFF MODE)
V
REMOVAL
BUS
ENTER IN POWER OFF
LATCHED, REQUIRES
EXTERNAL EVENT TO
RESTART
BATOC Irq
SYS_UVLO Irq
Figure 2. The full MAX20353 Boot Sequence
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LDO2 can be configured to be always-on as long as SYS
or BAT is present.
Power Sequencing
The sequencing of the switching regulators, LDOs, and
charge pump during power-on is configurable. See
each regulator’s sequencing bits for details. Regulators
can turn on at one of three points during the power-on
process: 75ms after the power-on event, at the time the
RST signal is released, or at two points in between. The
two points between SYS and RST are fixed proportionally
to the duration of the Power-On Reset (POR) process
The SYS voltage is monitored during the power-on
sequence. If V falls below V during the
SYS
SYS_UVLO_F
sequencing process with a valid voltage at CHGIN, the
process repeats from the point where SYS was enabled
to allow more time for the voltage to stabilize. If there is
not a valid voltage at CHGIN, the device returns to the
OFF state to avoid draining the battery. Power is also
turned off if BAT experiences a current greater than
(t
). The timing relationship is presented graphically
RST
in Figure 3.
I
for more than t
.
BAT_OC_R
BAT_OC_D
Alternatively, the regulators can remain off by default
2
and turn on with an I C command after RST is released.
Figure 3. Reset Sequence Programming
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Current Sink
Input Limiter
The input limiter distributes power from the external
adapter to the system load and battery charger. In
addition to the input limiter’s primary function of passing
power to the system load and charger, it performs several
additional functions to optimize use of available power.
Invalid CHGIN Voltage Protection: If CHGIN is above
the overvoltage threshold, the device enters overvoltage
lockout (OVL). OVL protects the MAX20353 and down-
stream circuitry from high-voltage stress up to +28V and
down to -5.5V. During positive OVL, the internal circuit
remains powered and an interrupt is sent to the host.
The negative voltage protection disconnects CHGIN and
the device is powered only by BAT. The charger turns off
and the system load switch closes, allowing the battery to
In addition to several voltage regulators, the MAX20353
also includes three low-dropout linear current regulators
from LED_ to GND. The sink current of each current
regulator is independently programmable through its
respective LED_ISet[4:0] bits in direct registers LED_
Direct (0x2D–0x2F). The current regulators can be
programmed to sink 0.6mAto 30mA with configurable step
sizes and are ideal for sinking current from external LEDs.
The LEDIStep[1:0] bits in direct register LEDStepDirect
(0x2C) control the size of the current steps for all current
sinks. This step size also sets an effective limit on the
sinking current as the number of steps remains constant
while the step size varies. Current sinks are enabled
2
through an I C command, by an internal charger status
power SYS. CHGIN is also invalid if it is less than V
,
signal, or by an external MPC pin allowing for LED status
indicators. Note that the current sinks always draw
quiescent current when tied to an MPC_ control or status
signal regardless of the MPC_ or status state.
BAT
or less than the USB undervoltage threshold. With an
invalid input voltage, the BAT-SYS load switch closes and
allows the battery to power SYS.
CHGIN Input Current Limit: The CHGIN input current
is limited to prevent input overload. The input current
limit is controlled by I C. To accommodate systems with
a high in-rush current, the limiter includes a program-
mable blanking time during which the input current limit
System Load Switch
An internal 80mΩ (typ) MOSFET connects BAT to SYS
when no voltage source is available on CHGIN. When an
external source is detected at CHGIN, this switch opens
and SYS is powered from the input source through the
input current limiter. The SYS-to-BAT switch also prevents
2
increases to I
.
LIM_MAX
Thermal Limiting: In case the die temperature exceeds
the normal limit (T ), the MAX20353 attempts
V
SYS
from falling below V
when the system load
BAT
CHG_LIM
exceeds the input current limit. If V
drops to V
BAT
SYS
to limit temperature increase by reducing the input
current from CHGIN. In this condition, the system load has
priority over the charger current, so the input current is
first reduced by lowering the charge current. If the junction
temperature continues to rise and reaches the maximum
due to the current limit, the BAT-SYS switch turns on so
the load is supported by the battery. If the system load
continuously exceeds the input current limit, the battery
is not charged. This is useful for handling loads that are
nominally below the input current limit but have high
current peaks exceeding the input current limit. During
these peaks, battery energy is used, but at all other times
the battery charges.
operating limit (T
), no input current is drawn
CHGIN_SHDN
from CHGIN and the battery powers the entire system load.
Adaptive Battery Charging: While the system is powered
from CHGIN, the charger draws power from SYS to
charge the battery. If the total load exceeds the input
current limit, an adaptive charger control loop reduces
Smart Power Selector
The smart power selector seamlessly distributes power
from the external CHGIN input to the BAT and SYS
nodes. With both an external adapter and battery
connected, the smart power selector basic functions are:
charge current to prevent V
from collapsing. When
SYS
the charge current is reduced below 50% due to I
or
LIM
T
limits, the timer clock operates at half speed.
CHG_LIM
When the charge current is reduced below 20% due to
or T limits, the timer clock is paused.
●
●
●
When the system load requirements are less than
the input current limit, the battery is charged with
residual power from the input.
When the system load requirements exceed the
input current limit, the battery supplies supplemental
current to the load.
I
LIM
CHG_LIM
Fast-Charge Current Setting: The MAX20353 uses an
external resistor connected from SET to GND to set the
fast-charge current. The precharge and charge-termina-
tion currents are programmed as a percentage of this
value by opcode 0x14. The fast-charge current resistor
can be calculated as:
When the battery is connected and there is no external
power input, the system is powered from the battery.
R
SET
= K
x V /I
SET FChg
SET
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where K
has a typical value of 2000A/A and V
has
SET
Table 3. SAR ADC Full-Scale Voltages and
Conversions
SET
a typical value of +1V. The range of acceptable resistors
for R is 4kΩ to 400kΩ.
SET
VOLTAGE
RAIL
AVAILABLE
CONVERSION (V)
A capacitive load on SET can cause instability of the
charger if the condition (C < 5μs/R ) pF is violated.
RANGE
+2.6V to +5.5V
0V to +5.5V
SET
SET
SYS
(Result[7:0] * 5.5)/255
(Result[7:0] * 5.5)/255
(Result[7:0] * 100)/255
(Result[7:0] * 8.25)/255
(Result[7:0] * 8.25)/255
(Result[7:0] * 21.0)/255
SAR ADC/Monitor MUX
In order to simplify system monitoring, the MAX20353
includes a voltage monitor multiplexer (MUX). The I C
controlled MUX connects the MON pin to the scaled value
of one of six voltage regulators, BAT, or SYS. A resistive
divider scales the voltage to one of four ratios determined
by MONRatioCfg[1:0] (opcode 0x50, Table 124). Because
MON
THM
0% to 100% V
+3V to +8V
+3V to +8V
+3V to +21V
DIG
2
CHGIN
CPOUT
BSTOUT
the MUX can only tolerate voltages up to +5.5V, V
,
CHGIN
fully configurable through the ChargerThermalLimits_Config_
Write (opcode 0x16, Table 76) and ChargerThermalReg_
Config_Write (opcode 0x18, Table 80) commands detailed in
Table 76 and Table 80. Some example profiles are included
in Figure 4. It is important to note that, because battery
temperature is measured by the internal ADC, JEITA moni-
toring is unavailable when automatic level compensation is
enabled in the haptic driver.
V
, and V
are not available to MON.
CPOUT
BSTOUT
An internal ADC reads the remaining voltage rails and
performs system tasks such as JEITA temperature monitor-
ing and SYS tracking during haptic driver operations.
Manual ADC measurements are initiated by writing the
desired channel to ADC_Measure_Launch (opcode 0x53,
Table 128) and reading the response from APDataIn0-3.
The ADC can also measure the MON voltage when the
MUX is enabled with a 1:1 ratio. The full-scale range of
the ADC for different voltage rails is detailed in Table 3.
Haptic Driver
Note: The haptic driver registers must be updated to to
the recommended default values shown in Table 199 and
Table 200. Failure to overwrite the default values after a
POR results in poor haptic driver performance.
JEITA Monitoring with Charger Control
ToenhancesafetywhenchargingLi+batteries, theMAX20353
includes JEITA-compliant temperature monitoring. A resistive
divider is formed on THM by attaching a pullup resistor to
TPU and connecting the thermistor of a battery-pack (do not
exceed 1mA load on TPU). The divider output is read by the
internalADC when JEITAmonitoring is enabled and the result-
ing temperature measurement places the battery into one of
five temperature zones: cold, cool, room, warm, and hot.
Zone-specific temperature limits and charging behavior are
The MAX20353 features a versatile, integrated haptic
driver. The driver allows for real time control of haptic
2
devices through PWM or I C as well as the ability to run
haptic patterns from internal RAM. For added flexibility,
the driver is capable of driving both Linear Resonant
Actuator (LRA) and Eccentric Rotating Mass (ERM)
actuators.
PREQUAL:
FAST CHARGE CONSTANT CURRENT:
V
< V
BAT_PCHG
BAT
V
< V
< V
BAT BAT_REG
BAT_PCHG
I
ROOMFChg
I
I
WARMFChg
COOLFChg
I
HOTFChg
I
I
I
PCHG
PCHG
PCHG
CHARGING
I
COLDFChg
ColdChgEn CoolChgEn
WarmChgEn HotChgEn
ColdChgEn = 0
CoolChgEn
CHARGING
WarmChgEn HotChgEn = 0
T
T
2
T
T
4
1
3
T
T
T
T
4
1
2
3
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 4a. Sample JEITA Pre Charge Profile
Figure 4b. Sample JEITA Fast Charge Profile
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MAINTAIN:
V
≥ BatReg- BatReChg
BAT
ColdBatReg CoolBatReg
BatReg
WarmBatReg
HotBatReg
HotEn
CHARGING
ColdEn
CoolEn
WarmEn
T
1
T
2
T
3
T
4
TEMPERATURE (°C)
Figure 4c. Sample JEITA Maintain Charge Profile
FROM ANY STATE
T
> T
CHGIN_LIM
DIE
RESET CHARGE TIMER
JEITA ENABLE CHARGING
OR V
> V
SYS
BAT
OR ChgEn = 0
OR INPUT LIMITER OFF
1s
FRESH BATTERY
INSERTION
V
< V
– V
BATREG BATRECHG
BAT
CHARGE SUSPEND
CHARGER OFF
TIMER FAULT
ChgStat = 001
LED = 1.5s PERIOD
ChgStat = 000
LED = OFF
ChgStat = 111
LED = 0.15s PERIOD
ChgStat = 110
LED = 1s PULSE
ChgEn = 1,
I
= 0
I
= 0
I
= 0
CHG
JEITA DISABLE CHARGING
CHG
CHG
I
= 0
CHG
V
BAT
> V
– V
BATREG
BATRECHG
ChgEn = 1,
V
BAT
< V
– V
BATREG
BATRECHG
ChgEn=1,
PAUSE
AND V
> V
RISE
CHARGE
TIMER
V
BAT
> V
– V
BATREG BATRECHG
SYS
FCHG-MTCHG
V
BAT
< V
– V
BATREG
BATRECHG
AND ChgAutoReSta = 1
AND V < V RISE
RESET CHARGE TIMER
SYS
FCHG-MTCHG
MAINTAIN CHARGE
DONE
PREQUAL
PREQUAL SUSPEND
JEITA DISABLE CHARGING
JEITA ENABLE CHARGING
JEITA DISABLE CHARGING
ChgStat = 010
LED = ON
ChgStat = 001
LED = 1.5s PERIOD
ChgStat = 110
LED = OFF
I
= I
I
= 0
CHG
CHG PCHG
I
= 0
CHG
t
> t
CHG_TIMER PCHG
V
BAT
< V
V >V
BAT PCHG_R
PCHG_R
RESET CHARGE TIMER
RESET CHARGE TIMER
PAUSE
CHARGE
TIMER
JEITA DISABLE CHARGING
FAST CHARGE
CONSTANT CURRENT
FAST CHARGE CC
SUSPEND
JEITA DISABLE CHARGING
t
> t
CHG_TIMER MTCHG
ChgStat = 011
LED = ON
ChgStat = 001
LED = 1.5s PERIOD
AND
ChgAutoStp=1
JEITA ENABLE CHARGING
I
= I
I
= 0
CHG
CHG FCHG**
T < T2 OR T > T3
VOLTAGE MODE=0* AND
> V
VOLTAGE MODE = 1*
AND V > V
t
> t
CHG_TIMER FCHG
V
SYS
FCHG-MTCHG
SYS
FCHG-MTCHG
PAUSE
CHARGE
TIMER
RISE OR V
< V
PCHG_R
BAT
CHG CHG_DONE
RISE
I
> I
JEITA DISABLE
CHARGING
RESET CHARGE TIMER
FAST CHARGE
CONSTANT VOLTAGE
FAST CHARGE CV
MAINTAIN CHARGE
SUSPEND
ChgStat = 101
LED = ON
ChgStat = 100
LED = ON
ChgStat = 001
LED = 1.5s PERIOD
I
< I
CHG CHG_DONE
JEITA ENABLE CHARGING
I
< I
CHG CHG_DONE
AND V
> V
RISE
FCHG-MTCHG
SYS
I
= I
I
= 0
CHG
CHG FCHG
NOTES:
AND T < T
DIE
CHG_LIM
RESET CHARGE TIMER
*
VOLTAGE MODE IS AN INTERNAL SIGNAL
t
MTCHG
** CHARGE TIMER IS SLOWED BY 50% IF
I
CHG<IFCHG/2 AND PAUSED IF ICHG<IFCHG/5
ONLY IN FAST CHARGE CONSTANT
CURRENT STATE
Figure 5. Charger State Diagram
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AutoBrkMeasTh[1:0] (register 0x27) for more than half
ERM
of the duration of AutoBrkMeasWdw[3:0] (register 0x27)
over a number of consecutive sample points (set by
AutoBrkMeasEnd[1:0], register 0x27), then the driver
determines that the BEMF is sufficiently small and driv-
ing stops. Recommended braking settings are provided in
Table 199 and Table 200.
An ERM is the simplest haptic actuator to drive. The
driving signal is taken directly as the output of an
integrated H-bridge, allowing for bidirectional operation
of the actuator. To configure the MAX20353 to drive an
ERM, the HptSel bit must be set to 0 using the opcode
0xA0 or 0xAD (Table 134 or Table 160).
Driver Amplitude
LRA
The haptic driver features a configurable voltage basis
for the amplitude of the driving signal. Setting this basis,
Unlike the on-off control of an ERM, LRAs require a sinu-
soidal driving signal. The MAX20353 realizes this with a
Class-D amplifier that converts the driver input to a sinu-
soidal output.
referred to as the full-scale voltage (V ), configures the
FS
maximum amplitude of the driver output. It is set using
HptVfs[7:0] with opcode 0xA2 or 0xB2 (Table 138 or Table
170) and has a range of 0V to 5.5V (LSB = 21.57mV).
An LRA’s vibration magnitude is maximized when the
driving signal matches the LRA’s resonant frequency. To
ensure the haptic driver closely tracks this frequency, the
MAX20353 includes an auto-resonance tracking feature
that measures the back-electromotive force (BEMF) of
the LRA and modulates the drive frequency to minimize
the phase error between the BEMF and the driving signal.
The resonant tracking feature should remain enabled any
time an LRA is driven. Resonance tracking is enabled by
setting the EmfEn bit to 1 with opcode 0xA0 or 0xAD. The
range of resonant frequencies that are tracked is clamped
by the driver to be no lower than max(200k/IniGss[11:0],
100)Hz and no greater than min(800k/IniGss[11:0], 500)
Hz. See description of IniGss[11:0] in Table 134 for calcu-
lation of frequency. This mitigates the risk of audible noise
during a fault event.
Since the H-bridge is supplied by V
, the actual full-
SYS
scale voltage of the driver at any given moment is the
minimum of the value stored in HptVfs[7:0] and V
.
SYS
Once V has been set, all driver amplitudes are scaled
FS
as a percentage of the full-scale voltage. The resolution
of the amplitude is always V
/128. Therefore, the
SYS
effective resolution of the amplitude scales with the V
/
FS
V
ratio. For example, if V
= V
/2, the effective
SYS
SYS
FS
resolution is 6 bits.
Automatic Level Compensation
Because V can vary over time, the driver must adjust
SYS
its output duty cycle to maintain a constant reference to the
full-scale voltage. An Automatic Level Compensation (ALC)
function measures V
and handles this adjustment. ALC
SYS
To select LRA mode, set the HptSel bit to 1 using opcode
0xA0 or 0xAD.
can be enabled by setting the AlcMod bit to 1 using opcode
0xA0 or 0xAD and uses the MAX20353’s internal ADC to
monitor V
. The ALC function then scales the haptic
SYS
LRA Braking
driver’s duty cycle as needed to maintain the programmed
driver amplitude. If ALC is not enabled, V is assumed
The haptic driver features enhanced BEMF tracking and
automatic braking to efficiently stop or reverse the direc-
tion of an LRA. Each time the driving polarity is reversed,
the BEMF measurement configurations are overridden by
the values in BrkLpGain[1:0] (opcode 0xB0), BrkCyc[4:0]
(opcode 0xB1), and BrkWdw[4:0] (opcode 0xB9) for
BrkCyc[4:0] number of half cycles. This allows the haptic
driver to optimize the redetection of the BEMF after the
sudden change in direction.
SYS
to be V
.
FS
Haptic UVLO
Additionally, V
but prior to starting a vibration. At any moment, if V
goes below the programmed UVLO value, which is set
through HptSysUVLO[7:0] with opcode 0xA6 (Table 146),
the vibration event is aborted and the haptic driver is
locked. See the Haptic Driver Lock section for details
regarding restarting vibration if a haptic UVLO condition
is reached.
is measured after the driver is enabled
SYS
SYS
Additionally, the haptic driver can automatically detect the
optimal braking time when running patterns in the RAMHP
and ETRG modes. When the RAM pattern reaches a
brake sample (nLSx[1:0] = 00 and RPTx[3:0] = 0000),
or when the ETRG pattern reaches the brake amplitude,
the haptic driver measures the LRA’s BEMF amplitude.
The BEMF amplitude measurements are taken at either
two or four sample points along the sine wave depend-
ing on AutoBrkPeakMeas setting in register 0x26. If the
absolute value of the BEMF is lower than the threshold
The time required to perform the V
measurement, as
SYS
well as other startup delays, results in an initial latency of
the haptic driver. To avoid partial pattern skipping in real-
time modes, vibration patterns should be provided at least
t
after enabling the desired real-time vibration
HD_START
2
mode (PPWM or RTI C).
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Vibration Timeout
Pure-PWM (PPWM)
A vibration timeout parameter is programmable through
I C. If a vibration lasts longer than the programmed time-
PPWM mode offers real-time control of the haptic driver.
Patterns are generated by applying a PWM signal to the
MPC_ pin selected by HptDrvMode[4:0]. The duty cycle of
the applied signal determines the amplitude of the driving
2
out period, the vibration is aborted. The timeout period
is stored in HptDrvTmo[5:0] (LSB = 1s), which can be
written using opcode 0xB7 (Table 180). Writing code
“000000” disables the timeout function. See the Haptic
Driver Lock section for details regarding restarting vibration
if a timeout is reached.
signal, scaled by V . The driving direction is centered
FS
about a 50% duty cycle. A duty cycle of 0% to 47.5%
produces a (100 to 0)%V
amplitude in the negative
FS
direction and a duty cycle of 52.5% to 100% produces a
(0 to 100)%V amplitude in the positive direction. The
FS
Overcurrent/Thermal Protection
region between 47.5% and 52.5% duty cycle is a dead
zone and inputs within this range correspond to a null output.
The haptic driver also includes overcurrent and thermal
shutdown protection. While the haptic driver is active,
the MAX20353 monitors the current from DRP and DRN.
If overcurrent protection is enabled (HptOCProtDis = 0)
A timeout feature prevents idle PWM inputs from causing
unwanted vibrations of the haptic motor. If the input signal
remains at 0% duty cycle or 100% duty cycle for more
than 2.56ms, the output is null and vibration stops. As
such, the MPC_ input must remain dynamic to produce a
continuous output.
and the DRP or DRN current exceeds I
, the
HD_OC_THR
haptic driver issues a fault, aborts vibration, and enters
the locked state.
Thermal protection allows the MAX20353 to immediately
shut down the haptic driver should the die temperature
2
2
Real-Time I C (RTI C)
2
exceed T
. This feature is enabled by setting
Similar to PPWM mode, RTI C mode offers real-time
control of the haptic driver. The direct register
HptRTI2CAmp (0x32) determines the amplitude of the
output signal. The lower seven bits of the register
(HptRTI2CAmp[6:0]) set the amplitude as a percentage
HD_OC_THR
HptThmProtDis = 0.
See the Haptic Driver Lock section for details regarding
restarting vibration if an overcurrent or overtemperature
condition is reached.
of V and the MSB (HptRTI2CSign) sets the direction of
FS
Haptic Driver Lock
rotation. 100% amplitude, reverse drive, for example, is
produced by setting HptRTI2CAmp to 0x7F (0b01111111).
If the MAX20353 detects a fault in the haptic driver, vibrations
in progress are aborted and the haptic driver is locked
by the HptLock bit. The user must manually clear the
HptLock bit using opcode 0xA8 (Table 150) in order to
run a new vibration attempt. A fault occurs under any of
2
Once RTI C mode is enabled through HptDrvMode[4:0],
the haptic driver continuously outputs the amplitude and
direction defined by the latest data in HptRTI2CAmp.
In order to generate haptic patterns, the HptRTI2CAmp
register must receive new data.
the following conditions: V
drops below the threshold
SYS
programmed in HptSysUVLO[7:0] (SystemError 0x25), an
overcurrent is detected on DRN or DRP (SystemError =
0x20, 0x21, 0x22, or 0x23), the die temperature exceeds
the thermal protection threshold (SystemError = 0x24), or
a vibration duration exceeds the timeout period stored in
HptDrvTmo[5:0] (SystemError 0x04). Writing any value
other than 0x00 with opcode 0xA8 will set HptLock high
and disable the driver output.
External Triggered Stored Pattern (ETRG)
In ETRG mode, a rising edge on an MPC_ pin or a 0-to-1
2
transition of the HptExtTrig bit in direct I C register 0x31
initiates a vibration sequence. The sequence is contained
in six registers and comprises an overdrive (startup)
amplitude, active drive amplitude, braking amplitude, and
the duration of each driving behavior.
Amplitudes
contained
in
ETRGOdAmp[7:0],
Interface Modes
ETRGActAmp[7:0], and ETRGBrkAmp[7:0], which are
set through opcode 0xA2–0xA4 or 0xB3 (Table 138 thru
Table 143 and Table 172), follow the same format as
HptRTI2CSign + HptRTI2CAmp[6:0] in direct I C register
0x32 (i.e., the lower-seven bits store the amplitude as a
There are a total of four interface modes for controlling
the haptic driver. These include two real-time modes and
two stored memory modes. The haptic driver mode is
2
2
set through HptDrvMode[4:0] with the direct-access I C
register 0x31. Selecting an operation mode also enables
the driver. In addition, HptDrvEn must be set and kept to
1 before setting HptDrvMode[4:0] and for the whole dura-
tion of vibration. Once vibration finishes, HptDrvMode[4:0]
must be set to “00000” before the haptic driver may be
disabled via HptDrvEn = 0 for power savings.
percentage of V and the MSB determines the direction).
FS
The trigger input is selected when the driver enters ETRG
mode via HptDrvMode[4:0] in direct I C register 0x31. In
order to properly register the rising edge, the trigger sig-
nal must remain high for a few clock cycles of the driver.
2
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Once the sequence begins, the haptic driver follows
the duration values stored in ETRGOdDur[7:0],
ETRGActDur[7:0], and ETRGBrkDur[7:0]. It is possi-
ble, however, to extend the active drive time by leav-
ing the trigger high longer than the time specified in
ETRGActDur[7:0]. Doing so will cause the driver to output
the amplitude stored in ETRGActAmp[7:0] until a falling
edge is detected. Once the trigger signal falls low, the
brake sequence executes.
to HptDataH, HptDataM, and HptDataL (0x29, 0x2A, and
0x2B, respectively) is stored. It is possible to read back
data from RAM. Writing an address to HptRAMAddr,
2
then initiating an I C read transaction of register 0x29,
will allow readback of the three bytes stored in the RAM
address. RAM read and write procedures are depicted
graphically in Figure 6.
A haptic pattern is composed of multiple pattern samples.
Pattern samples define the amplitude, duration, wait time,
transition, and repetition of a segment of a haptic pattern.
These samples are defined in three bytes and written
to RAM through HptDataH, HptDataM, and HptDataL.
HptDataH contains the sign of the sample’s amplitude
(AxSign), the upper-five bits of the amplitude (Ax[6:2]),
and instructions to the haptic driver on handling the pattern
sample (nLSx). HptDataM contains the lower two bits
of the sample’s amplitude (Ax[1:0]), the duration of the
sample (Dx), and the upper bit of the wait time before the
next sample in the pattern (Wx[4]). HptDataL contains the
lower four bits of the wait time (Wx[3:0]) and the repetition
behavior (RPTx). Table 4 describes the definition of a
pattern sample and Figure 7 provides a sample haptic
pattern with corresponding waveform.
RAM Stored Haptic Pattern (RAMHP)
The final method of controlling the haptic driver is
RAMHP mode. The MAX20353 contains an internal 256
x 24 bit RAM in which haptic patterns are stored. By
storing haptic sequences in RAM at startup, the driver
can perform sophisticated haptic sequences upon receipt
2
of a trigger signal as in ETRG mode. The direct I C
register HptPatRAMAddr (0x33) specifies the RAM
address where the sequence begins.
RAM should be loaded when the MAX20353 comes out
of Off mode. To write data to the RAM, the HptRAMEn bit
in direct register HptDirect1 (0x31) must first be set high.
Next, writing a value to the direct register HptRAMAddr
(0x28) specifies the RAM address in which data written
WRITING RAM DATA BYTES AT RAM ADDRESS[7:0]
S
SLAVE ADDRESS-W
A
HptRAMAddr (0x28)
A
RAM ADDRESS[7:0]
A
RAMDataH[7:0]
A
RAMDataM[7:0]
A
RAMDataL[7:0]
A
P
READING RAM DATA BYTES FROM RAM ADDRESS[7:0]
S
S
SLAVE ADDRESS-W
SLAVE ADDRESS-W
A
A
HptRAMAddr (0x28)
HptDataH (0x29)
A
A
RAM ADDRESS[7:0]
A
Sr SLAVE ADDRESS-R
A
RAMDataH[7:0]
A
RAMDataM[7:0]
A
RAMDataL[7:0]
NA
P
FROM MASTER TO SLAVE
FROM SLAVE TO MASTER
START CONDITION
REPEATED START
S
Sr
P
STOP CONDTION
A
ACKNOWLEDGE
NA
NOT ACKNOWLEDGE
Figure 6. Read and Write Processes for RAM
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Table 4. RAMHP Pattern Storage Format
ADDRESS
BIT
0x28-0x2B
B7
B6
B5
B4
B3
B2
B1
B0
HptRAMAddr
HptDataH
HptDataM
HptDataL
HptRAMAddr[7:0]
nLSx[1:0]
Amp[1:0]
AmpSign
Amp[6:2]
Dur[4:0]
Wait[4]
Wait[3:0]
RPTx[3:0]
HptRAMAddr
[7:0]
The RAM address in which the pattern sample is stored
Sets the behavior of a sample in the pattern.
00 = Current sample is the last sample in the pattern
01 = Current sample is not the last sample in the pattern
10 = Interpolate current sample with next sample
nLSx[1:0]
11 = Current sample is the last sample in the pattern. Repeat the entire pattern RPTx[3:0] times
Sign of haptic amplitude in current sample
AmpSign[1:0] 0 = Positive
1 = Negative
Sets the amplitude of pattern sample x as a 7-bit percentage of V and a 1-bit direction. See HptVfs[7:0] in
Table 138.
FS
Amp[6:2]
Sets the duration of time the driver outputs the amplitude of the current sample in increments of 5ms
00000 = 0ms
00001 = 5ms
...
Dur[4:0]
11110 = 150ms
11111 = 155ms
Sets the duration of time the driver waits at zero amplitude before the next sample in increments of 5ms
00000 = 0ms
00001 = 5ms
...
Wait[4:0]
11110 = 150ms
11111 = 155ms
Sets the number of times to repeat the sample before moving to the next sample in the pattern. If nLSx[1:0] = 11,
this sets the number of times to repeat the whole pattern.
0000 = Repeat 0 times. If nLSx = 00, automatic braking is performed on this sample with a maximum braking time
equal to Wait[4:0].
0001 = Repeat 1 time
…
RPTx[3:0]
1110 = Repeat 14 times
1111 = Repeat 15 times
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nLS0[1:0]
Amp[7:0]
Dur[4:0]
Wait[4:0]
Rpt[3:0]
END OF PREVIOUS
PATTERN
nLS
Amp
Dur
Wait
Rpt
PREV
PREV
PREV
PREV
PREV
01
A0
00010
00011
00011
00011
DC
00001
0001
01
10
10
11
A1
A2
A3
A4
00000
00000
00000
00010
0010
X
X
0010
Figure 7a. Sample Pattern Stored in RAM
SAMPLE 0
A0
SAMPLE 1
SAMPLE 2
A2
SAMPLE 3 SAMPLE 4
REPEAT PATTERN
A1
A3
A4
20ms
30ms
30ms
30ms
30ms
20ms
30ms
30ms
30ms
30ms
WAIT 10ms
WAIT 20ms
WAIT 10ms
WAIT 20ms
Figure 7b. Haptic Driver Output of Stored Pattern
small, but never precisely zero. Error accumulates over
time in such systems (typically, 0.5%–2% per day) and
requires periodic corrections. Some algorithms correct
drift using occasional events and, until such an event
occurs, the algorithm’s error is boundless:
Fuel Gauge
ModelGauge Theory of Operation
The MAX20353 fuel gauge is based on the MAX17048
stand-alone fuel gauge and simulates the internal, non-
linear dynamics of a Li+ battery to determine its State of
Charge (SOC). The sophisticated battery model considers
impedance and the slow rate of chemical reactions in
the battery. ModelGauge performs best with a custom
model, obtained by characterizing the battery at multiple
discharge currents and temperatures to precisely model
it. At power-on reset (POR), the ICs have a preloaded
ROM model that performs well for some batteries. For
more details on the fuel gauge, refer to the MAX17048
data sheet.
●
●
Reaching predefined SOC levels near full or empty
Measuring the relaxed battery voltage after a long
period of inactivity
●
Completing a full charge/discharge cycle
ModelGauge requires no correction events because
it uses only voltage, which is stable over time. The
ModelGauge remains accurate despite the absence of
any of the above events; it neither drifts nor accumulates
error over time.
Fuel-Gauge Performance
To correctly measure performance of a fuel gauge as
experienced by end-users, exercise the battery dynamically.
Accuracy cannot be fully determined from only simple
cycles.
In coulomb counter-based fuel gauges, SOC drifts
because offset error in the current-sense ADC measurement
accumulates over time. Instantaneous error can be very
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of SOC. Initial error caused by the battery not being
Battery Voltage and State of Charge
in a relaxed state diminishes over time, regardless of
loading following this initial conversion. While SOC
estimated by a coulomb counter diverges, ModelGauge
SOC converges, correcting error automatically. Initial
error has no long-lasting impact.
Open-circuit voltage (OCV) of a Li+ battery uniquely
determines its SOC; one SOC can have only one value of
OCV. In contrast, a given V
can occur at many differ-
CELL
ent values of OCV because V
is a function of time,
CELL
OCV, load, temperature, age, impedance, etc.; one value
of OCV can have many values of V . Therefore, one
Battery Insertion Debounce
Any time the IC powers on or resets (see the VRESET/
ID Register (0x18) section), it estimates that OCV is the
CELL
SOC can have many values of V
uniquely determine SOC.
, so V
cannot
CELL
CELL
maximum of 16 V
resolution). OCV is ready 17ms after battery insertion,
and SOC is ready 175ms after that.
samples (1ms each, full 12-bit
Even the use of sophisticated tables to consider both
voltage and load results in significant error due to the
load transients typically experienced in a system. During
charging or discharging, and for approximately 30 min
CELL
Battery Swap Detection
after, V
and OCV differ substantially, and V
has
CELL
CELL
If V
falls below V
, the IC quick-starts once V
CELL
RST CELL
been affected by the preceding hours of battery activity.
ModelGauge uses voltage comprehensively.
returns above V
. This handles battery swap; the SOC
RST
of the previous battery does not affect that of the new
one. See the Quick-Start and VRESET/ID Register (0x18)
sections.
Temperature Compensation
For best performance, the host microcontroller must measure
battery temperature periodically, and compensate the
RCOMP ModelGauge parameter accordingly, at least
once per minute. Each custom model defines constants
RCOMP0 (0x97, default), TempCoUp (-0.5, default), and
TempCoDown (-5.0, default). To calculate the new value
of CONFIG.RCOMP:
Quick-Start
If the IC generates an erroneous initial SOC, the battery
insertion and system power-up voltage waveforms must
be examined to determine if a quick-start is necessary,
as well as the best time to execute the command. The IC
samples the maximum VCELL during the first 17ms. See
the Battery Insertion Debounce section. Unless V
is
CELL
// T is battery temperature (degrees Celsius)
fully relaxed, even the best sampled voltage can appear
greater or less than OCV. Therefore, quick-start must be
used cautiously.
if (T > 20) {
RCOMP = RCOMP0 + (T - 20) x TempCoUp;
}
Most systems should not use quick-start because the
ICs handle most startup problems transparently, such as
intermittent battery-terminal connection during insertion.
If battery voltage stabilizes faster than 17ms, do not use
quick-start.
The quick-start command restarts fuel-gauge calculations
in the same manner as initial power-up of the IC. If the
system power-up sequence is so noisy that the initial
estimate of SOC has unacceptable error, the system
microcontroller may be able to reduce the error by using
quick-start. A quick-start is initiated by a rising edge on
the QSTRT pin, or by writing 1 to the quick-start bit in the
MODE register.
else {
RCOMP = RCOMP0 + (T - 20) x TempCoDown;
}
Impact of Empty-Voltage Selection
Most applications have a minimum operating voltage
below which the system immediately powers off (empty
voltage). When characterizing the battery to create a
custom model, choose empty voltage carefully. Capacity
unavailable to the system increases at an accelerating
rate as empty voltage increases.
To ensure a controlled shutdown, consider including
operating margin into the fuel gauge based on some low
threshold of SOC, for example shutting down at 3% or
5%. This utilizes the battery more effectively than adding
error margin to empty voltage.
Power-On Reset (POR)
POR includes a quick-start, so only use it when the battery
is fully relaxed. See the Quick-Start section. This
command restores all registers to their default values.
After this command, reload the custom model. See the
CMD Register (0xFE) section.
Battery Insertion
When the battery is first inserted into the system, the
fuel-gauge IC has no previous knowledge about the battery’s
SOC. Assuming that the battery is relaxed, the IC translates
its first V
measurement into the best initial estimate
CELL
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Hold SDA and SCL logic-low for a period for t
rising edge on SDA or SCL wakes up the IC.
. A
Hibernate Mode
SLEEP
The ICs have a low-power hibernate mode that can accu-
rately fuel gauge the battery when the charge/discharge
rate is low. By default, the device automatically enters
and exits hibernate mode according to the charge/dis-
charge rate, which minimizes quiescent current (below
5µA) without compromising fuel-gauge accuracy. The ICs
can be forced into hibernate or active modes. Force the
IC into hibernate mode to reduce power consumption in
applications with less than C/4-rate maximum loading.
For applications with higher loading, Maxim recommends
the default configuration of automatic control of hibernate
mode.
Write CONFIG.SLEEP = 1. To wake up the IC, write
CONFIG.SLEEP = 0. Other communication does not
wake up the IC. POR does wake up the IC.
Therefore, applications that can tolerate 4µA should use
hibernate mode rather than Sleep mode.
2
I C Interface
The MAX20353 uses the two-wire I C interface to
2
communicate with a host microcontroller. The configura-
tion settings and status information provided through
this interface are detailed in the register descriptions. To
simplify the use of existing code and drivers designed
for interfacing with the ModelGauge fuel gauge, the
In hibernate mode, the device reduces its ADC conversion
period and SOC update to once per 45s. See the
HIBRT Register (0x0A) section for details on how the IC
automatically enters and exits hibernate mode.
2
MAX20353 appears as two devices on an I C bus. The
main device controlling the regulators, charger, and
other system functions has the seven-bit slave address
0b0101000 (0x50 for writes, 0x51 for reads). Accessing
the fuel gauge is done using the seven-bit slave address
0b0110110 (0x6C for writes, 0x6D for reads).
Alert Interrupt
The ICs can interrupt a system microcontroller with
five configurable alerts. All alerts can be disabled or
enabled with software. When the interrupt occurs, the
system microcontroller can determine the cause from the
STATUS register.
Applications Information
2
I C Interface
The MAX20353 contains an I C-compatible interface
When an alert is triggered, the IC drives the ALRT pin
logic-low and sets CONFIG.ALRT = 1. The ALRT pin
remains logic-low until the system software writes
CONFIG.ALRT = 0 to clear the alert. The alert function
is enabled by default, so any alert can occur immediately
upon power-up. Entering sleep mode clears no alerts.
2
for data communication with a host controller (SCL and
SDA). The interface supports a clock frequency of up to
400kHz. SCL and SDA require pullup resistors that are
connected to a positive supply.
Start, Stop, And Repeated Start Conditions
Sleep Mode
2
When writing to the MAX20353 using I C, the master
In sleep mode, the IC halts all operations, reducing current
consumption to below 1µA. After exiting sleep mode, the
IC continues normal operation. In sleep mode, the IC does
not detect self-discharge. If the battery changes state
while the IC sleeps, the IC cannot detect it, causing SOC
error. Wake up the IC before charging or discharging. To
enter sleep mode, write MODE.EnSleep = 1 and either:
sends a START condition (S) followed by the MAX20353
2
I C address. After the address, the master sends the
register address of the register that is to be programmed.
The master then ends communication by issuing a
STOP condition (P) to relinquish control of the bus, or
a REPEATED START condition (Sr) to communicate to
2
another I C slave. See Figure 8.
S
Sr
P
SCL
SDA
2
Figure 8. I C START, STOP and REPEATED START Conditions
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The master sends 8 data bits
Slave Address
Set the Read/Write bit high to configure the MAX20353
to read mode. Set the Read/Write bit low to configure the
MAX20353 to write mode. The address is the first byte
of information sent to the MAX20353 after the START
condition.
The slave asserts an ACK on the data line
The master generates a STOP condition
Burst Write
In this operation, the master sends an address and mul-
tiple data bytes to the slave device (Figure 10). The slave
device automatically increments the register address after
each data byte is sent, unless the register being accessed
is 0x00, in which case the register address remains the
same. The following procedure describes the burst write
operation:
Bit Transfer
One data bit is transferred on the rising edge of each SCL
clock cycle. The data on SDA must remain stable during
the high period of the SCL clock pulse. Changes in SDA
while SCL is high and stable are considered control sig-
nals (see the Start, Stop, And Repeated Start Conditions
section). Both SDA and SCL remain high when the bus is
not active.
The master sends a START condition
The master sends the 7-bit slave address plus a write bit
(low)
Single-Byte Write
The addressed slave asserts an ACK on the data line
The master sends the 8-bit register address
In this operation, the master sends an address and two
data bytes to the slave device (Figure 9). The following
procedure describes the single byte write operation:
The slave asserts an ACK on the data line only if the
address is valid (NAK if not)
The master sends a START condition
The master sends 8 data bits
The master sends the 7-bit slave address plus a write bit
(low)
The slave asserts an ACK on the data line
Repeat 6 and 7 N-1 times
The addressed slave asserts an ACK on the data line
The master sends the 8-bit register address
The master generates a STOP condition
The slave asserts an ACK on the data line only if the
address is valid (NAK if not)
WRITE SINGLE BYTE
DEVICE SLAVE ADDRESS-W
S
A
A
REGISTER ADDRESS
A
P
8 data bits
FROM MASTER TO SLAVE
FROM SLAVE TO MASTER
Figure 9. Write Byte Sequence
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The slave asserts an ACK on the data line only if the
Single Byte Read
address is valid (NAK if not)
In this operation, the master sends an address plus two
data bytes and receives one data byte from the slave
device (Figure 11). The following procedure describes the
single byte read operation:
The master sends a REPEATED START condition
The master sends the 7-bit slave address plus a read bit
(high)
The master sends a START condition
The addressed slave asserts an ACK on the data line
The slave sends 8 data bits
The master sends the 7-bit slave address plus a write bit
(low)
The master asserts a NACK on the data line
The master generates a STOP condition
The addressed slave asserts an ACK on the data line
The master sends the 8-bit register address
BURST WRITE
DEVICE SLAVE ADDRESS-W
S
A
A
A
A
A
REGISTER ADDRESS
8 DATA BITS - 2
8 DATA BITS - 1
………………
P
8 DATA BITS - N
FROM MASTER TO SLAVE
FROM SLAVE TO MASTER
Figure 10. Burst Write Sequence
READ SINGLE BYTE
S
REGISTER ADDRESS
8 DATA BITS
A
DEVICE SLAVE ADDRESS-W
A
A
DEVICE SLAVE ADDRESS-R
P
Sr
NA
FROM MASTER TO SLAVE
FROM SLAVE TO MASTER
Figure 11. Read Byte Sequence
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The slave sends 8 data bits
Burst Read
In this operation, the master sends an address plus two
data bytes and receives multiple data bytes from the slave
device (Figure 12). The following procedure describes the
burst byte read operation:
The master asserts an ACK on the data line
Repeat 9 and 10 N-2 times
The slave sends the last 8 data bits
The master asserts a NACK on the data line
The master generates a STOP condition
The master sends a START condition
The master sends the 7-bit slave address plus a write bit
(low)
Acknowledge Bits
The addressed slave asserts an ACK on the data line
The master sends the 8-bit register address
Data transfers are acknowledged with an acknowledge bit
(ACK) or a not-acknowledge bit (NACK). Both the master
and the MAX20353 generate ACK bits. To generate an
ACK, pull SDA low before the rising edge of the ninth
clock pulse and hold it low during the high period of the
ninth clock pulse (see Figure 13). To generate a NACK,
leave SDA high before the rising edge of the ninth clock
pulse and leave it high for the duration of the ninth clock
pulse. Monitoring for NACK bits allows for detection of
unsuccessful data transfers.
The slave asserts an ACK on the data line only if the
address is valid (NAK if not)
The master sends a REPEATED START condition
The master sends the 7-bit slave address plus a read bit
(high)
The slave asserts an ACK on the data line
BURST READ
A
A
A
S
DEVICE SLAVE ADDRESS-W
REGISTER ADDRESS
8 DATA BITS - 1
A
A
Sr
DEVICE SLAVE ADDRESS-R
8 DATA BITS - 2
A
8 DATA BITS - 3
8 DATA BITS - N
P
NA
FROM MASTER TO SLAVE
FROM SLAVE TO MASTER
Figure 12. Burst Read Sequence
S
SCL
SDA
1
2
8
9
NOT ACKNOWLEDGE
ACKNOWLEDGE
Figure 13. Acknowledge
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AP Read
Application Processor Interface
To read a configuration register, APCmdOut is set to a read
opcode. Read opcodes signal the controller to transfer the
internal register contents to the APDataIn0-5 registers.
When the transfer is complete, APDataIn0-5 contain the
stored configuration settings or operation results and can
be read over I C. Because read opcodes expect no inputs,
any data stored in APDataOut0-5 is ignored. Figure 15
illustrates the AP read processes.
Several of the MAX20353’s functions are controlled by an
Application Processor (AP). AP commands read and write
configuration settings to the internal registers. Data transfer
is handled by the AP controller and is triggered by writes
to APCmdOut. There is a 5ms (typ), 9ms (max) latency
associated with setting commands. This delay increases if
the command requires additional processes such as ADC
measurements, haptic autotune, etc. When the transfer is
complete, INT goes low, APCmdResponseInt (bit seven
of direct register Int2 (0x05)) is set, and the controller
writes the value of the received opcode to APResponse.
Reading the data in APResponse provides verification of
the successful execution of an opcode.
2
AP Launch
Certain commands trigger additional functions in the
MAX20353. These commands, such as ADC_Measure_
Launch (opcode 0x53) and HPT_Autotune (opcode
0xAC), can require additional elaboration time for taking
measurements and computing the result. When the
processiscomplete,resultsmaybereadfromAPDataIn0-5
as in normal AP Read commands.
AP Write
To set configuration registers, data must first be written
to the APDataOut0-5 registers. Tables 54 to 197 detail
the functions of each APDataOut_ register for a given
opcode. Once APDataOut0-5 contain the configuration
bytes, writing an opcode to APCmdOut signals the
controller to transfer data to the internal registers. Note that
a write opcode only transfers the number of bytes defined
by the command. The controller ignores the contents of
all extra APDataOut_ registers. See Figure 14 for the
structure of an AP write procedure with an APResponse
opcode check.
Write-Protected Commands and Fields
If the factory configured bit WriteProtect is enabled,
the AP commands InputCurrent_Config_Write (0x10),
Charger_Config_Write (0x14), and Charger_ControlWrite
(0x1A) are not accessible. If the application processor
issues a request to one of these commands, the device
will respond with the SysError code MA_SYSERROR_
APCMD_WRITEPROTECT.
A settings are also write protected, but it is possible
to write these settings using an additional field in the
command that contains a password.
AP WRITE COMMAND
AP READ COMMAND
2
2
START I C WRITE
START I C WRITE
APCmdOut
APDataOut_ PAYLOAD
APCmdOut
2
I C STOP
AP COMMAND ELABORATION TIME
(5ms TYP, 9ms MAX)
2
I C STOP
2
I C STOP
AP COMMAND ELABORATION TIME
(5ms TYP, 9ms MAX)
APResponse
2
I C READ
APDataIn PAYLOAD
APResponse
Figure 14. Executing a Write Opcode and Reading the
MAX20353 Response
Figure 15. Executing a Read Opcode and Reading the
MAX20353 Response
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2
Direct Access I C Register Descriptions
Table 5. HardwareID Register (0x00)
ADDRESS:
MODE:
BIT
0x00
Read Only
7
6
5
4
3
2
1
0
NAME
HardwareID[7:0]
HardwareID
[7:0]
HardwareID[7:0] bits show information about the hardware revision of the MAX20353
Table 6. FirmwareID Register (0x01)
ADDRESS:
MODE:
BIT
0x01
Read Only
7
6
5
4
3
2
1
0
NAME
FirmwareID[7:0]
FirmwareID
[7:0]
FirmwareID[7:0] bits show information about the firmware revision of the MAX20353
Interrupt Registers
Table 7. Int0 Register (0x03)
ADDRESS:
MODE:
BIT
0x03
Clear On Read
7
6
5
4
3
2
1
0
ChgThmS
DInt
NAME
ThmStatInt
ChgStatInt
ILimInt
UsbOVPInt
UsbOkInt
ThmRegInt ChgTmoInt
ThmStatInt
ChgStatInt
ILimInt
Change in ThmStat caused interrupt.
Change in ChgStat caused interrupt, or first detection complete after POR.
Input current limit caused interrupt.
UsbOVPInt
Change in USBOVP caused interrupt.
Change in USBOk caused interrupt. Note: Registers written using opcodes 0x10, 0x14, 0x16, 0x18, 0x1A, and
0x1C are reset on charger insertion. After receiving a UsbOk interrupt, wait 10ms before writing any data using
these opcodes. Failure to wait 10ms may result in the data being overwritten to the default.
Change in ChgThmSD caused interrupt.
UsbOkInt
ChgThmSDInt
ThmRegInt
ChgTmoInt
Change in ChgThmReg caused interrupt.
Change in ChgTmoInt caused interrupt.
Table 8. Int1 Register (0x04)
ADDRESS:
MODE:
BIT
0x04
Clear On Read
7
6
5
4
3
2
1
0
ThmBuck
2Int
ThmBuck
1Int
UVLOLDO
2Int
UVLOLDO
1Int
ThmLDO
2Int
ThmLDO
1Int
NAME
ThmSDInt
BstFltInt
ThmSDInt
Change in ThmSD caused interrupt.
Change in BstFlt caused interrupt.
Change in ThmBuck2 caused interrupt
Change in ThmBuck1 caused interrupt.
BstFltInt
ThmBuck2Int
ThmBuck1Int
UVLOLDO2Int Change in UVLOLDO2 caused interrupt.
UVLOLDO1Int Change in UVLOLDO1 caused interrupt.
ThmLDO2Int
ThmLDO1Int
Change in ThmLDO2 caused interrupt.
Change in ThmLDO1 caused interrupt.
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Table 9. Int2 Register (0x05)
ADDRESS:
MODE:
BIT
0x05
Clear On Read
7
6
5
4
3
2
1
0
APCmdRes
pInt
ChgSysLi
mInt
NAME
SysErrInt
—
LRALockInt LRAActInt BBstThmInt SysBatLimInt
AP Command Response Interrupt
APCmdRespInt 0 = No new data available in APDataIn registers.
1 = New data available in APDataIn registers.
System Error Interrupt
SysErrInt
0 = No new error
1 = New Asynchronous System Error
LRA Lock Interrupt
Change in LRALock caused interrupt.
LRALockInt
LRAActInt
Change in LRAAct caused interrupt.
Change in BBstThm caused interrupt.
Change in SysBatLim caused interrupt.
Change in ChgSysLim caused interrupt.
BBstThmInt
SysBatLimInt
ChgSysLimInt
Status Registers
Table 10. Status0 Register (0x06)
ADDRESS:
MODE:
BIT
0x06
Read Only
7
6
5
4
3
2
1
0
NAME
—
—
ThmStat[2:0]
ChgStat[2:0]
Status of Thermistor Monitoring
000 = T < T1
001 = T1 < T < T2
010 = T2 < T < T3
011 = T3 < T < T4
100 = T > T4
ThmStat[2:0]
101 = No thermistor detected/THM high due to external pull-up
110 = NTC input disabled via ThmEn
111 = Automatic monitoring disabled because CHGIN is not present. THM can still be measured by ADC_
Measure_Launch
Status of Charger Mode
000 = Charger off
001 = Charging suspended due to temperature (see battery charger state diagram)
010 = Pre-charge in progress
ChgStat[2:0]
011 = Fast-charge constant current mode in progress
100 = Fast-charge constant voltage mode in progress
101 = Maintain charge in progress
110 = Maintain charger timer done
111 = Charger fault condition (see battery charger state diagram)
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Table 11. Status1 Register (0x07)
ADDRESS:
MODE:
BIT
0x07
Read Only
7
6
5
4
3
2
1
0
ChgJEITA
SD
ChgJEITA
Reg
NAME
—
—
ILim
UsbOVP
UsbOk
ChgTmo
CHGIN Input Current Limit
ILim
0 = CHGIN input current below limit
1 = CHGIN input current limit active
Status of CHGIN OVP
UsbOVP
UsbOk
0 = CHGIN overvoltage not detected
1 = CHGIN overvoltage detected
Status of CHGIN Input
0 = CHGIN Input not present or outside of valid range
1 = CHGIN Input present and valid
Status of Thermal Shutdown
ChgJEITASD
0 = Charger in normal operating mode
1 = Charger is in thermal shutdown
Status of Thermal Regulation
0 = Charger is functioning normally, or disabled
1 = Charger is running in thermal regulation mode and charging current is being actively reduced according to
JEITA settings
ChgJEITAReg
ChgTmo
Status of Time-Out Condition
0 = Charger is running normally, or disabled
1 = Charger has reached a time-out condition
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Table 12. Status2 Register (0x08)
ADDRESS:
MODE:
BIT
0x08
Read Only
7
6
5
4
3
2
1
0
UVLOLD
O2
NAME
ThmSD
BstFlt
ThmBuck2
ThmBuck1
UVLOLDO1
ThmLDO2
ThmLDO1
0 = Device operating normally
1 = Device in thermal shutdown
ThmSD
0 = HV Boost operating normally
1 = HV Boost in fault mode due to overcurrent or thermal shutdown
BstFlt
0 = Buck2 operating normally
1 = Buck2 in thermal shutdown
ThmBuck2
ThmBuck1
UVLOLDO2
UVLOLDO1
ThmLDO2
ThmLDO1
0 = Buck1 operating normally
1 = Buck1 in thermal shutdown
0 = LDO2 operating normally
1 = LDO2 UVLO active
0 = LDO1 operating normally
1 = LDO1 UVLO active
0 = LDO2 operating normally
1 = LDO2 in thermal shutdown
0 = LDO1 operating normally
1 = LDO1 in thermal shutdown
Table 13. Status3 Register (0x09)
ADDRESS:
MODE:
BIT
0x09
Read Only
7
6
5
4
3
2
1
0
NAME
APCmdResp
SysErr
—
LRALock
LRAAact
BBstThm
SysBatLim ChgSysLim
AP Command Response Ready
0 = APResponse register is empty
1 = APResponse register contains an opcode
APCmdResp
SysErr
System Error Detect
0 = No system error
1 = System error detected. See SystemError (register 0x0B)
0 = Haptic driver is not active or has not yet locked onto LRA resonant frequency
1 = Haptic driver has locked onto LRA resonant frequency
LRALock
LRAAct
0 = LRA driver not active
1 = LRA driver active
0 = Buck-boost converter operating normally
1 = Buck-boost converter in thermal shutdown
BBstThm
SysBatLim
ChgSysLim
0 = Charge current is not being actively reduced to regulate SYS
1 = Charge current actively being reduced to regulate SYS collapse
0 = Input current limit normal
1 = Input current limit being reduced to regulate CHGIN collapse
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Table 14. SystemError Register (0x0B)
ADDRESS:
MODE:
BIT
0x0B
Read Only
7
6
5
4
3
2
1
0
NAME
SystemError[7:0]
Last System Error Code:
0x00 - MA_SYSERROR_NONE: No System Error
0x01 - MA_SYSERROR_BOOT:
0x02 - MA_SYSERROR_BOOT_WDT: Restart due to a watchdog event
0x03 - MA_SYSERROR_BOOT_SWRSTREQ: Restart after Hard-Reset procedure
0x04 - MA_SYSERROR_HPT_TIMEOUT: Haptic driver disabled after timeout set through HptDrvTmo[5:0] has
expired
0x10 - MA_SYSERROR_APCMD_INPROGRESS: Attempt to use an AP command before previous command
completed
0x11 - MA_SYSERROR_APCMD_WRITEPROTECT: Attempt to use a write protected command or invalid
password
0x12 - MA_SYSERROR_APCMD_UNKNOWN: Attempt to use an undefined command
0x13 - MA_SYSERROR_APCMD_FAIL: AP command failed to execute
SystemError[7:0]
0x20 - MA_SYSERROR_HPT_DRP_LOW: Haptic driver disabled due to overcurrent condition on the DRP low-
side switch
0x21 - MA_SYSERROR_HPT_DRP_HIG: Haptic driver disabled due to overcurrent condition on the DRP high-
side switch
0x22 - MA_SYSERROR_HPT_DRN_LOW: Haptic driver disabled due to overcurrent condition on the DRN low-
side switch
0x23 - MA_SYSERROR_HPT_DRN_HIG: Haptic driver disabled due to overcurrent condition on the DRN high-
side switch
0x24 - MA_SYSERROR_HPT_THM_ERR: Haptic driver disabled due to thermal shutdown
0x25 - MA_SYSERROR_HPT_SYS_THR_HIT: Haptic driver disabled due to SYS falling below
HptSysUVLO[7:0] threshold
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Interrupt Mask Registers
Table 15. IntMask0 Register (0x0C)
ADDRESS:
MODE:
BIT
0x0C
Read/Write
7
6
5
4
3
2
1
0
ThmStat
IntM
ChgStat
IntM
UsbOVP
IntM
UsbOk
IntM
ChgJEITASD
IntM
ThmJEITA
RegIntM
ChgTmo
IntM
NAME
ILimIntM
ThmStatIntM masks the ThmStatInt interrupt in the Int0 register (0x03).
ThmStatIntM
0 = Masked
1 = Not masked
ChgStatIntM masks the ChgStatInt interrupt in the Int0 register (0x03).
ChgStatIntM
ILimIntM
0 = Masked
1 = Not masked
ILimIntM masks the ILimInt interrupt in the Int0 register (0x03).
0 = Masked
1 = Not masked
UsbOVPIntM masks the UsbOVPInt interrupt in the Int0 register (0x03).
UsbOVPIntM
UsbOkIntM
0 = Masked
1 = Not masked
UsbOkIntM masks the UsbOkInt interrupt in the Int0 register (0x03).
0 = Masked
1 = Not masked
ChgThmSDIntM masks the ChgThmSDInt interrupt in the Int0 register (0x03).
ChgJEITASDIntM
ChgJEITARegIntM
ChgTmoIntM
0 = Masked
1 = Not masked
ThmRegIntM masks the ThmRegInt interrupt in the Int0 register (0x03).
0 = Masked
1 = Not masked
ChgTmoIntM masks the ChgTmoInt interrupt in the Int0 register (0x03).
0 = Masked
1 = Not masked
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Table 16. IntMask1 Register (0x0D)
ADDRESS:
MODE:
BIT
0x0D
Read/Write
7
6
5
4
3
2
1
0
ThmSd
IntM
ThmBuck
2IntM
ThmBuck
1IntM
UVLOLDO
2IntM
UVLOLDO
1IntM
ThmLDO
2IntM
ThmLDO
1IntM
NAME
BstFltIntM
ThmSdIntM masks the ThmSdInt interrupt in the Int1 register (0x04).
ThmSdIntM
0 = Masked
1 = Not masked
BstFltIntM masks the BstFltInt interrupt in the Int1 register (0x04).
BstFltIntM
0 = Masked
1 = Not masked
ThmBuck2IntM masks the ThmBuck2Int interrupt in the Int1 register (0x04).
ThmBuck2IntM
ThmBuck1IntM
0 = Masked
1 = Not masked
Masks the ThmBuck1Int interrupt in the Int1 register (0x04).
0 = Masked
1 = Not masked
Masks the UVLOLDO2Int interrupt in the Int1 register (0x04).
UVLOLDO2IntM 0 = Masked
1 = Not masked
Masks the UVLOLDO1Int interrupt in the Int1 register (0x04).
UVLOLDO1IntM 0 = Masked
1 = Not masked
Masks the ThmLDO2Int interrupt in the Int1 register (0x04).
ThmLDO2IntM
ThmLDO1IntM
0 = Masked
1 = Not masked
Masks the ThmLDO1Int interrupt in the Int1 register (0x04).
0 = Masked
1 = Not masked
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Table 17. IntMask2 Register (0x0E)
ADDRESS:
MODE:
BIT
0x0E
Read/Write
7
6
5
4
3
2
1
0
APCmd
RespIntM
SysErr
IntM
LRALock
IntM
LRAAct
IntM
BBstThm
IntM
SysBatLim
IntM
ChgSys
LimIntM
NAME
—
Masks the APCmdRespInt interrupt in the Int2 register (0x05).
APCmdRespIntM 0 = Masked
1 = Not masked
Masks the SysErrInt interrupt in the Int2 register (0x05).
SysErrIntM
0 = Masked
1 = Not masked
Masks the LRALockInt interrupt in the Int2 register (0x05).
LRALockIntM
LRAActIntM
0 = Masked
1 = Not masked
Masks the LRAActInt interrupt in the Int2 register (0x05).
0 = Masked
1 = Not masked
Masks the BBstThmInt interrupt in the Int2 register (0x05).
BBstThmIntM
SysBatLimIntM
ChgSysLimIntM
0 = Masked
1 = Not masked
Masks the SysBatLimInt interrupt in the Int2 register (0x05).
0 = Masked
1 = Not masked
Masks the ChgSysLimInt interrupt in the Int2 register (0x05).
0 = Masked
1 = Not masked
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AP Interface Registers
Table 18. APDataOut0 Register (0x0F)
ADDRESS:
MODE:
BIT
0x0F
Read/Write
7
6
5
4
3
2
2
2
2
2
1
1
1
1
1
0
0
0
0
0
NAME
APDataOut0[7:0]
APDataOut0[7:0] Data register 0 for AP write commands.
Table 19. APDataOut1 Register (0x10)
ADDRESS:
MODE:
BIT
0x10
Read/Write
7
6
5
4
3
NAME
APDataOut1[7:0]
APDataOut1[7:0] Data register 1 for AP write commands.
Table 20. APDataOut2 Register (0x11)
ADDRESS:
MODE:
BIT
0x11
Read/Write
7
6
5
4
3
NAME
APDataOut2[7:0]
APDataOut2[7:0] Data register 2 for AP write commands.
Table 21. APDataOut3 Register (0x12)
ADDRESS:
MODE:
BIT
0x12
Read/Write
7
6
5
4
3
NAME
APDataOut3[7:0]
APDataOut3[7:0] Data register 3 for AP write commands.
Table 22. APDataOut4 Register (0x13)
ADDRESS:
MODE:
BIT
0x13
Read/Write
7
6
5
4
3
NAME
APDataOut4[7:0]
APDataOut4[7:0] Data register 4 for AP write commands.
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Table 23. APDataOut5 Register (0x14)
ADDRESS:
MODE:
BIT
0x14
Read/Write
7
6
5
4
3
2
1
0
NAME
APDataOut5[7:0]
APDataOut5[7:0] Data register 5 for AP write commands.
Table 24. APDataOut6 Register (0x15)
ADDRESS:
MODE:
BIT
0x15
Read/Write
7
6
5
4
3
2
1
0
NAME
APDataOut6[7:0]
APDataOut6[7:0] Data register 6 for AP write commands.
Table 25. APCmdOut Register (0x17)
ADDRESS:
MODE:
0x17
Read/Write
7
BIT
6
5
4
3
2
1
0
NAME
APCmdOut[7:0]
APCmdOut[7:0]
Opcode command register
Table 26. APResponse Register (0x18)
ADDRESS:
MODE:
BIT
0x18
Read Only
7
6
5
4
3
2
1
0
NAME
APResponse [7:0]
APResponse[7:0] AP command response register
Table 27. APDataIn0 Register (0x19)
ADDRESS:
MODE:
0x19
Read Only
7
BIT
6
5
4
3
2
1
0
NAME
APDataIn0[7:0]
APDataIn0[7:0]
Data register 0 for AP read commands.
Table 28. APDataIn1 Register (0x1A)
ADDRESS:
MODE:
0x1A
Read Only
7
BIT
6
5
4
3
2
1
0
NAME
APDataIn1[7:0]
APDataIn1[7:0]
Data register 1 for AP read commands.
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Table 29. APDataIn2 Register (0x1B)
ADDRESS:
MODE:
0x1B
Read Only
7
BIT
6
5
4
3
2
2
2
2
1
1
1
1
0
0
0
0
NAME
APDataIn2[7:0]
APDataIn2[7:0]
Data register 2 for AP read commands.
Table 30. APDataIn3 Register (0x1C)
ADDRESS:
MODE:
0x1C
Read Only
7
BIT
6
5
4
3
NAME
APDataIn3[7:0]
APDataIn3[7:0]
Data register 3 for AP read commands.
Table 31. APDataIn4 Register (0x1D)
ADDRESS:
MODE:
BIT
0x1D
Read Only
7
6
5
4
3
NAME
APDataOut4[7:0]
APDataOut4[7:0] Data register 4 for AP write commands.
Table 32. APDataIn5 Register (0x1E)
ADDRESS:
MODE:
0x1E
Read Only
7
BIT
6
5
4
3
NAME
APDataIn5[7:0]
APDataIn5[7:0]
Data register 5 for AP read commands.
Buck1 DVS Registers
Table 33. Buck1I2CDVS Register (0x1F)
ADDRESS:
MODE:
BIT
0x1F
Read/Write
7
6
5
4
3
2
1
0
Buck1DVS
En
NAME
—
—
—
—
—
—
—
Buck1 Alternate Output Voltage Setting 1
Sets the Buck1 voltage when MPC1 = 0 and MPC0 = 1. 0.700V to 2.275V, linear scale, increments of 25mV.
000000 = 0.700V
000001 = 0.725V
…
Buck1DVSEn
111111 = 2.275V
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LDO Direct Register
Table 34. LDODirect Register (0x20)
ADDRESS:
MODE:
BIT
0x20
Read/Write
7
6
5
4
3
2
1
0
LDO2Dir
En
LDO1Dir
En
NAME
—
—
—
—
—
—
LDO2 Direct Enable. Valid only if LDO2En = 11
0 = LDO2 Off
LDO2DirEn
1 = LDO2 On
LDO1 Direct Enable Valid only if LDO1En = 11
0 = LDO1 Off
LDO1DirEn
1 = LDO1 On
MPC Direct Registers
Table 35. MPCDirectWrite Register (0x21)
ADDRESS:
MODE:
BIT
0x21
Read/Write
7
6
5
4
3
2
1
0
NAME
—
—
—
MPC4Write MPC3Write MPC2Write MPC1Write MPC0Write
MPC4 Direct Write (returns 0 if MPC is configured as output (GPIO_HiZB = 1))
MPC4Write
MPC3Write
MPC2Write
MPC1Write
MPC0Write
0 = set MPC4 low
1 = set MPC4 high
MPC3 Direct Write (returns 0 if MPC is configured as output (GPIO_HiZB = 1))
0 = set MPC3 low
1 = set MPC3 high
MPC2 Direct Write (returns 0 if MPC is configured as output (GPIO_HiZB = 1))
0 = set MPC2 low
1 = set MPC2 high
MPC1 Direct Write (returns 0 if MPC is configured as output (GPIO_HiZB = 1))
0 = set MPC1 low
1 = set MPC1 high
MPC0 Direct Write (returns 0 if MPC is configured as output (GPIO_HiZB = 1))
0 = set MPC0 low
1 = set MPC0 high
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Table 36. MPCDirectRead Register (0x22)
ADDRESS:
MODE:
BIT
0x22
Read Only
7
6
5
4
3
2
1
0
NAME
—
—
—
MPC4Read MPC3Read MPC2Read MPC1Read MPC0Read
MPC4 Direct Readback
0 = MPC4 is low
1 = MPC4 is high
MPC4Read
MPC3Read
MPC2Read
MPC1Read
MPC0Read
MPC3 Direct Readback
0 = MPC3 is low
1 = MPC3 is high
MPC2 Direct Readback
0 = MPC2 is low
1 = MPC2 is high
MPC1 Direct Readback
0 = MPC1 is low
1 = MPC1 is high
MPC0 Direct Readback
0 = MPC0 is low
1 = MPC0 is high
Table 37. DVSVlt1 Register (0x23)
ADDRESS:
MODE:
BIT
0x23
Read/Write
7
6
5
4
3
2
1
0
NAME
—
—
Buck1DVSVSet1[5:0]
Buck1 Alternate Output Voltage Setting 1
Sets the Buck1 voltage when MPC1 = 0 and MPC0 = 1. 0.700V to 2.275V, linear scale, increments of 25mV.
Buck1DVSV
Set1[5:0]
000000 = 0.700V
000001 = 0.725V
…
111111 = 2.275V
Table 38. DVSVlt2 Register (0x24)
ADDRESS:
MODE:
BIT
0x24
Read/Write
7
6
5
4
3
2
1
0
NAME
—
—
Buck1DVSVSet2[5:0]
Buck1 Alternate Output Voltage Setting 2
Sets the Buck1 voltage when MPC1 = 1 and MPC0 = 0. 0.700V to 2.275V, linear scale, increments of 25mV.
Buck1DVSV
Set2[5:0]
000000 = 0.700V
000001 = 0.725V
…
111111 = 2.275V
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Table 39. DVSVlt3 Register (0x25)
ADDRESS:
MODE:
BIT
0x25
Read/Write
7
6
5
4
3
2
1
0
NAME
—
—
Buck1DVSVSet3[5:0]
Buck1 Alternate Output Voltage Setting 3
Sets the Buck1 voltage when MPC1 = 1 and MPC0 = 1. 0.700V to 2.275V, linear scale, increments of 25mV.
Buck1DVSV
Set3[5:0]
000000 = 0.700V
000001 = 0.725V
…
111111 = 2.275V
Haptic Braking Registers
Table 40. AutoBrkCfg0 Register (0x26)
ADDRESS:
MODE:
BIT
0x26
Read/Write
7
6
5
4
3
2
1
0
AutoBrk
PeakMeas
AutoBrkFltr
SatStop
NAME
—
—
—
—
—
AutoBrkDis
BEMF Amplitude Detection Sample Points
AutoBrkPeak
Meas
Determines if two or four BEMF sample points are used during automatic braking.
0 = Four sample points are used to measure the BEMF amplitude
1 = Two sample points are used to measure the BEMF amplitude
BEMF Zero Crossing Comparator Counter Saturation
If enabled, the automatic braking function exits when the counter on the zero crossing comparator is saturated
during a braking window within one of the BrkCyc[4:0] half periods.
0 = Do not exit braking when the zero crossing comparator counter is saturated
1 = Exit braking when the zero crossing comparator counter is saturated
AutoBrkFltrSat
Stop
Automatic Braking Disable
AutoBrkDis
0 = Automatic braking enabled
1 = Automatic braking disabled
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Table 41. AutoBrkCfg1 Register (0x27)
ADDRESS:
MODE:
BIT
0x27
Read/Write
7
6
5
4
3
2
1
0
NAME
AutoBrkMeasWdw [3:0]
BEMF Amplitude Detection Window
Duration of BEMF amplitude measurement window during automatic braking. LSB = 128/25.6MHz
AutoBrkMeasTh [1:0]
AutoBrkMeasEnd [1:0]
AutoBrkMeas
Wdw [3:0]
BEMF Amplitude Detection Threshold
Threshold for BEMF absolute amplitude measurement during automatic braking.
AutoBrkMeas
Th [1:0]
00 = 2.5mV
01 = 5.0mV
10 = 7.5mV
11 = 10.0mV
BEMF Amplitude Detection End Counter
Sets the number of consecutive BEMF amplitude detections in which the absolute amplitude of the BEMF
must be less than AutoBrkMeasTh[1:0] for more than half of AutoBrkMeasWdw[3:0] in order to stop automatic
AutoBrkMeas
End[1:0]
braking.
00 = 1
01 = 2
10 = 3
11 = 4
Haptic RAM Registers
Table 42. HptRAMAddr Register (0x28)
ADDRESS:
MODE:
BIT
0x28
Read/Write
7
6
5
4
3
2
1
0
NAME
HptRAMAdd[7:0]
HptRAMAdd[7:0] RAM address to which haptic pattern data in registers 0x29, 0x2A, 0x2B will be written.
Table 43. HptRAMDataH Register (0x29)
ADDRESS:
MODE:
BIT
0x29
Read/Write
7
6
5
4
3
2
1
0
NAME
nLSx[1:0]
AmpSign
Amp[6:2]
Table 44. HptRAMDataM Register (0x2A)
ADDRESS:
MODE:
BIT
0x2A
Read/Write
7
6
5
4
4
3
2
2
1
1
0
NAME
Amp[1:0]
Dur[4:0]
Wait[4]
Table 45. HptRAMDataL Register (0x2B)
ADDRESS:
MODE:
BIT
0x2B
Read/Write
7
6
5
3
0
NAME
Wait[3:0]
Rpt[3:0]
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LED Direct Registers
Table 46. LEDStepDirect Register (0x2C)
ADDRESS:
MODE:
BIT
0x2C
Read/Write
7
6
5
4
3
2
1
0
LDO1_
MPC2CNT
LDO1_
MPC2CNF
NAME
LED2Open LED1Open LED0Open
—
LEDIStep[1:0]
LED2 Open detection (Read only)
LED2Open
0 = V
1 = V
> V
LED_DET
V
LED2
LED2 ≤ LED_DET
or LED2 disabled
LED1 Open detection (Read only)
LED1Open
LED0Open
0 = V
1 = V
> V
V
LED1
LED1 ≤ LED_DET
LED_DET
or LED1 disabled
LED0 Open detection (Read only)
0 = V
1 = V
> V
LED0
LED0 ≤ LED_DET
LED_DET
V
or LED0 disabled
LDO1/MPC2 Control Bit
LDO1_
Enables the LDO1_MPC2CNF functionality for LDO1.
MPC2CNT
0 = MPC2 has no effect on LDO1
1 = LDO1_MPC2CNF is valid and MPC2 function is enabled.
LDO1/MPC2 Configuration Bit
LDO1_
Sets the effect of MPC2 on LDO1 when LDO1_MPC2CNT = 1.
MPC2CNF
0 = MPC2 controls LDO/SW mode of LDO1 (MPC2 Low = LDO mode, MPC2 High = SW mode).
1 = MPC2 controls LDO1 Enable (MPC2 Low = LDO1 disabled, MPC2 High = LDO1 enabled in SW mode).
LED Direct Current Step Register
00 = 0.6mA
LEDIStep[1:0]
01 = 1.0mA
10 = 1.2mA
11 = RESERVED
Table 47. LED0Direct Register (0x2D)
ADDRESS:
MODE:
BIT
0x2D
Read/Write
7
6
5
4
3
2
1
0
NAME
LED0En[2:0]
LED0ISet[4:0]
LED0 Driver Enable
000 = Off
001 = LED0 On
010 = Controlled by internal charger status signal
011 = Controlled by MPC0
LED0En[2:0]
100 = Controlled by MPC1
101 = Controlled by MPC2
110 = Controlled by MPC3
111 = Controlled by MPC4
LED0 Direct Step Count
LED0 current in mA is given by (LED0ISet[4:0] + 1) x LEDIStep[1:0]
0x00 = 0.6mA/1.0mA/1.2mA
0x01 = 1.2mA/2.0mA/2.4mA
…
LED0ISet[4:0]
0x18 = 15mA/25mA/30mA
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Table 48. LED1Direct Register (0x2E)
ADDRESS:
MODE:
BIT
0x2E
Read/Write
7
6
5
4
3
2
1
0
NAME
LED1En[2:0]
LED1ISet[4:0]
LED1 Driver Enable
000 = Off
001 = LED1 On
010 = Controlled by internal charger status signal
011 = Controlled by MPC0
LED1En[2:0]
100 = Controlled by MPC1
101 = Controlled by MPC2
110 = Controlled by MPC3
111 = Controlled by MPC4
LED1 Direct Step Count
LED1 current in mA is given by (LED1ISet[4:0] + 1) x LEDIStep[1:0]
0x00 = 0.6mA/1.0mA/1.2mA
0x01 = 1.2mA/2.0mA/2.4mA
…
LED1ISet[4:0]
0x18 = 15mA/25mA/30mA
Table 49. LED2Direct Register (0x2F)
ADDRESS:
MODE:
BIT
0x2F
Read/Write
7
6
5
4
3
2
1
0
NAME
LED2En[2:0]
LED2ISet[4:0]
LED2 Driver Enable
000 = Off
001 = LED2 On
010 = Controlled by internal charger status signal
011 = Controlled by MPC0
LED2En[2:0]
100 = Controlled by MPC1
101 = Controlled by MPC2
110 = Controlled by MPC3
111 = Controlled by MPC4
LED2 Direct Step Count
LED2 current in mA is given by (LED2ISet[4:0] + 1) x LEDIStep[1:0]
0x00 = 0.6mA/1.0mA/1.2mA
0x01 = 1.2mA/2.0mA/2.4mA
…
LED2ISet[4:0]
0x18 = 15mA/25mA/30mA
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Haptic Direct Registers
Table 50. HptDirect0 Register (0x30)
ADDRESS:
MODE:
BIT
0x30
Read/Write
7
6
5
4
3
2
1
0
HptThmProt
Dis
HptOCPr
otDis
NAME
—
—
—
—
—
HptOffImp
Haptic Driver Output Off State Impedance
HptOffImp
0 = When haptic driver is disabled, outputs are strongly shorted to GND through low-side driver FETs.
1 = When haptic driver is disabled, outputs are shorted to GND with 15kΩ pull-down.
Haptic Driver Thermal Protection Disable
If HptThmProtDis = 0 and the haptic driver shuts down due to an over temperature condition, SystemError[7:0]
= 0x24 is issued and HptLock = 1. See Opcode 0xA8 for restarting the haptic driver
HptThmProtDis
HptOCProtDis
0 = Thermal protection enabled. Haptic driver will shut down if T ≥ 150°C (typ)
J
1 = Thermal protection disabled.
Haptic Driver Overcurrent Protection Disable
If HptOCProtDis = 0 and the haptic driver shuts down due to an overcurrent condition, SystemError[7:0] will
equal to one of four codes (0x20-0x23) is issued and HptLock = 1. See Opcode 0xA8 for restarting the haptic
driver
0 = Overcurrent protection enabled. Haptic driver will shut down if current exceeds 1A (typ)
1 = Overcurrent protection disabled.
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Table 51. HptDirect1 Register (0x31)
ADDRESS:
MODE:
BIT
0x31
Read/Write
7
6
5
4
3
2
1
0
NAME
HptExtTrig
HptRamEn
HptDrvEn
HptDrvMode[4:0]
Haptic driver external trigger pattern for ETRG and RAMHPI driver mode (HptDrvMode = 01100, 10010,
respectively).
0 = No pattern triggered.
1 = Vibration triggered
HptExtTrig
HptRamEn
Haptic RAM Block Enable
0 = RAM disabled.
1 = RAM enabled.
Haptic Driver Enable
In all modes, the haptic driver must be enabled at the same time or before providing the desired mode in
HptDrvMod[4:0]. The HptDrvEn bit must remain set during the vibration. Once vibration finishes, HptDrvMod[4:0]
must be set to “00000” before the haptic driver may be disabled via HptDrvEn = 0 for power savings.
0 = Haptic driver block disabled.
HptDrvEn
1 = Haptic driver block enabled.
Haptic Driver Mode Selection
00000 = Disable haptic driver
00001 = Enable PPWM0 mode and provide amplitude based on PWM duty cycle on MPC0
00010 = Enable PPWM1 mode and provide amplitude based on PWM duty cycle on MPC1
00011 = Enable PPWM2 mode and provide amplitude based on PWM duty cycle on MPC2
00100 = Enable PPWM3 mode and provide amplitude based on PWM duty cycle on MPC3
00101 = Enable PPWM4 mode and provide amplitude based on PWM duty cycle on MPC4
00110 = Enable RTI2C mode and provide current output amplitude based on the contents of HptRTI2CAmp(0x32)
00111 = Enable ETRG0 mode. Provide a pulse on MPC0 to start vibration (See “ETRG Mode” section for details)
01000 = Enable ETRG1 mode. Provide a pulse on MPC1 to start vibration (See “ETRG Mode” section for details)
01001 = Enable ETRG2 mode. Provide a pulse on MPC2 to start vibration (See “ETRG Mode” section for details)
01010 = Enable ETRG3 mode. Provide a pulse on MPC3 to start vibration (See “ETRG Mode” section for details)
01011 = Enable ETRG4 mode. Provide a pulse on MPC4 to start vibration (See “ETRG Mode” section for details)
01100 = Enable ETRGI mode via I2C. Set HptExtTrg(0x31[7]) bit to start vibration (See “ETRG Mode” section for
details)
HptDrvMode
[4:0]
01101 = Enable RAMHP0 mode. Provide a pulse on MPC0 to start vibration (See “RAMHP Mode” section for
details)
01110 = Enable RAMHP1 mode. Provide a pulse on MPC1 to start vibration (See “RAMHP Mode” section for
details)
01111 = Enable RAMHP2 mode. Provide a pulse on MPC2 to start vibration (See “RAMHP Mode” section for
details)
10000 = Enable RAMHP3 mode. Provide a pulse on MPC3 to start vibration (See “RAMHP Mode” section for
details)
10001 = Enable RAMHP4 mode. Provide a pulse on MPC4 to start vibration (See “RAMHP Mode” section for
details)
10010 = Enable RAMHPI mode via I2C. Set HptExtTrg(0x31[7]) bit to start vibration (See “RAMHP Mode” section
for details)
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Table 52. HptRTI2CAmp Register (0x32)
ADDRESS:
MODE:
BIT
0x32
Read/Write
7
6
5
4
3
2
1
0
HptRTI2C
Sign
NAME
HptRTI2CAmp[6:0]
HptRTI2CSign
Sign of haptic pattern amplitude in RTI2C mode (HptDrvMode = 00110)
Amplitude of haptic pattern in RTI2C mode (HptDrvMode = 00110). LSB = V
HptRTI2Camp
[6:0]
/128
SYS
Table 53. HptPatRAMAddr Register (0x33)
ADDRESS:
MODE:
BIT
0x33
Read/Write
7
6
5
4
3
2
1
0
NAME
HptPatRAMAddr[7:0]
HptPatRAMAddr
[7:0]
Address of first sample in vibration pattern to be run in RAMHP_ mode (HptDrvMode = 01101, 01111, 10000,
10001, 10010)
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AP Command Register Descriptions
GPIO Config Commands
Table 54. 0x01 – GPIO_Config_Write
MODE
Write
B7
BIT
B6
B5
B4
B3
B2
B1
B0
APCmdOut
(0x01)
0
0
0
0
0
0
0
1
APDataOut0
APDataOut1
APDataOut2
APDataOut3
APDataOut4
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
GPIO0Cmd
GPIO1Cmd
GPIO2Cmd
GPIO3Cmd
GPIO4Cmd
GPIO0OD
GPIO1OD
GPIO2OD
GPIO3OD
GPIO4OD
GPIO0HiZB
GPIO1HiZB
GPIO2HiZB
GPIO3HiZB
GPIO4HiZB
GPIO0Res
GPIO1Res
GPIO2Res
GPIO3Res
GPIO4Res
GPIO0Pup
GPIO1Pup
GPIO2Pup
GPIO3Pup
GPIO4Pup
GPIO Output Control
Valid only if GPIO_ is configured as output (GPIO_HiZB = 1)
GPIO_Cmd
0 = MPC_ output controlled by AP command
2
1 = MPC_ output controlled by I C direct register
GPIO Output Configuration
Valid only if GPIO_ is configured as output (GPIO_HiZB = 1)
0 = MPC_ is push-pull connected to BK2OUT
1 = MPC_ is open drain
GPIO_OD
GPIO_HiZB
GPIO_Res
GPIO Direction
0 = MPC_ is Hi-Z. Input buffer enabled
1 = MPC_ is not Hi-Z. Output buffer enabled
GPIO Resistor Presence
Valid only if GPIO_ is configured as input (GPIO_HiZB = 0)
0 = Resistor not connected to MPC_
1 = Resistor connected to MPC_
GPIO Resistor Configuration
Valid only if there is a resistor on GPIO_ (GPIO_Res = 1)
0 = Pulldown connected to MPC_
GPIO_Pup
1 = Pullup to V
connected MCP_
CCINT
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Table 55. GPIO_Config_Write Response
BIT
B7
B6
B5
B4
B3
B2
B1
B0
APResponse
(0x01)
0
0
0
0
0
0
0
1
Table 56. 0x02 – GPIO_Config_Read
MODE
Read
B7
BIT
B6
B5
B4
B3
B2
B1
B0
APCmdOut
(0x02)
0
0
0
0
0
0
1
0
Table 57. GPIO_Config_Read Response
BIT
B7
B6
B5
B4
B3
B2
B1
B0
APResponse
(0x02)
0
0
0
0
0
0
1
0
APDataIn0
APDataIn1
APDataIn2
APDataIn3
APDataIn4
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
GPIO0Cmd GPIO0OD
GPIO1Cmd GPIO1OD
GPIO2Cmd GPIO2OD
GPIO3Cmd GPIO3OD
GPIO4Cmd GPIO4OD
GPIO0HiZB
GPIO1HiZB
GPIO2HiZB
GPIO3HiZB
GPIO4HiZB
GPIO0Res
GPIO1Res
GPIO2Res
GPIO3Res
GPIO4Res
GPIO0Pup
GPIO1Pup
GPIO2Pup
GPIO3Pup
GPIO4Pup
Table 58. 0x03 – GPIO_Control_Write
MODE
Write
B7
BIT
B6
0
B5
0
B4
0
B3
0
B2
0
B1
1
B0
1
APCmdOut
(0x03)
0
APDataOut0
—
—
—
GPIO4Out
GPIO3Out
GPIO2Out
GPIO1Out
GPIO0Out
Valid only if GPIO_ is configured as output driven by AP Command (GPIO_Cmd = 0)
0 = Set GPIO_ LOW
GPIO_Out
1 = Set GPIO_ HIGH (if GPIO_OD = 0)/Hi-Z (if GPIO_OD = 1)
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Table 59. GPIO_Control_Write Response
BIT
B7
B6
B5
B4
B3
B2
B1
B0
APResponse
(0x03)
0
0
0
0
0
0
1
1
Table 60. 0x04 – GPIO_Control_Read
MODE
Read
B7
BIT
B6
B5
B4
B3
B2
B1
B0
APCmdOut
(0x04)
0
0
0
0
0
1
0
0
Table 61. GPIO_Control_Read Response
MODE
Write
B7
BIT
B6
B5
B4
B3
B2
B1
B0
APResponse
(0x04)
0
0
0
0
0
1
0
0
APDataIn0
—
—
—
—
—
—
GPIO4Out
GPIO4Stat
GPIO3Out
GPIO3Stat
GPIO2Out
GPIO2Stat
GPIO1Out
GPIO1Stat
GPIO0Out
GPIO0Stat
APDataIn1
GPIO State
GPIO_Stat
0 = GPIO_ LOW
1 = GPIO_ HIGH (if GPIO_Od = 0) / Hi-Z (if GPIO_Od = 1)
Table 62. 0x06 – MPC_Config_Write
MODE
Write
B7
BIT
B6
B5
B4
B3
B2
B1
B0
APCmdOut (0x06)
0
0
0
0
0
1
1
0
BBstMPC
En
SFOUTM
PCEn
CPMP
CEn
LDO2MP
CEn
LDO1MP
CEn
Buck2MP
CEn
Buck1MP
BstMP
CEn
APDataOut0 MPC0
APDataOut1 MPC1
APDataOut2 MPC2
APDataOut3 MPC3
APDataOut4 MPC4
CEn
BBstMPC
En
SFOUTM
PCEn
CPMP
CEn
LDO2MP
CEn
LDO1MP
CEn
Buck2MP
Buck1MP
CEn
BstMP
CEn
CEn
BBstMPC
En
SFOUTM
PCEn
CPMP
CEn
LDO2MP
CEn
LDO1MP
CEn
Buck2MP
CEn
Buck1MP
CEn
BstMP
CEn
BBstMPC
En
SFOUTM
PCEn
CPMP
CEn
LDO2MP
CEn
LDO1MP
CEn
Buck2MP
CEn
Buck1MP
CEn
BstMP
CEn
BBstMPC
SFOUTM
PCEn
CPMP
CEn
LDO2MP
CEn
LDO1MP
CEn
Buck2MP
CEn
Buck1MP
CEn
BstMP
CEn
En
Shaded fields are defaulted to 1 if the corresponding resources contain the following OTP setting:
XXXSeq = 111 (controlled by BstEn after 100% of Boot/POR Process Delay Control)
XXXEn = 10 (MPC registers control)
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Table 62. 0x06 – MPC_Config_Write (continued)
Buck-Boost Enable Configuration
Effective only when BBstSeq = 111 and BBstEn = 10
0 = MPC_ has no effect on Buck-boost
BBstMPCEn
1 = Buck-boost enabled when MPC_ is high
SFOUT LDO Enable Configuration
Effective only when SFOUTEn = 10
0 = MPC_ has no effect on SFOUT LDO
SFOUTMPCEn
1 = SFOUT LDO enabled when CHGIN is present and MPC_ is high
Charge Pump Enable Configuration
Effective only when CPSeq = 111 and CPEn = 10
0 = MPC_ has no effect on Charge Pump
CPMPCEn
1 = Charge Pump enabled when MPC_ is high
LDO2 Enable Configuration
Effective only when LDO2Seq = 111 and LDO2En = 10
0 = MPC_ has no effect on LDO2
LDO2MPCEn
1 = LDO2 enabled when MPC_ is high
LDO1 Enable Configuration
Effective only when LDO1Seq = 111 and LDO1En = 10
0 = MPC_ has no effect on LDO1
LDO1MPCEn
1 = LDO1 enabled when MPC_ is high
Buck2 Enable Configuration
Effective only when Buck2Seq = 111 and Buck2En = 10
0 = MPC_ has no effect on Buck2
Buck2MPCEn
1 = Buck2 enabled when MPC_ is high
Buck1 Enable Configuration
Effective only when Buck1Seq = 111 and Buck1En = 10
0 = MPC_ has no effect on Buck1
Buck1MPCEn
1 = Buck1 enabled when MPC_ is high
Boost Enable Configuration
Effective only when BstSeq = 111 and BstEn = 10
0 = MPC_ has no effect on Boost
BstMPCEn
1 = Boost enabled when MPC_ is high
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Table 63. MPC_Config_Write Response
BIT
B7
B6
B5
B4
B3
B2
B1
B0
APResponse
(0x06)
0
0
0
0
0
1
1
0
Table 64. 0x07 – MPC_Config_Read
MODE
Read
B7
BIT
B6
B5
B4
B3
B2
B1
B0
APCmdOut
(0x07)
0
0
0
0
0
1
1
1
Table 65. MPC_Config_Read Response
BIT
B7
B6
B5
B4
B3
B2
B1
B0
APResponse
(0x07)
0
0
0
0
0
1
1
1
BBstMPC
En
SFOUTM
PCEn
CPMP
CEn
LDO2MP
CEn
LDO1MP
CEn
Buck2MP
CEn
Buck1MP
CEn
BstMP
CEn
APDataIn0 MPC0
APDataIn1 MPC1
APDataIn2 MPC2
APDataIn3 MPC3
APDataIn4 MPC4
BBstMPC
En
SFOUTM
PCEn
CPMP
CEn
LDO2MP
CEn
LDO1MP
CEn
Buck2MP
CEn
Buck1MP
CEn
BstMP
CEn
BBstMPC
En
SFOUTM
PCEn
CPMP
CEn
LDO2MP
CEn
LDO1MP
CEn
Buck2MP
CEn
Buck1MP
CEn
BstMP
CEn
BBstMPC
En
SFOUTM
PCEn
CPMP
CEn
LDO2MP
CEn
LDO1MP
CEn
Buck2MP
CEn
Buck1MP
CEn
BstMP
CEn
BBstMPC
En
SFOUTM
PCEn
CPMP
CEn
LDO2MP
CEn
LDO1MP
CEn
Buck2MP
CEn
Buck1MP
CEn
BstMP
CEn
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Input Current Limit Commands
Note: Registers written using opcodes 0x10, 0x14, 0x16, 0x18, 0x1A, and 0x1C are reset on charger insertion. After receiving a
UsbOk interrupt, wait 10ms before writing any data using these opcodes. Failure to wait 10ms may result in the data being overwrit-
ten to the default.
Table 66. 0x10 – InputCurrent_Config_Write
MODE
Write
B7
BIT
B6
0
B5
0
B4
B3
B2
B1
0
B0
APCmdOut
(0x10)
0
1
0
0
0
APDataOut0
—
—
—
ILimBlank[1:0]
ILimCntl[2:0]
CHGIN Current Limiter Blanking Time
00 = No debounce (allow a few clock cycles for resampling)
01 = 0.5ms
10 = 1ms
ILimBlank
[1:0]
11 = 10ms
CHGIN Programmable Input Current Limit
(See EC table for details)
000 = 50mA
001 =100mA
010 = 150mA
011 = 200mA
ILimCntl[2:0]
100 = 300mA
101 = 400mA
110 = 500mA
111 = 1000mA
Table 67. InputCurrent_Config_Write Response
BIT
B7
B6
B5
B4
B3
B2
B1
B0
APResponse
(0x10)
0
0
0
1
0
0
0
0
Table 68. 0x11 – InputCurrent_Config_Read
MODE
Read
B7
BIT
B6
B5
B4
B3
B2
B1
B0
APCmdOut
(0x11)
0
0
0
1
0
0
0
0
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Table 69. InputCurrent_Config_Read Response
BIT
B7
B6
B5
B4
B3
B2
B1
0
B0
APResponse
(0x11)
0
0
0
1
0
0
0
APDataIn0
—
—
—
ILimBlank[1:0]
ILimCntl[2:0]
Thermal Shutdown Configuration Commands
Table 70. 0x12 – ThermalShutdown_Config_Read
MODE
Write
B7
BIT
B6
0
B5
0
B4
1
B3
B2
B1
B0
APCmdOut
(0x12)
0
0
0
1
0
APDataOut0
—
—
—
—
—
—
TShdnTmo[1:0]
Thermal Shutdown Retry Timeout Boot sequence only
00 = Latch-Off (See Power State diagrams (Figure 1a to Figure 1f) for restart procedure)
01 = 500ms
10 = 1s
TShdnTmo
[1:0]
11 = 5s
Table 71. ThermalShutdown_Config_Read Response
B7
B6
B5
B4
B3
B2
B1
B0
APResponse
(0x12)
0
0
0
1
0
0
1
0
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Charger Configuration Commands
Table 72. 0x14 – Charger_Config_Write
MODE
Write
B7
BIT
B6
0
B5
B4
B3
B2
B1
B0
APCmdOut
(0x14)
0
0
1
0
1
0
0
APDataOut0
APDataOut1
—
—
—
MtChgTmr[1:0]
FChgTmr[1:0]
IPChg[1:0]
PChgTmr[1:0]
VPChg[2:0]
ChgDone[1:0]
ChgAuto
Stp
ChgAuto
Re
APDataOut2
APDataOut3
BatReChg[1:0]
BatReg[3:0]
—
—
—
—
SysMinVlt[2:0]
Maintain Charge Timer Setting
00 = 0min
MtChgTmr[1:0] 01 = 15min
10 = 30min
11 = 60min
Fast Charge Timer Setting
00 = 75min
01 = 150min
10 = 300min
11 = 600min
FChgTmr[1:0]
PChgTmr[1:0]
Pre-charge Timer Setting
00 = 30min
01 = 60min
10 = 120min
11 = 240min
Precharge Voltage Threshold Setting
000 = 2.1V
001 = 2.25V
010 = 2.40V
VPChg[2:0]
011 = 2.55V
100 = 2.70V
101 = 2.85V
110 = 3.00V
111 = 3.15V
Precharge Current Setting
00 = 0.05 x IFChg
01 = 0.1 x IFChg
IPChg[1:0]
10 = 0.2 x IFChg
11 = 0.3 x IFChg
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Table 72. 0x14 – Charger_Config_Write (continued)
Charge Done Threshold Setting
00 = 0.05 x IFChg
ChgDone[1:0]
01 = 0.1 x IFChg
10 = 0.2 x IFChg
11 = 0.3 x IFChg
Charger Auto-Stop
Controls the transition from Maintain Charger to Maintain Charger Done.
0 = Auto-Stop disabled.
1 = Auto-Stop enabled.
ChgAutoStp
ChgAutoRe
Charger Auto-Restart Control
0 = Charger remains in maintain charge done even when V
state diagram)
is less than charge restart threshold (see Charger
BAT
1 = Charger automatically restarts when V
drops below charge restart threshold
BAT
Recharge Threshold in Relation to BatReg[3:0]
00 = BatReg - 70mV
01 = BatReg - 120mV
BatReChg[1:0]
10 = BatReg - 170mV
11 = BatReg - 220mV
Battery Regulation Voltage
0000 = 4.05V
0001 = 4.10V
0010 = 4.15V
0011 = 4.20V
0100 = 4.25V
0101 = 4.30V
0110 = 4.35V
0111 = 4.40V
1000 = 4.45V
1001 = 4.5V
BatReg[3:0]
1010 = 4.55V
1011 = 4.6V
System Voltage Minimum Threshold
000 : 3.6V
001: 3.7V
010: 3.8V
011: 3.9V
100: 4.0V
101: 4.1V
110: 4.2V
111: 4.3V
SysMinVlt[2:0]
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Table 73. Charger_Config_Write Response
BIT
B7
B6
B5
B4
B3
B2
B1
B0
APResponse
(0x14)
0
0
0
1
0
1
0
0
Table 74. 0x15 – Charger_Config_Read
MODE
Read
B7
BIT
B6
B5
B4
B3
B2
B1
B0
APCmdOut
(0x15)
0
0
0
1
0
1
0
1
Table 75. Charger_Config_Read Response
BIT
B7
B6
B5
B4
B3
B2
B1
B0
APResponse
(0x15)
0
0
0
1
0
1
0
1
APDataIn0
APDataIn1
—
—
—
MtChgTmr[1:0]
FChgTmr[1:0]
IPChg[1:0]
PChgTmr[1:0]
VPChg[2:0]
ChgDone[1:0]
ChgAuto
Stp
ChgAuto
Re
APDataIn2
APDataIn3
BatReChg[1:0]
BatReg[3:0]
—
—
—
—
SysMinVlt[2:0]
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Table 76. 0x16 – ChargerThermalLimits_Config_Write
MODE
Write
B7
BIT
B6
B5
B4
B3
B2
B1
B0
APCmdOut
(0x16)
0
0
0
1
0
1
1
0
APDataOut0
APDataOut1
APDataOut2
APDataOut3
APDataOut4
APDataOut5
ColdLim[7:0]
CoolLim[7:0]
WarmLim[7:0]
HotLim[7:0]
Password[15:8]
Password[7:0]
Cold Zone Boundary
ColdLim[7:0]
CoolLim[7:0]
WarmLim[7:0]
HotLim[7:0]
Defines the falling threshold voltage on THM that defines the cold charging temperature zone. 8-bit value, 1.8V
full-scale voltage.
Cool Zone Boundary
Defines the falling threshold voltage on THM that defines the cool charging temperature zone. 8-bit value, 1.8V
full-scale voltage.
Warm Zone Boundary
Defines the rising threshold voltage on THM that defines the cool charging temperature zone. 8-bit value, 1.8V
full-scale voltage.
Hot Zone Boundary
Defines the rising threshold voltage on THM that defines the hot charging temperature zone. 8-bit value, 1.8V
full-scale voltage.
Thermal Limit Configuration Password
Password[15:0] If Write-Protect enabled, ChargerThermalLimits can be configured using the following password: 0x1E7A.
If Write-Protect enabled, incorrect password will result in SystemError[7:0] = 0x11.
Table 77. ChargerThermalLimits_Config_Write Response
BIT
B7
B6
B5
B4
B3
B2
B1
B0
APResponse
(0x16)
0
0
0
1
0
1
1
0
Table 78. 0x17 – ChargerThermalLimits_Config_Read
MODE
Read
B7
BIT
B6
B5
B4
B3
B2
B1
B0
APCmdOut
(0x17)
0
0
0
1
0
1
1
1
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Table 79. ChargerThermalLimits_Config_Read Response
BIT
B7
B6
B5
B4
B3
B2
B1
B0
APResponse
(0x17)
0
0
0
1
0
1
1
0
APDataIn0
APDataIn1
APDataIn2
APDataIn3
ColdLim[7:0]
CoolLim[8:0]
WarmLim[7:0]
HotLim[7:0]
Table 80. 0x18 – ChargerThermalReg_Config_Write
MODE
Write
B7
BIT
B6
B5
B4
B3
B2
B1
B0
APCmdOut
(0x18)
0
0
0
1
1
0
0
0
APDataOut0
APDataOut1
APDataOut2
APDataOut3
APDataOut4
APDataOut5
APDataOut6
ColdChgEn
CoolChgEn
—
—
—
—
—
—
—
—
—
—
—
ColdBatReg[1:0]
CoolBatReg[1:0]
RoomBatReg[1:0]
WarmBatReg[1:0]
HotBatReg[1:0]
Password[15:8]
Password[7:0]
ColdFChg[2:0]
CoolFChg[2:0]
RoomFChg[2:0]
WarmFChg[2:0]
HotFChg[2:0]
WarmChgEn
HotChgEn
Cold Zone Charger Control
Determines if charger is enabled for cold temperature zone.
0 = Charging disabled in cold temperature zone.
1 = Charging enabled in cold temperature zone.
ColdChgEn
Cold Zone Battery Regulation Voltage
Sets modified BatReg[3:0] in the cold temperature zone.
00 = BatReg-150mV
ColdBatReg
[1:0]
01 = BatReg-100mV
10 = BatReg-50mV
11 = BatReg
Cold Zone Fast Charge Current Scaling
Sets modified fast charge in the cold temperature zone.
000 = 0.2 x IFChg
001 = 0.3 x IFChg
ColdFChg
[2:0]
010 = 0.4 x IFChg
011 = 0.5 x IFChg
100 = 0.6 x IFChg
101 = 0.7 x IFChg
110 = 0.8 x IFChg
111 = 1.0 x IFChg
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Table 80. 0x18 – ChargerThermalReg_Config_Write (continued)
Cool Zone Charger Control
Determines if charger is enabled for cool temperature zone.
0 = Charging disabled in cool temperature zone.
CoolChgEn
1 = Charging enabled in cool temperature zone.
Cool Zone Battery Regulation Voltage
Sets modified BatReg[3:0] in the cool temperature zone.
CoolBatReg
[1:0]
00 = BatReg-150mV
01 = BatReg-100mV
10 = BatReg-50mV
11 = BatReg
Cool Zone Fast Charge Current Scaling
Sets modified fast charge in the cool temperature zone.
000 = 0.2 x IFChg
001 = 0.3 x IFChg
CoolFChg
[2:0]
010 = 0.4 x IFChg
011 = 0.5 x IFChg
100 = 0.6 x IFChg
101 = 0.7 x IFChg
110 = 0.8 x IFChg
111 = 1.0 x IFChg
Room Zone Battery Regulation Voltage
Sets the modified BatReg[3:0] in the room temperature zone.
00 = BatReg-150mV
RoomBat
Reg[4:3]
01 = BatReg-100mV
10 = BatReg-50mV
11 = BatReg
Room Zone Fast Charge Current Scaling
Sets the modified fast charge in the room temperature zone.
000 = 0.2 x IFChg
001 = 0.3 x IFChg
RoomFChg
[2:0]
010 = 0.4 x IFChg
011 = 0.5 x IFChg
100 = 0.6 x IFChg
101 = 0.7 x IFChg
110 = 0.8 x IFChg
111 = 1.0 x IFChg
Warm Zone Charger Control
WarmChg
En
Determines if charger is enabled for warm temperature zone.
0 = Charging disabled in warm temperature zone.
1 = Charging enabled in warm temperature zone.
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Table 80. 0x18 – ChargerThermalReg_Config_Write (continued)
Warm Zone Battery Regulation Voltage
Sets the modified BatReg[3:0] in the warm temperature zone.
WarmBat
Reg[1:0]
00 = BatReg-150mV
01 = BatReg-100mV
10 = BatReg-50mV
11 = BatReg
Warm Zone Fast Charge Current Scaling
Sets the modified fast charge in the warm temperature zone.
000 = 0.2 x IFChg
001 = 0.3 x IFChg
WarmFChg
[2:0]
010 = 0.4 x IFChg
011 = 0.5 x IFChg
100 = 0.6 x IFChg
101 = 0.7 x IFChg
110 = 0.8 x IFChg
111 = 1.0 x IFChg
Hot Zone Charger Control
Determines if charger is enabled for hot temperature zone.
0 = Charging disabled in hot temperature zone.
1 = Charging enabled in hot temperature zone.
HotChgEn
Hot Zone Battery Regulation Voltage
Sets the modified BatReg[3:0] in the hot temperature zone.
00 = BatReg-150mV
HotBatReg
[1:0]
01 = BatReg-100mV
10 = BatReg-50mV
11 = BatReg
Hot Zone Fast Charge Current Scaling
Sets the modified fast charge in the hot temperature zone.
000 = 0.2 x IFChg
001 = 0.3 x IFChg
HotFChg
[2:0]
010 = 0.4 x IFChg
011 = 0.5 x IFChg
100 = 0.6 x IFChg
101 = 0.7 x IFChg
110 = 0.8 x IFChg
111 = 1.0 x IFChg
Charger Thermal Limit Configuration Password
If Write protect enabled, ChargerThermalLimits can be configured using the following password: 0x1E7A
If Write Protect enabled, incorrect password will result in System Error 0x11.
Password
[15:0]
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Table 81. ChargerThermalReg_Config_Write Response
BIT
B7
B6
B5
B4
B3
B2
B1
B0
APResponse
(0x18)
0
0
0
1
1
0
0
0
Table 82. 0x19 – ChargerThermalReg_Config_Read
MODE
Read
B7
BIT
B6
B5
B4
B3
B2
B1
B0
APCmdOut
(0x19)
0
0
0
1
1
0
0
1
Table 83. ChargerThermalReg_Config_Read Response
BIT
B7
B6
B5
B4
B3
B2
B1
B0
APResponse
(0x19)
0
0
0
1
1
0
0
1
APDataIn0
APDataIn1
APDataIn2
APDataIn3
APDataIn4
ColdChgEn
CoolChgEn
—
—
—
—
—
—
—
—
—
—
—
ColdBatReg[1:0]
CoolBatReg[1:0]
RoomBatReg[1:0]
WarmBatReg[1:0]
HotBatReg[1:0]
ColdFChg[2:0]
CoolFChg[2:0]
RoomFChg[2:0]
WarmFChg[2:0]
HotFChg[2:0]
WarmChgEn
HotChgEn
Table 84. 0x1A – Charger_ControlWrite
MODE
Write
B7
BIT
B6
0
B5
0
B4
1
B3
B2
B1
1
B0
0
APCmdOut
(0x1A)
0
1
0
APDataOut0
—
—
—
—
—
—
ThmEn
ChgEn
On/Off Control for Thermal Monitor
0 = Thermal monitor disabled
1 = Thermal monitor enabled
ThmEn
On/Off Control for Charger (does not affect SYS node).
0 = Charger disabled
ChgEn
1 = Charger enabled
Table 85. Charger_ControlWrite Response
BIT
B7
B6
B5
B4
B3
B2
B1
B0
APResponse
(0x1A)
0
0
0
1
1
0
1
0
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Table 86. 0x1B – Charger_ControlRead
MODE
Read
B7
BIT
B6
B5
B4
B3
B2
B1
B0
APCmdOut
(0x1B)
0
0
0
1
1
0
1
1
Table 87. Charger_Control_Read Response
BIT
B7
B6
B5
B4
1
B3
1
B2
0
B1
1
B0
1
APResponse
(0x1B)
0
0
0
APDataIn0
—
—
—
—
—
—
ThmEn
ChgEn
Table 88. 0x1C – Charger_ JEITAHyst_ControlWrite
MODE
Write
B7
BIT
B6
B5
B4
B3
B2
B1
B0
APCmdOut
(0x1C)
0
0
0
1
1
1
0
0
JEITAHys
En
APDataOut0
—
—
JEITAHysLvl
JEITA Hysteresist Control
0 = Hysteresis disabled.
1 = Hysteresis enabled.
JEITAHys
En
Amplitude of JEITA Hysteresis (LSB = 0.39%V
)
DIG
00001 = 0.39%V
00010 = 0.78%V
DIG
DIG
JEITAHys
Lvl
…
11111 = 12.09%VDIG
Table 89. Charger_JEITAHyst_ControlWrite Response
BIT
B7
B6
B5
B4
B3
B2
B1
B0
APResponse
(0x1C)
0
0
0
1
1
1
0
0
Table 90. Charger_JEITAHyst_ControlRead
MODE
Read
B7
BIT
B6
B5
B4
B3
B2
B1
B0
APCmdOut
(0x1D)
0
0
0
1
1
1
0
1
Table 91. Charger_JEITAHyst_ControlRead Response
BIT
B7
B6
B5
B4
B3
B2
1
B1
B0
APResponse
(0x1D)
0
0
0
1
1
0
1
APDataIn0
JEITAHysEn
—
—
JEITAHysLvl
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Boost Configuration Commands
Table 92. 0x30 – Bst_Config_Write
MODE
Write
B7
BIT
B6
B5
B4
B3
B2
B1
B0
APCmdOut
(0x30)
0
0
1
1
0
0
0
0
APDataOut0
APDataOut1
APDataOut2
APDataOut3
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
BstEn[1:0]
BstPsvDsc
BstIAdptEn
BstFastStrt
BstFetScale
BstISet[3:0]
BstVSet[5:0]
Boost Enable Configuration (effective only when BstSeq = 111)
00 = Disabled
BstEn[1:0]
01 = Enabled
10 = Controlled by MPC_Config_Write command
11 = RESERVED
Boost Passive Discharge Control
BstPsvDsc
BstIAdptEn
BstFastStrt
BstFetScale
0 = Boost output will be discharged only when entering Off and Hard-Reset modes.
1 = Boost output will be discharged only when entering Off and Hard-Reset modes and when BstEn is set to 000.
Boost Adaptive Peak Current Control
0 = Inductor peak current fixed at the programmed value by means of BstISet
1 = Inductor peak current automatically increased to provide better load regulation
Boost Fast Start Time
0 = Time to full current capability during Startup =100ms
1 = Time to full current capability during Startup = 50ms. Precharge with 2x current
Boost FET Scaling
0 = No FET scaling
1 = Active boost FET size scaled down by half to optimize efficiency for low inductor peak current settings
Boost Nominal inductor Peak Current Setting
25mA step resolution
0000 = 100mA
0001 = 125mA
0010 = 150mA
….
BstISet[3:0]
1111 = 475mA
Boost Output Voltage Setting
Linear scale from 5V to 20V in 250mV increments
000000 = 5V
000001 = 5.25V
…
BstVSet[5:0]
111011 = 19.75V
111011 = 20V
>111100 = Reserved
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Table 93. Bst_Config_Write Response
BIT
B7
B6
B5
B4
B3
B2
B1
B0
APResponse
(0x30)
0
0
1
1
0
0
0
0
Table 94. 0x31 – Bst_Config_Read
MODE
Read
B7
BIT
B6
B5
B4
B3
B2
B1
B0
APCmdOut
(0x31)
0
0
1
1
0
0
0
1
Table 95. Bst_Config_Read Response
BIT
B7
B6
B5
B4
B3
B2
B1
B0
APResponse
(0x31)
0
0
1
1
0
0
0
1
APDataIn0
APDataIn1
APDataIn2
APDataIn3
APDataIn4
—
—
—
—
—
—
—
—
—
—
—
—
—
—
BstEn[1:0]
—
BstPsvDsc
BstIAdptEn
BstFastStrt
BstFetScale
—
RESERVED
—
BstISet[3:0]
BstVSet[5:0]
—
—
—
BstSeq[2:0]
Boost Enable Configuration (Read only)
000 = Disabled
001 = RESERVED
010 = Enabled at 0% of Boot/POR Process Delay Control
011 = Enabled at 25% of Boot/POR Process Delay Control
100 = Enabled at 50% of Boot/POR Process Delay Control
101 = RESERVED
BstSeq[2:0]
110 = RESERVED
111 = Controlled by Bst1En after 100% of Boot/POR Process Delay Control
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Buck Configuration Commands
Table 96. 0x35 – Buck1_Config_Write
MODE
Write
B7
BIT
B6
B5
B4
B3
B2
B1
B0
APCmdOut
(0x35)
0
0
1
1
0
1
0
1
Buck1Psv
Dsc
Buck1Sft
Strt
Buck1Act
Dsc
Buck1Low
EMI
Buck1IAdpt
En
Buck1Fet
Scale
Buck1Wait
ZC
APDataOut0
—
APDataOut1
APDataOut2
APDataOut3
—
—
—
—
—
—
Buck1VSet[5:0]
Buck1ISet[3:0]
Buck1IZCSet[1:0]
—
—
—
—
Buck1En[1:0]
Buck1 Passive Discharge Control
0 = Buck1 passively discharged only in Hard-Reset
1 = Buck1 passively discharged in Hard-Reset or Enable Low
Buck1Psv
Dsc
Buck1 Soft Start Time
Buck1Sft
Strt
Buck1 has reduced current capability during soft-start
0 = 50ms
1 = 25ms
Buck1 Active Discharge Control
0 = Buck1 actively discharged only in Hard-Reset
1 = Buck1 actively discharged in Hard-Reset or Enable Low
Buck1Act
DSC
Buck1 Low EMI Mode
0 = Normal operation
1 = Increase rise/fall time on BLX by 3x
Buck1Low
EMI
Buck1 Adaptive Peak Current Mode
0 = Inductor peak current fixed at the programmed value by means of Buck1ISet
1 = Inductor peak current automatically increased to provide better load regulation
Buck1IAdpt
En
Buck1 Force FET Scaling
Buck1FET
Scale
Reduce the FET size by factor 2. Use it to optimize the efficiency for Buck1Iset <100mA
0: FET scaling disabled
1: FET scaling enabled
Buck1 LX Sense Wait
Selects the conditions needed for Buck 1 to enter the freewheeling state. When set to 1, Buck1WaitZC improves
efficiency by transferring the residual energy in the inductor in case of positive zero crossing error. Buck1WaitZC
should not be set to 1 if Buck1VSet < 1.6V.
0 = Buck1 can freewheel at zero-current crossing detection
1 = Buck1 can freewheel after the following conditions are met:
- inductor zero crossing
Buck1WaitZC
- BK1LX exceeds 1.6V (max)
Buck1 Output Voltage Setting
0.7V to 2.275V, Linear Scale, 25mV increments
Buck1VSet
[5:0]
000000 = 0.7V
000001 = 0.725V
…
111111 = 2.275V
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Table 96. 0x35 – Buck1_Config_Write (continued)
Buck1 Zero Crossing Current Threshold
Optimizes Buck1 for a given voltage setting.
Buck1IZC
Set[1:0]
00 = 10mA, Use for Buck1VSet < 1V
01 = 20mA, Use for 1V < Buck1VSet < 1.8V
10 = 30mA, Use for 1.8V < Buck1VSet < 3V
11 = 40mA, Use for Buck1Vset > 3V
Buck1 Inductor current Peak Current Setting
25mA step
Buck1ISet
[3:0]
0000 = 0mA
0001 = 25mA
1111 = 375mA
Buck1 Enable Configuration (effective only when Buck1Seq == 111)
00 = Disabled: BK1OUT not actively discharged unless Hard-Reset/Shutdown/Off mode
01 = Enabled
10 = Controlled by MPC_ (See MPC_Config_Write)
11 = RESERVED
Buck1En
[1:0]
Table 97. Buck1_Config_Write Response
BIT
B7
B6
B5
B4
B3
B2
B1
B0
APResponse
(0x35)
0
0
1
1
0
1
0
1
Table 98. 0x36 – Buck1_Config_Read
MODE
Read
B7
BIT
B6
B5
B4
B3
B2
B1
B0
APCmdOut
(0x36)
0
0
1
1
0
1
1
0
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Table 99. Buck1_Config_Read Response
BIT
B7
B6
B5
B4
B3
B2
B1
B0
APResponse
(0x36)
0
0
1
1
0
1
1
0
Buck1Psv
Dsc
Buck1Act
Dsc
Buck1Low
EMI
Buck1En
Fmax
Buck1Fet
Scale
Buck1Wait
ZC
APDataIn0
—
Buck1Fast
APDataIn1
APDataIn2
APDataIn3
APDataIn4
—
—
—
—
—
—
—
—
Buck1VSet[5:0]
Buck1ISet[3:0]
Buck1IZCSet[1:0]
—
—
—
—
—
—
—
Buck1En[1:0]
Buck1Seq[2:0]
Buck1 Enable Configuration (Read only)
000 = Disabled
001 = Reserved
010 = Enabled at 0% of Boot/ POR Process Delay Control
011 = Enabled at 25% of Boot/ POR Process Delay Control
100 = Enabled at 50% of Boot/ POR Process Delay Control
101 = Reserved
Buck1Seq
[2:0]
110 = Reserved
111 = Controlled by Buck1En [1:0] after 100% of Boot/POR Process Delay Control
Table 100. 0x37 – Buck1_DVSConfig_Write
MODE
Write
B7
BIT
B6
B5
B4
B3
B2
B1
B0
APCmdOut
(0x37)
0
0
1
1
0
1
1
1
APDataOut0
APDataOut1
APDataOut2
—
—
—
—
—
—
Buck1VSet[5:0]
Buck1AlternateVSet[5:0]
MPC3 MPC2
—
MPC4
MPC1
MPC0
Buck1 Voltage Setting for Dynamic Voltage Scaling Function:
This is the voltage set on Buck1 after a positive edge on MPC_.
0.7V to 2.275V, Linear Scale, 25mV increments
Buck1VSet
[5:0]
000000 = 0.7V
000001 = 0.725V
…
111111 = 2.275V
Buck1 Alternate Voltage Setting for Dynamic Voltage Scaling Function:
This is the voltage set on Buck1 upon writing this command or after a negative edge on MPC_.
0.7V to 2.275V, Linear Scale, 25mV increments
Buck1Altern
ateVSet[5:0]
000000 = 0.7V
000001 = 0.725V
…
111111 = 2.275V
This selects the MPC pin used for alternate voltage function.
MPC_
If an MPC is used for dynamic voltage scaling, all other functions of that MPC are disabled.
MPC works on edge, so the static value of MPC does not matter.
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Table 101. Buck1_DVSConfig_Write Response
BIT
B7
B6
B5
B4
B3
B2
B1
B0
APResponse
(0x37)
0
0
1
1
0
1
1
1
Table 102. 0x3A – Buck2_Config_Write
MODE
Write
B7
BIT
B6
B5
B4
B3
B2
B1
B0
APCmdOut
(0x3A)
0
0
1
1
1
0
1
0
Buck2Psv
Dsc
Buck2Sft
Strt
Buck2Act
Dsc
Buck2Low
EMI
Buck2IAdpt
En
Buck2Fet
Scale
Buck2Wait
ZC
APDataOut0
—
APDataOut1
APDataOut2
APDataOut3
—
—
—
—
—
—
Buck2VSet[5:0]
Buck2ISet[3:0]
Buck2IZCSet[1:0]
—
—
—
—
Buck2En[1:0]
Buck2 Passive Discharge Control
0 = Buck2 passively discharged only in Hard-Reset
1 = Buck2 passively discharged in Hard-Reset or Enable Low
Buck2Psv
DSC
Buck2 Soft Start Time
Buck2 has reduced current capability during soft-start
0 = 50ms
1 = 25ms
Buck2SftStrt
Buck2 Active Discharge Control
0 = Buck2 actively discharged only in Hard-Reset
1 = Buck2 actively discharged in Hard-Reset or Enable Low
Buck2Act
DSC
Buck2 Low EMI Mode
0 = Normal operation
1 = Increase rise/fall time on BLX by 3x
Buck2Low
EMI
Buck2 Adaptive Peak Current Mode
0 = Inductor peak current fixed at the programmed value by means of Buck1ISet
1 = Inductor peak current automatically increased to provide better load regulation
Buck2IAdpt
En
Buck2 Force FET Scaling
Buck2FET
Scale
Reduce the FET size by factor 2. Use it to optimize the efficiency for Buck1Iset <100mA
0 = FET scaling disabled
1 = FET scaling enabled
Buck2 LX Sense Wait
Selects the conditions needed for Buck2 to enter the freewheeling state. When set to 1, Buck2WaitZC improves
efficiency by transferring the residual energy in the inductor in case of positive zero crossing error. Buck2WaitZC
should not be set to 1 if Buck2VSet < 1.6V.
Buck2WaitZC
0 = Buck2 can freewheel at the inductor zero crossing point
1 = Buck2 can freewheel after the following conditions are met:
- inductor zero crossing
- BK2LX exceeds the detection threshold (1.6V (max))
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Table 102. 0x3A – Buck2_Config_Write (continued)
Buck2 Output Voltage Setting
0.7V to 3.85V, Linear Scale, 50mV increments
Buck2VSet
[5:0]
000000 = 0.7V
000001 = 0.75V
…
111111 = 3.85V
Buck2 Zero Crossing Current Threshold
Optimizes Buck2 for a given voltage setting.
00 = 10mA, Use for Buck2VSet < 1V
01 = 20mA, Use for 1V < Buck2VSet < 1.8V
10 = 30mA, Use for 1.8V < Buck2VSet < 3V
11 = 40mA, Use for Buck2Vset > 3V
Buck2IZCSet
[1:0]
Buck2 Inductor Current Peak Current Setting
25mA step
Buck2ISet
[3:0]
0000 = 0mA
0001 = 25mA
1111 = 375mA
Buck2 Enable Configuration (effective only when Buck2Seq == 111)
00 = Disabled
Buck2En[1:0]
01 = Enabled
10 = Controlled by MPC_Config_Write command
11 = Reserved
Table 103. Buck2_Config_Write Response
BIT
B7
B6
B5
B4
B3
B2
B1
B0
APResponse
(0x3B)
0
0
1
1
1
0
1
0
Table 104. 0x3B – Buck2_Config_Read
MODE
Read
B7
BIT
B6
B5
B4
B3
B2
B1
B0
APCmdOut
(0x3B)
0
0
1
1
1
0
1
1
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Table 105. Buck2_Config_Read Response
BIT
B7
B6
B5
B4
B3
B2
B1
B0
APResponse
(0x3B)
0
0
1
1
1
0
1
1
Buck2Psv
Dsc
Buck2Sft
Strt
Buck2Act
Dsc
Buck2Low
EMI
Buck2IAdpt
En
Buck2Fet
Scale
Buck2Wait
ZC
APDataIn0
—
APDataIn1
APDataIn2
APDataIn3
APDataIn4
—
—
—
—
—
—
—
—
Buck2VSet[5:0]
Buck2ISet[3:0]
Buck2IZCSet[1:0]
—
—
—
—
—
—
—
Buck2En[1:0]
Buck2Seq[2:0]
Buck2 Enable Configuration (Read Only)
000 = Disabled
001 = RESERVED
010 = Enabled at 0% of Boot/ POR Process Delay Control
011 = Enabled at 25% of Boot/ POR Process Delay Control
100 = Enabled at 50% of Boot/ POR Process Delay Control
101 = RESERVED
Buck2Seq
[2:0]
110 = RESERVED
111 = Controlled by Buck2En [1:0] after 100% of Boot/POR Process Delay Control
Table 106. 0x3C – Buck2_DVSConfig_Write
MODE
Write
B7
BIT
B6
B5
B4
B3
B2
B1
B0
APCmdOut
(0x3C)
0
0
1
1
1
1
0
0
APDataOut0
APDataOut1
APDataOut2
—
—
—
—
—
—
Buck2VSet[5:0]
Buck2AlternateVSet[5:0]
MPC3 MPC2
—
MPC4
MPC1
MPC0
Buck2 Voltage Setting for Dynamic Voltage Scaling Function:
This is the voltage set on Buck2 after a positive edge on MPC_.
0.7V to 3.85V, Linear Scale, 50mV increments
Buck2VSet
[5:0]
000000 = 0.7V
000001 = 0.75V
…
111111 = 3.85V
Buck2 Alternate Voltage Setting for Dynamic Voltage Scaling Function:
This is the voltage set on Buck2 upon writing this command or after a negative edge on MPC_.
0.7V to 3.85V, Linear Scale, 50mV increments
Buck2Altern
ateVSet[5:0]
000000 = 0.7V
000001 = 0.75V
…
111111 = 3.85V
This selects the MPC pin used for alternate voltage function.
MPC_
If an MPC is used for dynamic voltage scaling, all other functions of that MPC are disabled.
MPC works on edge, so the static value of MPC does not matter.
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Table 107. Buck2_DVSConfig_Write Response
BIT
B7
B6
B5
B4
B3
B2
B1
B0
APResponse
(0x3C)
0
0
1
1
1
1
0
0
LDO Configuration Commands
Table 108. 0x40 – LDO1_Config_Write
MODE
Write
B7
BIT
B6
B5
B4
B3
B2
B1
B0
APCmdOut
(0x40)
0
1
0
0
0
0
0
0
LDO1Pas
Dsc
LDO1Act
Dsc
APDataOut0
APDataOut1
—
—
—
—
—
LDO1Md
LDO1En[1:0]
LDO1VSet[5:0]
LDO1 Passive Discharge Control
0 = LDO1 output will be discharged only entering Off and Hard-Reset modes.
1 = LDO1 output will be discharged only entering Off and Hard-Reset modes and when the enable is Low
LDO1Pas
Dsc
LDO1 Active Discharge Control
0 = LDO1 output will be actively discharged only in Hard-Reset mode
1 = LDO1 output will be actively discharged in Hard-Reset mode and also when its Enable goes Low
LDO1Act
Dsc
LDO1 Mode Control
When FET is On, the output is unregulated. This setting is internally latched and can change only when the LDO
LDO1Md
is disabled.
0 = Normal LDO operating mode
1 = Load switch mode. FET is either fully On or Off depending on state of LDO1En.
LDO1 Enable Configuration (effective only when LDO1Seq[2:0] == 111)
00 = Disabled
01 = Enabled
10 = Controlled by MPC_Config_Write command
11 = Controlled by LDODirect register
LDO1En
[1:0]
LDO1 Output Voltage Setting–Limited by input supply
0.5V to 1.95V, Linear Scale, 25mV increments
000000 = 0.5V
000001 = 0.525V
…
LDO1VSet
[5:0]
111010 = 1.95V
>111010 = Limited by input supply
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Table 109. LDO1_Config_Write Response
BIT
B7
B6
B5
B4
B3
B2
B1
B0
APResponse
(0x40)
0
1
0
0
0
0
0
0
Table 110. 0x41 – LDO1_Config_Read
MODE
Read
B7
BIT
B6
B5
B4
B3
B2
B1
B0
APCmdOut
(0x41)
0
1
0
0
0
0
0
1
Table 111. LDO1_Config_Read Response
BIT
B7
B6
B5
B4
B3
B2
B1
B0
APResponse
(0x41)
0
1
0
0
0
0
0
1
LDO1Pas
Dsc
LDO1Act
Dsc
APDataIn0
—
—
—
LDO1Md
LDO1En[1:0]
APDataIn1
APDataIn2
—
—
—
—
—
—
LDO1VSet[4:0]
—
—
LDO1Seq[2:0]
LDO1 Enable Configuration (Read only)
000 = Disabled
001 = RESERVED
010 = Enabled at 0% of Boot/POR Process Delay Control
011 = Enabled at 25% of Boot/POR Process Delay Control
100 = Enabled at 50% of Boot/POR Process Delay Control
101 = RESERVED
LDO1Seq
[2:0]
110 = RESERVED
111 = Controlled by LDO1En [1:0] after 100% of Boot/POR Process Delay Control
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Table 112. 0x42 – LDO2_Config_Write
MODE
Write
B7
BIT
B6
B5
B4
B3
B2
B1
B0
APCmdOut
(0x42))
0
1
0
0
0
0
1
0
LDO2Pas
Dsc
LDO2Act
Dsc
APDataOut0
APDataOut1
—
—
—
—
—
—
LDO2Md
LDO2En[1:0]
LDO2VSet[4:0]
LDO2 Passive Discharge Control
0 = LDO2 output will be discharged only entering Off and Hard-Reset modes.
1 = LDO2 output will be discharged only entering Off and Hard-Reset modes and when the enable is low.
LDO2Pas
Dsc
LDO2 Active Discharge Control
0 = LDO2 output will be actively discharged only in Hard-Reset mode
1 = LDO2 output will be actively discharged in Hard-Reset mode and also when its Enable goes Low
LDO2Act
Dsc
LDO2 Mode Control
When FET is On, the output is unregulated. This setting is internally latched and can change only when the LDO2
LDO2Md
is disabled.
0 = Normal LDO2 operating mode
1 = Load switch mode. FET is either fully On or Off depending on state of LDO2En
LDO2 Enable Configuration (effective only when LDO2Seq[2:0] == 111)
00 = Disabled
01 = Enabled
10 = Controlled by MPC_Config_Write command
11 = Controlled by LDODirect register
LDO2En
[1:0]
LDO2 Output Voltage Setting–Limited by input supply
0.9V to 4V, Linear Scale, 100mV increments
000000 = 0.9V
000001 = 1V
…
LDO2VSet
[4:0]
11110 = 3.9V
11111 = 4V
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Table 113. LDO2_Config_Write Response
BIT
B7
B6
B5
B4
B3
B2
B1
B0
APResponse
(0x42)
0
1
0
0
0
0
1
0
Table 114. 0x43 – LDO2_Config_Read
MODE
Read
B7
BIT
B6
B5
B4
B3
B2
B1
B0
APCmdOut
(0x43)
0
1
0
0
0
0
1
1
Table 115. LDO2_Config_Read Response
BIT
B7
B6
B5
B4
B3
B2
B1
B0
APResponse
(0x43)
0
1
0
0
0
0
1
1
LDO2Pas
Dsc
LDO2Act
Dsc
APDataIn0
—
—
—
LDO2Md
LDO2En[1:0]
APDataIn1
APDataIn2
—
—
—
—
—
—
LDO2VSet[4:0]
—
—
LDO2Seq[2:0]
LDO2 Enable Configuration (Read only)
000 = Disabled
001 = Enabled always when BAT/SYS is present
010 = Enabled at 0% of Boot/ POR Process Delay Control
011 = Enabled at 25% of Boot/ POR Process Delay Control
100 = Enabled at 50% of Boot/ POR Process Delay Control
101 = RESERVED
LDO2Seq
[2:0]
110 = RESERVED
111 = Controlled by LDO2En [1:0] after 100% of Boot/POR Process Delay Control
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MAX20353
PMIC with Ultra-Low Iq Regulators, Charger,
Fuel Gauge, and Haptic Driver for
Small Li+ Systems
Charge Pump Configuration Commands
Table 116. 0x46 – ChargePump_Config_Write
MODE
Write
B7
BIT
B6
B5
B4
B3
B2
B1
B0
APCmdOut
(0x46)
0
1
0
0
0
1
1
0
APDataOut0
APDataOut1
—
—
—
—
—
—
—
—
—
—
—
—
CPEn[1:0]
CPPscDisch
CPVSet
Charge Pump Enable Configuration (effective only when CPSeq = 111)
00 = Disabled
CPEn[1:0]
01 = Enabled
10 = Controlled by MPC_Config_Write command
11 = RESERVED
Charge Pump Passive Discharge Enable
0 = Disabled
1 = Enabled
CPpsvDisch
CPVSet
0 = 6.6V
1 = 5V
Table 117. ChargePump_Config_Write Response
BIT
B7
B6
B5
B4
B3
B2
B1
B0
APResponse
(0x46)
0
1
0
0
0
1
1
0
Table 118. 0x47 – ChargePump_Config_Read
MODE
Read
B7
BIT
B6
B5
B4
B3
B2
B1
B0
APCmdOut
(0x47)
0
1
0
0
0
1
1
1
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PMIC with Ultra-Low Iq Regulators, Charger,
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Small Li+ Systems
Table 119. ChargePump_Config_Read Response
BIT
B7
B6
B5
B4
B3
B2
B1
B0
APResponse
(0x47)
0
1
0
0
0
1
1
1
APDataIn0
APDataIn1
APDataIn2
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CPEn[1:0]
CPPscDisch
CPSeq[2:0]
CPVSet
Charge Pump Enable Configuration (Read only)
000 = Disabled
001 = RESERVED
010 = Enabled at 0% of Boot/POR Process Delay Control
011 = Enabled at 25% of Boot/POR Process Delay Control
100 = Enabled at 50% of Boot/POR Process Delay Control
101 = RESERVED
CPSeq[2:0]
110 = RESERVED
111 = Controlled by CPEn after 100% of Boot/POR Process Delay Control
SFOUT Configuration Commands
Table 120. 0x48 – SFOUT_Config_Write
MODE
Write
B7
BIT
B6
B5
B4
B3
B2
B1
B0
APCmdOut
(0x48)
0
1
0
0
1
0
0
0
SFOUTV
Set
APDataOut0
—
—
—
—
—
SFOUTEn[1:0]
SFOUT Output Voltage Setting
0 = 5V
1 = 3.3V
SFOUTV
Set
SFOUT LDO Enable Configuration
00 = Disabled (regardless of CHGIN)
01 = Enabled when CHGIN is present
SFOUTE
n[1:0]
10 = Enabled when CHGIN is present and Controlled by MPC_Config_Write command
11 = RESERVED
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PMIC with Ultra-Low Iq Regulators, Charger,
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Small Li+ Systems
Table 121. SFOUT_Config_Write Response
BIT
B7
B6
B5
B4
B3
B2
B1
B0
APResponse
(0x48)
0
1
0
0
1
0
0
0
Table 122. 0x49 – SFOUT_Config_Read
MODE
Read
B7
BIT
B6
B5
B4
B3
B2
B1
B0
APCmdOut
(0x49)
0
1
0
0
1
0
0
1
Table 123. SFOUT_Config_Read Response
BIT
B7
B6
B5
B4
B3
B2
0
B1
B0
APResponse
(0x49)
0
1
0
0
1
0
1
APDataIn0
—
—
—
—
—
SFOUTVSet
SFOUTEn[1:0]
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MON Mux Configuration Commands
Table 124. 0x50 – MONMux_Config_Write
MODE
Write
B7
BIT
B6
1
B5
0
B4
B3
B2
B1
B0
APCmdOut
(0x50)
0
1
0
0
0
0
APDataOut0
MONEn
—
MONHiZ
MONRatioCfg[1:0]
MONCtrl[2:0]
Enable Signal For MON Mux
MONEn
0 = MON is not connected to any internal node and its state depends on MONHIZ
1 = MON is connected based on MONCtrl[2:0] configuration
MON Off Mode Condition
0 = Pulled LOW by 59kΩ pulldown resistor
1 = Hi-Z
MONHiZ
MON Resistive Partition Selector
00 = 1:1
01 = 2:1
10 = 3:1
11 = 4:1
MONRatio
Cfg[1:0]
MON Pin Source Selection (80µs BBM after any change of MONCtrl[2:0])
000 = MON connected to a resistive partition of BAT
001 = MON connected to a resistive partition of SYS
010 = MON connected to a resistive partition of BK2OUT
MONCtrl[2:0] 011 = MON connected to a resistive partition of BK1OUT
100 = MON connected to a resistive partition of L2OUT
101 = MON connected to a resistive partition of L1OUT
110 = MON connected to a resistive partition of SFOUT
111 = MON connected to a resistive partition of BBOUT
Table 125. MONMux_Config_Write Response
BIT
B7
B6
B5
B4
B3
B2
B1
B0
APResponse
(0x51)
0
1
0
1
0
0
0
0
Table 126. 0x51 – MONMux_Config_Read
MODE
Read
B7
BIT
B6
B5
B4
B3
B2
B1
B0
APCmdOut
(0x51)
0
1
0
1
0
0
0
1
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PMIC with Ultra-Low Iq Regulators, Charger,
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Small Li+ Systems
Table 127. MONMux_Config_Read Response
BIT
B7
B6
B5
B4
B3
B2
B1
B0
APResponse
(0x51)
0
1
0
1
0
0
0
1
APDataIn0
MONEN
—
MONHiZ
MONRatioCfg[1:0]
MONCtrl[2:0]
Table 128. 0x53 – ADC_Measure_Launch
MODE
Launch
BIT
B7
B6
1
B5
B4
B3
B2
B1
1
B0
APCmdOut
(0x53)
0
0
1
0
0
1
APDataOut0
—
—
ADCAvgSiz[2:0]
ADCSel[2:0]
ADCAvg
Siz[2:0]
ADC Averaging Size
ADC performs 2
ADCAvgSiz[2:0]
consecutive averaged measurements
ADC Channel Selection
000 = SYS
001 = MON
ADCSel
[2:0]
010 = THM
011 = CHGIN
100 = CPOUT
101 = BSTOUT
11x = RESERVED
Table 129. ADC_Measure_Launch Response
BIT
B7
B6
B5
B4
B3
0
B2
B1
B0
APResponse
(0x53)
0
1
0
1
0
1
1
APDataIn0
APDataIn1
APDataIn2
APDataIn3
—
—
—
—
—
—
ADCResult[1:0]
ADCMax[7:0]
ADCMin[7:0]
ADCAvg[7:0]
ADC Result Ready
00 = Success, measurement completed
01 = ADC busy
ADCResult
10 = ADC measurement aborted by Haptic Automatic Level Compensation engine
11 = RESERVED
ADC Maximum Value
Contains the maximum value measured by the ADC
ADCMax[7:0]
ADCMin[7:0]
ADCAvg[7:0]
ADC Minimum Value
Contains the minimum value measured by the ADC
ADC Average Value
Contains the average value of 2
ADCAvgSiz[2:0]
ADC measurements
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PMIC with Ultra-Low Iq Regulators, Charger,
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Buck-Boost Configuration Commands
Table 130. 0x70 – BBst_Config_Write
MODE
Write
B7
BIT
B6
B5
B4
B3
B2
B1
B0
APCmdOut
(0x70)
0
1
1
1
0
0
0
0
APDataOut0
APDataOut1
APDataOut2
RESERVED (Set to 0x00)
—
—
—
—
—
—
—
BBstISet[2:0]
BBstVSet[4:0]
BBstInd
BBstRip
Red
BBstAct
Dsc
BBstPas
Dsc
APDataOut3
—
BBstMd
BBstEn[1:0]
Buck-Boost Peak Current Limit Setting
000 = 0 (Minimum On-time)
001 = 50mA
010 = 100mA
011 = 150mA
100 = 200mA
BBstISet
[2:0]
101 = 250mA
110 = 300mA
111 = 350mA
Buck-Boost Output Voltage Setting This setting is internally latched and can change only when Buck-Boost is
Disabled.
2.5V to 5.0V, Linear Scale, 100mV increments
BBstVSet
[4:0]
000000 = 2.5V
000001 = 2.6V
…
011001 = 5.0V
>011001 = 5.0V
BBstRip
Red
Buck-Boost Ripple Reduction
Leave set to 1
Buck-Boost Active Discharge Control
0 = Actively discharged only in Hard-Reset
1 = Actively discharged in Hard-Reset or Enable Low
BBstAct
Dsc
Buck-Boost Passive Discharge Control
0 = Passively discharged only in Hard-Reset
1 = Passively discharged in Hard-Reset or Enable Low
BBstPas
Dsc
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PMIC with Ultra-Low Iq Regulators, Charger,
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Table 130. 0x70 – BBst_Config_Write (continued)
Buck-Boost EMI Reduction
BBstMd
0 = Damping enabled
1 = Damping disabled
Buck-Boost Inductance select
0 = Inductance is 4.7µH
1 = Inductance is 3.3µH
BBstInd
Buck-Boost Enable Configuration (effective only when BBstSeq[2:0] == 111)
00 = Disabled
01 = Enabled
10 = Controlled by MPC_Config_Write command
11 = RESERVED
BBstEn
[1:0]
Table 131. BBst_Config_Write Response
BIT
B7
B6
B5
B4
B3
B2
B1
B0
APResponse
(0x70)
0
1
1
1
0
0
0
0
Table 132. 0x71 – BBst_Config_Read
MODE
Read
B7
BIT
B6
B5
B4
B3
B2
B1
B0
APCmdOut
(0x71)
0
1
1
1
0
0
0
1
Table 133. BBst_Config_Read Response
BIT
B7
B6
B5
B4
B3
B2
B1
B0
APResponse
(0x71)
0
1
1
1
0
0
0
1
ClkDiv
Ena
APDataIn0
ClkDivSet[6:0]
—
APDataIn1
APDataIn2
APDataIn3
APDataIn4
—
—
—
—
—
—
—
—
—
—
BBstISet[2:0]
—
BBstActDsc
—
BBstVSet[4:0]
BBstInd
BBstPasDsc
—
BBstMd
—
BBstEn[1:0]
BBstSeq[2:0]
Buck-Boost Enable Configuration (Read only)
000 = Disabled
001 = RESERVED
010 = Enabled at 0% of Boot/ POR Process Delay Control
011 = Enabled at 25% of Boot/ POR Process Delay Control
100 = Enabled at 50% of Boot/ POR Process Delay Control
101 = RESERVED
BBstSeq
[2:0]
110 = RESERVED
111 = Controlled by BBstEn [1:0] after 100% of Boot/POR Process Delay Control
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PMIC with Ultra-Low Iq Regulators, Charger,
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Small Li+ Systems
Haptic Configuration Commands
Table 134. 0xA0 – Hpt_Config_Write0
MODE
Write
B7
BIT
B6
0
B5
1
B4
0
B3
0
B2
0
B1
0
B0
0
APCmdOut
(0xA0)
1
APDataOut0
APDataOut1
—
—
—
—
EmfEn
HptSel
AlcMod
ZccHysEn
IniGss[7:0]
ZccSlow
En
APDataOut2
APDataOut3
APDataOut4
APDataOut5
—
—
—
—
—
—
FltrCntrEn
IniGss[11:8]
—
—
—
IniDly[4:0]
IniGssRes
Dis
WidWdw[4:0]
BrkLpGain[1:0]
NarWdw[3:0]
Back EMF and Resonance Detection Control
Can also be set using opcode 0xAD.
0 = Disabled
EmfEn
1 = Enabled
Haptic Mode Select
Can also be set using opcode 0xAD.
0 = ERM Mode
HptSel
1 = LRA Mode
Automatic Level Compensation (ALC) Control
Can also be set using opcode 0xAD.
0 = Disabled
AlcMod
ZccHysEn
1 = Enabled
Zero-Crossing Comparator Hysteresis Control
Can also be set using opcode 0xAD
0 = Disabled
1 = Enabled (6mV typ).
Back EMF Initial Guess
Can also be set using opcode 0xAE.
Initial estimate for BEMF frequency = ((25.6MHz/64) / IniGss[11:0])
IniGss
[11:0]
Zero-Crossing Comparator Slow-Down Enable
Can also be set using opcode 0xBA.
0 = Zero-crossing comparator operates in normal mode.
ZccSlowEn
1 = Slows down the zero-crossing comparator by 2X for stronger antialiasing filtering.
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Table 134. 0xA0 – Hpt_Config_Write0 (continued)
Zero-Crossing Event Capturing Filter Enable
Can also be set using opcode 0xBA
0 = Zero-crossing measured using single comparator/transition.
1 = Zero-crossing measured using an up/down counter (samples at 25.6MHz). Samples the output of the
comparator for the whole duration of the enabled window (wide, narrow, or braking). The counter starts at zero
(mid-code) and will end at a positive or negative code depending on whether the average zero-crossing event
FltrCntrEn
occurs before or after than the expected time. The closer the zero-crossing is on average to the expected time,
the closer to zero code returned at the end of the window will be. Phase error (in 25.6MHz period units) can be
calculated by dividing the resulting code at the end of the window by 2. The usage of the up/down counter enables
filtering/noise rejection that could otherwise cause a systematic shift in the phase error detected.
Number of sine wave periods to be skipped before (re)starting BEMF measurement after:
Start of vibration pattern.
IniDly[4:0]
Change of output polarity (e.g., braking)
Programmed percentage output amplitude (w.r.t. V ) becomes again higher than EmfSkipTh[6:0] after having
FS
previously gone below it. Can also be set using Opcode 0xAF.
Disable Initial Guess Restore
0 = Haptic driver uses IniGss[11:0] as the driving frequency after the end of BrkCyc[4:0] sinewave half periods.
IniGssResDis 1 = Haptic driver does not use IniGss[11:0] as the driving frequency after the end of BrkCyc[4:0] sine wave half
periods.
Can also be set using opcode 0xB0
.
nd
WidWdw
[4:0]
Wide window duration for BEMF zero-crossing detection LSB =1/32 of currently imposed sinewave period.
Can also be set using Opcode 0xB0
Braking Window Gain
Sets gain by which the phase delay found by the zero-crossing comparator is multiplied to calculate the shift for
the new sine wave half period with respect to the previously imposed sine wave. This value is used when the
braking window is active.
Can also be set using opcode 0xB0.
00 = 1
BrkLpGain
[1:0]
01 = 1/2
10 = 1/4
11 = 1/8
nd
NarWdw
[3:0]
Narrow window duration for BEMF zero-crossing detection LSB =1/32 of currently imposed sinewave period.
Can also be set using Opcode 0xB0
Table 135. Hpt_Config_Write0 Response
BIT
B7
B6
B5
B4
B3
B2
B1
B0
APResponse
(0xA0)
1
0
1
0
0
0
0
0
Table 136. 0xA1 – Hpt_Config_Read0
MODE
Read
B7
BIT
B6
B5
B4
B3
B2
B1
B0
APCmdOut
(0xA1)
1
0
1
0
0
0
0
1
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PMIC with Ultra-Low Iq Regulators, Charger,
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Table 137. Hpt_Config_Read0 Response
BIT
B7
B6
B5
B4
0
B3
0
B2
0
B1
0
B0
1
APResponse
(0xA1)
1
0
1
APDataIn0
—
—
—
—
EmfEn
HptSel
AlcMod
ZccHysEn
APDataIn1
IniGss[7:0]
ZccSlow
En
APDataIn2
APDataIn3
APDataIn4
APDataIn5
—
—
—
—
—
—
FltrCntrEn
IniGss[11:8]
—
—
—
IniDly[4:0]
IniGssRes
Dis
WidWdw[4:0]
BrkLpGain[1:0]
NarWdw[3:0]
Table 138. 0xA2 – Hpt_Config_Write1
MODE
Write
B7
BIT
B6
B5
B4
B3
B2
B1
B0
APCmdOut
(0xA2)
1
0
1
0
0
0
1
0
APDataOut0
APDataOut1
APDataOut2
APDataOut3
APDataOut4
APDataOut5
BrkCyc[4:0]
EmfSkipCyc[2:0]
BlankWdw[2:0]
—
BrkWdw[4:0]
—
—
—
—
BlankWdw[5:3]
HptVfs[7:0]
ETRGOdAmp[7:0]
ETRGOdDur [7:0]
Sets the number of consecutive sine wave half periods during which active braking is applied after a change in
driving polarity. During these half periods, the gain used becomes BrkLpGain[1:0], the window duration becomes
BrkWdw[4:0], and the effects of IniDly[4:0], EmfSkipCyc[2:0], and NarCntLck[5:0] are masked.
Can also be set using opcode 0xB1.
BrkCyc[4:0]
Sets number of consecutive sine wave half periods during which BEMF detection is skipped after a BEMF
detection completes.
Can also be set using opcode 0xB1.
EmfSkipCyc
[2:0]
Zero-crossing comparator blanking time applied after entering or prior to exiting the wide, narrow, and
th
BlankWdw
[5:0]
braking windows. The blanking window duration cannot exceed 1/64 of the current sine wave period unless
AutoBrkPeakMeas = 1 and the driver is in the automatic braking state. LSB = 128/25.6MHz
Can also be set using opcode 0xB9.
nd
Braking window duration for BEMF zero-crossing detection. LSB = 1/32 of current sine wave period.
Can also be set using opcode 0xB9.
BrkWdw[4:0]
HptVfs[7:0]
Stores the full-scale voltage (V ) to which the desired percentage output amplitude is referred. The actual V
will be the minimum between the value programmed on HptVfs[7:0] and the current SYS value. LSB = 21.57mV
FS
FS
Can also be set using opcode 0xB2.
Sets amplitude of the overdrive period as a percentage of V (ETRG mode). LSB = 0.78%V . Note that the
MSB represents the sign of the amplitude to be driven.
Can also be set using opcode 0xB3.
FS
FS
ETRGOd
Amp[7:0]
ETRGOdDur
[7:0]
Sets duration of the overdrive period. LSB = 5ms
Can also be set using opcode 0xB3. (ETRG mode)
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PMIC with Ultra-Low Iq Regulators, Charger,
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Small Li+ Systems
Table 139. Hpt_Config_Write1 Response
BIT
B7
B6
B5
B4
B3
B2
B1
B0
APResponse
(0xA2)
1
0
1
0
0
0
1
0
Table 140. 0xA3 – Hpt_Config_Read1
MODE
Write
B7
BIT
B6
B5
B4
B3
B2
B1
B0
APCmdOut
(0xA3)
1
0
1
0
0
0
1
1
Table 141. Hpt_Config_Read1 Response
BIT
B7
B6
B5
B4
B3
B2
B1
B0
APResponse
(0xA3)
1
0
1
0
0
0
1
1
APDataIn0
APDataIn1
APDataIn2
APDataIn3
APDataIn4
APDataIn5
BrkCyc[4:0]
EmfSkipCyc[2:0]
BlankWdw[2:0]
—
BrkWdw[4:0]
—
—
—
—
BlankWdw[5:3]
HptVfs[7:0]
ETRGOdAmp[7:0]
ETRGOdDur [7:0]
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Table 142. 0xA4— Hpt_Config_Write2
MODE
Write
B7
BIT
B6
B5
B4
B3
B2
B1
B0
APCmdOut
(0xA4)
1
0
1
0
0
1
0
0
APDataOut0
APDataOut1
APDataOut2
APDataOut3
APDataOut4
APDataOut5
ETRGActAmp[7:0]
ETRGActDur[7:0]
ETRGBrkAmp[7:0]
ETRGBrkAmp[7:0]
—
—
—
NarLpGain[2:0]
WidLpGain[2:0]
—
NarCntLck[5:0]
ETRGAct
Amp[7:0]
Sets amplitude of the normal drive period as a percentage of V (ETRG mode). LSB = 0.78%V plus sign bit.
FS FS
Can also be set using opcode 0xB3.
ETRGAct
Dur[7:0]
Sets duration of the normal drive period. LSB = 10ms (ETRG mode)
Can also be set using opcode 0xB3.
Sets amplitude of the braking period as a percentage of V (ETRG mode). Triggers the automatic braking
FS
ETRGBrk
Amp[7:0]
process with a maximum braking time of ETRGBrkDur[7:0]. LSB = 0.78%V plus sign bit. Can also be set using
FS
opcode 0xB3.
ETRGBrk
Dur[7:0]
Sets duration of the braking period. LSB = 5ms (ETRG mode)
Can also be set using opcode 0xB3.
Sets gain by which the phase delay found by the zero-crossing comparator is multiplied to calculate the shift
for the new sinewave half period with respect to the previously imposed sinewave. This value is used when the
narrow window is active. Can also be set using opcode 0xB4.
000 = 1
001 = 1/2
010 = 1/4
011 = 1/8
100 = 1/16
101 = 1/32
110 = 1/64
111 = 1/128
NarLpGain
[2:0]
Sets gain by which the phase delay found by the zero-crossing comparator is multiplied to calculate the shift for
the new sinewave half period with respect to the previously imposed sinewave. This value is used when the wide
window is active. Can also be set using opcode 0xB4.
000 = 1
001 = 1/2
010 = 1/4
011 = 1/8
100 = 1/16
101 = 1/32
110 = 1/64
111 = 1/128
WidLpGain
[2:0]
Sets number of consecutive sinewave half periods where the BEMF is detected and where the phase delay must
fall within the narrow window before detection window is reduced from wide to narrow. Can also be set using
opcode 0xB5.
NarCntLck
[5:0]
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Small Li+ Systems
Table 143. Hpt_Config_Write2 Response
BIT
B7
B6
B5
B4
B3
B2
B1
B0
APResponse
(0xA4)
1
0
1
0
0
1
0
0
Table 144. 0xA5 – Hpt_Config_Read2
MODE
Write
B7
BIT
B6
B5
B4
B3
B2
B1
B0
APCmdOut
(0xA5)
1
0
1
0
0
1
0
1
Table 145. Hpt_Config_Read2 Response
BIT
B7
B6
B5
B4
B3
B2
B1
B0
APResponse
(0xA5)
1
0
1
0
0
1
0
1
APDataIn0
APDataIn1
APDataIn2
APDataIn3
APDataIn4
APDataIn5
ETRGActAmp[7:0]
ETRGActDur[7:0]
ETRGBrkAmp[7:0]
ETRGBrkAmp[7:0]
—
—
—
NarLpGain[2:0]
WidLpGain[2:0]
—
NarCntLck[5:0]
Table 146. 0xA6 – Hpt_SYS_Threshold_Config_Write
MODE
Write
B7
BIT
B6
B5
B4
B3
B2
B1
B0
APCmdOut
(0xA6)
1
0
1
0
0
1
1
0
APDataOut0
HptSysUVLO[7:0]
Haptic SYS UVLO Threshold
Sets the SYS undervoltage threshold. If V
HptSys
falls below this UVLO threshold, the haptic driver is locked
SYS
UVLO[7:0]
(HptLock = 1) and System-Error[7:0] = 0x25 is issued. See Opcode 0xA8 for details on restarting the haptic driver.
LSB = 5.5V/255
Table 147. Hpt_SYS_threshold_Config_Write Response
BIT
B7
B6
B5
B4
B3
B2
B1
B0
APResponse
(0xA6)
1
0
1
0
0
1
1
0
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Table 148. 0xA7—Hpt_SYS_threshold_Config_Read
MODE
Read
B7
BIT
B6
B5
B4
B3
B2
B1
B0
APCmdOut
(0xA7)
1
0
1
0
0
1
1
1
Table 149. Hpt_SYS_threshold_Config_Read Response
BIT
B7
B6
B5
B4
B3
B2
B1
B0
APResponse
(0xA7)
1
0
1
0
0
1
1
1
APDataIn0
HptSysUVLO[7:0]
Table 150. 0xA8 – Hpt_Lock_Config_Write
MODE
Write
B7
BIT
B6
0
B5
1
B4
0
B3
1
B2
0
B1
0
B0
0
APCmdOut
(0xA8)
1
APDataOut0
—
—
—
—
—
—
—
HptLock
Haptic Driver Lock
When a fault condition causes the haptic driver to lock, this bit can only be cleared by manually writing HptLock =
0 to opcode 0xA8. The haptic driver output will be off while HptLock = 1.
0 = Unlock Haptic Driver
HptLock
1 = Lock Haptic Driver
Table 151. Hpt_Lock_Config_Write Response
BIT
B7
B6
B5
B4
B3
B2
B1
B0
APResponse
(0xA8)
1
0
1
0
1
0
0
0
Table 152. 0xA9 – Hpt_Lock_Config_Read
MODE
Read
B7
BIT
B6
B5
B4
B3
B2
B1
B0
APCmdOut
(0xA9)
1
0
1
0
1
0
0
1
Table 153. Hpt_Lock_Config_Read Response
BIT
B7
B6
B5
B4
B3
1
B2
0
B1
0
B0
1
APResponse
(0xA9)
1
0
1
0
APDataIn0
—
—
—
—
—
—
—
HptLock
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Table 154. 0xAA – Hpt_EMF_Threshold_Config_Write
MODE
Write
B7
BIT
B6
B5
B4
B3
B2
B1
B0
APCmdOut
(0xAA)
1
0
1
0
1
0
1
0
APDataOut0
—
EmfSkipTh[6:0]
Back EMF Skip Threshold
Percentage of the full-scale output amplitude under which to skip the BEMF measurement as the returned BEMF
would be too small to measure in these cases. LSB = 0.78%V
EMFSkipTh
[6:0]
.
FS
Table 155. Hpt_EMF_Threshold_Config_Write Response
BIT
B7
B6
B5
B4
B3
B2
B1
B0
APResponse
(0xAA)
1
0
1
0
1
0
1
0
Table 156. 0xAB – Hpt_EMF_Threshold_Config_Read
MODE
Read
B7
BIT
B6
B5
B4
B3
B2
B1
B0
APCmdOut
(0xAB)
1
0
1
0
1
0
1
1
Table 157. HPT_EMF_Threshold_Config_Read Response
BIT
B7
B6
B5
B4
B3
B2
B1
B0
APResponse
(0xAB)
1
0
1
0
1
0
1
1
APDataIn0
—
EmfSkipTh[6:0]
Table 158. 0xAC—HPT_Autotune
MODE
Launch
BIT
B7
B6
B5
B4
B3
B2
B1
B0
APCmdOut
(0xAC)
1
0
1
0
1
1
0
0
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Table 159. HPT_Autotune Response
BIT
B7
B6
B5
B4
B3
B2
B1
B0
APResponse
(0xAC)
1
0
1
0
1
1
0
0
APDataIn0
APDataIn1
APDataIn2
Result[7:0]
BEMFPeriod[7:0]
—
—
—
—
BEMFPeriod[11:8]
0x00 = Auto-tune done, BEMFPeriod[11:0] available.
0x01 = Auto-tune failed.
Result [7:0]
BEMFPeriod
[11:0]
Resonant frequency resolved by autotune function = ((25.6MHz / 64) / BEMF_freq)
Table 160. 0xAD— HPT_SetMode
MODE
Write
B7
BIT
B6
0
B5
1
B4
0
B3
1
B2
1
B1
0
B0
1
APCmdOut
(0xAD)
1
APDataOut0
—
—
—
—
EmfEn
HptSel
AlcMod
ZccHysEn
Table 161. HPT_SetMode Response
BIT
B7
B6
B5
B4
B3
B2
B1
B0
APResponse
(0xAD)
1
0
1
0
1
1
0
1
Table 162. 0xAE— HPT_SetInitialGuess
MODE
Write
B7
BIT
B6
B5
B4
B3
B2
B1
B0
APCmdOut
(0xAE)
1
0
1
0
1
1
1
0
APDataOut0
APDataOut1
IniGss[7:0]
—
—
—
—
IniGss[11:8]
Table 163. HPT_SetInitialGuess Response
BIT
B7
B6
B5
B4
B3
B2
B1
B0
APResponse
(0xAE)
1
0
1
0
1
1
1
0
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Table 164. 0xAF— HPT_SetInitialDelay
MODE
Write
B7
BIT
B6
0
B5
1
B4
B3
B2
1
B1
B0
APCmdOut
(0xAF)
1
0
1
1
1
APDataOut0
—
—
—
IniDly[4:0]
Table 165. HPT_SetInitialDelay Response
BIT
B7
B6
B5
B4
B3
B2
B1
B0
APResponse
(0xAF)
1
0
1
0
1
1
1
1
Table 166. 0xB0—HPT_SetWindow
MODE
Write
B7
BIT
B6
B5
B4
B3
B2
B1
B0
APCmdOut
(0xB0)
1
0
1
1
0
0
0
0
IniGssRes
Dis
APDataOut0
APDataOut1
—
—
—
—
WidWdw[4:0]
BrkLpGain[1:0]
NarWdw[3:0]
Table 167. HPT_SetWindow Response
BIT
B7
B6
B5
B4
B3
B2
B1
B0
APResponse
(0xB0)
1
0
1
1
0
0
0
0
Table 168. 0xB1 – HPT_SetBackEMFCycle
MODE
Write
B7
BIT
B6
B5
1
B4
B3
B2
B1
B0
APCmdOut
(0xB1)
1
0
1
0
0
0
1
APDataOut0
BrkCyc[4:0]
EmfSkipCyc[2:0]
Table 169. HPT_SetBackEMFCycle Response
BIT
B7
B6
B5
B4
B3
B2
B1
B0
APResponse
(0xB1)
1
0
1
1
0
0
0
1
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Table 170. 0xB2—HPT_SetFullScale
MODE
Write—
BIT
B7
B6
B5
B4
B3
B2
B1
B0
APCmdOut
(0xB2)
1
0
1
1
0
0
1
0
APDataOut0
HptVfs[7:0]
Table 171. HPT_SetFullScale Response
BIT
B7
B6
B5
B4
B3
B2
B1
B0
APResponse
(0xB2)
1
0
1
1
0
0
1
0
Table 172. 0xB3—Hpt_SetHptPattern
MODE
Write
B7
BIT
B6
B5
B4
B3
B2
B1
B0
APCmdOut
(0xB3)
1
0
1
1
0
0
1
1
APDataOut0
APDataOut1
APDataOut2
APDataOut3
APDataOut4
APDataOut5
ETRGOdAmp[7:0]
ETRGOdDur[7:0]
ETRGActAmp[7:0]
ETRGActDur[7:0]
ETRGBrkAmp[7:0]
ETRGBrkDur[7:0]
Table 173. Hpt_SetHptPattern Response
BIT
B7
B6
B5
B4
B3
B2
B1
B0
APResponse
(0xB3)
1
0
1
1
0
0
1
1
Table 174. 0xB4—Hpt_SetGain
MODE
Write
B7
BIT
B6
B5
B4
B3
0
B2
B1
B0
APCmdOut
(0xB4)
1
0
1
1
1
0
0
APDataOut0
—
NarLpGain[2:0]
—
WidLpGain[2:0]
Table 175. Hpt_SetGain Response
BIT
B7
B6
B5
B4
B3
B2
B1
B0
APResponse
(0xB4)
1
0
1
1
0
1
0
0
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Table 176. 0xB5—HPT_SetLock
MODE
Write
B7
BIT
B6
0
B5
B4
B3
B2
B1
B0
APCmdOut
(0xB5)
1
1
1
0
1
0
1
APDataOut0
—
—
NarCntLck[5:0]
Table 177. Hpt_SetLock Response
BIT
B7
B6
B5
B4
B3
B2
B1
B0
APResponse
(0xB5)
1
0
1
1
0
1
0
1
Table 178. 0xB6—Hpt_ReadResonanceFrequency
MODE
Read
B7
BIT
B6
B5
B4
B3
B2
B1
B0
APCmdOut
(0xB6)
1
0
1
1
0
1
1
0
Table 179. Hpt_ReadResonanceFrequency Response
BIT
B7
B6
B5
B4
B3
B2
B1
B0
APResponse
(0xB6)
1
0
1
1
0
1
1
0
APDataIn0
BEMFPeriod[7:0]
—
APDataIn1
—
—
—
BEMFPeriod[11:8]
Table 180. 0xB7—Hpt_SetTimeout
MODE
Write
B7
BIT
B6
0
B5
B4
B3
B2
B1
B0
APCmdOut
(0xB7)
1
1
1
0
1
1
1
APDataOut0
—
—
HptDrvTmo[5:0]
Haptic Driver Timeout
See Opcode 0xA8 for details on restarting the haptic driver. 1s Step resolution. If timeout is reached, the haptic
driver is locked (HptLock = 1) and SystemError[7:0] = 0x04 is issued.
000000 = Disabled
000001 = 1s
Table 181. Hpt_SetTimeout Response
BIT
B7
B6
B5
B4
B3
B2
B1
B0
APResponse
(0xB7)
1
0
1
1
0
1
1
1
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Table 182. 0xB8—Hpt_GetTimeout
MODE
Read
B7
BIT
B6
B5
B4
B3
B2
B1
B0
APCmdOut
(0xB8)
1
0
1
1
1
0
0
0
Table 183. Hpt_GetTimeout Response
BIT
B7
B6
B5
B4
B3
B2
B1
B0
APResponse
(0xB8)
1
0
1
1
1
0
0
0
APDataIn0
—
—
HptDrvTmo[5:0]
Table 184. 0xB9—Hpt_SetBlankingWindow
MODE
Write
B7
BIT
B6
B5
B4
B3
B2
0
B1
B0
APCmdOut
(0xB9)
1
0
1
1
1
0
1
APDataOut0
APDataOut1
BlankWdw[2:0]
—
BrkWdw[4:0]
—
—
—
—
BlankWdw[5:3]
Table 185. Hpt_SetBlankingWindow Response
BIT
B7
B6
B5
B4
B3
B2
B1
B0
APResponse
(0xB9)
1
0
1
1
1
0
0
1
Table 186. 0xBA—Hpt_SetZCC
MODE
Write
B7
BIT
B6
0
B5
1
B4
B3
B2
0
B1
1
B0
0
APCmdOut
(0xBA)
1
1
1
APDataOut0
—
—
—
—
—
—
ZccSlowEn
FltrCntrEn
Table 187. Hpt_SetZCC Response
BIT
B7
B6
B5
B4
B3
B2
B1
B0
APResponse
(0xBA)
1
0
1
1
1
0
1
0
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Power and Reset Commands
Table 188. 0x80—PowerOff_Command
MODE
Write
B7
BIT
B6
B5
B4
B3
B2
B1
B0
APCmdOut
(0x80)
1
0
0
0
0
0
0
0
APDataOut0
PwrOffCmd[7:0]
Power-Off Command
Writing 0xB2 to this register will immediately place the part in the OFF state.
All other codes = Do nothing
PwrOffCmd
[7:0]
Table 189. PowerOff_Command Response
BIT
B7
B6
B5
B4
B3
B2
B1
B0
APResponse
(0x80)
1
0
0
0
0
0
0
0
PwrOffRes
ponse
APDataIn0
—
—
—
—
—
—
—
Power-Off Response
0 = Password good, preparing Off mode
1 = Password is wrong
PwrOffResp
onse
Table 190. 0x81 – SoftReset_Command
MODE
Write
B7
BIT
B6
B5
B4
B3
B2
B1
B0
APCmdOut
(0x81)
1
0
0
0
0
0
0
1
APDataOut0
SoftResetCmd[7:0]
Soft-Reset Command
SoftReset
Cmd [7:0]
Writing 0xB3 to this register will force a Soft-Reset, all registers will be reset to their default values and the RST
line will be asserted.
All other codes = Do nothing
Table 191. SoftReset_Command Response
BIT
B7
B6
B5
B4
B3
B2
B1
B0
APResponse
(0x81)
1
0
0
0
0
0
0
1
SoftReset
Response
APDataIn0
—
—
—
—
—
—
—
Soft-Reset Response
0 = Password good, preparing Soft-Reset
1 = Password is wrong
SoftReset
Response
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Table 192. 0x82—Hard-Reset_Command
MODE
Write
B7
BIT
B6
B5
B4
B3
B2
B1
B0
APCmdOut
(0x82)
1
0
0
0
0
0
1
0
APDataOut0
HardResetCmd [7:0]
Hard-Reset Command
HardReset
Cmd[7:0]
Writing 0xB4 to this register will force the system to perform a Hard-Reset. All supplies will turn Off and system
will perform a full power-on sequence.
All other codes = Do nothing
Table 193. Hard-Reset_Command Response
BIT
B7
B6
B5
B4
B3
B2
B1
B0
APResponse
(0x82)
1
0
0
0
0
0
1
0
HardReset
Response
APDataIn0
—
—
—
—
—
—
—
Hard-Reset Response
0 = Password good, preparing Hard-Reset
1 = Password is wrong
HardReset
Response
Table 194. 0x83—StayOn_Command
MODE
Write
B7
BIT
B6
B5
B4
B3
B2
B1
B0
APCmdOut
(0x83)
1
0
0
0
0
0
1
1
APDataOut0
—
—
—
—
—
—
—
StayOn
Stay On
This bit must be set within 5s of power-on to prevent the part from shutting down and returning to the power-off
StayOn
condition. This bit has no effect after being set.
0 = Shut down 5s after RST goes HIGH
1 = Stay on
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Table 195. 0x83—StayOn_Command Response
BIT
B7
B6
B5
B4
B3
B2
B1
B0
APResponse
(0x83)
1
0
0
0
0
0
1
1
Table 196. 0x84—PowerOff_Command_Delay
MODE
Write
B7
BIT
B6
B5
B4
B3
B2
B1
B0
APCmdOut
(0x84)
1
0
0
0
0
1
0
0
APDataOut0
PwrOffDlyCmd[7:0]
Power-Off Command with Delay
Writing 0xB2 to this register will place the part in the Off state after a 30ms delay.
All other codes = Do nothing
PwrOffDly
Cmd [7:0]
Table 197. PowerOff_Command_Delay Response
BIT
B7
B6
B5
B4
B3
B2
B1
B0
APResponse
(0x84)
1
0
0
0
0
1
0
0
PwrOffDly
Response
APDataIn0
—
—
—
—
—
—
—
Power-Off with Delay Response
0 = Password good, preparing Off mode
1 = Password is wrong
PwrOffDly
Response
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2
Fuel Gauge I C Registers
Register Summary
The upper byte least-significant bit has units of 1%. The
lower byte provides additional resolution.
All registers must be written and read as 16-bit words;
8-bit writes cause no effect. Any bits marked X (don’t
care) or read only must be written with the rest of the
register, but the value written is ignored by the IC. The
values read from don’t care bits are undefined. Calculate
the register’s value by multiplying the 16-bit word by the
register’s LSb value, as shown in Table 198.
The first update is available approximately 1s after POR
of the IC. Subsequent updates occur at variable intervals
depending on application conditions.
MODE Register (0x06)
The MODE register allows the system processor to send
special commands to the IC (see Figure 16).
VCELL Register (0x02)
The MAX20353 measures VCELL between the V
GND pins. VCELL is the average of four ADC conver-
sions. The value updates every 250ms in active mode
and every 45s in hibernate mode.
●
Quick-Start generates a first estimate of OCV and
SOC based on the immediate cell voltage. Use with
caution; see the Quick-Start section.
and
DD
●
●
EnSleep enables sleep mode. See the Sleep Mode
section.
SOC Register (0x04)
HibStat indicates when the IC is in hibernate mode
The ICs calculate SOC using the ModelGauge algorithm.
This register automatically adapts to variation in battery
size since ModelGauge naturally recognizes relative
SOC.
(read only).
VERSION Register (0x08)
The value of this read-only register indicates the produc-
tion version of the IC.
Table 198. Register Summary
REGISTER
ADDRESS
16-BIT LSb
DESCRIPTION
READ/WRITE
DEFAULT
NAME
VCELL
SOC
0x02
0x04
78.125µV/cell ADC measurement of VCELL.
R
R
—
—
1%/256
—
Battery state of charge.
Initiates quick-start, reports hibernate mode,
and enables sleep mode.
0x06
0x08
0x0A
MODE
VERSION
HIBRT
W
R
0x0000
0x001_
0x8030
—
IC production version.
Controls thresholds for entering and exiting
hibernate mode.
—
R/W
Compensation to optimize performance, sleep
mode, alert indicators, and configuration.
0x0C
0x14
0x16
CONFIG
VALRT
—
—
R/W
R/W
R
0x971C
0x00FF
—
Configures the VCELL range outside of which
alerts are generated.
Approximate charge or discharge rate of the
battery.
CRATE
0.208%/hr
Configures VCELL threshold below which
the IC resets itself, ID is a one-time factory-
programmable identifier.
0x18
0x1A
VRESET/ID
STATUS
—
—
R/W
R/W
0x96__
0x01__
Indicates overvoltage, undervoltage, SOC
change, SOC low, and reset alerts.
0x40 to 0x7F
0xFE
TABLE
CMD
—
—
Configures battery parameters.
W
—
Sends POR command.
R/W
0xFFFF
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sleep mode, and 0 forces the IC to exit. The POR
value of SLEEP is 0.
HIBRT Register (0x0A)
To disable hibernate mode, set HIBRT = 0x0000. To
always use hibernate mode, set HIBRT = 0xFFFF (see
Figure 17).
●
●
ALSC (SOC change alert) enables alerting when
SOC changes by at least 1%. Each alert remains
until STATUS.SC is cleared, after which the alert
automatically clears until SOC again changes by 1%.
Do not use this alert to accumulate changes in SOC.
●
ActThr (active threshold): If at any ADC sample
|OCV-CELL| is greater than ActThr, the IC exits
hibernate mode. 1 LSb = 1.25mV.
ALRT (alert status bit) is set by the IC when an alert
occurs. When this bit is set, the ALRT pin asserts
low. Clear this bit to service and deassert the ALRT
pin. The power-up default value for ALRT is 0. The
STATUS register specifies why the ALRT pin was
asserted.
●
HibThr (hibernate threshold). If the absolute value of
CRATE is less than HibThr for longer than 6min, the
IC enters hibernate mode. 1 LSb = 0.208%/hr.
CONFIG Register (0x0C)
See Figure 18
●
ATHD (empty alert threshold) sets the SOC thresh-
old, where an interrupt is generated on the ALRT pin
and can be programmed from 1% up to 32%. The
value is (32 - ATHD)% (e.g., 00000b → 32%, 00001b
→ 31%, 00010b → 30%, 11111b → 1%). The POR
value of ATHD is 0x1C, or 4%. The alert only occurs
on a falling edge past this threshold.
●
RCOMP is an 8-bit value that can be adjusted to
optimize IC performance for different lithium
chemistries or different operating temperatures. Con-
tact Maxim for instructions for optimization. The POR
value of RCOMP is 0x97.
●
SLEEP forces the IC in or out of sleep mode if
Mode.EnSleep is set. Writing 1 forces the IC to enter
MSB—ADDRESS 0x06
LSB—ADDRESS 0x07
Quick-
Start
X
EnSleep
HibStat
X
X
X
X
X
X
X
X
X
X
X
X
MSb
LSb
MSb
LSb
Figure 16. MODE Register Format
MSB (HibThr)—ADDRESS 0x0A
LSB (ActThr)—ADDRESS 0x0B
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
MSb
LSb
MSb
LSb
0
HibThr 2 UNIT: 0.208%/hr
0
ActThr 2 UNIT: 1.25mV
Figure 17. HIBRT Register Format
MSB (RCOMP)—ADDRESS 0x0C
RCOMP RCOMP RCOMP RCOMP RCOMP RCOMP RCOMP RCOMP
LSB—ADDRESS 0x0D
ATHD ATHD ATHD ATHD ATHD
SLEEP ALSC ALRT
MSb
7
6
5
4
3
2
1
0
4
3
2
1
0
MSb
LSb
LSb
Figure 18. CONFIG Register Format
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identifier to distinguish multiple cell types in produc-
tion. Writes to these bits are ignored.
VALRT Register (0x14)
This register is divided into two thresholds: Voltage
alert maximum (VALRT.MAX) and minimum (VALRT.
MIN). Both registers have 1 LSb = 20mV. The IC alerts
while VCELL > VALRT.MAX or VCELL < VALRT.MIN
(see Figure 19).
●
VRESET[7:1] adjusts a fast analog comparator and a
slower digital ADC threshold to detect battery removal
and reinsertion. For captive batteries, set to 2.5V. For
removable batteries, set to at least 300mV below the
application’s empty voltage, according to the desired
reset threshold for your application. If the compara-
tor is enabled, the IC resets 1ms after VCELL rises
above the threshold. Otherwise, the IC resets 250ms
after the VCELL register rises above the threshold.
CRATE Register (0x16)
The IC calculates an approximate value for the average
SOC rate of change. 1 LSb = 0.208% per hour (not for
conversion to ampere).
●
Dis. Set Dis = 1 to disable the analog comparator in
hibernate mode to save approximately 0.5µA
VRESET/ID Register (0x18)
See Figure 20.
●
ID is an 8-bit read-only value that is one-time pro-
grammable at the factory, which can be used as an
MSB (VALRT.MIN)—ADDRESS 0x14
LSB (VALRT.MAX)—ADDRESS 0x15
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
MIN MIN MIN MIN MIN MIN MIN MIN
MAX MAX MAX MAX MAX MAX MAX MAX
MSb LSb
MSb
LSb
UNIT: 20mV
Figure 19. VALRT Register Format
MSB (VRESET)—ADDRESS 0x18
LSB (ID)—ADDRESS 0x19
7
6
5
4
3
2
1
6
5
4
3
2
1
0
2
2
2
2
2
2
2
Dis
ID
ID
ID
ID
ID
ID
ID
ID
MSb
LSb
MSb
LSb
0
VRESET 2 UNITS: 40mV
Figure 20. VRESET/ID Register Format
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Enable or Disable VRESET Alert:
STATUS Register (0x1A)
●
EnVr (enable voltage reset alert) when set to 1 as-
serts the ALRT pin when a voltage-reset event occurs
under the conditions described by the VRESET/ ID
register.
An alert can indicate many different conditions. The
STATUS register identifies which alert condition was met.
Clear the corresponding bit after servicing the alert (see
Figure 21).
Reset Indicator:
TABLE Registers (0x40 to 0x7F)
●
RI (reset indicator) is set when the device powers
up. Any time this bit is set, the IC is not configured,
so the model should be loaded and the bit should be
cleared.
Contact Maxim for details on how to configure these
registers. The default value is appropriate for some Li+
batteries.
To unlock the TABLE registers, write 0x57 to address
0x3F, and 0x4A to address 0x3E. While TABLE is
unlocked, no ModelGauge registers are updated, so
relock as soon as possible by writing 0x00 to address
0x3F, and 0x00 to address 0x3E.
Alert Descriptors:
These bits are set only when they cause an alert (e.g., if
CONFIG.ALSC = 0, then SC is never set).
●
●
●
●
●
VH (voltage high) is set when VCELL has been above
ALRT.VALRTMAX.
CMD Register (0xFE)
Writing a value of 0x5400 to this register causes the
device to completely reset as if power had been removed
(see the Power-On Reset (POR) section). The reset
occurs when the last bit has been clocked in. The IC
VL (voltage low) is set when VCELL has been below
ALRT.VALRTMIN.
VR (voltage reset) is set after the device has been
reset regardless of EnVr.
2
does not respond with an I C ACK after this command
HD (SOC low) is set when SOC crosses the value in
CONFIG.ATHD.
sequence.
SC (1% SOC change) is set when SOC changes by
at least 1% if CONFIG.ALSC is set.
MSB—ADDRESS 0x1A
LSB—ADDRESS 0x1B
X
EnVR SC
HD
VR
VL
VH
RI
X
X
X
X
X
X
X
X
MSb
LSb
MSb
LSb
Figure 21. STATUS Register Format
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PMIC with Ultra-Low Iq Regulators, Charger,
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Table 199. Haptic Driver Recommended Default Values
REGISTER BITS
BINARY SETTING
VALUE
BEMF detection enabled
EmfEn
1
HptSel
1
LRA
AlcMod
1
ALC enabled
ZccHysEn
ZccSlowEn
FltrCntrEn
0
ZCC Hysteresis Disabled
Normal ZCC operation
Improved noise rejection
Restore initial guess after braking
Four points
0
1
IniGssResDis
AutoBrkPeakMeas
AutoBrkFltrSatStop
AutoBrkMeasWdw
AutoBrkMeasTh
AutoBrkDis
AutoBrkMeasEnd
IniDly
0
0
0
Do not exit braking
40µs
1000
01
5.0mV
0
Automatic braking enabled
1 BEMF detection below threshold
00
00010
00101
011
0010
2 sine wave half periods skipped
nds
WidWdw
5/32
1/8
of current sine wave period
of current sine wave period
WidLpGain
NarWdw
nds
2/32
NarCntLck
000110
00
6 sine wave half periods
BrkLpGain
Gain = 1
1/4
NarLpGain
010
BlankWdw
001000
01000
11110
000
40µs
nds
BrkWdw
8/32
of current sine wave period
BrkCyc
30 sine wave half periods
0 sine wave half periods
EmfSkipCyc
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Table 200. Haptic Driver Recommended Default Values
OPCODE
REGISTER
APDataOut0
APDataOut1
APDataOut2
APDataOut3
APDataOut4
APDataOut5
APDataOut0
APDataOut1
APDataOut2
APDataOut3
APDataOut4
APDataOut5
APDataOut0
APDataOut1
APDataOut2
APDataOut3
APDataOut4
APDataOut5
VALUE
0x0E
User Value
0x1X (X = User Value)
0x02
Hpt_Config_Write0 (0xA0)
0x05
0x02
0xF0
0x08
0x01
Hpt_Config_Write1 (0xA2)
User Value
User Value
User Value
User Value
User Value
User Value
User Value
0x23
Hpt_Config_Write2 (0xA4)
0x06
Table 201. Register Bit Default Values
DEFAULT VALUE
MAX20353B
Hi-Z
MAX20353A
MAX20353C
PFN2PUD_CFG*
PFN1PUD_CFG*
WriteProtect
ILimBlank
ILimCntl
Hi-Z
PU/PD Connected
Disabled
Disabled
500mA
PU/PD Connected
PU/PD Connected
Disabled
Disabled
500mA
PU/PD Connected
Disabled
10ms
300mA
MtChgTmr
FChgTmr
0min
0min
0min
600min
150min
600min
PChgTmr
30min
60min
30min
TShdnTmo
ChgAutoRe
VPChg
10s
5s
5s
Auto-Restart
3.15V
Auto-Restart
3V
Auto-Restart
3.15V
IPChg
10% I
10% I
10% I
FCHG
5% I
FCHG
FCHG
FCHG
5% I
5% I
FCHG
FCHG
ChgDone
ChgEn
Disabled
Enabled
200mV
Enabled
Enabled
170mV
Disabled
Enabled
220mV
ChgAutoStp
BatReChg
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Table 201. Register Bit Default Values (continued)
DEFAULT VALUE
MAX20353B
4.35V
MAX20353A
MAX20353C
BatReg
4.35V
1397.65mV
529.41mV
425mA
4.35V
1037.65mV
240mV
ColdLim
1327.06mV
416.47mV
275mA
HotLim
BstISet
125mA
BstIAdptEn
BstFastStrt
BstFetScale
BstVSet
Enabled
50ms
Enabled
100ms
Enabled
100ms
Disabled
20V
Disabled
14.5V
Disabled
5V
Buck1FetScale
Buck2FetScale
BstSeq
Disabled
Disabled
BstEn After 100%
Disabled
1.8V
Disabled
Enabled
BstEn After 100%
Disabled
1.825V
Disabled
Disabled
BoostEn After 100%
MPC Reg Defined
1.825V
BstEn
Buck1VSet
Buck1IZCSet
Buck2VSet
Buck2IZCSet
Buck2ISet
Buck1ISet
BootDly**
Buck2SftStrt
Buck1SftStrt
Buck2En
30mA
30mA
30mA
0.9V
2.00V
3.20V
10mA
30mA
10mA
150mA
75mA
150mA
150mA
150mA
150mA
120ms
80ms
120ms
50ms Soft-Start
50ms Soft-Start
Disabled
Enabled
LDO
25ms Soft-Start
25ms Soft-Start
Enabled
Enabled
Load Switch
Disabled
LDO
50ms Soft-Start
50ms Soft-Start
Disabled
Enabled
Buck1En
LDO1Md
Load Switch
Direct Reg Control
LDO
LDO1En
Disabled
LDO
LDO2Md
LDO2En
Disabled
Enabled
3.2V
Disabled
Enabled
3.6V
Direct Reg Control
Enabled
PassDiscEna***
LDO2VSet
StayOn
3.2V
Enabled
3.3V
Enabled
5.0V
Enabled
SFOUTVSet
LDO1VSet
SysMinVlt
SFOUTEn
CPVSet
3.3V
1.2V
1.825V
1.8V
3.6V
3.6V
3.6V
CHGIN
Disabled
5.0V
Disabled
5.0V
6.6V
CPEn
Disabled
CPEn After 100%
Disabled
Disabled
Disabled
CPEn After 100%
CPSeq
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PMIC with Ultra-Low Iq Regulators, Charger,
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Table 201. Register Bit Default Values (continued)
DEFAULT VALUE
MAX20353B
0b0111
MAX20353A
MAX20353C
PwrRstCfg
Buck2Seq
Buck1Seq
BBstEn
0b0110
Buck2En After 100%
Buck1En After 100%
Disabled
0b1000
Buck2En After 100%
0%
Buck2En After 100%
0%
Disabled
Disabled
LDO2Seq
LDO1Seq
ThmEn
LDO2En After 100%
LDO1En After 100%
Disabled
LDO2En After 100%
LDO1En After 100%
Enabled
LDO2En After 100%
LDO1En After 100%
Enabled
BBstVset
BBstISet
BatOcThr
BBstRipRed
BBstInd
5V
3.8V
4.5V
100mA
100mA
50mA
1000mA
400mA
1000mA
Lower Ripple
4.7µH
Lower Ripple
4.7µH
Lower Ripple
4.7µH
BBstSeq
EmfEn
BBstEn After 100%
Disabled
BBstEn After 100%
Enabled
BBstEn After 100%
Enabled
HptSel
ERM
ERM
LRA
AlcMod
Enabled
Disabled
Enabled
HptSysUVLO
HptDrvTmo
ILimMax****
3V
3V
3.21V
10s
Disabled
10s
1000mA
450mA
1000mA
T
100°C
100°C
CHGIN_SHDN
100°C
*See Table 202
**Sets t time. See Figure 3
RST
***If enabled, passive discharge is enabled for all rails in off mode.
****Current limit during t
ILimBlank
Table 202. PFN Connections and Logic Configurations
DEVICE CONFIGURATION
FUNCTION
MAX20353A
MAX20353B
MAX20353C
Pullup
PFN1
PFN2
Pullup
Hi-Z
Pullup
Hi-Z
Pullup
V
, V
V
, V
V , V
PFN_IH PFN_IL
ON STATE LOGIC LEVELS*
PFN_IH PFN_IL
PFN_IH PFN_IL
*Values in this row reference EC table parameters. In OFF mode, V
and V
logic levels always apply.
PFN_IH
PFN_IL
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2
Table 203. I C Direct Register Default Values
DEFAULT VALUE
MAX20353B
0x03
REGISTER
NAME
MAX20353A
0x03
0x02
0x00
0x00
0x00
0x40
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x4A
0x74
0x63
0x00
0x00
0x00
0x00
0x04
0x00
0x00
0x00
MAX20353C
0x03
0x02
0x00
0x00
0x00
0x40
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x4A
0x74
0x63
0x00
0x00
0x00
0x00
0x04
0x00
0x00
0x00
0x00
0x01
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
0x11
0x12
0x13
0x14
0x15
0x17
0x18
0x19
0x1A
0x1B
0x1C
0x1D
0x1E
0x20
0x21
0x28
0x29
0x2A
0x2B
0x2C
0x2D
0x2E
0x2F
0x30
0x31
0x32
0x33
HardwareID
FirmwareID
SystemError
IntMask0
0x02
0x00
0x00
IntMask1
0x00
IntMask2
0x40
APDataOut0
APDataOut1
APDataOut2
APDataOut3
APDataOut4
APDataOut5
APDataOut6
APCmdOut
APResponse
APDataIn0
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
APDataIn1
0x00
APDataIn2
0x00
APDataIn3
0x00
APDataIn4
0x00
APDataIn5
0x00
LDODirect
0x00
MPCDirectWrite
HptRAMAddr
HptRAMDataH
HptRAMDataM
HptRAMDataL
LEDStepDirect
LED0Direct
LED1Direct
LED2Direct
HptDirect0
0x00
0x00
0x4A
0x74
0x63
0x00
0x00
0x00
0x00
0x04
HptDirect1
0x00
HptRTI2Camp
HptPatRAMAddr
0x00
0x00
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Table 204. Read Opcode Default Values
DEFAULT VALUE
OPCODE
REGISTER
MAX20353A
0x00
MAX20353B
0x00
MAX20353C
0x00
APDataIn0
APDataIn1
APDataIn2
APDataIn3
APDataIn4
0x00
0x00
0x00
GPIO_Config_Read
0x00
0x00
0x00
(0x02)
0x00
0x00
0x00
0x00
0x00
0x00
GPIO_Control_Read
(0x04)
APDataIn0
0x00
0x00
0x00
APDataIn0
APDataIn1
APDataIn2
APDataIn3
APDataIn4
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
MPC_Config_Read
(0x07)
InputCurrent_Config_Read
(0x11)
APDataIn0
APDataIn0
0x06
0x03
0x1C
0x03
0x06
0x03
ThermalShutdown_Config_Read
(0x12)
APDataIn0
APDataIn1
APDataIn2
APDataIn3
APDataIn0
APDataIn1
APDataIn2
APDataIn3
APDataIn0
APDataIn1
APDataIn2
APDataIn3
APDataIn4
0x0C
0x75
0xF6
0x00
0xC6
0xC6
0x4B
0x4B
0x00
0x00
0x1F
0x00
0x00
0x05
0x64
0xE6
0x00
0xBC
0xBC
0x3B
0x3B
0x00
0x00
0x1F
0x00
0x00
0x0C
0x70
0xF6
0x00
0x93
0x93
0x22
0x22
0x00
0x00
0x1F
0x00
0x00
Charger_Config_Read
(0x15)
ChargerThermalLimits_Config_Read
(0x17)
ChargerThermalReg_ConfigRead
(0x19)
Charger_Control_Read
(0x1B)
APDataIn0
APDataIn0
0x00
0x86
0x03
0x86
0x02
0x86
Charger_JEITAHyst_ControlRead
(0x1D)
APDataIn0
APDataIn1
APDataIn2
APDataIn3
APDataIn4
0x00
0x06
0x0D
0x3C
0x00
0x00
0x04
0x07
0x26
0x07
0x02
0x04
0x01
0x00
0x07
Bst_Config_Read
(0x31)
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Small Li+ Systems
Table 204. Read Opcode Default Values (continued)
DEFAULT VALUE
MAX20353B
0x20
OPCODE
REGISTER
MAX20353A
0x00
0xA8
0x26
0x01
0x07
0x00
0x82
0x06
0x00
0x07
0x00
0x1C
0x07
0x00
0x17
0x07
0x00
0x00
0x07
MAX20353C
0x00
0xAD
0x26
0x01
0x07
0x00
0xB2
0x06
0x00
0x07
0x00
0x34
0x07
0x00
0x17
0x07
0x00
0x01
0x07
APDataIn0
APDataIn1
APDataIn2
APDataIn3
APDataIn4
APDataIn0
APDataIn1
APDataIn2
APDataIn3
APDataIn4
APDataIn0
APDataIn1
APDataIn2
APDataIn0
APDataIn1
APDataIn2
APDataIn0
APDataIn1
APDataIn2
0xAD
0x26
Buck1_Config_Read
(0x36)
0x01
0x02
0x22
0x9A
Buck2_Config_Read
0x23
(0x3B)
0x01
0x07
0x00
LDO1_Config_Read
0x35
(0x41)
0x07
0x00
LDO2_Config_Read
0x1B
(0x43)
0x07
0x00
ChargePump_Config_Read
0x01
(0x47)
0x00
SFOUT_Config_Read
(0x49)
APDataIn0
APDataIn0
0x05
0x00
0x00
0x00
0x04
0x00
MONMux_Config_Read
(0x51)
APDataIn0
APDataIn1
APDataIn2
APDataIn3
APDataIn4
APDataIn0
APDataIn1
APDataIn2
APDataIn3
APDataIn4
APDataIn5
0x00
0x02
0x19
0x50
0x07
0x02
0xD0
0x97
0x00
0x05
0x01
0x00
0x02
0x0D
0x50
0x07
0x08
0xD0
0x17
0x03
0x05
0x01
0x00
0x01
0x14
0x50
0x07
0x0E
0xD0
0x17
0x03
0x05
0x01
BBst_Config_Read
(0x71)
Hpt_Config_Read0
(0xA1)
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│ 151
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MAX20353
PMIC with Ultra-Low Iq Regulators, Charger,
Fuel Gauge, and Haptic Driver for
Small Li+ Systems
Table 204. Read Opcode Default Values (continued)
DEFAULT VALUE
MAX20353B
0x01
OPCODE
REGISTER
MAX20353A
0x01
MAX20353C
0x01
APDataIn0
APDataIn1
APDataIn2
APDataIn3
APDataIn4
APDataIn5
APDataIn0
APDataIn1
APDataIn2
APDataIn3
APDataIn4
APDataIn5
0x00
0x00
0x00
0x02
0x02
0x02
Hpt_Config_Read1
(0xA3)
0x8B
0x7F
0x8B
0x8B
0x7F
0x7F
0x04
0x04
0x04
0xCC
0x32
0x4C
0x4C
0x32
0x32
0xFF
0x04
0xFF
0xFF
0x04
Hpt_Config_Read2
(0xA5)
0x04
0x24
0x24
0x24
0x06
0x06
0x06
Hpt_SYS_Threshold_Config_Read
(0xA7)
APDataIn0
APDataIn0
APDataIn0
0x8B
0x00
0x19
0x8B
0x00
0x19
0x95
0x00
0x19
Hpt_Lock_Config_Read
(0xA9)
Hpt_EMF_Threshold_Config_Read
(0xAB)
Ordering Information
Chip Information
PROCESS: BiCMOS
PART
TEMP RANGE
PIN-PACKAGE
56 WLP
MAX20353AEWN+
MAX20353AEWN+T
MAX20353BEWN+
MAX20353BEWN+T
MAX20353CEWN+
MAX20353CEWN+T
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
56 WLP
56 WLP
56 WLP
56 WLP
56 WLP
+Denotes a lead (Pb)-free package/RoHS-compliant package.
T = Tape and reel
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MAX20353
PMIC with Ultra-Low Iq Regulators, Charger,
Fuel Gauge, and Haptic Driver for
Small Li+ Systems
Revision History
REVISION REVISION
PAGES
CHANGED
DESCRIPTION
NUMBER
DATE
0
6/19
Initial release
—
Updated the title, Table 201–204, and added MAX20353BEWN+ and
MAX20353BEWN+T to the Ordering Information table
1
2
7/20
2/21
1–153
Updated Tables 201‒204, and added MAX20353CEWN+ and
MAX20353CEWN+T to the Ordering Information table
146‒152
For pricing, delivery, and ordering information, please visit Maxim Integrated’s online storefront at https://www.maximintegrated.com/en/storefront/storefront.html.
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses
are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits)
shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
©
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.
2021 Maxim Integrated Products, Inc.
│ 153
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