MAX20317EWP+T [MAXIM]
Consumer Circuit,;
| 型号： | MAX20317EWP+T |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Consumer Circuit, 商用集成电路 |
| 文件： | 总47页 (文件大小：751K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MAX20317
Universal 3.5mmØ Accessory Management IC
General Description
Benefits and Features
● Allows Wide Range of Applications by Supporting
2
The MAX20317 is an I C controllable, universal 3.5mmØ
accessory management IC. The device provides a universal
jack interface solution, as well as a compact solution for
the power management and interface control of a powered
accessory, such as an active noise cancelling (ANC)
headset.
The MAX20317 automatically measures headset
impedance with a high precision, triple current source
8 bit ADC. After impedance detection, the device also
detects when a headset is in a CTIA or OMTP configuration
and automatically configures the SLEEVE and RING2
terminals to correctly connect the microphone and ground
lines.
When a boost supply is applied, the MAX20317 can
detect the presence of an ANC headset. When the ANC
headset is detected and enabled, a button-press monitoring
circuit activates and flags button presses by detecting the
voltage drop across a sense resistor.
The MAX20317 provides a power line communication tool
to a headset to exchange the data with the host device.
The MAX20317 has the two separate ground sense inputs
from the SLEEVE and RING2 terminals of the connector
to provide a high ground isolation to the audio codec.
Universal 3.5mm Jack Types
• Auto-Configuration for CTIA and OMTP Headsets
• Supports MEMS Microphone
• 50mΩ Ground Switch
● Enables Long Utilization of Accessories by Supplying
Power Through 3.5mm Jack
• Powered Accessory/Headset Detection
• Bypass Switch to Power Accessories such as
ANC Headsets
• Programmable Button Detection in Powered
Accessory Mode
● Empowers New Path in Data Communication to
Accessories
• Power Line Communication by 3.5mm Jack
• Bidirectional Digital Data Communication in Power
Mode
• Allow Emergence of New Accessory Types
● Provides Comfortable Sounds by Introducing
Automatic Volume Adjustment
• Adaptive Volume Control Based on Precision
Headset Impedance
• False Insertion Detection
The MAX20317 is available in a space-saving, 20-bump,
0.4mm pitch, 1.65mm x 2.05mm wafer-level package
(WLP) and operates over the -40°C to +85°C extended
temperature range.
● Saves Board Space with Small Form Factor
• 1.65mm x 2.05mm 4 x 5 Array 20 Bump 0.4mm
Pitch WLP
Applications
● Smart Phones
Ordering Information appears at end of data sheet.
● Tablet PCs
● Phablet
● Notebook PCs
Typical Application Circuit
CODEC
VCC
+5V
MIC1
MIC1-BIAS
R-G L-G R-A L-A
1µF
1µF
6.8
VIO
RSEN
MIC_OUT
V
CC
V
BOOST
G_SNSR
G_SNSL
SLEEVE
APPLICATION
PROCESSOR
MIC
MAX20317
LEFT
DET
RING2
DETIN
SDA
SCL
SDA
SCL
INT
SLEEVE_SL
RIGHT
GND
SLEEVE_SR
RING2_SL
RING2_SR
DGND
GND
19-100037; Rev 0; 5/17
MAX20317
Universal 3.5mmØ Accessory Management IC
Absolute Maximum Ratings
All voltages are referred to GND unless otherwise noted
Continuous Current into Any Other Terminal .................±100mA
V
V
, SCL, SDA, INT...............................................-0.3V to +6V
BOOST
Continuous Power Dissipation (Multilayer Board)
CC
, RSEN.....................................................-0.3V to +12V
(Derate 18.02mW/°C above +70°C).......................1441.6mW
Operating Temperature Range........................... -40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range............................ -65°C to +150°C
Soldering Temperature (Reflow)......................................+260°C
MIC_OUT ....................................................-0.3V to V
DETIN.............................................................-3V to V
SLEEVE, SLEEVE_SL, SLEEVE_SR,
RING2, RING2_SL, RING2_SR..........................-0.3V to +6V
G_SNSL, G_SNSR ..............................................-0.3V to +0.3V
+ 0.3V
+ 0.3V
CC
CC
Continuous Current into V
, RSEN,
BOOST
MIC_OUT, RING2, SLEEVE.......................................±200mA
(Note 1)
Package Thermal Characteristics
WLP
Junction-to-Ambient Thermal Resistance,
Four Layer Board (θ ) ..........................................55.49°C/W
JA
Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer
board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Electrical Characteristics
(V
= +3.0V to +5.5V, V
= 0V to +5.5V, T = -40°C to +85°C, unless otherwise noted. Typical values are at V
= +3.5V,
CC
CC
BOOST
A
T
= +25°C.) (Note 2)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
V
CC
Supply Voltage Range
V
3
5.5
V
V
CC
V
POR
V
0.9
1.7
2
2.45
5
CC
CC
CCPOR
V
= +3.5V, DETIN = 1
CC
µA
BYPASS (0x08[2]) = 0, DETIN = 0
10
15
V
Supply Current
I
VCC
V
= +3.5V, BYPASS (0x08[2]) = 1,
CC
0.1
0.2
5.5
mA
V
DETIN = 0, I
= 30mA
VBOOST
Bypass Supply Voltage
Range
V
BOOST
DETIN
DETIN Pullup Current
I
4.5
µA
V
DETIN_PU
DETIN Detection
Threshold
1/3 x
1/2 x
2/3 x
V
CC
V
V
CC
CC
SET_IDET (0x0B[5:4]) = 01
SET_IDET (0x0B[5:4]) = 10
SET_IDET (0x0B[5:4]) = 11
95
100
1.1
5.5
105
1.15
5.75
µA
1.05
5.25
DETIN Current Source
I
DETIN
mA
Maxim Integrated
│ 2
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MAX20317
Universal 3.5mmØ Accessory Management IC
Electrical Characteristics (continued)
(V
= +3.0V to +5.5V, V
= 0V to +5.5V, T = -40°C to +85°C, unless otherwise noted. Typical values are at V
= +3.5V,
CC
CC
BOOST
A
T
= +25°C.) (Note 2)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
BYPASS SWITCH
Output Shutdown
V
V
= 5.0V
BOOST
1.28
1.36
1
1.44
1.5
V
Ω
SH
R
Drop
SEN
V
= 4.2V, V
= 5.0V,
CC
BOOST
Bypass Switch R
R
BYPASS
ON
I
= 150mA
BYPASS
V
= 5V ± 50mV,
RSEN
Off Isolation to SLEEVE
SLEEVE, RING2 (GND MUX SWITCH)
-90
dB
f = 20Hz to 20kHz
Ground MUX Switch R
R
V = 3.5V
CC
50
300
85
mΩ
MHz
dB
ON
GMP
Ground MUX Switch
Bandwidth
R
= R
= 50Ω
SOURCE
LOAD
Ground Switch PSRR
PSRR
V
= 3.5V, R
= 50Ω, f = 217Hz
-96
GNDSW
CC
SOURCE
Ground Bypass Switch
THD
100mV
to 20KHz, R
, DC bias = 0V, f = 20Hz
Pk-Pk
0.002
%
= R
= 50Ω
SOURCE
LOAD
SLEEVE, RING2 (MIC MUX SWITCH)
MIC Switch Turn-On Time
5
4
1
µs
µs
Ω
MIC Switch Turn-Off Time
MIC Switch R
R
V = 3.5V, I = 10mA
CC
2
ON
MIC
MIC Switch Bandwidth
MIC Switch PSRR
R
= R
= 50Ω
25
MHz
SOURCE
LOAD
V
= 3.5V, R
= 50Ω,
CC
SOURCE
-90
dB
f = 217Hz
MIC Switch Isolation
-90
dB
V
, RSEN (ANC DETECTION)
BOOST
Using 6.8Ω External Sense for ANC
detection, range from 1.5 to 5mA
(ADC2_HL(0x0B[2])) = 1.
Thresholds I C Programmable by
HSDET_VAL
ANC Headset Detection
Accuracy
-3
-3
+3
+3
%
%
2
Using 6.8Ω External Sense, range from
5mA to 200mA (ADC2_HL(0x0B[2])) = 0.
Button Press Current
Measurement Accuracy
2
Thresholds I C Programmable by
HSDET_VAL
COM_THRS[1:0](0x08[1:0]) = 00
COM_THRS[1:0] (0x08[1:0]) = 01
COM_THRS[1:0] (0x08[1:0]) = 10
COM_THRS[1:0] (0x08[1:0]) = 11
87
89
91
93
88
90
92
94
89
91
93
95
%V
BOOST
BOOST
BOOST
BOOST
ANC Button Detection
Interrupt Falling Edge
Threshold
%V
%V
%V
V
COM_DET
BOOST OVP OVLO
Threshold
V
V
slew rate ≤ 1V/µs
BOOST
5.6
5.75
5.94
V
BOOST_OVLO
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MAX20317
Universal 3.5mmØ Accessory Management IC
Electrical Characteristics (continued)
(V
= +3.0V to +5.5V, V
= 0V to +5.5V, T = -40°C to +85°C, unless otherwise noted. Typical values are at V
= +3.5V,
CC
CC
BOOST
A
T
= +25°C.) (Note 2)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
GROUND SENSE SWITCH (G_SNSR/G_SNSL)
G_SNS Switch Turn-On
Time
50
3
µs
µs
G_SNS Switch Turn-Off
Time
G_SNS Switch R
I
= 10mA
LOAD
0.8
300
-90
-90
1.5
Ω
ON
R
C
= R
= 50Ω,
SOURCE
LOAD
G_SNS Switch Bandwidth
G_SNS Switch PSRR
MHz
dB
dB
= 10pF
LOAD
V
= 3.3V, R
= R
LOAD
= 50Ω,
= 50Ω,
CC
SOURCE
f = 217Hz, V = 3.3V ±0.1V
IN
V
= 3.3V, R
= R
CC
SOURCE LOAD
G_SNS Switch Cross talk
f = 20Hz to 20kHz, V
= ±150mV
MIC
DIGITAL SIGNALS (SDA, SCL, INT)
Input Logic-High
V
1.4
-1
V
V
IH
Input Logic-Low
V
0.4
1
IL
Input Leakage Current
µA
Output Logic-High
Leakage Current
(Open-Drain)
I
V
= 5V
1
µA
V
OH_LKG
IO
Output Logic-Low
V
I
= 4mA
SINK
0.4
OL
POWER LINE COMMUNICATION
V
V
= 5V, Low is V
below
BOOST
RSENSE
PLC Logic-High
V
V
V
COM_DET
COM_DET
V
V
= 5V, High is V
above
RSENSE
BOOST
PLC Logic-Low
V
COM_DET
COM_DET
2
I C Programmable (24/30µs)
Inferred from 1µs clock
Time Unit
t
24/30
µs
UNIT
TX Logic 0
TX Logic 1
RX Logic 0
RX Logic 1
t
t
90
40
85
35
90
70
110
60
% t
UNIT
TXLOGIC0
TXLOGIC1
RXLOGIC0
RXLOGIC1
Period for low and high
% t
UNIT
t
t
115
65
% t
UNIT
UNIT
Period for low and high
PLC_SINK (0x18[6]) = 0
PLC_SINK(0x18[6]) = 1
% t
100
80
110
90
mA
mA
PLC TX Current Sink
I
PLC
Maxim Integrated
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MAX20317
Universal 3.5mmØ Accessory Management IC
Electrical Characteristics (continued)
(V
= +3.0V to +5.5V, V
= 0V to +5.5V, T = -40°C to +85°C, unless otherwise noted. Typical values are at V
= +3.5V,
CC
CC
BOOST
A
T
= +25°C.) (Note 2)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DYNAMIC
DETIN Falling Edge, DET_DEBOUNCE
(0x08[6]) = 0
115
300
30
DETIN Debounce Time
t
ms
ms
DIDEB
DETIN Falling Edge, DET_DEBOUNCE
(0x08[6]) = 1
SEND/END Debounce
Time
2
t
I C selectable: 20/30/40/50ms
SEDEB
I
I
Rise Time
Fall Time
t
Rising
Falling
50
50
ms
ms
DETIN
IDETINR
t
DETIN
IDETINF
2
I C TIMING
2
I C Serial Clock
f
400
kHz
SCL
Frequency
ESD PROTECTION
DETIN
Human Body Model
Human Body Model
Human Body Model
±15
±10
±2
kV
kV
kV
SLEEVE, RING2,
SLEEVE_SR, SLEEVE_
SL, RING2_SR, RING2_
SL
All Other Pins
THERMAL PROTECTION
Thermal Shutdown
T
Low to high
130
20
°C
°C
SHDN
Thermal Hysteresis
T
High to low
HYST
Note 2: All devices are 100% production tested at T = +25°C. Limits over the operating temperature range are guaranteed by
A
design.
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MAX20317
Universal 3.5mmØ Accessory Management IC
Typical Operating Characteristics
(V
= +3.5V, R
= 6.8Ω, T = +25°C unless otherwise noted.)
CC
SEN A
SUPPLY CURRENT
vs. SUPPLY VOLTAGE
SUPPLY CURRENT
vs. SUPPLY VOLTAGE
SUPPLY CURRENT
vs. SUPPLY VOLTAGE
toc01
toc02
toc03
8
7
6
5
4
3
2
1
0
16
14
12
10
8
200
180
160
140
120
100
80
VBOOST = 5V
6
VBOOST = 0V
60
4
40
2
DETIN LOW, BYPASS = 0
VMIC_OUT = 2.8V, VBOOST = 0V
DETIN LOW, BYPASS = 1
VMIC_OUT = 2.8V, VBOOST = 5V
20
DETIN HIGH
5.0
0
0
3.0
3.5
4.0
4.5
5.5
3.0
3.5
4.0 4.5 5.0
SUPPLY VOLTAGE (V)
5.5
3.0
3.5
4.0 4.5 5.0
SUPPLY VOLTAGE (V)
5.5
SUPPLY VOLTAGE (V)
SLEEVE OUTPUT VOLTAGE
vs. SUPPLY VOLTAGE
BYPASS SWITCH OUTPUT VOLTAGE
vs. LOAD CURRENT
BYPASS SWITCH OUTPUT VOLTAGE
vs. LOAD CURRENT
toc06
toc04
toc05
2.85
2.84
2.83
2.82
2.81
2.80
2.79
2.78
2.77
2.76
2.75
6
5
4
3
2
1
0
6
5
4
3
2
1
0
ISLEEVE = 0mA
ISLEEVE = 1mA
ISLEEVE = 4mA
WITH 6.8Ω
VCC = 5V, VBOOST = 5V, CTIA
VCC = 5V, VBOOST = 5V, CTIA
VMIC_OUT = 2.8V, CTIA
3.0
3.5
4.0
4.5
5.0
5.5
0
50
100
150
200
0
50
100
150
200
SUPPLY VOLTAGE (V)
LOAD CURRENT (mA)
LOAD CURRENT (mA)
BYPASS SWITCH NORMALIZED ON-RESISTANCE
BYPASS SWITCH OFF-ISOLATION
TO SLEEVE
vs. SUPPLY VOLTAGE
toc08
toc07
1.4
0
1.2
1.0
0.8
0.6
0.4
0.2
0.0
-20
-40
TA = +85ºC
TA = +25ºC
-60
TA = -40ºC
-80
-100
-120
VBOOST = 5V, ILOAD = 150mA
NORMALIZED TO VCC = 4.5V, TA = +25ºC
3.0
3.5
4.0
4.5
5.0
5.5
20
200
2000
20000 200000 2000000
SUPPLY VOLTAGE (V)
FREQUENCY (Hz)
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MAX20317
Universal 3.5mmØ Accessory Management IC
Typical Operating Characteristics (continued)
(V
= +3.5V, R
= 6.8Ω, T = +25°C unless otherwise noted.)
CC
SEN A
BYPASS SWITCH OFF-ISOLATION
TO RING2
MIC MUX PSRR
vs. FREQUENCY
MIC MUX PSRR
vs. FREQUENCY
toc09
toc10
toc11
0
0
-20
0
-20
-20
-40
-40
-40
-60
-60
-60
-80
-80
-80
-100
-120
-100
-120
-100
-120
CTIA
100000
OMTP
10000 100000
20
200
2000
20000 200000 2000000
10
100
1000
10000
10
100
1000
FREQUENCY (Hz)
FREQUENCY (Hz)
FREQUENCY (Hz)
MIC MUX NORMALIZED ON-RESISTANCE
vs. SUPPLY VOLTAGE
toc12
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
TA = +85ºC
TA = +85ºC
TA = +25ºC
TA = +85ºC
TA = +25ºC
TA = +25ºC
TA = -40ºC
TA = -40ºC
TA = -40ºC
VIN = 3V, ILOAD = 100mA, OMTP
NORMALIZED TO VCC = 4.5V, TA = +25ºC
VIN = 3V, ILOAD = 100mA, CTIA
NORMALIZED TO VCC = 4.5V, TA = +25ºC
CTIA, NORMALIZED TO VCC = 4.5V, TA = +25ºC
3.0
3.5
4.0
4.5
5.0
5.5
3.0
3.5
4.0
4.5
5.0
5.5
3.0
3.5
4.0
4.5
5.0
5.5
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
GND MUX NORMALIZED ON-RESISTANCE
GND MUX PSRR
vs. FREQUENCY
vs. SUPPLY VOLTAGE
toc16
toc15
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
0
-20
-40
-60
-80
TA = +85ºC
TA = +25ºC
TA = -40ºC
-100
-120
-140
OMTP, NORMALIZED TO VCC = 4.5V, TA = +25ºC
3.0
3.5
4.0
4.5
5.0
5.5
10
100
1000
10000
100000
SUPPLY VOLTAGE (V)
FREQUENCY (Hz)
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MAX20317
Universal 3.5mmØ Accessory Management IC
Typical Operating Characteristics (continued)
(V
= +3.5V, R
= 6.8Ω, T = +25°C unless otherwise noted.)
CC
SEN A
GND SENSE NORMALIZED ON-RESISTANCE
GND SENSE NORMALIZED ON-RESISTANCE
GND SENSE PSRR
vs. FREQUENCY
vs. SUPPLY VOLTAGE
vs. SUPPLY VOLTAGE
toc19
toc17
toc18
1.8
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
TA = +85ºC
TA = +25ºC
TA = -40ºC
TA = +85ºC
TA = +25ºC
TA = -40ºC
VIN = 0.2V, ILOAD = 10mA, OMTP
NORMALIZED TO VCC = 4.5V, TA = +25ºC
VIN = 0.2V, ILOAD = 10mA, CTIA
NORMALIZED TO VCC = 4.5V, TA = +25ºC
3.0
3.5
4.0
4.5
5.0
5.5
3.0
3.5
4.0
4.5
5.0
5.5
10
100
1000
10000
100000
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
FREQUENCY (Hz)
BANDWIDTH, OFF-ISOLATION, CROSSTALK
BANDWIDTH, OFF-ISOLATION, CROSSTALK
DETIN DEBOUNCE TIMING
OF SLEEVE/RING2 MIC SWITCH
OF GROUND SENSE SWITCH
toc22
toc20
toc21
0
-20
0
-20
BANDWIDTH
BANDWIDTH
CTIA 32Ω
-40
-40
OFF-ISOLATION
OFF-ISOLATION
VDETIN
1V/div
-60
-60
-80
-80
CROSSTALK
CROSSTALK
VINT
-100
-120
-100
-120
5V/div
0.02 0.2
2
20
200 2000 20000 200000
0.02 0.2
2
20
200 2000 20000 200000
200ms/div
FREQUENCY (kHz)
FREQUENCY (kHz)
DETIN DEBOUNCE TIMING
DETIN DEBOUNCE TIMING
toc23
toc24
OMTP 32Ω
CTIA 220Ω
VDETIN
VDETIN
1V/div
5V/div
1V/div
5V/div
VINT
VINT
200ms/div
200ms/div
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MAX20317
Universal 3.5mmØ Accessory Management IC
Typical Operating Characteristics (continued)
(V
= +3.5V, R
= 6.8Ω, T = +25°C unless otherwise noted.)
CC
SEN A
SLEEVE WAVEFORM
BYPASS FROM 0 TO 1
SLEEVE WAVEFORM
BYPASS FROM 1 TO 0
DETIN DEBOUNCE TIMING
toc25
toc26
toc27
CTIA 1kΩ
VSLEEVE
0V
VSLEEVE
0V
2V/div
5V/div
2V/div
5V/div
VDETIN
1V/div
5V/div
VINT
VSCL
VSCL
CTIA, VBOOST = 5V
CTIA, VBOOST = 5V
MIC_OUT 2.2kΩ PULL UP TO 2.8V
MIC_OUT 2.2kΩ PULL UP TO 2.8V
200ms/div
100µs/div
100µs/div
SLEEVE DISCHARGE TIME
VBOOST OVP
toc28
toc29
VSLEEVE
VBOOST
1V/div
5V/div
5V/div
5V/div
0V
VSLEEVE
0V
VDETIN
CTIA, DETIN 0 TO 1
MIC_OUT 2.2kΩ PULL UP TO 2.8V
BYPASS ON, RSEN = 6.8Ω
100µs/div
4µs/div
PLC COMMUNICATION
(SLEEVE) RX
PLC COMMUNICATION
(SLEEVE) TX
toc30
toc31
VSLEEVE
1V/div
VSLEEVE
1V/div
0V
0V
MAX20317 RECEIVE
200µs/div
MAX20317 TRANSMIT
200µs/div
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MAX20317
Universal 3.5mmØ Accessory Management IC
Bump Configuration
TOP VIEW
(BUMP SIDE DOWN)
MAX20317
1
2
3
4
5
+
SLEEVE
DETIN
RSEN
A
B
C
D
V
V
CC
BOOST
RING2
GND
GND
GND
SDA
DGND
MIC_
OUT
G_SNSL
G_SNSR
SCL
RING2
_SL
RING2
_SR
SLEEVE
_SL
SLEEVE
_SR
INT
WLP
(2.05mm x 1.65mm)
Bump Descriptions
BUMP
NAME
FUNCTION
A1
SLEEVE
Jack Sleeve Pin Contact
Jack Insertion Detection Input. An internal comparator monitors DETIN for jack insertion/
removal events.
A2
A3
A4
DETIN
RSEN
RSEN connection for Bypass mode
Supply Voltage Input for Bypass Mode. Bypass V
capacitor as close as possible to the device.
to ground with a 1µF ceramic
BOOST
V
BOOST
Supply Voltage Input. Bypass V
as close as possible to the device.
to ground with a 1µF decoupling capacitor
CC
A5
V
CC
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MAX20317
Universal 3.5mmØ Accessory Management IC
Bump Descriptions (continued)
BUMP
NAME
RING2
GND
FUNCTION
B1
Jack Ring2 Pin Connection
B2, B3, B4
B5
Ground. Connect all GND and DGND pins together.
Digital Ground. Connect all GND and DGND pins together.
Microphone to Phone Codec Output
DGND
C1
MIC_OUT
Left Ground Reference Sense. G_SNSL is a ground reference prior to the ground switch
to obtain a high ground isolation for the audio codec.
C2
C3
G_SNSL
G_SNSR
Right Ground Reference Sense. G_SNSL is a ground reference prior to the ground switch
to obtain a high ground isolation for the audio codec.
2
C4
C5
D1
D2
D3
D4
D5
SDA
SCL
I C Data Line
2
I C Clock
SLEEVE_SL
RING2_SL
SLEEVE_SR
RING2_SR
INT
Jack Sleeve Kelvin Pin Contact for Left Audio Line
Jack Ring2 Kelvin Pin Contact for Left Audio Line
Jack Sleeve Kelvin Pin Contact for Right Audio Line
Jack Ring2 Kelvin Pin Contact for Right Audio Line
2
I C Active-Low, Open-Drain Interrupt Output. Connect INT to an external pullup resistor.
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MAX20317
Universal 3.5mmØ Accessory Management IC
Block Diagram
V
V
SYS
+5V
6.8Ω
1µF
1µF
RSEN
RSEN
V
V
BOOST
CC
V
RSEN
HIGH PSRR
INTERNAL SUPPLY
V
V
BOOST
ANC BUTTON
DETECTION
V
BST_FT
ADC2
MAX20317
ANC
V
(τB=S1Tm_FsT)
DETECTION
GAIN CONTROL
BYPASS_SW
PLC
SCL
SDA
MIC_OUT
INT
MIC_SW
JACK
CONTROL
2
I C
SLEEVE
RING2
I
PLC
PLC
DGND
GND
GND_SW
DEBOUNCE
SLEEVE_SL
SLEEVE_SR
COM_THRS[1:0]
x V
BOOST
V
MIC
RING2_SL
RING2_SR
V
IDETIN
ADC1
G_SNSL
G_SNSR
V
CC
0.5V
CC
DETIN
DENOTES OMTP CONFIGURATION
DENOTES CTIA CONFIGURATION
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MAX20317
Universal 3.5mmØ Accessory Management IC
the headset microphone. The full system flowchart is
shown in Figure 1, while Figure 2 details the jack detection
process when a headset is connected.
Detailed Description
The MAX20317 supports both CTIA and OMTP headsets.
The advanced method used to detect the headset type
provides error free connections to ground and the microphone
line. Manual control allows for future expansion of accessory
types and functions.
Impedance Detection
When the MAX20317 detects the presence of a headset,
it can measure the headset impedance. DETIN applies a
In addition to detecting the jack configuration, the
MAX20317 also reliably detects ANC headsets and head-
set button press events. A built-in, low offset 8-bit ADC
provides a precise method of detecting an ANC headset
and button presses in ANC music mode. These functions
are handled automatically by the device, but can also be
controlled manually.
current, I
, to the left channel of the 3.5mm jack and
DETIN
reads the resulting DC voltage with ADC1. This measurement
occurs automatically when DET goes low after a DETIN
debounce period or triggers manually upon receipt of an
2
I C command while DET = 0. The start condition is set
with ADC_CTRL[1:0] (0x0A[3:2]).
Automatic impedance measurements begin when a head-
set insertion event forces DET low. The MIC and GND
switches close in a CTIA configuration. If the OPEN_
For both ANC and normal headsets, the MAX20317
measures the impedance of the speaker. High precision
current sources and an 8-bit ADC permit high accuracy
sensing of low impedance headsets, even distinguishing
between 16Ω and 32Ω speakers. This is useful in dynamic
volume scaling applications.
DETECT bit (0x09[4]) is HIGH, I
is set to 100µA for
DETIN
a high-impedance measurement. If the voltage measured
by ADC1 is less than the value saved in HIHS_VAL
(register 0x0E), or if OPEN_DETECT is low, a low impedance
measurement is performed with I
= 1.1mA. If the
DETIN
The MAX20317 features power-line communication (PLC)
for accessories powered by the microphone line. Data
transmits above audio frequencies to prevent interference
with the audio signal to the headset. This permits
accessories to communicate with the device while a
system is in music mode.
voltage is still too low, the low-impedance measurement
is repeated with I = 5.5mA. This automatic process
DETIN
is illustrated in Figure 3.
Alternatively, the MAX20317 can measure impedance
2
only upon receipt of an I C command. Setting ADC1_
CTRL[1:0] to 01 or 10 causes the impedance measurement
to trigger when FORCE_ADC1_START (0x0B[1]) goes
After the startup process is complete and the DEVICE_
READY bit (0x03[2]) is set, the MAX20317 enters normal
operation. During this stage, an external controller and
CODEC can confirm the jack type, either 3P or 4P, to
enable or disable a MIC bias, detect the presence of an
ANC headset, and communicate with accessories or use
high. The I
value for manual impedance measurements
DETIN
is set by SET_IDET[1:0] (0x0B[5:4]). After an automatic
measurement, SET_IDET[1:0] equals the last I
DETIN
value used in the impedance check, but it can be forced
to any value for manual tests.
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MAX20317
Universal 3.5mmØ Accessory Management IC
START
RESET
NO
DET = 0?
NO ACCESSORY
YES
SEND DET INTERRUPT
ANC MODE
MIC BYPASS = AUTO
VBOOST BYPASS ON
AD2 ENABLE BUTTON
DET MODE
RUN AUTOMATIC
JACK
CONFIGURATION?
AUTOMATIC JACK
DETECTION
SEE FIGURE 2
YES
ANC MODE
NO
CHECK ANC
MIC BYPASS OFF
APPLY +5V TO VBOOST
BOOST BYPASS ON
ADC2 READ
APPLY MIC BIAS
CHECK MPSs = 1
OR EXTERNAL
3P CHECK
ANC CALL MODE
YES
NO
CALL MODE?
BYPASS OFF
MIC BIAS ON
YES
ANC HEADSET
DETECTED?
NO
NO
YES
JACK REMOVAL
DET = 1?
YES
NO
3P MODE
4P MODE
ANC MUSIC MODE
VCONN BYPASS ON
DATA TRANSFER TO
ACCESSORY
DEVICE = 4P HEADSET
MIC BIAS ON
KEY DETECTION
MIC BIAS OFF
DEVICE = 3P HEADSET
NO
YES
NO
YES
JACK REMOVAL
DET = 1?
KEY PRESS?
COM_DET = 1
JACK REMOVAL
DET = 1?
ANC CHECK?
YES
NO
READ ADC2 FOR
SEND/END,
VOLUME UP, AND
VOLUME DOWN
NO
YES
JACK REMOVAL
DET_I = 1?
YES
Figure 1. Full operation of the MAX20317
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MAX20317
Universal 3.5mmØ Accessory Management IC
START
ADC1 AUTOMATIC
IMPEDANCE DETECTION
NO
JACK_TYP_CHK_DIS
YES
MIC/GND MUX = CTIA
REPORT OPEN IF
SET_IDET = 1 AND
OPEN_CABLE = 1
CHECK
IMPEDANCE FOR
OMTP ?
REPEAT ADC1
IMPEDANCE DETECTION
IDETIN = 100µA OR 1.1mA
HEADSET
IMPEDANCE LOWER
THAN THRESHOLD?
NO
YES
MIC/GND SWITCH =
OMTP
YES
NO
DEVICE READY
MIC/GND MUX CAN BE
CONFIGURED MANUALY
Figure 2. Automatic Jack Detection
START
NO
OPEN_DETECT
= 1?
YES
SET_IDET[1:0] = 01
I
= 100µA
DETIN
RUN IMPEDANCE
DETECTION
RUN LOW IMPEDANCE DECTION
(1.1mA FIRST, 5.5mA IF BELOW
THRESHOLD)
YES
NO
ADC1 >
HIHS_VAL[7:0]
ADC1_LI_CHK = 1?
YES
NO
END
Figure 3. ADC1 Automatic Impedance Detection
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MAX20317
Universal 3.5mmØ Accessory Management IC
CTIA/OMTP Detection
Microphone Short Protection
The impedance measurement process is also used
to identify a jack as CTIA or OMTP. When JACK_
TYP_CHK_DIS = 0 (0x0A[6]), CTIA/OMTP detection
begins after an automatic impedance measurement. This
Overcurrent protection on RSEN protects the MAX20317
from drawing too much current through the sense resistor.
When the voltage drop across the sense resistor exceeds
V
for longer than the time set in tSHO_DEB[1:0]
SH
second measurement keeps the last value of I
,
(0x0D[1:0]), the MPSs bit (0x04[4]) is set and triggers an
interrupt. The MAX20317 exits bypass mode and resets
BYPASS to “0.” The device also exits bypass mode if an
DETIN
either 100µA or 1.1mA, and measures the L-channel
impedance with the MIC and GND MUX switches closed
in OMTP mode. If the voltage measured by ADC1 is less
than the threshold defined in OMTP_VAL (register 0x0F)
when testing a low-impedance headset, or HIHS_VAL
for high-impedance headsets, the MIC and GND MUX
switches remain configured for OMTP. Otherwise, the
switches connect in the CTIA configuration. Automatic
jack detection is disabled when ADC1 is controlled
manually or when JACK_TYP_CHK_DIS = 1 and the MIC
and GND switches must be set by FORCE_MG_SW[1:0]
(0x09[1:0]) and MANUAL_MG_SW (0x09[5]).
overvoltage condition occurs on V
.
BOOST
Power Line Communication
A
one-wire accessory Power-Line-Communication
Protocol (PLC) enables communication between a
master device and a single accessory device over the
microphone power line. The protocol allows the master
to configure, control, and read the status of the attached
accessory. When the accessory is powered, power line
communication takes place over the microphone using
biphase mark code (BMC).
Open Cable Check
The PLC can be implemented on any single power
line between two devices. Error checking, including
parity and checksum, is included in the protocol to
validate all data transferred between devices. The protocol
is defined by a physical layer, which describes the physical
communication protocol, and the logical layer that
includes high-level commands and handshakes. Figure 4
and Figure 5 show the process of sending and receiving
PLC data, respectively. The MAX20317 supports physical
data transfer between the master device and slave acces-
sory. The meaning of the data contained in each individual
accessory must be defined by the manufacturer of the
master device.
If OPEN_DETECT = 1 (0x09[4], the MAX20317 performs
an open cable check after determining the jack type. If a
high-impedance measurement exceeds the HIHS_VAL
threshold, the cable is considered open and the OPEN_
CABLE flag (0x03[4]) is set. This feature helps ensure
that a there is a clean connection to a real headset when
DET goes LOW after the DETIN debounce period.
ANC Headset Detection
The MAX20317 identifies ANC headsets by measuring
the current drawn through an external resistor connected
to RSEN. If there is +5V present on V , an automatic
BOOST
measurement launches when the bypass switch closes.
An internal, high-gain differential amplifier measures the
current through the sense resistor and is read by ADC2.
If the current is higher than HSDET_VAL (register 0x10),
the headset is considered to be ANC and the ANC_HS bit
(0x05[7]) is set. ANC headset detection is only compatible
with CTIA headsets.
SLEEVE and RING2 Ground Sense
Because audio systems require high levels of isolation
between audio channels, the MAX20317 incorporates
separate ground sense connections for SLEEVE and
RING2. These ground sense contacts provide channel
isolation with a Kelvin contact, especially when an
EMC filter is included between the 3.5mm jack and the
MAX20317. Individual left- and right-channel ground
sense outputs provide separate return paths for SLEEVE
and RING2.
ANC Current Sense
The MAX20317 automatically detectsANC button presses
while in BYPASS mode through the current sense resis-
tor. When a button is pressed, the microphone voltage
drops, triggering a COM_DET interrupt. This also triggers
an automatic ADC2 conversion. The ADC2 conversion
continues as long as the microphone voltage is below the
COM_DET threshold set by COM_THRS[1:0] (0x08[1:0]).
2
I C Interface
The MAX20317 uses the two-wire I C interface to
2
communicate with a host application processor. The
configuration settings and status information provided
through this interface are detailed in the register descrip-
tions (Tables 2 – 31). MAX20317 uses the seven-bit slave
address 0b0010101 (0x2A for writes, 0x2B for reads).
Pop-Up Noise Suppression
In order to prevent any pop-up noise, SLEEVE and RING2
are discharged immediately after a headset is unplugged.
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MAX20317
Universal 3.5mmØ Accessory Management IC
START
NO
SEND_CMD = 1?
YES
BUTTON OR
NO
INCOMING DATA
CONFLICT?
START PREAMBLE
YES
TRANSMITTING
POSTAMBLE?
NO
BUTTON OR
INCOMING DATA
CONFLICT?
BUTTON OR
INCOMING DATA
CONFLICT?
YES
NO
SEND DATA
NO
ABORT TRANSIMSSION
REPORT TX FAILURE
NO
END OF
POSTAMBLE?
CLEAR SEND_CMD
TX END
YES
TRANSMISSION
STOPPED
TX SUCCESSFUL
CLEAR SEND_CMD
TX END
Figure 4. PLC TX Process
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MAX20317
Universal 3.5mmØ Accessory Management IC
START
NO
BYPASS MODE?
YES
NO
PREAMBLE
DETECTED?
SET PLC_RX_DET = 1
YES
DATA
CORRUPTED?
NO
NO
POSTAMBLE
DETECTED?
KEEP RECEIVING DATA
RX ERROR
NEW_DATA = 1
RX END
Figure 5. PLC RX Process
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MAX20317
Universal 3.5mmØ Accessory Management IC
SDA. The SCL line operates only as an input. A pullup
resistor is required on SCL if there are multiple masters
on the 2-wire interface, or if the master in a single-master
system has an open drain SCL output. Each transmission
consists of a START condition sent by a master, followed
by the MAX20317 7-bit slave address plus R/W bit, a
register address byte, one or more data bytes, and finally
a STOP condition.
Applications Information
2
I C Serial Interface
2
The I C serial interface is used to configure the device.
2
Figure 6 shows the I C timing diagram.
Serial Addressing
2
When in I C mode, the device operates as a slave
2
device that sends and receives data through an I C-
Start and Stop Conditions
compatible 2-wire interface. The interface uses a seri-
al data line (SDA) and a serial-clock line (SCL) to
achieve bidirectional communication between master(s)
and slave(s). A master (typically a microcontroller) initi-
ates all data transfers to and from the MAX20317 and
generates the SCL clock that synchronizes the data
transfer. The SDA line operates as both an input and
an open drain output. A pullup resistor is required on
Both SCL and SDA remain high when the interface is not
busy. A master signals the beginning of a transmission
with a START (S) condition by transitioning SDA from high
to low while SCL is high (Figure 7). When the master has
finished communicating with the slave, it issues a STOP
(P) condition by transitioning SDA from low to high while
SCL is high. The bus is then free for another transmission.
SDA
t
BUF
t
F
t
SP
t
HD:STA
t
LOW
SCL
t
HIGH
SPIKE
SUPPRESSION
t
SU:STA
t
t
R
HD:STA
t
SU:STO
t
t
SU:DAT
HD:DAT
STOP
START
REPEATED
START
NOTE: TIMING IS REFERENCED TO V
IL(MAX)
AND V
.
IH(MIN)
2
Figure 6. I C Timing Diagram
SDA
SCL
P
S
STOP
CONDITION
START
CONDITION
Figure 7. Start and Stop Conditions
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MAX20317
Universal 3.5mmØ Accessory Management IC
Bit Transfer
Slave Address
One data bit is transferred during each clock pulse
(Figure 8). The data on SDA must remain stable while
SCL is high.
The device has a 7-bit slave address. The bit following
a 7-bit slave address is the R/W bit, which is low for a
write command and high for a read command. The slave
address for the device is 0b00101011 for read commands
and 0b00101010 for write commands. This is summarized
in Table 1.
Acknowledge
The acknowledge bit is a clocked 9th bit (Figure 9), which
the recipient uses to handshake receipt of each byte of
data. Thus, each byte transferred effectively requires 9
bits. The master generates the 9th clock pulse, and the
recipient pulls down SDA during the acknowledge clock
pulse. The SDA line is stable low during the high period
of the clock pulse. When the master is transmitting to the
MAX20317, it generates the acknowledge bit because the
device is the recipient. When the device is transmitting
to the master, the master generates the acknowledge bit
because the master is the recipient. If the device does not
pull SDA low, a not acknowledge is indicated.
2
Table 1. I C Slave Addresses
VALUE
ADDRESS FORMAT
HEX
0x15
0x2A
0x2B
BINARY
001 0101
0010 1010
0010 1011
7-BIT SLAVE ADDRESS
WRITE ADDRESS
READ ADDRESS
SDA
SCL
DATA LINE STABLE;
DATA VALID
CHANGE OF DATA
ALLOWED
Figure 8. Bit Transfer
START
CONDITION
CLOCK PULSE FOR
ACKNOWLEDGE
1
2
8
9
SCL
SDA
BY
TRANSMITTER
SDA
BY
RECEIVER
S
Figure 9. Acknowledge
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MAX20317
Universal 3.5mmØ Accessory Management IC
data bytes go into subsequent registers (Figure 10). If
multiple data bytes are transmitted before a STOP condition,
these bytes are stored in subsequent registers because the
register addresses auto-increments (Figure 11).
Bus Reset
2
The MAX20317 resets the bus with the I C start condition
for reads. When the R/W bit is set to 1, the MAX20317
transmits data to the master, thus the master is reading
from the device.
Format for Reading
The MAX20317 is read using the internally stored register
address as an address pointer, the same way the stored
register address is used as an address pointer for a write.
The pointer auto-increments after each data byte is read
using the same rules as for a write. Thus, a read is initiated
by first configuring the register address by performing a
write (Figure 12). The master can now read consecutive
bytes from the device, with the first data byte being read
from the register addressed pointed by the previously written
register address (Figure 13). Once the master sends a
NACK, the MAX20317 stop sending valid data.
Format for Writing
A write to the MAX20317 comprises the transmission of
the slave address with the R/W bit set to zero, followed
by at least 1 byte of information. The first byte of information
is the register address or command byte. The register
address determines which register of the device is to
be written by the next byte, if received. If a STOP (P)
condition is detected after the register address is received,
then the device takes no further action beyond storing
the register address. Any bytes received after the register
address are data bytes. The first data byte goes into the
register selected by the register address and subsequent
ADDRESS = 0x2A
REGISTER ADDRESS = 0x01
0 = WRITE
S
0
0
1
0
1
0
1
0
A
0
0
0
0
0
0
0
1
A
REGISTER 0x01 WRITE DATA
S = START BIT
P = STOP BIT
A = ACK
d7
d6
d5
d4
d3
d2
d1
d0
A
P
N = NACK
d_ = DATA BIT
2
Figure 10. Format for I C Write
ADDRESS = 0x2A
REGISTER ADDRESS = 0x01
0 = WRITE
S
0
0
1
0
1
0
1
0
A
0
0
0
0
0
0
0
1
A
REGISTER 0x02 WRITE DATA
REGISTER 0x01 WRITE DATA
d7
d6
d5
d4
d3
d2
d1
d0
A
A/N
d7
d6
d5
d4
d3
d2
d1
d0
P
Figure 11. Format for Writing to Multiple Registers
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MAX20317
Universal 3.5mmØ Accessory Management IC
0 = WRITE
REGISTER ADDRESS = 0x01
ADDRESS = 0x2A
S
0
0
0
0
1
1
0
1
0
0
1
1
0
A
A
0
0
0
0
0
0
0
1
A/N
A/N
1 = READ
ADDRESS = 0x2B
REGISTER 0x01 READ DATA
Sr
0
1
1
d7
d6
d5
d4
d3
d2
d1
d0
P
Figure 12. Format for Reads (Repeated Start)
0 = WRITE
REGISTER ADDRESS = 0x01
ADDRESS = 0x2A
S
Sr
d7
0
0
0
0
1
1
0
1
0
0
1
1
0
A
A
0
d7
d7
0
d6
d6
0
0
0
0
0
d1
d1
1
d0
d0
A/N
1 = READ
ADDRESS = 0x2B
REGISTER 0x01 READ DATA
A
0
1
1
d5
d4
d3
d2
REGISTER 0x02 READ DATA
REGISTER 0x03 READ DATA
A
A/N
d6
d5
d4
d3
d2
d1
d0
d5
d4
d3
d2
P
Figure 13. Format for Reading Multiple Registers
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MAX20317
Universal 3.5mmØ Accessory Management IC
Transmission Format
Power Line Communication
Physical Structure
In biphase mark code, high and low bits are defined by
state transitions. In the MAX20317, the PLC code com-
prises a time unit and the low and high states of the MIC
A valid PLC packet comprises a preamble, two data
bytes, checksum, and postamble. The preamble is eight
consecutive 1 bits. After a successful preamble, data
transfer takes place until an error condition occurs or the
end of transmission is reached.
line. The time unit, t
defines the interval of time in
UNIT
Each byte of data begins with a 0 bit to indicate the start
condition followed by one byte of data. A parity and stop
bit are transmitted at the end of each byte. The stop bit is
always 1. If parity is disabled, a parity bit of 1 will be sent,
but ignored by the device.
which a bit is determined to be either 0 or 1. By default,
= 24µs, but setting the FREQ bit (0x18[4]) HIGH
t
UNIT
increases t
to 30µs. A bit is considered 0 if no MIC
UNIT
state transition occurs during t
. If there is a state
UNIT
change, either high to low or low to high, the bit is 1.
Following the data bytes, a checksum is transmitted.
The checksum is generated as NOT(DATA1 + DATA2).
Transmission will end with the checksum unless the postam-
ble is enabled. The postamble transmits 0 for a duration of
50ms. A typical data packet is shown in Figure 15.
When the MIC line is above the V threshold, a
low state is recorded. Conversely, a high state is recorded
COM_DET
when the MIC line is below the V threshold. For
COM_DET
example, MIC line transitions and their corresponding
logic values and BMC bits are shown in Figure 14.
VOLTAGE
V
CC
MIC LINE
V
COM_DET
GND
TIME
DIGITIZED
VALUE
HI LO HI
LO
0
HI LO HI
BMC
1
0
0
1
Figure 14. Determination of PLC Data Bit
START
0
PARITY STOP
1
0
1
0
1
1
0
0
1
1
CHECK
SUM
POSTAMBLE: 2000 BITS
OF ‘0’
DATA2
PREAMBLE: 8 BITS OF ‘1’
DATA1
Figure 15. Sample PLC Data Packet
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MAX20317
Universal 3.5mmØ Accessory Management IC
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MAX20317
Universal 3.5mmØ Accessory Management IC
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MAX20317
Universal 3.5mmØ Accessory Management IC
Table 2. DEVICE_ID Register (0x00)
ADDRESS
MODE
BIT
0x00
Read Only
7
6
0
5
4
1
3
0
2
1
0
0
0
NAME
RESET
CHIP_ID[3:0]
CHIP_REV[3:0]
0
0
0
CHIP_ID
Chip ID
[3:0]
Shows information about the version of MAX20317
CHIP_REV
Chip Revision
[3:0]
Shows information about the revision of MAX20317
Table 3. ADC1_VAL Register (0x01)
ADDRESS
MODE
BIT
0x01
Read Only
7
6
0
5
0
4
0
3
ADC1_VAL[7:0]
0
2
0
1
0
0
0
NAME
RESET
0
ADC1_VAL
[7:0]
ADC1 Value
Read only register for the latest ADC1 conversion (8-bit resolution)
Table 4. ADC2_VAL Register (0x02)
ADDRESS
MODE
BIT
0x02
Read Only
7
6
0
5
0
4
0
3
ADC2_VAL[7:0]
0
2
0
1
0
0
0
NAME
RESET
0
ADC2_VAL
[7:0]
ADC2 Value
Read only register for the latest ADC2 conversion (8-bit resolution)
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Universal 3.5mmØ Accessory Management IC
Table 5. STATUS1 Register (0x03)
ADDRESS
MODE
BIT
0x03
Read Only
7
6
5
4
3
2
1
EOC1
0
0
EOC2
0
OPEN_
CABLE
JACK_
TYPE
DEVICE_
RDY
NAME
IDET_LVL[1:0]
COM_DET
0
RESET
0
0
0
0
0
I
Level
DETIN
Shows the last I
current level used in an ADC1 Impedance Detection
DETIN
IDET_LVL
[1:0]
00 = No Jack Insertion Default
01 = 100µA
10 = 1.1mA
11 = 5.5mA
Communication Request Status
Indicates a valid button press when MIC_IN drops below the threshold set by COM_THRS[1:0]
0 = No communication is requested.
COM_DET
1 = MIC voltage is below threshold after the debounce time.
Open Cable Detected
OPEN_
CABLE
Indicates if a cable is an open connection
0 = Cable is not open
1 = High impedance is detected for both CTIA and OMTP, and SET_IDET[1:0] = 01.
Jack Type
Shows the jack type identified by automatic jack detection.
This feature is disabled if JACK_TYP_CHK_DIS = 1. 0x0B).
0 = CTIA (L-R-G-M)
JACK_
TYPE
1 = OMTP (L-R-M-G)
Device Ready
Indicates the device is ready for manual control after jack detection is complete. This bit is set after impedance
detection if JACK_TYP_CHK_DIS = 1.
0 = MIC/GND switch position has NOT been finalized.
DEVICE_
RDY
1 = MIC/GND SW position is set. Device is ready.
End of ADC1 conversion
EOC1
EOC2
0 = ADC1 conversion is not started or is in progress.
1 = ADC1 conversion is complete and the result is available in ADC1_VAL (register 0x01).
End of ADC2 conversion
0 = ADC2 conversion is not started or is in progress.
1 = ADC2 conversion is complete and the result is available in ADC2_VAL (register 0x02).
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Universal 3.5mmØ Accessory Management IC
Table 6. STATUS2 Register (0x04)
ADDRESS
MODE
BIT
0x04
Read Only
7
6
5
4
MPSs
0
3
MIC_IN
0
2
SWD
0
1
DET
0
0
DETIN
0
VBOOST_
OV
NAME
VOL_UP
0
VOL_DWN
0
RESET
0
Volume Up Status
Indicates a volume up press was detected in BYPASS mode. ADC2
Cleared if bypass switch is open or VMIC > COM_THRS[1:0].
Updated in bypass mode with low gain.
VOL_UP
0 = No volume up press detected. NOT (VOL1_TH < ADC2 < VOL2_TH)
1 = Volume up press detected VOL1_TH < ADC2 < VOL2_TH
Indicates a volume down press was detected in BYPASS mode. VOL2_TH < ADC2 < VOL3_TH
Cleared if bypass switch is open or VMIC > COM_THRS[1:0].
Updated in bypass mode with low gain.
VOL_
DWN
Updated in bypass mode with low gain.
0 = No Volume down pressed. NOT (VOL2_TH < ADC2 < VOL3_TH)
1 = Volume down pressed. VOL2_TH < ADC2 < VOL3_TH
V
0 = V
Bypass Mode Overvoltage Status
BOOST
VBOOST_
OV
operating normally
BOOST
1 = Overvoltage detected on V
in Bypass Mode
BOOST
RSEN Overcurrent Status
MPSs
0 = Current Protection is NOT detected.
1 = Current Protection is Triggered.
MIC_IN Switch Status
MIC_IN
0 = MIC_IN switch is open
1 = MIC_IN switch is closed
SEND/END Status
Indicates a SEND/END press was detected in BYPASS mode. VOL0_TH< ADC2 <VOL1_TH
Cleared if bypass switch is open or VMIC > COM_THRS[1:0]. Updated in bypass mode with low gain.
0 = No SEND/END press detected. NOT(VOL0_TH< ADC2 <VOL1_TH)
1 = SEND/END press detected. VOL0_TH< ADC2 <VOL1_TH
SWD
Jack Insertion Debounce
DET
0 = Jack was detected after debounce
1 = No jack detected
DETIN Detection
DETIN
0 = DETIN is detected
1 = DETIN is not detected
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Universal 3.5mmØ Accessory Management IC
Table 7. STATUS3 Register (0x05)
ADDRESS
MODE
BIT
0x05
Read Only
7
ANC_HS
0
6
THT_CMP
0
5
SAR_CMP
0
4
V94_CMP
0
3
0
2
RFU[2:0]
0
1
0
0
VOL_RFU
0
NAME
RESET
ANC Headset Detection
ANC_HS
0 = No ANC headset detected. VRSEN < HSDET_VAL[7:0]
1 = ANC headset detected. VRSEN > HSDET_VAL[7:0]
Thermal Comparator Status
Output of the analog thermal comparator
THT_CMP
SAR Comparator Status
Output of the analog SAR comparator
SAR_CMP
V94 Comparator Status
Output of the COM_THRS comparator.
V94_CMP
RFU[2:0]
Reserved for future use
Button Press Reserved for Future Use Only.
Cleared if bypass is open or VMIC > COM_THRS[1:0]. Updated in BYPASS mode,
ADC2 value (VRSEN) with low gain.
VOL_RFU
0 = No RFU Button pressed. NOT (VOL3_TH < ADC2)
1 = RFU Button pressed. VOL3_TH < ADC2
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Table 8. IRQ Register (0x06)
ADDRESS
MODE
BIT
0x06
Clear On Read
7
6
EOCi
0
5
4
3
MIC_INi
0
2
1
DETi
0
0
DETINi
0
MPS/
VBOOST_
OVi
DEVICE_
RDYi
NAME
RESET
SWDi
SWDi
0
COM_DETi
0
0
0
SEND/END Button Press Detection Interrupt
0 = Interrupt not occurred
1 = Interrupt occurred (both edges of SWD)
End of ADC1/2 Conversion Interrupt
0 = Interrupt not occurred
EOCi
1 = Interrupt occurred (only the rising edge of either EOC1 or EOC2)
Communication Request Interrupt (Button Press) in Bypass Mode
0 = Interrupt not occurred
COM_DETi
1 = Interrupt occurred (both edges of COM_DET, that is button pressed or released)
MPS/
VBOOST_
OVi
Microphone line short or Vboost overvoltage interrupt
0 = Interrupt not occurred
1 = Interrupt occurred (only rising edge of either MPS or VBOOST_OV)
MIC_IN Switch Open or Close Interrupt
0 = Interrupt not occurred
MIC_INi
1 = Interrupt occurred (both edges of MIC_IN)
DEVICE_RDY MIC/GND Switch position finalized Interrupt
0 = Interrupt not occurred
1 = Interrupt occurred (only rising edge of DEVICE_READY)
DEVICE_
RDYi
Jack Insertion and Removal Detection Interrupt
0 = Interrupt not occurred
DETi
1 = Interrupt occurred (both edges of debounced DETIN)
DETIN Detection Interrupt
0 = Interrupt not occurred
1 = Interrupt occurred
DETINi
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Universal 3.5mmØ Accessory Management IC
Table 9. MASK Register (0x07)
ADDRESS
MODE
BIT
0x07
Read/Write
7
6
EOCm
0
5
4
3
MIC_INm
0
2
1
DETm
0
0
DETINm
0
MPS/
VBOOST_
OVm
COM_
DETm
DEVICE_
RDYm
NAME
RESET
SWDm
SWDm
0
0
0
0
SEND/END Button Press Detection Interrupt Mask
0 = Masked
1 = Not masked
End of ADC Conversion Interrupt Mask
0 = Masked
EOCm
1 = Not masked
Communication Request Interrupt Mask
0 = Masked
1 = Not masked
COM_
DETm
MPS/
Microphone Line Short/VBOOST_OV Interrupt Mask
VBOOST_
OVm
0 = Masked
1 = Not masked
MIC_IN Switch Interrupt Mask
0 = Masked
MICINm
1 = Not masked
Device Ready Interrupt Mask
0 = Masked
1 = Not masked
DEVICE_
RDYm
Jack Insertion Detection Interrupt Mask
0 = Masked
DETm
1 = Not masked
DETIN Detection Interrupt Mask
0 = Masked
DETINm
1 = Not masked
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Table 10. CONTROL1 Register (0x08)
ADDRESS
MODE
BIT
0x08
Read/Write
7
6
5
4
3
RFU
0
2
BYPASS
0
1
0
DET_
DEBOUNCE
DETIN_
OVERRIDE
MIC_OUT
DELAY
NAME
RFU
0
COM_THRS[1:0]
0** 1**
RESET
0**
0**
1**
RFU
Reserved For Future Use
DET Debounce Time
0 = 115ms,
1 = 300ms
DET_
DEBOUNCE
DETIN Override
0 = No effect
1 = Simulates a jack insertion.
DETIN_
OVERRIDE
MIC_OUT Output Delay Control
0 = MIC SW close output follows after DET becomes low
1 = MIC SW close delayed until Impedance detection after DET becomes low
MIC_OUT_
DELAY
RFU
Reserved For Future Use
BYPASS MODE Enable
0 = BYPASS is OFF
1 = BYPASS is ON
BYPASS
COM (Button Press) Detection Threshold
00 = 88%
01 = 90%
10 = 92%
11 = 94%
COM_
THRS[1:0]
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Table 11. CONTROL2 Register (0x09)
ADDRESS
MODE
BIT
0x09
Read/Write
7
6
5
4
3
2
1
0
MANUAL_
G_SNS
MANUAL_
MIC_SW
MANUAL_
MG_SW
OPEN_
DETECT
FORCE_
G_SNS
FORCE_
MIC_SW
NAME
FORCE_MG_SW [1:0]
RESET
0
0
0
1
0
0
0
0
Manual G_SNS Switch Setting
0 = G_SNS operates normally in synch Mic/Ground switch
1 = G_SNS follows FORCE_G_SNS bit
MANUAL_
G_SNS
Manual MIC_IN Switch Setting
0 = MIC_SW operates normally
1 = MIC_SW follows FORCE_MIC_SW bit
MANUAL_
MIC_SW
Manual MG Switch Setting
0 = MG_SW operates normally
1 = MG_SW follows FORCE_MG_SW bit
MANUAL_
MG_SW
OPEN_
DETECT
When high, enables the first automatic impedance detection at 100uA.
FORCE_G_SNS Switch Control (effective only when “MANUAL_G_SNS = 1”)
0 = Close Ring2 to G_SNS pin
1 = Close Sleeve to G_SNS pin
FORCE_
G_SNS
Force MIC_IN Switch Control (effective only when “MANUAL_MIC_SW = 1”)
0 = MIC_SW closed
1 = MIC_SW open
FORCE_
MIC_SW
Force MIC/GND Switch Control (effective only when “MANUAL_MG_SW = 1”)
00 = Switches closed in CTIA position
01 = Both MIC-side switches OPEN, ground connection in CTIA position
10 = Switches closed in OMTP position
FORCE_
MG_
SW [1:0]
11 = Both MIC-side switches OPEN, ground connection in OMTP position
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Table 12. ADC CONTROL1 Register (0x0A)
ADDRESS
MODE
BIT
0x0A
Read/Write
7
6
5
RFU
0
4
3
2
1
0
IDET_
FLAT
JACK_TYP
_CHK_DIS
ADC1_LI
_CHK
NAME
ADC1_CTL [1:0]
ADC2_CTL [1:0]
RESET
0**
0**
1
1
1
1
1
Flat top period of the IDET for ADC conversion (OTP programmable)
IDET_FLAT
0 = 10msec
1 = 100msec
JACK_
TYP_CHK_
DIS
CTIA/OMTP Jack Type Detection Disable (OTP programmable)
0 = Automatic Jack Type Detection
1 = Disabled.
RFU
Reserved For Future Use
ADC1 Low Impedance Check
0 = Disable the 1.1mA/5.5mA impedance detection if ADC1 < HIHS_VAL
1 = Enable the 1.1mA/5.5mA impedance detection if ADC1 < HIHS_VAL
ADC1_
LI_CHK
ADC1 Conversion Control
00 = impedance detection and A-D conversion are always off.
01 = impedance detection is manual and one conversion when forced.
10 = impedance detection is manual and multiple (ADC1_AVG#) conversions and averaged.
11 = ADC follows FSM. (After DET = 0 transition)
ADC1_CTL
[1:0]
ADC2 Conversion Control
00 = impedance detection and A-D conversion are always off.
01 = impedance detection is manual and one conversion when forced.
10 = impedance detection is manual and multiple ( ADC2_AVG#) conversions and averaged.
11 = ADC2 follows FSM.
ADC2_CTL
[1:0]
If COM_DET = 0, set ADC2_HL_SET = 1, ADC2 one averaged conversion after tANC_DET from Bypass on =1.
ADC2_HL_SET = 0, While COM_DET = 1, ADC2 conversion continuous.
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Table 13. ADC2 CONTROL Register (0x0B)
ADDRESS
MODE
BIT
0x0B
Read/Write
7
6
5
4
0
3
RFU
0
2
ADC2_HL
0
1
0
FORCE_
ADC1_
START
FORCE_
ADC2_
START
NAME
RFU
SET_IDET[1:0]
RESET
0
0
0
0
0
RFU
Reserved For Future Use
Set I
DETIN
Set the I
current level in manual ADC1 mode. This should be used with Force_ADC1_START
DETIN
SET_IDET
[1:0]
00 = Do not use
01 = 100µA
10 = 1.1mA
11 = 5.5mA
RFU
Reserved For Future Use
ADC2 ANC Headset Detection Method Selection.
ADC2_HL
0 = ANC Comparator Low Gain; used for ANC Button detection
1 = ANC Comparator High Gain; used for ANC HS detection
Force ADC1 Start
FORCE_
ADC1_
START
Execute a manual ADC1 measurement when ADC1_CTL[1:0] = 01 or 10
0 = ADC1 operates normally
1 = ADC1 start (only one conversion). End of conversion set the EOC status set.
Force ADC2 Start
FORCE_
ADC2_
START
Execute a manual ADC2 measurement when ADC2_CTL[1:0] = 01 or 10
0 = ADC2 operates normally
1 = ADC2 start (only one conversion). End of conversion set the EOC status set.
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Table 14. Register (0x0C)
ADDRESS
MODE
BIT
0x0C
Read/Write
7
6
5
4
3
2
1
0
ADC1_AVG#
[1:0]
ADC2_AVG#
[1:0]
tANCDET_DEB
[1:0]
tANCBPD_DEB
[1:0]
NAME
RESET
0**
0**
0**
0**
0**
0**
0**
0**
ADC1 Averaging Number
Sets the number of samples to average when ADC1_CTL[1:0] = 10
ADC1_AVG
#[1:0]
00 = 2
01 = 4
10 = 8
11 = 16
ADC2 Averaging Number
Sets the number of samples to average when ADC2_CTL[1:0] = 10
ADC2_AVG
#[1:0]
00 = 2
01 = 4
10 = 8
11 = 16
ANC Headset Detection Debounce Time
00 = 20ms
01 = 30ms
10 = 50ms
11 = 100ms
tANCDET_
DEB [1:0]
ANC Button Press Detection Debounce Time
00 = 20ms
01 = 30ms
10 = 50ms
11 = 100ms
tANCBPD_
DEB [1:0]
Table 15. Short Current Control Register (0x0D)
ADDRESS
MODE
BIT
0x0D
Read/Write
7
6
5
4
3
2
1
0
NAME
RESET
FU [5:0]
FU[5:0]
tSHO_DEB[1:0]
0** 0**
0**
0**
0**
0**
0**
Factory Use Only. Do not overwrite
Short Circuit Debounce
Sets the debounce time for short-circuit current protection
tSHO_DEB
[1:0]
00 = 360µs
01 = 600µs
10 = 1080µs
11 = 1920µs
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Table 16. HIHS_VAL Register (0x0E)
ADDRESS
MODE
BIT
0x0E
Read/Write
7
6
0
5
0
4
0
3
HIHS_VAL[7:0]
0
2
0
1
0
0
0
NAME
RESET
0
HIHS_VAL
[7:0]
High impedance threshold for ADC1 conversions.
Table 17. OMTP_VAL Register (0x0F)
ADDRESS
MODE
BIT
0x0F
Read/Write
7
6
0
5
0
4
3
2
0
1
0
0
0
NAME
RESET
OMTP_VAL[7:0]
0 0
0
OMTP_VAL
[7:0]
OMTP Headset Detection Threshold for ADC1 conversion.
Table 18. HSDET_VAL Register (0x10)
ADDRESS
MODE
BIT
0x10
Read/Write
7
6
0
5
0
4
3
2
0
1
0
0
0
NAME
RESET
HSDET_VAL[7:0]
0
0
0
HSDET_
VAL[7:0]
ANC Headset Detection Threshold for ADC2 conversion when ADC_HL_SET = 1. If ADC2>HSDET_VAL,
then set ANC_HS (0x05h bit7) = 1.
Table 19. VOL0_TH Register (0x11)
ADDRESS
MODE
BIT
0x11
Read/Write
7
6
0
5
0
4
0
3
VOL0_TH[7:0]
0
2
0
1
0
0
0
NAME
RESET
0
VOL0_TH
[7:0]
Headset Button Detection Threshold in BYPASS mode for ADC2 conversion.
Higher than or equal to this value and lower than VOL1_TH[7:0] means the SEND/END button is pressed.
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Table 20. VOL1_TH Register (0x12)
ADDRESS
MODE
BIT
0x12
Read/Write
7
6
0
5
0
4
0
3
VOL1_TH[7:0]
0
2
0
1
0
0
0
NAME
RESET
0
VOL1_TH
[7:0]
Headset Button Detection Threshold in BYPASS mode for ADC2 conversion.
Higher than or equal to this value and lower than VOL2_TH means the Volume up button is pressed.
Table 21. VOL2_TH Register (0x13)
ADDRESS
MODE
BIT
0x13
Read/Write
7
6
0
5
0
4
0
3
VOL2_TH[7:0]
0
2
0
1
0
0
0
NAME
RESET
0
VOL2_TH
[7:0]
Headset Button Detection Threshold in BYPASS mode for ADC2 conversion.
Higher than or equal to this value and lower than VOL3_TH means the Volume down button is pressed.
Table 22. VOL3_TH Register (0x14)
ADDRESS
MODE
BIT
0x14
Read/Write
7
6
0
5
0
4
0
3
VOL3_TH[7:0]
0
2
0
1
0
0
0
NAME
RESET
0
VOL3_TH
[7:0]
Headset Button Detection Threshold in BYPASS mode for ADC2 conversion.
Higher than or equal to this value means the reserved button is pressed.
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Universal 3.5mmØ Accessory Management IC
Table 23. PLC_STAT: POWER LINE COMMUNICATION STATUS Register (0x15)
ADDRESS 0x15
MODE
BIT
Read Only
7
6
5
4
3
2
1
0
PLC_TX_
ERR
PLC_TX_
OK
PLC_RX_
ERR
NEW_
DATA
PLC_RX_
DET
NAME
RFU[1:0]
PLC_TX_P
0
RESET
0
0
0
0
0
0
0
RFU[1:0]
Reserved for Future Use
Power Line Communication TX Error
Cleared when a new SEND_CMD is issued.
0 = No TX Error
PLC_TX_
ERR
1 = TX Error
Power Line Communication TX Successful
Cleared when the new SEND_CMD issued.
0 = Communication not successful
1 = Communication successful
PLC_TX_
OK
Power Line Communication TX in Progress
PLC_TX_P 0 = Not Transmitting
1 = PLC Transmitting in progress
Power Line Communication RX Error
0 = No error
1 = Error (start bit, parity, checksum or stalled line).
PLC_RX_
ERR
New Data Available
NEW_
DATA
Indicates that new data is available. Once ACC_ID/ACC_DB1/ACC_DB2 are read, it is cleared.
0 = No New Data Set
1 = New Data Set Arrived
Power Line Communication Receiving Detection (only during preamble and data excluding post-amble)
0 = No PLC (within 4-bit length of no or invalid signal)
1 = PLC is ongoing (within 4-bit of preamble signal)
PLC_RX_
DET
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Universal 3.5mmØ Accessory Management IC
Table 24. PLC_IRQ: POWER LINE COMMUNICATION INTERRUPT Register (0x16)
ADDRESS 0x16
MODE
BIT
Read Only
7
6
5
4
3
2
1
0
PLC_TX_
ERRi
PLC_TX_
OKi
PLC_RX_
ERRi
NEW_
DATAi
PLC_RX_
DETi
NAME
RFU[1:0]
PLC_TX_Pi
0
RESET
0
0
0
0
0
0
0
RFU[1:0]
Reserved For Future Use
Power Line Communication TX Error Interrupt
0 = Interrupt Not occurred
1 = Interrupt occurred (rising edge of PLC_TX_ERR)
PLC_TX_
ERRi
Power Line Communication TX OK Interrupt
0 = Interrupt Not occurred
1 = Interrupt occurred (rising edge of PLC_TX_OK)
PLC_TX_
OKi
Power Line Communication TX in Progress Interrupt
0 = Interrupt Not occurred
1 = Interrupt occurred (both edges of PLC_TX_P)
PLC_TX_
Pi
Power Line Communication RX Error Interrupt
0 = Interrupt not occurred
1 = Interrupt occurred (rising edge of PLC_RX_ERR)
PLC_RX_
ERRi
New Data RX Interrupt.
0 = Interrupt Not occurred
1 = Interrupt occurred (rising edge of NEW_DATA)
NEW_
DATAi
Power Line Communication RX Detection Interrupt
0 = Interrupt Not occurred
1 = Interrupt occurred (both edges of PLC_RX_DET)
PLC_RX_
DETi
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Universal 3.5mmØ Accessory Management IC
Table 25. PLC_MASK: POWER LINE COMMUNICATION MASK Register (0x17)
ADDRESS 0x17
MODE
BIT
Read/Write
7
6
5
4
3
2
1
0
PLC_TX_
ERRm
PLC_TX_
OKm
PLC_TX_
Pm
PLC_RX_
ERRm
NEW_
DATAm
PLC_RX_
DETm
NAME
RFU[1:0]
RESET
0
0
0
0
0
0
0
0
RFU[1:0]
Reserved For Future Use
PLC TX Error Interrupt Mask.
0 = Masked
1 = Not masked
PLC_TX_
ERRM
PLC TX Successful Interrupt Mask.
0 = Masked
1 = Not masked
PLC_TX_
OKm
PLC TX in Progress Interrupt Mask.
0 = Masked
1 = Not masked
PLC_TX_
Pm
PLC_RX_ERR mask
0 = Masked
1 = Not masked
PLC_RX_
ERRm
New Data Interrupt Mask.
0 = Masked
1 = Not masked
NEW_
DATAm
Power Line Communication Receiving Detection Interrupt Mask.
0 = Masked
1 = Not masked
PLC_RX_
DETm
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Universal 3.5mmØ Accessory Management IC
Table 26. PLC_CON1: POWER LINE COMMUNICATION CONTROL Register (0x18)
ADDRESS 0x18
MODE
BIT
Read/Write
7
6
PLC_SINK
0
5
4
FREQ
0
3
0
2
1
1
RFU
0
0
POST_
AM_DIS
SEND_
CMD
NAME
RFU
0
PARITY[1:0]
RESET
0
0
RFU
Reserved for Future Use
PLC Current Sink Selection
0 = 100mA
PLC_SINK
1 = 80mA
Transmit Post-Amble Disable
POST_
0 = Post-amble enabled. The transmitter sends 2000 low bits. The receiver expects at least 16 low bits as a
AM_DIS
proper post-amble.
1 = Post-amble disabled
Communication Time Unit
0 = 24µsec
FREQ
1 = 30µsec
Parity Bit
PARITY
[1:0]
00/11 = No Parity. A high parity bit is transmitted, but is ignored by the receiver.
01 = Odd
10 = Even
RFU
Reserved for Future Use
Send Command
SEND_
CMD
Send the address (ACC_ADD) and data (ACC_DATA) bytes to the slave. Clears on completion of data transmission.
0 = No action
1 = Transfer the data
Table 27. ACCESSORY ID Register (0x19)
ADDRESS
MODE
BIT
0x19
Read Only
7
6
0
5
4
0
3
0
2
1
0
0
0
NAME
RESET
ACC_ID[3:0]
ACC_CAT[3:0]
0
0
0
ACC_ID
[3:0]
Accessory ID
Upper four bits of the first valid transmission. Four bit ID of the connected accessory.
ACC_CAT
[3:0]
Accessory Category
Lower four bits of the first valid transmission. Accessory category or revision information.
Maxim Integrated
│ 42
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MAX20317
Universal 3.5mmØ Accessory Management IC
Table 28. ACC_DATA1 Receive Register (0x1A)
ADDRESS
MODE
BIT
0x1A
Read Only
7
6
0
5
0
4
3
2
0
1
0
0
0
NAME
RESET
ACC_DATA1[7:0]
0 0
0
ACC_
Accessory Data 1
DATA1[7:0]
First byte of raw data read from accessory
Table 29. ACC_DATA2 Receive Register (0x1B)
ADDRESS
MODE
BIT
0x1B
Read Only
7
6
0
5
0
4
3
2
0
1
0
0
0
NAME
RESET
ACC_DATA2[7:0]
0
0
0
ACC_
Accessory Data 2
DATA2[7:0]
Second byte of raw data read from accessory
Table 30. ACC_ADD Transmit Register (0x1C)
ADDRESS
MODE
BIT
0x1C
Read/Write
7
6
0
5
0
4
0
3
ACC_ADD[7:0]
0
2
0
1
0
0
0
NAME
RESET
0
ACC_
ADD[7:0]
Accessory Target Address
Table 31. ACC_DATA Transmit Register (0x1D)
ADDRESS
MODE
BIT
0x1D
Read/Write
7
6
0
5
0
4
3
ACC_DATA[7:0]
0
2
0
1
0
0
0
NAME
RESET
0
0
ACC_
DATA[7:0]
Accessory Target Data
**Denotes a factory programmable value
Maxim Integrated
│ 43
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MAX20317
Universal 3.5mmØ Accessory Management IC
Application Circuits
ANC HEADSET
L-A
LA+
LA-
R-A
LMIC
ANC DSP
RA+
RA-
RMIC
PWR GND
BATTERY
CHARGER
50
200
600
56
36
CODEC
MIC1-BIAS R-G L-G R-A L-A
VCC
+5V
MIC1
1µF
1µF
SEND/
END
VOL
UP
VOL
DOWN
6.8
RSEN
MIC_OUT
G_SNSR
V
CC
V
BOOST
VIO
G_SNSL
SLEEVE
VCC
RST
MIC
MAX16083
AP
MAX20317
GND
LEFT
DET
RING2
DETIN
GND
SDA
SCL
SDA
SCL
INT
SLEEVE_SL
SLEEVE_SR
RING2_SL
RING2_SR
RIGHT
GND
L-A R-A
MIC/PWR
DGND
GND
Maxim Integrated
│ 44
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MAX20317
Universal 3.5mmØ Accessory Management IC
Application Circuits (continued)
HR HEADSET
HR CONTROL BLOCK
L-A
LA+
GND
R-A
HR
MONITOR
HR SENSOR
RA+
GND
LDO
MCU
50
200
600
56
36
CODEC
MIC1-BIAS R-G L-G R-A L-A
VCC
+5V
MIC1
1µF
1µF
SEND/
END
VOL
UP
VOL
DOWN
6.8
RSEN
MIC_OUT
G_SNSR
V
V
BOOST
CC
VIO
G_SNSL
SLEEVE
VCC
RST
MIC
MAX16083
AP
MAX20317
GND
LEFT
DET
RING2
DETIN
GND
SDA
SCL
SDA
SCL
INT
SLEEVE_SL
SLEEVE_SR
RING2_SL
RING2_SR
RIGHT
GND
L-A R-A
MIC/PWR
DGND
GND
Maxim Integrated
│ 45
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MAX20317
Universal 3.5mmØ Accessory Management IC
Ordering Information
Package Information
For the latest package outline information and land patterns
PART
TEMP RANGE
PIN-PACKAGE
(footprints), go to www.maximintegrated.com/packages. Note
that a “+”, “#”, or “-” in the package code indicates RoHS status
only. Package drawings may show a different suffix character, but
the drawing pertains to the package regardless of RoHS status.
MAX20317EWP+
MAX20317EWP+T
-40°C to +85°C
-40°C to +85°C
20 WLP
20 WLP
+Denotes a lead(Pb)-free/RoHS-compliant package.
T Denotes tape-and-reel
PACKAGE
TYPE
PACKAGE
CODE
OUTLINE
NO.
LAND
PATTERN NO.
Refer to
Application
Note 1891
Chip Information
PROCESS: BiCMOS
20 WLP
W201H2+1
21-100120
Maxim Integrated
│ 46
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MAX20317
Universal 3.5mmØ Accessory Management IC
Revision History
REVISION REVISION
PAGES
CHANGED
DESCRIPTION
NUMBER
DATE
0
5/17
Initial release
—
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim Integrated’s website at www.maximintegrated.com.
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses
are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits)
shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
©
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.
2017 Maxim Integrated Products, Inc.
│ 47
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