MAX199BEAI [MAXIM]
Multi-Range (【4V, 【2V, +4V, +2V), +5V Supply, 12-Bit DAS with 8+4 Bus Interface; 多范围（ 4V 【 【 2V ， 4V + ， + 2V ） ， + 5V电源，12位DAS ，8 + 4总线接口
| 型号： | MAX199BEAI |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Multi-Range (【4V, 【2V, +4V, +2V), +5V Supply, 12-Bit DAS with 8+4 Bus Interface |
| 文件： | 总16页 (文件大小：167K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-0401; Rev 0; 6/95
Mu lt i-Ra n g e (±4 V, ±2 V, +4 V, +2 V),
+5 V S u p p ly, 1 2 -Bit DAS w it h 8 +4 Bu s In t e rfa c e
MAX19
_______________Ge n e ra l De s c rip t io n
____________________________Fe a t u re s
♦ 12-Bit Resolution, 1/2LSB Linearity
♦ Single +5V Operation
The MAX199 multi-range, 12-bit data-acquisition system
(DAS) requires only a single +5V supply for operation,
and converts analog signals up to ±4V at its inputs. This
system provides eight analog input channels that are
independently software programmable for a variety of
♦ Software-Selectable Input Ranges:
±V
, ±V
, 0V to V
, 0V to V
REF REF/2
REF
REF/2
♦ Internal 4.096V or External Reference
♦ Fault-Protected Input Multiplexer (±16.5V)
♦ 8 Analog Input Channels
♦ 6µs Conversion Time, 100ksps Sampling Rate
♦ Internal or External Acquisition Control
♦ Two Power-Down Modes
ranges: ±V
, ±V
, 0V to V
, or 0V to V
.
REF
REF/2
REF
REF/2
This increases effective dynamic range to 14 bits, and
provides the user flexibility to interface 4mA-to-20mA,
±12V, and ±15V powered sensors to a single +5V sys-
tem. In addition, the converter is fault-protected to
±16.5V; a fault condition on any channel will not affect
the conversion result of the selected channel. Other fea-
tures include a 5MHz bandwidth track/hold, 100ksps
throughput rate, internal/external clock, internal/external
acquisition control, 8+4 parallel interface, and operation
with an internal 4.096V or external reference.
♦ Internal or External Clock
______________Ord e rin g In fo rm a t io n
PART
TEMP. RANGE
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
PIN-PACKAGE
28 Narrow Plastic DIP
28 Narrow Plastic DIP
28 Wide SO
A hardware SHDN pin and two programmable power-
down modes (STBYPD, FULLPD) provide low-current
shutdown between conversions. In STBYPD mode, the
reference buffer remains active, eliminating start-up
delays.
MAX199ACNI
MAX199BCNI
MAX199ACWI
MAX199BCWI
MAX199ACAI
MAX199BCAI
MAX199BC/D
28 Wide SO
The MAX199 employs a standard microprocessor (µP)
interface. Its three-state data I/O interface is configured
to operate with 8-bit data buses, and data-access and
bus-release timing specifications are compatible with
most popula r µPs. All logic inputs a nd outp uts a re
TTL/CMOS compatible.
28 SSOP
28 SSOP
Dice*
Ordering Information continued at end of data sheet.
*Dice are specified at TA = +25°C, DC parameters only.
__________________P in Co n fig u ra t io n
The MAX199 is available in 28-pin DIP, wide SO, SSOP,
and ceramic SB packages.
TOP VIEW
For a different combination of input ranges (±10V, ±5V,
0V to 10V, 0V to 5V), see the MAX197 data sheet. For 12-
bit bus interfaces, see the MAX196/MAX198 data sheet.
CLK
28 DGND
1
2
CS
WR
V
DD
27
26
25
24
23
REF
3
________________________Ap p lic a t io n s
Industrial-Control Systems
Robotics
REFADJ
INT
RD
4
HBEN
SHDN
D7
5
MAX199
CH7
6
Data-Acquisition Systems
Automatic Testing Systems
Medical Instruments
7
22 CH6
21 CH5
D6
8
D5
CH4
CH3
CH2
CH1
CH0
AGND
9
20
19
18
17
16
15
Telecommunications
D4
10
D3/D11 11
D2/D10 12
13
14
D1/D9
D0/D8
Functional Diagram appears at end of data sheet.
DIP/SO/SSOP/Ceramic SB
________________________________________________________________ Maxim Integrated Products
1
Ca ll t o ll fre e 1 -8 0 0 -7 2 2 -8 2 6 6 fo r fre e s a m p le s o r lit e ra t u re .
Mu lt i-Ra n g e (±4 V, ±2 V, +4 V, +2 V),
+5 V S u p p ly, 1 2 -Bit DAS w it h 8 +4 Bu s In t e rfa c e
ABSOLUTE MAXIMUM RATINGS
V
to AGND............................................................-0.3V to +7V
Wide SO (derate 12.50mW/°C above +70°C)..............1000mW
SSOP (derate 9.52mW/°C above +70°C) ......................762mW
Narrow Ceramic SB (derate 20.00mW/°C above +70°C)..1600mW
Operating Temperature Ranges
DD
AGND to DGND.....................................................-0.3V to +0.3V
REF to AGND..............................................-0.3V to (V + 0.3V)
REFADJ to AGND.......................................-0.3V to (V + 0.3V)
DD
DD
Digital Inputs to DGND...............................-0.3V to (V + 0.3V)
MAX199_C_ _ .......................................................0°C to +70°C
MAX199_E_ _.....................................................-40°C to +85°C
MAX199_M_ _..................................................-55°C to +125°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10sec) .............................+300°C
DD
Digital Outputs to DGND............................-0.3V to (V + 0.3V)
DD
CH0–CH7 to AGND ..........................................................±16.5V
MAX19
Continuous Power Dissipation (T = +70°C)
A
Narrow Plastic DIP (derate 14.29mW/°C above +70°C)....1143mW
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V = 5V ±5%; unipolar/bipolar range; external reference mode, V
DD
= 4.096V; 4.7µF at REF pin; external clock, f = 2.0MHz
CLK
REF
with 50% duty cycle; T = T
to T , unless otherwise noted.)
MAX
A
MIN
PARAMETER
ACCURACY (Note 1)
Resolution
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
12
Bits
LSB
LSB
MAX199A
MAX199B
±1/2
±1
Integral Nonlinearity
INL
Differential Nonlinearity
DNL
±1
MAX199A
±3
Unipolar
Bipolar
MAX199B
MAX199A
MAX199B
±5
Offset Error
LSB
LSB
±5
±10
Unipolar
Bipolar
±0.1
±0.5
Channel-to-Channel Offset
Error Matching
MAX199A
MAX199B
MAX199A
MAX199B
±7
±10
±7
Unipolar
Bipolar
Gain Error
(Note 2)
LSB
±10
Unipolar
Bipolar
3
5
Gain Temperature Coefficient
(Note 2)
ppm/°C
dB
DYNAMIC SPECIFICATIONS (10kHz sine-wave input, ±4.096Vp-p, f
= 100ksps)
SAMPLE
MAX199A
MAX199B
70
69
Signal-to-Noise + Distortion Ratio
SINAD
Total Harmonic Distortion
Spurious-Free Dynamic Range
Channel-to-Channel Crosstalk
Aperture Delay
THD
Up to the 5th harmonic
-85
-78
dB
dB
dB
ns
SFDR
80
50kHz, V = ±4V (Note 3)
IN
-86
15
External CLK mode/external acquisition control
External CLK mode/external acquisition
control
<50
10
ps
ns
Aperture Jitter
Internal CLK mode/internal acquisition
control (Note 4)
2
_______________________________________________________________________________________
Mu lt i-Ra n g e (±4 V, ±2 V, +4 V, +2 V),
+5 V S u p p ly, 1 2 -Bit DAS w it h 8 +4 Bu s In t e rfa c e
MAX19
ELECTRICAL CHARACTERISTICS (continued)
(V = 5V ±5%; unipolar/bipolar range; external reference mode, V
= 4.096V; 4.7µF at REF pin; external clock, f = 2.0MHz
CLK
DD
REF
with 50% duty cycle; T = T
to T , unless otherwise noted.)
MAX
A
MIN
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
ANALOG INPUT
Track/Hold Acquisition Time
f
= 2.0MHz
3
µs
CLK
±V
REF
range
5
±V
range
2.5
2.5
1.25
REF/2
Small-Signal Bandwidth
-3dB rolloff
MHz
0V to V
range
REF
0V to V
range
REF/2
0
0
V
REF
Unipolar (see Table 2)
V
REF/2
Input Voltage Range
V
-V
REF
V
REF
Bipolar (see Table 2)
Unipolar range
Bipolar
-V
V
REF/2
REF/2
0.1
10
Input Current
±V
range
-1200
-600
10
µA
REF
±V
REF/2
range
10
Unipolar
Bipolar
40
10
MΩ
kΩ
pF
Input Dynamic Resistance
Input Capacitance
(Note 5)
40
INTERNAL REFERENCE
REF Output Voltage
V
T
= +25°C
4.076
4.096
±15
4.116
V
REF
A
REF Output Tempco
MAX199_C
MAX199_E
MAX199_M
(Contact Maxim Applications
for guaranteed temperature
drift specifications)
TC V
±30
ppm/°C
REF
±40
Output Short-Circuit Current
30
mA
mV
0mA to 0.5mA output current (Note 6)
0mA to 0.1mA output current (Note 6)
7.5
Load Regulation
0.8
Capacitive Bypass at REF
REFADJ Output Voltage
REFADJ Adjustment Range
Buffer Voltage Gain
4.7
µF
V
2.465
2.500
±1.5
2.535
With recommended circuit (Figure 1)
%
1.6384
V/V
REFERENCE INPUT (Buffer disabled, reference input applied to REF pin)
Input Voltage Range
2.4
4.18
400
V
Normal, or STANDBY
power-down mode
FULL power-down
mode
Input Current
V
REF
= 4.18V
µA
1
Normal, or STANDBY power-down mode
FULL power-down mode
10
5
kΩ
Input Resistance
MΩ
REFADJ Threshold for
Buffer Disable
V
DD
- 50mV
V
_______________________________________________________________________________________
3
Mu lt i-Ra n g e (±4 V, ±2 V, +4 V, +2 V),
+5 V S u p p ly, 1 2 -Bit DAS w it h 8 +4 Bu s In t e rfa c e
ELECTRICAL CHARACTERISTICS (continued)
(V = 5V ±5%; unipolar/bipolar range; external reference mode, V
= 4.096V; 4.7µF at REF pin; external clock, f = 2.0MHz
CLK
DD
REF
with 50% duty cycle; T = T
to T , unless otherwise noted.)
MAX
A
MIN
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
POWER REQUIREMENTS
Supply Voltage
V
4.75
5.25
18
V
DD
1
Normal mode, bipolar ranges
Normal mode, unipolar ranges
Standby power-down (STBYPD)
Full power-down mode (FULLPD) (Note 7)
External reference = 4.096V
Internal reference
mA
6
10
Supply Current
I
DD
700
60
850
120
1
µA
± /
2
Power-Supply Rejection Ratio
(Note 8)
PSRR
LSB
1
± /
2
TIMING
Internal Clock Frequency
External Clock Frequency Range
f
C
= 100pF
CLK
1.25
0.1
3.0
3.0
3.0
1.56
2.00
2.0
MHz
MHz
CLK
f
CLK
External CLK
Internal CLK
t
Internal acquisition
ACQI
ACQE
CONV
5.0
Acquisition Time
µs
External acquisition (Note 9)
After FULLPD or STBYPD
External CLK
t
5
6.0
6.0
Conversion Time
Throughput Rate
t
µs
ksps
µs
Internal CLK, C
External CLK
= 100pF
7.7
10.0
100
CLK
Internal CLK, C
= 100pF
62
CLK
Bandgap Reference
Start-Up Time
Power-up (Note 10)
200
To 0.1mV, REF
bypass capacitor
fully discharged
C
C
= 4.7µF
= 33µF
8
REF
REF
Reference Buffer Settling
ms
60
DIGITAL INPUTS (D7–D0, CLK, RD, WR, CS, HBEN, SHDN) (Note 11)
Input High Voltage
Input Low Voltage
Input Leakage Current
Input Capacitance
V
2.4
V
V
INH
V
INL
0.8
±10
15
I
V
= 0V or V
DD
µA
pF
IN
IN
C
(Note 5)
IN
DIGITAL OUTPUTS (D7–D4, D3/D11, D2/D10, D1/D9, D0/D8, INT)
Output Low Voltage
V
V
= 4.75V, I
= 4.75V, I
= 1.6mA
0.4
15
V
V
OL
DD
SINK
Output High Voltage
V
OH
V
DD
= 1mA
V
DD
- 1
SOURCE
Three-State Output Capacitance
C
(Note 5)
pF
OUT
4
_______________________________________________________________________________________
Mu lt i-Ra n g e (±4 V, ±2 V, +4 V, +2 V),
+5 V S u p p ly, 1 2 -Bit DAS w it h 8 +4 Bu s In t e rfa c e
MAX19
TIMING CHARACTERISTICS
(V = 5V ±5%; unipolar/bipolar range; external reference mode, V
DD
= 4.096V; 4.7µF at REF pin; external clock, f = 2.0MHz
CLK
REF
with 50% duty cycle; T = T
to T , unless otherwise noted.)
MAX
A
MIN
PARAMETER
CS Pulse Width
SYMBOL
CONDITIONS
MIN
80
80
0
TYP
MAX
UNITS
ns
t
CS
WR Pulse Width
t
ns
WR
CS to WR Setup Time
CS to WR Hold Time
CS to RD Setup Time
CS to RD Hold Time
CLK to WR Setup Time
CLK to WR Hold Time
Data Valid to WR Setup
Data Valid to WR Hold
t
ns
CSWS
CSWH
t
0
ns
t
0
ns
CSRS
t
0
ns
CSRH
t
100
50
ns
CWS
t
ns
CWH
t
60
0
ns
DS
DH
DO
t
ns
RD Low to Output Data Valid
t
Figure 2, C = 100pF (Note 12)
120
120
ns
L
HBEN High or HBEN Low to
Output Valid
t
Figure 2, C = 100pF (Note 12)
L
ns
DO1
RD High to Output Disable
RD Low to INT High Delay
t
(Note 13)
70
ns
ns
TR
t
120
INT1
Note 1: Accuracy specifications tested at V = 5.0V. Performance at power-supply tolerance limits guaranteed by Power-Supply
DD
Rejection test. Tested for the ±4.096V input range.
Note 2: External reference: V
= 4.096V, offset error nulled, ideal last code transition = FS - 3/2LSB.
REF
Note 3: Ground “on” channel; sine wave applied to all “off” channels.
Note 4: Maximum full-power input frequency for 1LSB error with 10ns jitter = 3kHz.
Note 5: Guaranteed by design. Not tested.
Note 6: Use static loads only.
Note 7: Tested using internal reference.
Note 8: PSRR measured at full-scale. V = 4.75V to 5.25V.
DD
Note 9: External acquisition timing: starts at rising edge of WR with control bit ACQMOD = low; ends at rising edge of WR with
ACQMOD = high.
Note 10: Not subject to production testing. Provided for design guidance only.
Note 11: All input control signals specified with t = t = 5ns from a voltage level of 0.8V to 2.4V.
R
F
Note 12: t
and t
are measured with the load circuits of Figure 2 and defined as the time required for an output to cross 0.8V
DO
DO1
or 2.4V.
Note 13: t is defined as the time required for the data lines to change by 0.5V.
TR
_______________________________________________________________________________________
5
Mu lt i-Ra n g e (±4 V, ±2 V, +4 V, +2 V),
+5 V S u p p ly, 1 2 -Bit DAS w it h 8 +4 Bu s In t e rfa c e
__________________________________________Typ ic a l Op e ra t in g Ch a ra c t e ris t ic s
(T = +25°C, unless otherwise noted.)
A
INTEGRAL NONLINEARITY
EFFECTIVE NUMBER OF BITS
vs. INPUT FREQUENCY
vs. DIGITAL CODE
FFT PLOT
0
-20
0.250
12.0
11.5
11.0
10.5
f = 100kHz
SAMPLE
f
= 10kHz
= 100kHz
TONE
0.200
0.150
0.100
0.050
0
MAX19
f
SAMPLE
-40
-60
-80
-0.050
-0.100
-0.150
-100
-120
10.0
0
25
FREQUENCY (kHz)
50
0
1000
2000
3000
4000
1
10
INPUT FREQUENCY (kHz)
100
DIGITAL CODE
POWER-SUPPLY REJECTION RATIO
vs. TEMPERATURE
REFERENCE OUTPUT VOLTAGE (V
)
REF
vs. TEMPERATURE
0.4
4.100
V
DD
= 5V ±0.25V
120Hz
0.2
0
4.095
100Hz
4.090
-0.2
-0.4
A = 1.6384
V
+2.5V
INTERNAL
REFERENCE
4.085
4.080
REF
REFADJ
-0.6
-70 -50
110
130
-30 -10 10 30 50 70 90
TEMPERATURE (°C)
-55 -35
5
25 45 65
-15
85 105 125
TEMPERATURE (°C)
CHANNEL-TO-CHANNEL
CHANNEL-TO-CHANNEL
OFFSET-ERROR MATCHING vs. TEMPERATURE
GAIN-ERROR MATCHING vs. TEMPERATURE
0.33
0.20
0.32
0.31
0.30
0.18
0.16
0.14
0.12
0.10
0.29
0.28
0.27
130
130
-70 -50 -30 -10 10 30 50 70 90 110
-70 -50 -30 -10 10 30 50 70 90 110
TEMPERATURE (°C)
TEMPERATURE (°C)
6
_______________________________________________________________________________________
Mu lt i-Ra n g e (±4 V, ±2 V, +4 V, +2 V),
+5 V S u p p ly, 1 2 -Bit DAS w it h 8 +4 Bu s In t e rfa c e
MAX19
______________________________________________________________P in De s c rip t io n
PIN
NAME
CLK
CS
FUNCTION
Clock Input. In external clock mode, drive CLK with a TTL/CMOS compatible clock. In internal clock mode,
1
place a capacitor (C
) from this pin to ground to set the internal clock frequency; f
= 1.56MHz typical
CLK
CLK
with C
= 100pF.
CLK
2
Chip Select, active low.
When CS is low, in the internal acquisition mode, a rising edge on WRlatches in configuration data and starts an
acquisition plus a conversion cycle. When CS is low, in the external acquisition mode, the first rising edge on
WR starts an acquisition and a second rising edge on WRends acquisition and starts a conversion cycle.
3
WR
4
5
RD
When CS is low, a falling edge on RD will enable a read operation on the data bus.
Used to multiplex the 12-bit conversion result. When high, the 4 MSBs are multiplexed on the data bus;
when low, the 8 LSBs are available on the bus.
HBEN
6
7–10
11
SHDN
D7–D4
D3/D11
D2/D10
D1/D9
D0/D8
AGND
Shutdown. Puts the device into full power-down (FULLPD) mode when pulled low.
Three-State Digital I/O
Three-State Digital I/O. D3 output (HBEN = low), D11 output (HBEN = high).
Three-State Digital I/O. D2 output (HBEN = low), D10 output (HBEN = high).
Three-State Digital I/O. D1 output (HBEN = low), D9 output (HBEN = high).
Three-State Digital I/O. D0 output (HBEN = low), D8 output (HBEN = high). D0 = LSB.
Analog Ground
12
13
14
15
16–23 CH0–CH7
Analog Input Channels
24
INT
INT goes low when conversion is complete and output data is ready.
Bandgap Voltage-Reference Output / External Adjust Pin. Bypass with a 0.01µF capacitor to AGND.
Connect to V when using an external reference at the REF pin.
DD
25
REFADJ
Reference Buffer Output / ADC Reference Input. In internal reference mode, the reference buffer provides a
4.096V nominal output, externally adjustable at REFADJ. In external reference mode, disable the internal
26
REF
buffer by pulling REFADJ to V
.
DD
27
28
V
+5V Supply. Bypass with 0.1µF capacitor to AGND.
Digital Ground
DD
DGND
+5V
3k
+5V
MAX199
D
OUT
510k
100k
REFADJ
D
OUT
C
LOAD
3k
C
LOAD
0.01µF
24k
a) High-Z to V and V to V
OH
b) High-Z to V and V to V
OL
OH
OL
OL
OH
Figure 1. Reference-Adjust Circuit
Figure 2. Load Circuits for Enable Time
_______________________________________________________________________________________
7
Mu lt i-Ra n g e (±4 V, ±2 V, +4 V, +2 V),
+5 V S u p p ly, 1 2 -Bit DAS w it h 8 +4 Bu s In t e rfa c e
where R = 7kΩ, and t is never less than 2µs (0V to
IN
AZ
_______________De t a ile d De s c rip t io n
V
range) or 3µs (0V to V
range).
REF
REF/2
Co n ve rt e r Op e ra t io n
The MAX199, a multi-range, fault-tolerant ADC, uses
successive approximation and internal input track/hold
(T/H) circuitry to convert an analog signal to a 12-bit
digital output. The parallel-output format provides easy
interface to microprocessors (µPs). Figure 3 shows the
MAX199 in its simplest operational configuration.
In the external acquisition control mode (D5 = 1), the
T/H enters its tracking mode on the first WR rising edge
and enters its hold mode when it detects the second WR
rising edge with D5 = 0. See the External Acquisition
section.
MAX19
In p u t Ba n d w id t h
The ADC’s input tracking circuitry has a 5MHz small-
signal bandwidth. When using the internal acquisition
mode with an external clock frequency of 2MHz, a
100ksps throughput rate can be achieved. It is possible
to digitize high-speed transient events and measure
periodic signals with bandwidths exceeding the ADC’s
sampling rate by using undersampling techniques. To
avoid high-frequency signals being aliased into the fre-
quency band of interest, anti-alias filtering is recom-
mended (MAX274/MAX275 continuous-time filters).
An a lo g -In p u t Tra c k /Ho ld
In the internal acquisition control mode (control bit D5
set to 0), the T/H enters its tracking mode on WR’s ris-
ing edge, and enters its hold mode when the internally
timed (6 clock cycles) acquisition interval ends. In bipo-
lar mode, a low-impedance input source, which settles
in less than 1.5µs, is required to maintain conversion
accuracy at the maximum conversion rate.
When configured for unipolar mode, the input does not
need to be driven from a low-impedance source. The
In p u t Ra n g e a n d P ro t e c t io n
Figure 4 shows the equivalent input circuit. The MAX199
acquisition time (t ) is a function of the source output
AZ
resistance (R ), the channel input resistance (R ), and
S
IN
can be programmed for input ranges of ±V , ±V
,
REF
REF/2
the T/H capacitance.
0V to V , or 0V to V
by setting the appropriate
REF
REF/2
Acquisition time is calculated by:
control bits (D3, D4) in the control byte (see Tables 1 and
2). When an external reference is applied at REFADJ, the
For 0V to V : t = 9 x (R + R ) x 16pF
REF AZ
S
IN
voltage at REF is given by V
= 1.6384 x V
(2.4V
REF
REFADJ
For 0V to V : t = 9 x (R + R ) x 32pF
REF/2 AZ S IN
< V
< 4.18V).
REF
1
28
CLK
DGND
BIPOLAR
VOLTAGE
REFERENCE
100pF
S1
+5V
27
26
25
MAX199
V
DD
+4.096V
2
3
CS
REF
UNIPOLAR
OFF
0.1µF
WR
RD
REFADJ
µP
CONTROL
INPUTS
4.7µF
5.12k
4
24
23
22
21
20
19
18
17
16
INT
CH7
CH6
CH5
5
OUTPUT STATUS
HBEN
SHDN
D7
5.12k
6
CH_
C
HOLD
7
S2
T/H
OUT
8
ON
D6
CH4
9
ANALOG
INPUTS
D5
10
11
12
13
14
CH3
CH2
CH1
D4
S3
TRACK
TRACK S4
HOLD
D3/D11
HOLD
D2/D10
CH0
D1/D9
D0/D8
15
AGND
S1 = BIPOLAR/UNIPOLAR SWITCH
S2 = INPUT MUX SWITCH
S3, S4 = T/H SWITCH
µP DATA BUS
Figure 4. Equivalent Input Circuit
Figure 3. Operational Diagram
8
_______________________________________________________________________________________
Mu lt i-Ra n g e (±4 V, ±2 V, +4 V, +2 V),
+5 V S u p p ly, 1 2 -Bit DAS w it h 8 +4 Bu s In t e rfa c e
MAX19
The inp ut c ha nne ls a re ove rvolta g e p rote c te d to
±16.5V. This protection is active even if the device is in
power-down mode.
Input Format
The control byte is latched into the device, on pins
D7–D0, during a write cycle. Table 1 shows the control-
byte format.
Even with V = 0V, the input resistive network provides
DD
current-limiting that adequately protects the device.
Output Data Format
The output data format is binary in unipolar mode and
twos-complement binary in bipolar mode. When read-
ing the output data, CS and RD must be low. When
HBEN is low, the lower eight bits are read. When HBEN
is high, the upper four MSBs are available and the out-
p ut d a ta b its D4–D7 a re e ithe r s e t low (in unip ola r
mode) or set to the value of the MSB (in bipolar mode)
(Table 5).
Dig it a l In t e rfa c e
Input data (control byte) and output data are multiplexed
on a three-state parallel interface. This parallel I/O can
easily be interfaced with a µP. CS, WR, and RD control
the write and read operations. CS is the standard chip-
select signal, which enables a µP to address the MAX199
as an I/O port. When high, it disables the WR and RD
inputs and forces the interface into a high-Z state.
Table 1. Control-Byte Format
D7 (MSB)
D6
D5
D4
D3
D2
D1
D0 (LSB)
PD1
PD0
ACQMOD
RNG
BIP
A2
A1
A0
BIT
NAME
PD1, PD0
ACQMOD
RNG
DESCRIPTION
These two bits select the clock and power-down modes (Table 3).
7, 6
5
0 = internally controlled acquisition (6 clock cycles), 1 = externally controlled acquisition
Selects the full-scale voltage magnitude at the input (Table 2).
4
3
BIP
Selects unipolar or bipolar conversion mode (Table 2).
2, 1, 0
A2, A1, A0
These are address bits for the input mux to select the “on” channel (Table 4).
Table 2. Range and Polarity Selection
Table 3. Clock and Power-Down Selection
PD1 PD0
DEVICE MODE
BIP
RNG
INPUT RANGE (V)
0
0
0
1
Normal Operation / External Clock Mode
Normal Operation / Internal Clock Mode
0
0
1
0
1
0 to V
REF/2
0
0 to V
REF
Standby Power-Down (STBYPD); clock mode
is unaffected
1
1
0
1
1
±V
REF/2
1
±V
REF
Full Power-Down (FULLPD); clock mode is
unaffected
Table 4. Channel Selection
A2
0
A1
0
A0
0
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
_______________________________________________________________________________________
9
Mu lt i-Ra n g e (±4 V, ±2 V, +4 V, +2 V),
+5 V S u p p ly, 1 2 -Bit DAS w it h 8 +4 Bu s In t e rfa c e
Writing a new control byte during the conversion cycle
will abort the conversion in progress and start a new
acquisition interval.
Table 5. Data-Bus Output
PIN
D0
D1
D2
D3
D4
D5
D6
D7
HBEN = LOW
HBEN = HIGH
B0 (LSB)
B1
B8
Internal Acquisition
B9
Select internal acquisition by writing the control byte
with the ACQMOD bit cleared (ACQMOD = 0). This
causes the write pulse to initiate an acquisition interval
whose duration is internally timed. Conversion starts
when this six-clock-cycle acquisition interval (3µs with
B2
B10
B3
B11 (MSB)
MAX19
B4
B11 (BIP = 1) / 0 (BIP = 0)
B11 (BIP = 1) / 0 (BIP = 0)
B11 (BIP = 1) / 0 (BIP = 0)
B11 (BIP = 1) / 0 (BIP = 0)
B5
f
= 2MHz) ends. See Figure 5.
CLK
B6
External Acquisition
B7
Use the external acquisition timing mode for precise con-
trol of the sampling aperture and/or independent control of
acquisition and conversion times. The user controls acqui-
sition and start-of-conversion with two separate write puls-
es. The first pulse, written with ACQMOD = 1, starts an
acquisition interval of indeterminate length. The second
write pulse, written with ACQMOD = 0, terminates acquisi-
tion and starts conversion on WR’s rising edge (Figure 6).
However, if the second control byte contains ACQMOD =
1, an indefinite acquisition interval is restarted.
Ho w t o S t a rt a Co n ve rs io n
Conversions are initiated with a write operation, which
selects the mux channel and configures the MAX199 for
either unipolar or bipolar input range. A write pulse (WR
+ CS) can either start an acquisition interval or initiate a
combined acquisition plus conversion. The sampling
interval occurs at the end of the acquisition interval.
The ACQMOD bit in the input control byte offers two
options for acquiring the signal: internal or external.
The conversion period lasts for 12 clock cycles in either
internal or external clock or acquisition mode.
The address bits for the input mux must have the same
values on the first and second write pulses. Power-
down mode bits (PD0, PD1) can assume new values on
the second write pulse (see Power-Down Mode).
tCSRH
tCS
tCSRS
CS
tACQI
tCONV
tCSWS
tCSWH
tDH
tWR
WR
tDS
CONTROL
BYTE
D7–D0
ACQMOD ="0"
tINT1
INT
RD
HBEN
tTR
tD0
tD01
HIGH-Z
HIGH-Z
HIGH / LOW
BYTE VALID
HIGH / LOW
BYTE VALID
DOUT
Figure 5. Conversion Timing Using Internal Acquisition Mode
10 ______________________________________________________________________________________
Mu lt i-Ra n g e (±4 V, ±2 V, +4 V, +2 V),
+5 V S u p p ly, 1 2 -Bit DAS w it h 8 +4 Bu s In t e rfa c e
MAX19
tCSRS
tCSRH
tCS
CS
tCSWS
tACQI
tCSHW
tCONV
tWR
WR
tDH
tDS
CONTROL
CONTROL
BYTE
ACQMOD = "0"
D7–D0
INT
BYTE
ACQMOD = "1"
tINT1
RD
HBEN
tD01
tD0
tTR
HIGH-Z
HIGH-Z
HIGH / LOW
BYTE VALID
HIGH / LOW
BYTE VALID
DOUT
Figure 6. Conversion Timing Using External Acquisition Mode
shows a linear relationship between the internal clock
period and the value of the external capacitor used.
Ho w t o Re a d a Co n ve rs io n
A standard interrupt signal, INT, is provided to allow the
device to flag the µP when the conversion has ended
and a valid result is available. INT goes low when the
conversion is complete and the output data is ready
(Figures 5 and 6). It returns high on the first read cycle
or if a new control byte is written.
2000
1500
1000
Clo c k Mo d e s
The MAX199 ope ra te s with e ithe r a n inte rna l or a n
external clock. Control bits (D6, D7) select either inter-
nal or external clock mode. Once the desired clock
mod e is s e le c te d , c ha ng ing the s e b its to p rog ra m
power-down will not affect the clock mode. In each
mode, internal or external acquisition can be used. At
power-up, the MAX199 defaults to external clock mode.
500
0
Internal Clock Mode
Se le c t inte rna l c loc k mod e to fre e the µP from the
burden of running the SAR conversion clock. To select
this mode, write the control byte with D7 = 0 and D6 = 1.
A 100pF capacitor between the CLK pin and ground
s e ts this fre q ue nc y to 1.56MHz nomina l. Fig ure 7
0
50 100 150 200 250 300 350
CLOCK PIN CAPACITANCE (pF)
Figure 7. Internal Clock Period vs. Clock Pin Capacitance
______________________________________________________________________________________ 11
Mu lt i-Ra n g e (±4 V, ±2 V, +4 V, +2 V),
+5 V S u p p ly, 1 2 -Bit DAS w it h 8 +4 Bu s In t e rfa c e
External Clock Mode
Select external clock mode by writing the control byte
with D7 = 0 and D6 = 0. Figure 8 shows CLK and WR
timing relationships in internal and external acquisition
modes, with an external clock. A 100kHz to 2.0MHz
external clock with 45% to 55% duty cycle is required
for proper operation. Operating at clock frequencies
lower than 100kHz will cause a voltage droop across
the hold capacitor, and subsequently degrade perfor-
mance.
MAX19
ACQUISITION STARTS
CONVERSION STARTS
ACQUISITION ENDS
CLK
tCWS
WR
WR GOES HIGH WHEN CLK IS HIGH
ACQMOD = "0"
ACQUISITION ENDS
tCWH
ACQUISITION STARTS
CONVERSION STARTS
CLK
WR
ACQMOD = "0"
WR GOES HIGH WHEN CLK IS LOW
Figure 8a. External Clock and WR Timing (Internal Acquisition Mode)
ACQUISITION STARTS
ACQUISITION ENDS
CONVERSION STARTS
CLK
tCWS
tDH
WR
ACQMOD = "0"
ACQMOD = "1"
WR GOES HIGH WHEN CLK IS HIGH
ACQUISITION ENDS
ACQUISITION STARTS
CONVERSION STARTS
CLK
WR
tCWH
tDH
ACQMOD = "1"
WR GOES HIGH WHEN CLK IS LOW
ACQMOD = "0"
Figure 8b. External Clock and WR Timing (External Acquisition Mode)
12 ______________________________________________________________________________________
Mu lt i-Ra n g e (±4 V, ±2 V, +4 V, +2 V),
+5 V S u p p ly, 1 2 -Bit DAS w it h 8 +4 Bu s In t e rfa c e
MAX19
e xte rna l re fe re nc e a t REF mus t b e a b le to d e live r
400µA DC load currents, and must have an output
__________Ap p lic a t io n s In fo rm a t io n
P o w e r-On Re s e t
At power-up, the internal power-supply circuitry sets INT
high and puts the device in normal operation / external
clock mode. This state is selected to keep the internal
clock from loading the external clock driver when the
part is used in external clock mode.
impedance of 10Ω or less. If the reference has higher
input impedance or is noisy, bypass it close to the REF
pin with a 4.7µF capacitor to AGND.
With an external reference voltage of less than 4.096V
at the REF pin or less than 2.5V at the REFADJ pin, the
increase in the ratio of the RMS noise to the LSB value
(FS / 4096) results in performance degradation (loss of
effective bits).
In t e rn a l o r Ex t e rn a l Re fe re n c e
The MAX199 can operate with either an internal or external
reference. An external reference can be connected to
either the REF pin or to the REFADJ pin (Figure 9).
To use the REF input directly, disable the internal buffer
REF 26
4.096V
by tying REFADJ to V . Using the REFADJ input elimi-
DD
na te s the ne e d to b uffe r the re fe re nc e e xte rna lly.
Whe n the re fe re nc e is a p p lie d a t REFADJ , b yp a s s
REFADJ with a 0.01µF capacitor to AGND.
MAX199
4.7µF
C
REF
The REFADJ internal buffer gain is trimmed to 1.6384 to
provide 4.096V at the REF pin from a 2.5V reference.
V
DD
A = 1.638
V
REFADJ 25
Internal Reference
The inte rna lly trimme d 2.50V re fe re nc e is g a ine d
through the REFADJ buffer to provide 4.096V at REF.
Bypass the REF pin with a 4.7µF capacitor to AGND
and the REFADJ pin with a 0.01µF capacitor to AGND.
The internal reference voltage is adjustable to ±1.5%
(±65 LSBs) with the reference-adjust circuit of Figure 1.
10k
2.5V
External Reference
At REF and REFADJ, the input impedance is a mini-
mum of 10kΩ for DC currents. During conversions, an
Figure 9b. External Reference at REF
REF 26 4.096V
REF 26 4.096V
MAX199
4.7µF
C
REF
4.7µF
C
REF
MAX199
A = 1.638
V
A = 1.638
V
REFADJ 25
REFADJ 25
2.5V
0.01µF
0.01µF
10k
10k
2.5V
2.5V
Figure 9a. Internal Reference
Figure 9c. The external reference at REFADJ overdrives the
internal reference.
______________________________________________________________________________________ 13
Mu lt i-Ra n g e (±4 V, ±2 V, +4 V, +2 V),
+5 V S u p p ly, 1 2 -Bit DAS w it h 8 +4 Bu s In t e rfa c e
However, in FULLPD mode, only the bandgap refer-
ence is active. Connect a 33µF capacitor between REF
and AGND to maintain the reference voltage between
conversion and to reduce transients when the buffer is
enabled and disabled. Throughput rates down to 1ksps
can be achieved without allotting extra acquisition time
for reference recovery prior to conversion. This allows a
c onve rsion to be gin imme d ia te ly a fte r powe r-d own
ends. If the discharge of the REF capacitor during
FULLPD exceeds the desired limits for accuracy (less
than a fraction of an LSB), run a STBYPD power-down
cycle prior to starting conversions. Take into account
that the reference buffer recharges the bypass capaci-
tor at an 80mV/ms slew rate and add 50µs for settling
time. Throughput rates of 10ksps offer typical supply
c urre nts of 470µA, us ing the re c omme nd e d 33µF
capacitor value.
P o w e r-Do w n Mo d e
To save power, you can put the converter into low-
current shutdown mode between conversions. Two
programmable power-down modes are available, in
addition to a hardware shutdown. Select STBYPD or
FULLPD by programming PD0 and PD1 in the input
control byte. When software power-down is asserted, it
becomes effective only after the end of conversion. In all
power-down modes, the interface remains active and
conversion results may be read. Input overvoltage pro-
tection is active in all power-down modes. The device
returns to normal operation on the first WR falling edge
during a write operation.
MAX19
For hardware-controlled (FULLPD) power-down, pull
the SHDN pin low. When hardware shutdown is assert-
ed, it becomes effective immediately and the conver-
sion is aborted.
Auto-Shutdown
Selecting STBYPD on every conversion automatically
shuts the MAX199 down after each conversion without
requiring any start-up time on the next conversion.
Choosing Power-Down Modes
The bandgap reference and reference buffer remain
active in STBYPD mode, maintaining the voltage on the
4.7µF capacitor at the REF pin. This is a “DC” state that
does not degrade after power-down of any duration.
Therefore, you can use any sampling rate with this
mode, without regard to start-up delays.
OUTPUT CODE
2 FS
4096
OUTPUT CODE
1 LSB =
FS
4096
1 LSB =
FULL-SCALE
TRANSITION
011... 111
11... 111
011... 110
11... 110
11... 101
000... 001
000... 000
111... 111
00... 011
00... 010
00... 001
00... 000
100... 010
100... 001
100... 000
FS
0
1
2
3
-FS
0V
+FS - 1 LSB
3
FS - / LSB
INPUT VOLTAGE (LSB)
2
INPUT VOLTAGE (LSB)
Figure 10. Unipolar Transfer Function
Figure 11. Bipolar Transfer Function
14 ______________________________________________________________________________________
Mu lt i-Ra n g e (±4 V, ±2 V, +4 V, +2 V),
+5 V S u p p ly, 1 2 -Bit DAS w it h 8 +4 Bu s In t e rfa c e
MAX19
Tra n s fe r Fu n c t io n
Output data coding for the MAX199 is binary in unipolar
_Ord e rin g In fo rm a t io n (c o n t in u e d )
mode with 1LSB = (FS / 4096) and twos-complement
binary in bipolar mode with 1LSB = [(2 x FS ) / 4096].
Code transitions occur halfway between successive-
inte g e r LSB va lue s . Fig ure s 10 a nd 11 s how the
input/output (I/O) transfer functions for unipolar and
bipolar operations, respectively.
PART
TEMP. RANGE
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
PIN-PACKAGE
28 Narrow Plastic DIP
28 Narrow Plastic DIP
28 Wide SO
|
|
MAX199AENI
MAX199BENI
MAX199AEWI
MAX199BEWI
MAX199AEAI
MAX199BEAI
MAX199AMYI
MAX199BMYI
28 Wide SO
28 SSOP
La yo u t , Gro u n d in g , a n d Byp a s s in g
Careful printed circuit board layout is essential for best
s ys te m p e rforma nc e . For b e s t p e rforma nc e , us e a
ground plane. To reduce crosstalk and noise injection,
ke e p a na log a nd d ig ita l s ig na ls s e p a ra te . Dig ita l
ground lines can run between digital signal lines to
minimize interference. Connect analog grounds and
DGND in a star configuration to AGND. For noise-free
operation, ensure the ground return from AGND to the
supply ground is low impedance and as short as possi-
ble. Connect the logic grounds directly to the supply
28 SSOP
-55°C to +125°C 28 Narrow Ceramic SB**
-55°C to +125°C 28 Narrow Ceramic SB**
** Contact factory for availability and processing to MIL-STD-883.
___________________Ch ip To p o g ra p h y
WR CLK
CS
V
V
CC
DD
DGND
REF
ground. Bypass V
to AGND to minimize high- and low-frequency fluctua-
with 0.1µF and 4.7µF capacitors
DD
RD
REFADJ
INT
tions. If the supply is excessively noisy, connect a 5Ω
HBEN
SHDN
resistor between the supply and V , as shown in
DD
Figure 12.
D7
CH7
0. 231"
(5. 870mm)
SUPPLY
CH6
CH5
GND
+5V
D6
CH4
CH3
CH2
4.7µF
0.1µF
D5
D4
R* = 5Ω
D3
**
D1
CH0
V
DD
+5V
DGND
AGND
DGND
D2
D0 AGND
0. 144"
CH1
DIGITAL
CIRCUITRY
MAX199
(3. 659mm)
TRANSISTOR COUNT: 2956
SUBSTRATE CONNECTED TO GND
* OPTIONAL
** CONNECT AGND AND DGND WITH A GROUND PLANE OR A SHORT TRACE
Figure 12. Power-Supply Grounding Connection
______________________________________________________________________________________ 15
Mu lt i-Ra n g e (±4 V, ±2 V, +4 V, +2 V),
+5 V S u p p ly, 1 2 -Bit DAS w it h 8 +4 Bu s In t e rfa c e
_________________________________________________________Fu n c t io n a l Dia g ra m
REF
REFADJ
10k
+2.5V
REFERENCE
A =
V
1.638
CH7
CH6
CH5
CH4
CH3
CH2
CH1
CH0
MAX19
SIGNAL
CONDITIONING
BLOCK
T/H
&
CHARGE REDISTRIBUTION
12-BIT DAC
COMP
OVERVOLTAGE
TOLERANT
MUX
12
SUCCESSIVE-
APPROXIMATION
REGISTER
CLK
CLOCK
4
4
8
8
CS
WR
CONTROL LOGIC
&
RD
LATCHES
MUX
8
SHDN
HBEN
8
V
DD
MAX199
THREE-STATE, BIDIRECTIONAL
I/O INTERFACE
AGND
DGND
INT
D0–D7
8-BIT DATA BUS
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
16 __________________Ma x im In t e g ra t e d P ro d u c t s , 1 2 0 S a n Ga b rie l Drive , S u n n yva le , CA 9 4 0 8 6 (4 0 8 ) 7 3 7 -7 6 0 0
© 1995 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
相关型号：
©2020 ICPDF网 联系我们和版权申明