MAX19777EVKIT [MAXIM]
Time Domain, Frequency Domain, and Histogram Plotting in the EV Kit Software;
| 型号： | MAX19777EVKIT |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Time Domain, Frequency Domain, and Histogram Plotting in the EV Kit Software |
| 文件： | 总19页 (文件大小：1156K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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MAX19777
3Msps, Low-Power, Serial 12-Bit ADC
General Description
Benefits and Features
● 3Msps Conversion Rate, No Pipeline Delay
● 12-Bit Resolution
The MAX19777 is a 12-bit, compact, high-speed,
lowpower, successive approximation analog-to-digital
converter (ADC). This high-performance ADC includes a
high dynamic range sample-and-hold, as well as a high-
speed serial interface.
● 2-Channel, Single-Ended Analog Inputs
● Low-Noise 72.5dB SNR
● 2.2V to 3.3V Supply Voltage
The MAX19777 features dual, single-ended analog inputs
connected to the ADC core using a 2:1 MUX.
● Low Power
This ADC operates from a 2.2V to 3.3V supply and
consumes only 6.2mW at 3Msps. The device includes
a full power-down mode and fast wake up for optimal
power management and a high-speed 3-wire serial
interface. The 3-wire serial interface directly connects to
• 6.2mW at 3Msps
• Very Low Power Consumption at 2.5μA/ksps
● 2μA Power-Down Current
● SPI/QSPI/MICROWIRE-Compatible Serial Interface
● 8-Pin, 0.857mm x 1.431mm WLP Package
● Wide -40°C to +125°C Operation
®
SPI, QSPI™, and MICROWIRE devices without external
logic.
Excellent dynamic performance, low voltage, low power,
ease-of-use, and small package size make this converter
ideal for portable, battery-powered data-acquisition
applications, as well as for other applications that demand
low power consumption and minimal space.
Applications
● Data Acquisition
● Portable Data Logging
● Medical Instrumentation
● Battery-Operated Systems
● Communication Systems
● Automotive Systems
This ADC is available in an 8-pin wafer-level package
(WLP). This device operates over the -40°C to +125°C
temperature range.
Ordering Information continued at end of data sheet.
Typical Operating Circuit
V
DD
+3V
AIN1
AIN2
GND
MAX19777
SCLK
DOUT
SCK
ANALOG
INPUTS
CPU
MISO
CS
SS
CHSEL
QSPI is a trademark of Motorola, Inc.
MICROWIRE is a registered trademark of National Semiconductor Corp.
19-100204; Rev 0; 11/17
MAX19777
3Msps, Low-Power, Serial 12-Bit ADC
Absolute Maximum Ratings
V
to GND .........................................................-0.3V to +3.6V
Operating Temperature Range......................... -40°C to +125°C
Junction Temperature......................................................+150°C
Storage Temperature Range............................ -65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Soldering Temperature (reflow).......................................+260°C
DD
AIN1, AIN2, CS, SCLK, CHSEL, DOUT TO GND
.........................-0.3V to the lower of (V + 0.3V) and +3.6V
DD
Input/Output Current (all pins)............................................50mA
Continuous Power Dissipation (T = +70°C)
A
8-pin WLP (derate 11.6mW/°C above +70°C).............872mW
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Electrical Characteristics
(V
= 2.2V to 3.3V. f
= 48MHz, 50% duty cycle, 3Msps. C
= 10pF, T = -40°C to +125°C, unless otherwise noted. Typical
DOUT A
DD
SCLK
values are at T = +25°C.)
A
PARAMETER
DC ACCURACY
Resolution
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Bits
12
-1.5
-2
2Msps, V
2Msps, V
3Msps
MAX
+1.5
+2
DD
Integral Nonlinearity
INL
MIN
LSB
DD
±3
2Msps, V
1Msps, V
MAX
MAX
-1
-0.95
-4
+1.2
+1.2
+10
+7
DD
Differential Nonlinearity
DNL
LSB
DD
Offset Error
OE
GE
V
MAX
LSB
LSB
LSB
DD
DD
Gain Error
V
MAX
-7
Total Unadjusted Error
TUE
4
Channel-to-Channel Offset
Matching
±0.4
LSB
LSB
Channel-to-Channel Gain
Matching
±0.05
DYNAMIC PERFORMANCE (f
= 10kHz)
AIN_
2Msps
3Msps
2Msps
3Msps
70
71
72
69
Signal-to-Noise and Distortion
SINAD
dB
dB
72.5
69
Signal-to-Noise Ratio
SNR
Total Harmonic Distortion
Spurious-Free Dynamic Range
Intermodulation Distortion
Full-Power Bandwidth
THD
SFDR
IMD
-83
83
dB
dB
f = 1.0003MHz, f = 0.99955MHz
-84
40
dB
1
2
-3dB point
MHz
MHz
MHz
Full-Linear Bandwidth
SINAD > 68dB
2.5
45
Small-Signal Bandwidth
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MAX19777
3Msps, Low-Power, Serial 12-Bit ADC
Electrical Characteristics (continued)
(V
= 2.2V to 3.3V. f
= 48MHz, 50% duty cycle, 3Msps. C
= 10pF, T = -40°C to +125°C, unless otherwise noted. Typical
DOUT A
DD
SCLK
values are at T = +25°C.)
A
Crosstalk
-90
dB
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
CONVERSION RATE
Throughput
0.03
260
52
3
Msps
ns
Conversion Time
Acquisition Time
Aperture Delay
t
ns
ACQ
From CS falling edge
4
ns
Aperture Jitter
15
ps
Serial-Clock Frequency
ANALOG INPUT (AIN1, AIN2)
Input Voltage Range
Input Leakage Current
f
0.48
0
48
MHz
CLK
V
V
V
AIN_
DD
I
0.002
20
±1
µA
ILA
Track
Hold
Input Capacitance
C
pF
AIN_
4
DIGITAL INPUTS (SCLK, CS, CHSEL)
0.75 x
Digital Input High Voltage
V
V
V
V
IH
V
DD
0.25 x
Digital Input Low Voltage
V
IL
V
DD
0.15 x
Digital Input Hysteresis
V
HYST
V
DD
Digital Input Leakage Current
Digital Input Capacitance
DIGITAL OUTPUT (DOUT)
I
Inputs at GND or V
0.001
2
±1
µA
pF
IL
DD
C
IN
0.85 x
Output High Voltage
Output Low Voltage
V
I
= 200µA
SOURCE
V
V
OH
V
DD
0.15 x
V
I = 200µA
SINK
OL
OL
V
DD
High-Impedance Leakage
Current
I
±1.0
µA
pF
High-Impedance Output
Capacitance
C
4
OUT
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MAX19777
3Msps, Low-Power, Serial 12-Bit ADC
Electrical Characteristics (continued)
(V
= 2.2V to 3.3V. f
= 48MHz, 50% duty cycle, 3Msps. C
= 10pF, T = -40°C to +125°C, unless otherwise noted. Typical
DOUT A
DD
SCLK
values are at T = +25°C.)
A
PARAMETER
POWER SUPPLY
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Positive Supply Voltage
V
2.2
3.3
3.6
V
DD
Positive Supply Current
(Full-Power Mode)
I
I
Full-Power Mode, 2Msps
2.8
2.0
mA
VDD
VDD
Positive Supply Current (Full-
Power Mode), No Clock
mA
Full-Power Mode, No Clock
Leakage only
2.8
10
Power-Down Current
Line Rejection
I
1.3
0.7
µA
PD
V
= +2.2V to +3.3V
LSB/V
DD
TIMING CHARACTERISTICS (Note 1)
Quiet Time
t
(Note 2)
(Note 2)
(Note 2)
4
10
5
ns
ns
ns
Q
CS Pulse Width
t
1
2
CS Fall to SCLK Setup
t
CS Falling Until DOUT High-
Impedance Disabled
t
t
(Note 2)
Figure 2
1
ns
ns
3
4
Data Access Time After SCLK
Falling Edge
23
SCLK Pulse Width Low
SCLK Pulse Width High
t
t
Percentage of clock period (Note 2)
Percentage of clock period (Note 2)
40
40
60
60
%
%
5
6
Data Hold Time From SCLK
Falling Edge
t
t
Figure 3
5
ns
7
8
SCLK Falling Until DOUT High-
Impedance
Figure 4 (Note 2)
2.5
14
1
ns
Power-Up Time
Conversion cycle (Note 2)
Cycle
Note 1: All timing specifications given are with a 10pF capacitor.
Note 2: Guaranteed by design in characterization; not production tested.
Limits are 100% tested at T =25°C. Limits over the operating temperature range and relevant supply voltage range are
guaranteed by design and characterization.
Note 3:
A
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MAX19777
3Msps, Low-Power, Serial 12-Bit ADC
SAMPLE
SAMPLE
t
1
t
t
5
6
CS
t
2
SCLK
16
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
1
0
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
0
HIGH
IMPEDANCE
HIGH
IMPEDANCE
DOUT
(MSB)
t
t
t
t
t
8 QUIET
3
4
7
t
t
ACQ
CONVERT
1/f
SAMPLE
Figure 1. Interface Signals for Maximum Throughput, 12-Bit Devices
t
7
t
4
SCLK
DOUT
SCLK
V
V
IH
V
IH
OLD DATA
NEW DATA
OLD DATA
NEW DATA
DOUT
IL
V
IL
Figure 2. Setup Time After SCLK Falling Edge
Figure 3. Hold Time After SCLK Falling Edge
t
8
SCLK
HIGH IMPEDANCE
DOUT
Figure 4. SCLK Falling Edge DOUT Three-State
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MAX19777
3Msps, Low-Power, Serial 12-Bit ADC
Typical Operating Characteristics
(MAX19777AZA+, T = +25°C, unless otherwise noted.)
A
INTEGRAL NONLINEARITY vs.
DIFFERENTIAL NONLINEARITYvs.
DIGITAL OUTPUT CODE
OFFSET ERROR
vs. TEMPERATURE
DIGITAL OUTPUT CODE
toc 01
toc 02
toc 03
1
0.5
0
1
0.5
0
5
4
3
2
1
0
-0.5
-1
-0.5
-1
0
1000
2000
3000
4000
0
1000
2000
3000
4000
-40 -25 -10
5
20 35 50 65 80 95 110 125
DIGITAL OUTPUT CODE)
DIGITAL OUTPUT CODE)
TEMPERATURE (°C)
GAIN ERROR
vs. TEMPERATURE
SNR, SINAD vs. INPUT FREQUENCY
HISTOGRAM FOR30,000 CONVERSIONS
toc 06
toc 04
toc 05
5
4
3
2
1
0
72
71
70
69
68
35000
SNR
30000
25000
20000
15000
10000
5000
0
SINAD
-40 -25 -10
5
20 35 50 65 80 95 110 125
0
20 40 60 80 100 120 140 160 180 200
INPUT FREQUENCY (kHz)
TEMPERATURE (°C)
OUTPUT CODE
THD vs. INPUT FREQUENCY
SFDR vs. INPUT FREQUENCY
toc 07
toc 08
-75
-80
-85
-90
-95
-75
-80
-85
-90
-95
-100
0
20 40 60 80 100 120 140 160 180 200
INPUT FREQUENCY (kHz)
0
20 40 60 80 100 120 140 160 180 200
INPUT FREQUENCY (kHz)
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MAX19777
3Msps, Low-Power, Serial 12-Bit ADC
Typical Operating Characteristics (continued)
(MAX19777AZA+, T = +25°C, unless otherwise noted.)
A
10kHz SINE WAVE INPUT
(16,384-POINT FFT PLOT)
THD vs.
INPUT RESISTANCE
toc 09
toc 10
-75
-80
0
fS = 2Msps
IN = 9.886kHz
f
-20
-40
-85
-60
-90
-80
-95
-100
-120
-100
0
20
40
60
80
100
0
500
1000
1500
INPUT RESISTANCE (Ω)
FREQUENCY (kHz)
SNR vs.
ANALOG SUPPLY CURRENT
SUPPLY VOLTAGE (REFERENCE)
vs. TEMPERATURE
toc 12
toc 11
2.5
2.4
2.3
2.2
2.1
2
73
72
71
70
69
68
67
66
65
64
VDD = 3.0V
VDD = 2.2V
-40 -25 -10
5
20 35 50 65 80 95 110 125
TEMPERATURE (°C)
2.2
2.4
2.6
2.8
3
3.2
SUPPLY VOLTAGE (V)
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MAX19777
3Msps, Low-Power, Serial 12-Bit ADC
Bump Configuration
TOP VIEW
MAX19777
3
1
2
4
AIN1
AIN2
GND
V
DD
A
B
SCLK
CS
CHSEL
DOUT
8 WLP
Bump Descriptions
PIN
NAME
FUNCTION
A1
AIN1
Analog Input Channel 1. Single-ended analog input with respect to GND with range of 0V to V
.
DD
A2
A3
A4
AIN2
GND
Analog Input Channel 2. Single-ended analog input with respect to GND with range of 0V to V
Ground. Connect GND directly the GND ground plane.
DD.
Positive Supply Voltage. Bypass V
with a 10µF || 0.1µF capacitor to GND. V
range is 2.2V to 3.3V. For
DD
DD
V
DD
the WLP, V
also defines the signal range of the input signal AIN: 0V to V
.
DD
DD
Serial Clock Input. SCLK drives the conversion process. DOUT is updated on the falling edge of SCLK. See
Figure 2 and Figure 3.
B1
B2
B3
B4
SCLK
Active-Low Chip-Select Input. The falling edge of CS samples the analog input signal, starts a conversion,
and frames the serial data transfer.
CS
CHSEL Channel Select. Set CHSEL high to select AIN2 for conversion. Set CHSEL low to select AIN1 for conversion.
Three-State Serial Data Output. ADC conversion results are clocked out on the falling edge of SCLK, MSB
first. See Figure 1.
DOUT
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MAX19777
3Msps, Low-Power, Serial 12-Bit ADC
Functional Diagrams
V
DD
MAX19777
CS
SCLK
CONTROL
LOGIC
DOUT
OUTPUT
BUFFER
SAR
CHSEL
AIN1
AIN2
MUX
CDAC
GND
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MAX19777
3Msps, Low-Power, Serial 12-Bit ADC
Serial Interface
Detailed Description
The device features a 3-wire serial interface that directly
connects to SPI, QSPI, and MICROWIRE device without
external logic. Figure 1 and Figure 5 show the interface
signals for a single conversion frame to achieve maximum
throughput.
The MAX19777 is a fast, 12-bit, low-power, single-supply
ADC. The device operates from a 2.2V to 3.3V supply and
consume only 8.4mW (V
= 3V)/6.2mW (V
= 2.2V) at
DD
DD
3Msps. The 3Msps device is capable of sampling at full
rate when driven by a 48MHz clock.
The falling-edge of CS defines the sampling instant.
Once CS transitions low, the external clock signal (SCLK)
controls the conversion.
The conversion result appears at DOUT, MSB first, with a
leading zero followed by the 12-bit result. A 12-bit result is
followed by two trailing zeros. See Figure 1 and Figure 5.
The SAR core successively extracts binary-weighted
bits in every clock cycle. The MSB appears on the data
bus during the 2nd clock cycle with a delay outlined in
the timing specifications. All extracted data bits appear
successively on the data bus with the LSB appearing
during the 13th clock cycle for 12-bit operation. The serial
data stream of conversion bits is preceded by a leading
“zero” and succeeded by trailing “zeros.” The data output
(DOUT) goes into high-impedance state during the 16th
clock cycle.
The input signal range for AIN1/AIN2 is defined as 0V to
V
DD
with respect to GND.
This ADC includes a power-down feature allowing
minimized power consumption at 2.5µA/ksps for lower
throughput rates. The wake up and power-down feature
is controlled by using the SPI interface as described in the
Operating Modes section.
To sustain the maximum sample rate, the device has to be
resampled immediately after the 16th clock cycle. For lower
sample rates, the CS falling edge can be delayed leaving
DOUT in a high-impedance condition. Pull CS high after the
10th SCLK falling edge (see the Operating Modes section).
SAMPLE
SAMPLE
CS
SCLK
DOUT
16
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
1
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
HIGH
IMPEDANCE
HIGH
IMPEDANCE
Figure 5. 12-Bit Timing Diagrams
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MAX19777
3Msps, Low-Power, Serial 12-Bit ADC
amp, such as the MAX4430, to drive the analog input,
thereby decoupling the signal source and the ADC.
Analog Input
The devices produce a digital output that corresponds to
the analog input voltage within the specified operating
While the ADC is in conversion mode, the sampling switch
is open presenting a pin capacitance, C (C = 5pF),
range of 0 to V
for the dual-channel device.
DD
P
P
to the driving stage. See the Applications Information
section for information on choosing an appropriate buffer
for the ADC.
Figure 6 shows an equivalent circuit for the analog input
AIN1/AIN2. Internal protection diodes D1/D2 confine the
analog input voltage within the power rails (V , GND).
DD
The analog input voltage can swing from GND - 0.3V to
ADC Transfer Function
The output format is straight binary. The code transitions
midway between successive integer LSB values such
V
DD
+ 0.3V without damaging the device.
The electric load presented to the external stage driv-
ing the analog input varies depending on which mode
the ADC is in: track mode vs. conversion mode. In track
as 0.5 LSB, 1.5 LSB, etc. The LSB size for dual-channel
n
devices is V /2 , where n is the resolution. The ideal
DD
mode, the internal sampling capacitor C (16pF) has to
S
transfer characteristic is shown in Figure 10.
be charged through the resistor R (R = 50Ω) to the input
voltage. For faithful sampling of the input, the capacitor
Operating Modes
voltage on C has to settle to the required accuracy
during the track time.
The ICs offer two modes of operation: normal mode and
power-down mode. The logic state of the CS signal during
a conversion activates these modes. The power-down
mode can be used to optimize power dissipation with
respect to sample rate.
S
The source impedance of the external driving stage in
conjunction with the sampling switch resistance affects
the settling performance. The THD vs. Input Resistance
graph in the Typical Operating Characteristics shows THD
sensitivity as a function of the signal source impedance. Keep
the source impedance at a minimum for high dynamic
performance applications. Use a high-performance op
Normal Mode
In normal mode, the devices are powered up at all times,
thereby achieving their maximum throughput rates. Figure
7 shows the timing diagram of these devices in normal
mode. The falling edge of CS samples the analog input signal,
starts a conversion, and frames the serial data transfer.
SWITCH CLOSED IN TRACK MODE
SWITCH OPEN IN CONVERSION MODE
V
DD
To remain in normal mode, keep CS low until the falling
edge of the 10th SCLK cycle. Pulling CS high after the
10th SCLK falling edge keeps the part in normal mode.
However, pulling CS high before the 10th SCLK falling
edge terminates the conversion, DOUT goes into high-
impedance mode, and the device enters power-down
mode. See Figure 8.
D1
D2
C
S
R
AIN1/AIN2
AIN
C
P
Figure 6. Analog Input Circuit
KEEP CS LOW UNTIL AFTER THE 10TH SCLK FALLING EDGE
PULL CS HIGH AFTER THE 10TH SCLK FALLING EDGE
CS
SCLK
DOUT
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
VALID DATA
HIGH
HIGH
IMPEDANCE
IMPEDANCE
Figure 7. Normal Mode
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MAX19777
3Msps, Low-Power, Serial 12-Bit ADC
PULL CS HIGH AFTER THE 2ND AND BEFORE THE 10TH SCLK FALLING EDGE
CS
SCLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
DOUT
HIGH
IMPEDANCE
INVALID
DATA
INVALID DATA OR HIGH IMPEDANCE
HIGH IMPEDANCE
Figure 8. Entering Power-Down Mode
CS
SCLK
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
N
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
DOUT
HIGH
IMPEDANCE
INVALID DATA (DUMMY CONVERSION)
VALID DATA
HIGH
IMPEDANCE
HIGH
IMPEDANCE
Figure 9. Exiting Power-Down Mode
Power-Down Mode
In power-down mode, all bias circuitry is shut down draw-
ing typically only 1.3µA of leakage current. To save power,
put the device in power-down mode between conver-
sions. Using the power-down mode between conversions
is ideal for saving power when sampling the analog input
infrequently.
OUTPUT CODE
FS - 1.5 x LSB
111...111
111...110
111...101
Entering Power-Down Mode
To enter power-down mode, drive CS high between the
2nd and 10th falling edges of SCLK (see Figure 8). By
pulling CS high, the current conversion terminates and
DOUT enters high impedance.
000...010
000...001
000...000
Exiting Power-Down Mode
ANALOG
INPUT (LSB)
To exit power-down mode, implement one dummy
conversion by driving CS low for at least 10 clock cycles
(see Figure 9). The data on DOUT is invalid during this
dummy conversion. The first conversion following the
dummy cycle contains a valid conversion result.
n
n
n
0
1
2
3
2 -2 2 -1
2
FULL SCALE (FS):
AIN1/AIN2 = V (WLP)
DD
n = RESOLUTION
The power-up time equals the duration of the dummy
cycle, and is dependent on the clock frequency. The power-
up time for 3Msps operation (48MHz SCLK) is 333ns.
Figure 10. ADC Transfer Function
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MAX19777
3Msps, Low-Power, Serial 12-Bit ADC
The user can also power down the ADC between conversions
by using the power-down mode. Figure 12 shows for the
3Msps device that as the sample rate is reduced, the
device remains in the power-down state longer and the
Supply Current vs. Sampling Rate
For applications requiring lower throughput rates, the
user can reduce the clock frequency (f
) to lower the
SCLK
sample rate. Figure 11 shows the typical supply current
(I ) as a function of sample rate (f ) for the 3Msps
average supply current (I
) drops accordingly.
VDD
VDD
S
devices. The part operates in normal mode and is never
powered down.
5
5
VDD=3V
VDD=3V
fSCLK= VARIABLE
16 CYCLE/CONVERSION
fSCLK= VARIABLE
16 CYCLES/CONVERSION
4
4
3
2
1
0
3
2
1
0
0
500
1000 1500 2000 2500 3000
fS (ksps)
0
300
600
900
fS (ksps)
1200
1500
Figure 11. Supply Current vs. Sample Rate (Normal Operating
Mode, 3Msps Devices)
Figure 12. Supply Current vs. Sample Rate (Device Powered
Down Between Conversions, 3Msps Devices)
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MAX19777
3Msps, Low-Power, Serial 12-Bit ADC
Dual-Channel Operation
Applications Information
The MAX19777 features dual-input channels. This device
uses a channel-select (CHSEL) input to select between
analog input AIN1 (CHSEL = 0) or AIN2 (CHSEL = 1).
As shown in Figure 13, the CHSEL signal is required
to change between the 2nd and 12th clock cycle within
a regular conversion to guarantee proper switching
between channels.
Layout, Grounding, and Bypassing
For best performance, use PCBs with a solid ground
plane. Ensure that digital and analog signal lines are
separated from each other. Do not run analog and digital
(especially clock) lines parallel to one another or digital
lines underneath the ADC package. Noise in the V
DD
power supply affects the ADC’s performance. Bypass
to ground with 0.1µF and 10µF bypass capacitors.
V
14-Cycle Conversion Mode
DD
Minimize capacitor lead and trace lengths for best supply-
noise rejection.
The ICs can operate with 14 cycles per conversion.
Figure 14 shows the corresponding timing diagram.
Observe that DOUT does not go into high-impedance
Choosing an Input Amplifier
mode. Also, observe that t
needs to be sufficiently
ACQ
It is important to match the settling time of the input amplifier
to the acquisition time of the ADC. The conversion results
are accurate when the ADC samples the input signal
for an interval longer than the input signal’s worst-case
settling time. By definition, settling time is the interval
between the application of an input voltage step and the
long to guarantee proper settling of the analog input
voltage. See the Electrical Characteristics table for t
ACQ
requirements and the Analog Input section for a description
of the analog inputs.
CS
SCLK
CHSEL
DOUT
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
DATA CHANNEL AIN1
DATA CHANNEL AIN2
Figure 13. Channel Select Timing Diagram
SAMPLE
SAMPLE
CS
SCLK
DOUT
1
2
3
4
5
6
7
8
9
10
11
12
13
14
1
0
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
0
(MSB)
t
ACQ
1/f
SAMPLE
t
CONVERT
Figure 14. 14-Clock Cycle Operation
Maxim Integrated
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MAX19777
3Msps, Low-Power, Serial 12-Bit ADC
point at which the output signal reaches and stays within
a given error band centered on the resulting steady-state
amplifier output level. The ADC input sampling capacitor
charges during the sampling cycle, referred to as the
acquisition period. During this acquisition period, the
settling time is affected by the input resistance and the
input sampling capacitance. This error can be estimated
by looking at the settling of an RC time constant using
the input capacitance and the source impedance over the
acquisition time period.
Figure 15 shows a typical application circuit. The
MAX4430, offering a settling time of 37ns at 16 bits, is
an excellent choice for this application. See the THD
vs. Input Resistance graph in the Typical Operating
Characteristics.
+5V
0.1µF
10µF
3V
100pF COG
V
DD
500Ω
10µF
0.1µF
GND
AIN1
500Ω
5
AIN1
4
3
10Ω
MAX19777
1
MAX4430
470pF
COG CAPACITOR
-5V
SCLK
DOUT
CS
SCK
MISO
SS
V
DC
2
AIN2
470pF
COG CAPACITOR
CPU
0.1µF
10µF
CHSEL
+5V
0.1µF
10µF
100pF COG
500Ω
500Ω
5
AIN2
4
10Ω
1
MAX4430
-5V
V
3
DC
2
0.1µF
10µF
Figure 15. Typical Application Circuit
Maxim Integrated
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MAX19777
3Msps, Low-Power, Serial 12-Bit ADC
Signal-to-Noise Ratio and
Distortion (SINAD)
Definitions
For the MAX19777, V
is internally tied to V
.
REF
DD
SINAD is a dynamic figure of merit that indicates the
converter’s noise and distortion performance. SINAD is
computed by taking the ratio of the RMS signal to the
RMS noise plus distortion. RMS noise plus distortion
includes all spectral components to the Nyquist frequency
excluding the fundamental and the DC offset:
Integral Nonlinearity
Integral nonlinearity (INL) is the deviation of the values
on an actual transfer function from a straight line. For this
device, the straight line is a line drawn between the end
points of the transfer function after offset and gain errors
are nulled.
SIGNAL
Differential Nonlinearity
RMS
SINAD(dB) = 20 × log
NOISE + DISTORTION
(
)
Differential nonlinearity (DNL) is the difference between
an actual step width and the ideal value of 1 LSB. A DNL
error specification of ±1 LSB or less guarantees no missing
codes and a monotonic transfer function.
RMS
Total Harmonic Distortion
Total harmonic distortion (THD) is the ratio of the RMS
sum of the first five harmonics of the input signal to the
fundamental itself. This is expressed as:
Offset Error
The deviation of the first code transition (00 . . . 000) to
(00 . . . 001) from the ideal, that is, AGND + 0.5 LSB.
2
2
2
2
V
+ V + V + V
3 4 5
2
THD = 20× log
Gain Error
V
1
The deviation of the last code transition (111 . . . 110) to
(111 . . . 111) from the ideal after adjusting for the offset
where V is the fundamental amplitude and V –V are
the amplitudes of the 2nd- through 5th-order harmonics.
1
2
5
error, that is, V
- 1.5 LSB.
REF
Aperture Jitter
Spurious-Free Dynamic Range (SFDR)
Aperture jitter (t ) is the sample-to-sample variation in
AJ
SFDR is a dynamic figure of merit that indicates the low-
est usable input signal amplitude. SFDR is the ratio of
the RMS amplitude of the fundamental (maximum signal
component) to the RMS value of the next largest spurious
component, excluding DC offset. SFDR is specified in
decibels with respect to the carrier (dBc).
the time between the samples.
Aperture Delay
Aperture delay (t ) is the time between the falling edge
AD
of sampling clock and the instant when an actual sample
is taken.
Full-Power Bandwidth
Signal-to-Noise Ratio (SNR)
Full-power bandwidth is the frequency at which the input
signal amplitude attenuates by 3dB for a full-scale input.
SNR is a dynamic figure of merit that indicates the
converter’s noise performance. For
a
waveform
perfectlyreconstructedfromdigitalsamples, thetheoretical
maximum SNR is the ratio of the full-scale analog input
(RMS value) to the RMS quantization error (residual
error). The ideal, theoretical minimum analog-to-digital
noise is caused by quantization error only and results
directly from the ADC’s resolution (N bits):
Full-Linear Bandwidth
Full-linear bandwidth is the frequency at which the signal-
to-noise ratio and distortion (SINAD) is equal to a specified
value.
Intermodulation Distortion
Any device with nonlinearities creates distortion products
SNR (dB) (MAX) = (6.02 x N + 1.76) (dB)
when two sine waves at two different frequencies (f and
1
In reality, there are other noise sources such as thermal
noise, reference noise, and clock jitter that also degrade
SNR. SNR is computed by taking the ratio of the RMS
signal to the RMS noise. RMS noise includes all spectral
components to the Nyquist frequency excluding the
fundamental, the first five harmonics, and the DC offset.
f ) are applied into the device. Intermodulation distortion
2
(IMD) is the total power of the IM2 to IM5 intermodulation
products to the Nyquist frequency relative to the total
input power of the two input tones, f and f . The
1
2
individual input tone levels are at -6dBFS.
Maxim Integrated
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MAX19777
3Msps, Low-Power, Serial 12-Bit ADC
Package Information
For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”,
“#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing
pertains to the package regardless of RoHS status.
PACKAGE TYPE
PACKAGE CODE
OUTLINE NO.
21-100166
LAND PATTERN NO.
8 WLP
Z80B1+1
Refer to Application Note 1891
COMMON DIMENSIONS
Pin 1
Indicator
E
see Note 7
A
0.02
0.01
0.35
0.08
Marking
1
A1
A2
A
0.27 REF
AAAA
D
A3
b
BASIC
0.040
0.21
0.03
0.025
0.025
BASIC
BASIC
D
0.857
1.432
TOP VIEW
SIDE VIEW
E
D1
E1
0.35
1.05
A3
A1
e
0.35 BASIC
0.175 BASIC
0.175 BASIC
S
A2
A
SD
SE
0.05
S
DEPOPULATED BUMPS:
NONE
FRONT VIEW
E1
e
NOTES:
SE
1. Terminal pitch is defined by terminal center to center value.
2. Outer dimension is defined by center lines between scribe lines.
3. All dimensions in millimeter.
SD
D1
B
4. Marking shown is for package orientation reference only.
5. Tolerance is ± 0.02 unless specified otherwise.
B
6. All dimensions apply to PbFree (+) package codes only.
7. Front - side finish can be either Black or Clear.
A
1
234
b
0.05
maxim
A
M
S
AB
TM
integrated
TITLPE ACKAGE OUTLINE 8 BUMPS
BOTTOM VIEW
ULTRA THIN WLP PKG. 0.35 mm PITCH, Z80B1+1
REV.
DOCUMENT CO2NT1RO-L1N0O.0166
A
APPROVAL
1
- DRAWING NOT TO SCALE -
1
Maxim Integrated
│
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MAX19777
3Msps, Low-Power, Serial 12-Bit ADC
Ordering Information
PART
MAX19777AZA+
MAX19777AZA+T
PIN-PACKAGE
BITS
12
SPEED (Msps)
NO. OF CHANNELS
TOP MARK
AAAH
8 WLP
8 WLP
3
3
2
2
12
AAAH
Note: Devices specified over the -40°C to +125°C operating temperature range.
+Denotes a lead(Pb)-free/RoHS-compliant package.
T= Tape and reel.
Chip Information
PROCESS: CMOS
Maxim Integrated
│ 18
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MAX19777
3Msps, Low-Power, Serial 12-Bit ADC
Revision History
REVISION REVISION
PAGES
CHANGED
DESCRIPTION
NUMBER
DATE
0
11/17
Initial release
—
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim Integrated’s website at www.maximintegrated.com.
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses
are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits)
shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
©
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.
2017 Maxim Integrated Products, Inc.
│ 19
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