MAX1887 [MAXIM]
Quick-PWM Slave Controllers for Multiphase, Step-Down; 的Quick-PWM从控制器，用于多相，降压型
| 型号： | MAX1887 |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Quick-PWM Slave Controllers for Multiphase, Step-Down |
| 文件： | 总33页 (文件大小：1015K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-2188; Rev 1; 9/02
Quick-PWM Slave Controllers for
Multiphase, Step-Down Supplies
General Description
Features
The MAX1887/MAX1897 step-down slave controllers are
intended for low-voltage, high-current, multiphase DC-to-
DC applications. The MAX1887/MAX1897 slave con-
trollers can be combined with any of Maxim’s
Quick-PWM™ step-down controllers to form a multiphase
DC-to-DC converter. Existing Quick-PWM controllers,
such as the MAX1718, function as the master controller,
providing accurate output voltage regulation, fast tran-
sient response, and fault protection features.
Synchronized to the master’s low-side gate driver, the
MAX1887/MAX1897 include the Quick-PWM constant on-
time controller, gate drivers for a synchronous rectifier,
active current balancing, and precision current-limit cir-
cuitry.
o Quick-PWM Slave Controller
o Precise, Active Current Balance (±±1.25m ꢀ
o Accurate, Adjustable Current-Li5it Threshold
o Opti5ized for Low-Output moltages (≤.mꢀ
o 4m to .8m Battery Input Range
o Fixed 300kHz (MAX±887ꢀ or Selectable
.00kHz/300kHz/220kHz (MAX±897ꢀ Switching
Frequency
o Drive Large Synchronous-Rectifier MOSFETs
o 2.2µA (typꢀ I
Supply Current
CC
o .0µA Standby Supply Current
The MAX1887/MAX1897 provide the same high effi-
ciency, ultra-low duty factor capability, and excellent
transient response as other Quick-PWM controllers. The
MAX1887/MAX1897 differentially sense the inductor
currents of both the master and the slave across cur-
rent-sense resistors. These differential inputs and the
adjustable current-limit threshold derived from an exter-
nal reference allow the slave controller to accurately
balance the inductor currents and provide precise cur-
rent-limit protection. The MAX1887/MAX1897’s dual-
purpose current-limit input also allows the slave
controller to automatically enter a low-power standby
mode when the master controller shuts down.
o <±µA Shutdown (MAX±897ꢀ Supply Current
o S5all ±6-Pin QSOP (MAX±887ꢀ, Co5pact
.0-Pin 255 x 255 QFN (MAX±897ꢀ, or
.0-Pin 255 x 255 Thin QFN (MAX±897ꢀ
Ordering Information
PART
TEMP RANGE
PIN-PACKAGE
MAX±887EEE -40°C to +85°C 16 QSOP
MAX±897EGP*
✕
-40°C to +85°C 20 QFN 5mm 5mm
✕
MAX1897ETP -40°C to +85°C 20 Thin QFN 5mm 5mm
The MAX1887 triggers on the rising edge of the mas-
ter’s low-side gate driver, which staggers the on-times
of both master and slave, providing out-of-phase oper-
ation that can reduce the input ripple current and con-
sequently the number of input capacitors. The
MAX1897 features a selectable trigger polarity, allowing
out-of-phase or simultaneous in-phase operation.
*Contact factory for availability.
Pin Configuration
TOP VIEW
20
19 18
17 16
Applications
CM+
CM-
TON
LX
1
2
3
4
5
15
14
13
12
11
Notebook Computers
CPU Core Supply
DH
Single-Stage (BATT to V
) Converters
CORE
SHDN
MAX1897
Two-Stage (5V to V
) Converters
CORE
CS-
CS+
V
V
CC
DD
Servers/Desktop Computers
Telecom
6
7
8
9
10
Typical Operating Circuit appears at end of data sheet.
THIN QFN 255 x 255
Pin Configurations continued at end of data sheet.
Quick-PWM is a registered trademark of Maxim Integrated
Products, Inc.
________________________________________________________________ Maxim Integrated Products
±
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
Quick-PWM Slave Controllers for
Multiphase, Step-Down Supplies
ABSOLUTE MAXIMUM RATINGS
V+ to GND..............................................................-0.3V to +30V
, V to GND (Note 3) .......................................-0.3V to +6V
PGND to GND..................................................................... 0.3V
TRIG, LIMIT to GND .................................................-0.3V to +6V
SHDN to GND (MAX1897)........................................-0.3V to +6V
ILIM, CM+, CM-, CS+, CS-, COMP
DH to LX....................................................-0.3V to (V
LX to BST..................................................................-6V to +0.3V
+ 0.3V)
BST
V
CC DD
Continuous Power Dissipation (T = +70°C)
A
16-Pin QSOP (derate 8.3mW/°C above +70°C)...........667mW
20-Pin 5mm x 5mm QFN (derate 20.0mW/°C
above +70°C)..............................................................1.60W
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range.............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
to GND....................................................-0.3V to (V
TON, POL to GND (MAX1897) ...................-0.3V to (V
DL to PGND................................................-0.3V to (V
+ 0.3V)
+ 0.3V)
+ 0.3V)
CC
CC
DD
BST to GND............................................................-0.3V to +36V
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(Circuit of Figure 1, V+ = 15V, V
= V
= 5V, V
= V
= 1.2V, V
= V
= V
= V
= 1.2V, SHDN = V
CS- CC
CC
DD
OUT
COMP
CM+
CM-
CS+
(MAX1897), T = 0°C to +82°C, unless otherwise noted. Typical values are at T = +25°C.)
A
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
PWM CONTROLLER
Battery voltage, V+
, V
4.0
4.5
28.0
5.5
Input Voltage Range
On-Time (Note 1)
V
V
CC DD
MAX1887 (300kHz), V+ = 12V, V
= 1.2V
320
171
320
464
355
390
209
390
566
COMP
TON = GND
TON = open
190
355
515
75
MAX1897,
V+ = 12V,
t
ns
ns
ON
V
= 1.2V
COMP
TON = V
CC
Trigger Delay (Note 2)
t
TRIG
I+
SUPPLY CURRENTS
Quiescent Supply Current (V+)
Measured at V+; V
> 0.35V
25
525
<1
40
800
5
µA
µA
ILIM
MAX1887
MAX1897
Quiescent Supply Current (V
(Note 3)
)
)
Measured at V ; V
DD ILIM
> 0.35V
DD
I
DD
Quiescent Supply Current (V
(MAX1897, Note 3)
CC
I
Measured at V ; V > 0.35V
CC ILIM
525
800
µA
µA
µA
CC
Standby Supply Current (V+)
Measured at V+; ILIM = GND
<1
20
<1
5
40
5
MAX1887
MAX1897
Standby Supply Current (V
(Note 3)
)
)
Measured at V ; ILIM
DD
= GND
DD
Standby Supply Current (V
(MAX1897, Note 3)
CC
Measured at V ; ILIM = GND
20
<1
<1
<1
40
5
µA
µA
µA
µA
CC
Shutdown Supply Current (V+)
(MAX1897)
Measured at V+; V
= V
= 0 or 5V,
DD
CC
SHDN = GND
Shutdown Supply Current (V
(MAX1897, Note 3)
)
DD
Measured at V ; SHDN = GND
5
DD
Shutdown Supply Current (V
(MAX1897, Note 3)
)
CC
Measured at V ; SHDN = GND
5
CC
.
_______________________________________________________________________________________
Quick-PWM Slave Controllers for
Multiphase, Step-Down Supplies
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, V+ = 15V, V
= V
= 5V, V
= V
= 1.2V, V
= V
= V
= V
= 1.2V, SHDN = V
CS- CC
CC
DD
OUT
COMP
CM+
CM-
CS+
(MAX1897), T = 0°C to +85°C, unless otherwise noted. Typical values are at T = +25°C.)
A
A
PARAMETER
CURRENT SENSING
On-Time Adjustment Range
COMP Output Current
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
0.42 < V
< 2.8V, V
≥ 0.7V
-40
30
+40
%
COMP
OUT
I
Sink and source
µA
COMP
(V
(V
- V
) -
CM+
CM-
MAX1887
MAX1897
-1.25
-1.25
+1.25
+1.25
- V ), I
CS- COMP
=
CS+
Current-Balance Offset
mV
mS
0, -100mV ≤ (V
-
CM+
V
) ≤ +100mV
CM-
Current-Balance
Transconductance
(V
CM+
- V
CM-
) - (V
- V ) = 25mV
CS-
1.2
CS+
Current-Sense, Common-Mode
Range
CM+, CM-, CS+, CS-
CM+, CM-, CS+, CS-
-0.2
+2.0
V
Current-Sense Input Current
-1
+1
52.5
102.5
-70
µA
mV
V
V
V
V
= 0.5V
= 1V
47.5
97.5
-80
50.0
100.0
-75
ILIM
ILIM
ILIM
ILIM
V
V
- V
and
CM+
CS+
CM-
Positive Current-Limit Threshold
V
C_LIM
- V
CS-
= 0.5V
= 1V
Negative Current-Limit
Threshold
V
- V
CS-
mV
CS+
-160
0.2
-150
-140
0.3
ILIM Standby Threshold Voltage
ILIM Input Current
V
-100
+100
nA
µs
V
LIMIT Propagation Delay
LIMIT Output Low Voltage
LIMIT Leakage Current
FAULT PROTECTION
t
Falling edge, 3mV over trip threshold
= 1mA
1.5
LIMIT
V
I
0.1
OL(LIMIT)
SINK
I
LIMIT forced to 5.5V
< 0.01
1.00
µA
LIMIT
V
/V
Undervoltage Lockout
Rising edge, hysteresis = 20mV, switching
disabled below this level
CC DD
3.45
3.85
V
Threshold (Note 3)
Thermal Shutdown Threshold
GATE DRIVERS
Rising, hysteresis = 15°C (typ)
160
°C
MAX1887
1.0
1.0
1.0
1.0
0.4
0.4
3.5
4.5
3.5
4.5
1.0
2.0
DH Gate-Driver On-Resistance
(Note 4)
R
V
- V forced to 5V
Ω
Ω
A
ON(DH)
BST
LX
MAX1897
MAX1887
MAX1897
MAX1887
MAX1897
High state (pullup)
DL Gate-Driver On-Resistance
(Note 4)
R
ON(DL)
Low state (pulldown)
DH Gate-Driver Source/Sink
Current
I
DH forced to 2.5V, V
- V forced to 5V
LX
1.3
DH
BST
DL Gate-Driver Sink Current
I
I
DL forced to 2.5V
DL forced to 2.5V
DL rising
4.0
1.3
35
A
A
DL
DL
DL Gate-Driver Source Current
Dead Time
ns
DH rising
26
_______________________________________________________________________________________
3
Quick-PWM Slave Controllers for
Multiphase, Step-Down Supplies
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, V+ = 15V, V
= V
= 5V, V
= V
= 1.2V, V
= V
= V
= V
= 1.2V, SHDN = V
CS- CC
CC
DD
OUT
COMP
CM+
CM-
CS+
(MAX1897), T = 0°C to +85°C, unless otherwise noted. Typical values are at T = +25°C.)
A
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
LOGIC
Logic Input High Voltage
(MAX1897)
V
SHDN, POL; V
SHDN, POL; V
= 4.5V to 5.5V
= 4.5V to 5.5V
2.4
3.0
V
V
V
IH
CC
Logic Input Low Voltage
(MAX1897)
V
0.8
1.2
IL
CC
High
Low
TRIG Logic Levels
V
350mV hysteresis
TRIG
Logic high (V ; 200kHz operation)
CC
V
- 0.4
CC
TON Logic Levels (MAX1897)
V
Open (300kHz operation)
Logic low (GND; 550kHz operation)
TRIG
1.5
3.1
0.5
+1
+1
+1
+3
V
TON
-1
-1
-2
-2
SHDN (MAX1897)
Logic Input Current
µA
POL (MAX1897)
TON = GND or V
(MAX1897)
DD
ELECTRICAL CHARACTERISTICS
(Circuit of Figure 1, V+ = 15V, V
= V
= 5V, V
= V
= 1.2V, V
= V
= V
= V
= 1.2V, SHDN = V
CS- CC
CC
DD
OUT
COMP
CM+
CM-
CS+
(MAX1897), T = -40°C to +85°C, unless otherwise noted.) (Note 5)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
PWM CONTROLLER
MAX1887 (300kHz), V+ = 12V, V
= 1.2V
320
171
320
464
390
209
390
566
COMP
TON = GND (550kHz)
TON = open (300kHz)
MAX1897,
V+ = 12V,
On Time (Note 3)
t
ns
ON
V
= 1.2V
COMP
TON = V
(200kHz)
CC
SUPPLY CURRENTS
Quiescent Supply Current (V+)
I+
Measured at V+; V
> 0.35V
40
800
5
µA
µA
ILIM
MAX1887
MAX1897
Quiescent Supply Current (V
(Note 3)
)
)
Measured at V
;
DD
DD
I
DD
V
> 0.35V
ILIM
Quiescent Supply Current (V
(MAX1897, Note 3)
CC
I
Measured at V ; V
> 0.35V
800
µA
µA
µA
CC
CC ILIM
Standby Supply Current (V+)
Measured at V+; ILIM = GND
5
40
5
MAX1887
MAX1897
Standby Supply Current (V
(Note 3)
)
)
Measured at V
;
DD
DD
ILIM = GND
Standby Supply Current (V
(MAX1897, Note 3)
CC
Measured at V ; ILIM = GND
40
5
µA
µA
µA
CC
Shutdown Supply Current (V+)
(MAX1897)
Measured at V+; V
= V
= 0 or 5V,
DD
CC
SHDN = GND
Shutdown Supply Current (V
(MAX1897, Note 3)
)
DD
Measured at V ; SHDN = GND
5
DD
4
_______________________________________________________________________________________
Quick-PWM Slave Controllers for
Multiphase, Step-Down Supplies
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, V+ = 15V, V
= V
= 5V, V
= V
= 1.2V, V
= V
= V
= V
= 1.2V, SHDN = V
CS- CC
CC
DD
OUT
COMP
CM+
CM-
CS+
(MAX1897), T = -40°C to +85°C, unless otherwise noted.) (Note 5)
A
PARAMETER
SYMBOL
CONDITIONS
Measured at V ; SHDN = GND
MIN
TYP
MAX UNITS
Shutdown Supply Current (V
(MAX1897, Note 3)
)
CC
5
µA
CC
CURRENT SENSING
On-Time Adjustment Range
COMP Output Current
0.42 < V
< 2.8V, V
≥ 0.7V
-40
30
+40
%
COMP
OUT
I
Sink and source
µA
COMP
(V
(V
- V
) -
CM+
CS+
CM-
MAX1887
MAX1897
-2.0
-2.0
-0.2
+2.0
+2.0
+2.0
- V ), I
CS- COMP
= 0,
Current-Balance Offset
mV
-100mV ≤ (V
≤ +100mV
- V
)
CM+
CM-
Current-Sense, Common-Mode
Range
CM+, CM-, CS+, CS-
V
V
V
V
V
= 0.5V
= 1V
47.5
97.5
-80
52.5
102.5
-70
ILIM
ILIM
ILIM
ILIM
V
V
- V
and
CM+
CS+
CM-
Positive Current-Limit Threshold
V
mV
C_LIM
- V
CS-
= 0.5V
= 1V
Negative Current-Limit
Threshold
V
- V
CS-
mV
V
CS+
-160
0.2
-140
0.3
ILIM Standby Threshold Voltage
FAULT PROTECTION
V
/V
Undervoltage Lockout
Rising edge, hysteresis = 20mV, switching
disabled below this level
CC DD
3.45
3.85
V
Ω
Ω
Threshold (Note 3)
GATE DRIVERS
MAX1887
MAX1897
MAX1887
MAX1897
MAX1887
MAX1897
3.5
4.5
3.5
4.5
1.0
2.0
DH Gate-Driver On-Resistance
(Note 4)
V
5V
- V forced to
BST LX
R
R
ON(DH)
High state (pullup)
DL Gate-Driver On-Resistance
(Note 4)
ON(DL)
Low state (pulldown)
LOGIC
High
Low
3.0
TRIG Logic Levels
V
350mV hysteresis
V
V
TRIG
1.2
Logic high (V ; 200kHz operation)
CC
V
- 0.4
CC
TON Logic Levels (MAX1897)
V
TON
Open (300kHz operation)
1.5
3.1
0.5
Logic low (GND; 550kHz operation)
Note 1: On-time and off-time specifications are measured from 50% point to 50% point at the DH pin with LX = PGND, V
= 5V, and a
BST
500pF capacitor from DH to LX to simulate external MOSFET gate capacitance. Actual in-circuit times may be different due to
MOSFET switching speeds.
Note 2: The trigger delay time, t
, is measured from the time the TRIG pin transitions to time when the DL pin goes low.
TRIG
Note 3: The 20-pin MAX1897 has a separate analog PWM supply voltage input (V ) and gate-driver supply input (V ). For the 16-pin
CC
DD
MAX1887 device, the analog PWM supply voltage input and the gate-driver supply voltage input are internally connected and
named V
.
DD
Note 4: Production testing limitations due to package handling require relaxed maximum on-resistance specifications for the MAX1897’s
QFN package. The MAX1887 and MAX1897 contain the same die, and the QFN package imposes no additional resistance in-
circuit.
Note 5: Specifications to -40°C are guaranteed by design and not production tested.
_______________________________________________________________________________________
5
Quick-PWM Slave Controllers for
Multiphase, Step-Down Supplies
Typical Operating Characteristics
(Circuit of Figure 1, V+ = 12V, V
= V
= 5V, V
= 1.3V (ZMODE = GND) and 1V (ZMODE = V ), SHDN = V
(MAX1897))
CC
DD
OUT
CC
CC
TWO-PHASE
EFFICIENCY vs. LOAD CURRENT
TWO-PHASE
EFFICIENCY vs. LOAD CURRENT
TWO-PHASE
OUTPUT VOLTAGE vs. LOAD CURRENT
(V
= 1.3V)
(V
= 1V)
(V
= 1.3V, V
= -10mV)
OUT
OUT
OUT
OFFSET
1.30
100
90
100
90
V
= 12.0V
IN
1.29
1.28
1.27
1.26
1.25
1.24
1.23
1.22
1.21
1.20
V
= 8V
V = 8V
IN
IN
V
= 5V
V = 5V
IN
IN
80
80
70
60
70
60
V
= 12V
V
= 12V
IN
IN
50
40
30
20
50
40
30
20
V
= 20V
V
= 20V
IN
IN
0.1
1
10
100
0
10
20
30
40
50
0.1
1
10
100
LOAD CURRENT (A)
LOAD CURRENT (A)
LOAD CURRENT (A)
INDUCTOR CURRENT BALANCE
vs. LOAD CURRENT
NO-LOAD INPUT CURRENT
vs. INPUT VOLTAGE
TWO-PHASE
OUTPUT VOLTAGE vs. LOAD CURRENT
(V = 1.0V, V = -10mV)
1.0
80
70
60
50
40
30
20
10
0
OUT
OFFSET
1.00
0.99
0.98
0.97
0.96
0.95
0.94
0.93
0.92
V
= 12.0V
IN
0.8
0.6
0.4
I
= I + I
BIAS DD CC
I
IN
0.2
0
MASTER AND SLAVE
0
5
10
15
20
25
30
0
10
20
30
40
50
0
10
20
30
40
INPUT VOLTAGE (V)
LOAD CURRENT (A)
OFFSET VOLTAGE DEVIATION vs.
CURRENT-SENSE COMMON-MODE VOLTAGE
INDUCTOR CURRENT BALANCE
vs. INPUT VOLTAGE
OFFSET VOLTAGE DEVIATION
vs. COMPENSATION VOLTAGE
50
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
0.3
OUT = CM+ = CM- = CS+ = CS-
OUT = CM+ = CM- = CS+ = CS-
0.2
0.1
0
I
= 40A
OUT
25
0
-0.1
-0.2
-0.3
I
= NO LOAD
OUT
-25
-50
0
5
10
15
20
25
-0.5
0
0.5
V
1.0
(V)
1.5
2.0
0
0.5
1.0
1.5
2.0
INPUT VOLTAGE (V)
V
(V)
OUT
COMP
6
_______________________________________________________________________________________
Quick-PWM Slave Controllers for
Multiphase, Step-Down Supplies
Typical Operating Characteristics (continued)
(Circuit of Figure 1, V+ = 12V, V
= V
= 5V, V
= 1.3V (ZMODE = GND) and 1V (ZMODE = V ), SHDN = V
(MAX1897))
CC
DD
OUT
CC
CC
MINIMUM TRIGGER PULSE WIDTH
COMPENSATION OUTPUT CURRENT vs.
CURRENT-SENSE VOLTAGE DIFFERENTIAL
TRIGGER PROPAGATION DELAY
vs. OVERDRIVE VOLTAGE
vs. OVERDRIVE VOLTAGE
500
100
80
500
450
400
350
300
250
200
150
100
50
OUT = CM+ = CM- = CS-
450
400
350
300
250
200
150
100
50
I
= G (V - V
)
COMP
M
CS+
CS-
ON-TIME TRIGGERED
ABOVE THE LINE
60
40
20
RISING (OUT-OF-PHASE)
0
RISING (OUT-OF-PHASE)
FALLING (IN-PHASE)
-20
-40
-60
-80
-100
FALLING (IN-PHASE)
0
0
0
0.5
1.0
1.5
2.0
-150 -100
-50
V
0
50
100
150
0
0.5
1.0
1.5
2.0
OVERDRIVE VOLTAGE (V)
- V (V)
OVERDRIVE VOLTAGE (V)
CS+
CS-
POSITIVE CURRENT-LIMIT THRESHOLD
vs. ILIM VOLTAGE
160
140
120
100
80
60
MASTER OR SLAVE
40
20
0
0
0.5
1.0
1.5
V
(V)
ILIM
_______________________________________________________________________________________
7
Quick-PWM Slave Controllers for
Multiphase, Step-Down Supplies
Typical Operating Characteristics (continued)
(Circuit of Figure 1, V+ = 12V, V
= V
= 5V, V
= 1.3V (ZMODE = GND) and 1V (ZMODE = V ), SHDN = V
(MAX1897))
CC
DD
OUT
CC
CC
SWITCHING WAVEFORMS
(OUT-OF-PHASE)
SWITCHING WAVEFORMS
(IN-PHASE)
MAX1887 toc14
MAX1887 toc15
A
A
20mV/div
20mV/div
B
20A
20A
B
5A/div
5A/div
10V
0
10V
0
C
C
10V/div
10V/div
1µs/div
1µs/div
A. OUTPUT VOLTAGE, V = 1.290V (NO LOAD),
A. OUTPUT VOLTAGE, V
= 1.290V (NO LOAD),
OUT
OUT
B. MASTER/SLAVE INDUCTOR CURRENTS
B. MASTER/SLAVE INDUCTOR CURRENTS
C. MASTER/SLAVE LX WAVEFORMS,
C. MASTER/SLAVE LX WAVEFORMS,
V
IN
= 12.0V, I
= 40A, POL = V (MAX1897)
V
IN
= 12.0V, I
= 40A, POL = GND (MAX1897)
OUT
OUT
CC
LOAD TRANSIENT
(OUT-OF-PHASE)
LOAD TRANSIENT
(IN-PHASE)
MAX1887 toc16
MAX1887 toc17
40A
5A
40A
5A
A
A
40A/div
40A/div
B
B
1.282V
1.282V
50mV/div
50mV/div
C
C
0
0
10A/div
0
10A/div
D
D
0
10A/div
10A/div
20µs/div
20µs/div
A. LOAD CURRENT, I
= 5A TO 40A
OUT
A. LOAD CURRENT, I
= 5A TO 40A
OUT
OUT
OUT
B. OUTPUT VOLTAGE, V
= 1.290V (NO LOAD)
B. OUTPUT VOLTAGE, V
= 1.290V (NO LOAD)
C. SLAVE INDUCTOR CURRENT
C. SLAVE INDUCTOR CURRENT
D. MASTER INDUCTOR CURRENT
V = 12.0V, POL = GND (MAX1897)
IN
D. MASTER INDUCTOR CURRENT
V
IN
= 12.0V, POL = V (MAX1897)
CC
8
_______________________________________________________________________________________
Quick-PWM Slave Controllers for
Multiphase, Step-Down Supplies
Typical Operating Characteristics (continued)
(Circuit of Figure 1, V+ = 12V, V
= V
= 5V, V
= 1.3V (ZMODE = GND) and 1V (ZMODE = V ), SHDN = V
(MAX1897))
CC
DD
OUT
CC
CC
STARTUP WAVEFORM
(NO LOAD)
DYNAMIC OUTPUT VOLTAGE TRANSITION
MAX1887 toc19
MAX1887 toc18
5.0V
0
A
A
5V
5V/div
5V/div
0
B
B
1.3V
1.1V
200mV/div
1V
1.0V/div
0
0
C
C
0
0
10A/div
10A/div
D
D
10A/div
0
10A/div
100µs/div
40µs/div
A. MASTER SHUTDOWN, V
= 0 TO 5V
A. ZMODE = 0 TO 5V
SHDN
= 1.290V (NO LOAD)
B. OUTPUT VOLTAGE, V
B. OUTPUT VOLTAGE, V
= 1.30V (ZMODE = GND)
OUT
OUT
C. SLAVE INDUCTOR CURRENT
D. MASTER INDUCTOR CURRENT
OR 1.10V (ZMODE = V
C. SLAVE INDUCTOR CURRENT
D. MASTER INDUCTOR CURRENT
)
CC
STARTUP WAVEFORM
(20A LOAD)
SHUTDOWN WAVEFORM
MAX1887 toc21
MAX1887 toc20
A
5V
0
5V
0
A
5V/div
5V/div
B
B
1V
0
1.0V/div
1.0V/div
0
C
10A/div
C
0
0
0
0
D
10A/div
D
10A/div
10A/div
100µs/div
100µs/div
A. MASTER SHUTDOWN, V
A. MASTER SHUTDOWN, V
= 0 TO 5V
= 5V TO 0
SHDN
= 1.290V (NO LOAD)
OUT
SHDN
= 1.290V (NO LOAD)
B. OUTPUT VOLTAGE, V
B. OUTPUT VOLTAGE, V
OUT
C. SLAVE INDUCTOR CURRENT
D. MASTER INDUCTOR CURRENT
C. SLAVE INDUCTOR CURRENT
D. MASTER INDUCTOR CURRENT
R
OUT
= 65mΩ (I
= 20A)
OUT
_______________________________________________________________________________________
9
Quick-PWM Slave Controllers for
Multiphase, Step-Down Supplies
Pin Description
PIN
NAME
DESCRIPTION
MAX1887
MAX1897
Dual-Mode Current-Limit Adjustment and Standby Input. The current-limit threshold
voltage is 1/10 the voltage seen at ILIM (V
drops below 250mV, the slave controller enters a low-power standby mode, forcing
DL high and DH low.
) over a 400mV to 1.5V range. If V
ILIM
ILIM
1
19
ILIM
Trigger Input. Connect to the master controller’s low-side gate driver. For the
MAX1887, a rising edge triggers a single cycle. For the MAX1897, the trigger input’s
2
20
TRIG
polarity is pin selectable. POL = V
or floating triggers on the rising edge (out-of-
CC
phase operation), and POL = GND triggers on the falling edge (in-phase operation).
3
4
1
2
CM+
CM-
Master Controller’s Positive Current-Sense Input
Master Controller’s Negative Current-Sense Input
On-Time Selection Control Input. This is a three-level input used to determine the DH
on time (see On-Time Control and Active Current Balancing). For the MAX1897,
connect TON as follows for the indicated switching frequencies:
GND = 550kHz
—
3
TON
floating = 300kHz
V
= 200kHz.
CC
For the MAX1887, the switching frequency is internally configured for 300kHz
operation. The slave controller’s switching frequency should be selected to closely
match the frequency of the master PWM controller.
5
6
4
5
CS-
Slave Controller’s Negative Current-Sense Input
Slave Controller’s Positive Current-Sense Input
CS+
Current Balance Compensation. Connect a series resistor and capacitor between
COMP and OUT. See the Current Balance Compensation section.
7
6
7
COMP
POL
TRIG Polarity Select Input. Connect POL to V or float to trigger on the rising edge of
CC
TRIG (out-of-phase operation). Connect POL to GND to trigger on the falling edge of TRIG
—
(in-phase operation). For the MAX1887, POL is internally connected to V
.
CC
8
9
8
9
GND
Analog Ground. Connect the MAX1897’s exposed pad to analog ground.
PGND
Power Ground
Low-Side Gate-Driver Output. DL swings from PGND to V . DL is forced high
DD
when the MAX1897 enters standby or shutdown mode.
10
10
DL
Supply Voltage Input for the DL Gate Driver. For the MAX1887, V also serves as
DD
the analog supply voltage input that powers the PWM core. Connect to the system
supply voltage (4.5V to 5.5V). Bypass to PGND with a 1µF or greater ceramic
capacitor, as close to the IC as possible.
11
11
V
V
DD
CC
Analog Supply Voltage Input for PWM Core. Connect V
to the system supply
CC
—
—
12
13
voltage (4.5V to 5.5V) through a series 10Ω resistor. Bypass to GND with a 0.22µF
or greater ceramic capacitor, as close to the MAX1897 as possible.
Active-Low Shutdown Input. A logic low shuts down the MAX1897 slave controller,
SHDN
immediately pulling DL high and DH low. Connect to V for normal operation.
CC
10 ______________________________________________________________________________________
Quick-PWM Slave Controllers for
Multiphase, Step-Down Supplies
Pin Description (continued)
PIN
NAME
DESCRIPTION
MAX1887
MAX1897
12
14
DH
LX
High-Side Gate-Driver Output. DH swings from LX to BST.
Inductor Connection. Connect LX to the switched side of the inductor. LX serves as
the lower supply rail for the DH high-side gate driver.
13
14
15
16
Boost Flying-Capacitor Connection. Connect to an external capacitor and diode
according to the Standard Application Circuit (Figure 1). An optional resistor in
series with BST allows DH pullup current to be adjusted.
BST
V+
Battery Voltage Sense Connection. Connect V+ to the input power source. V+ is
used only for PWM one-shot timing (see the On-Time Control and Active Current
Balancing section).
15
16
17
18
Open-Drain Current-Limit Output. Connect to the master controller’s adjustable current-
limit input (ILIM) according to the Standard Application Circuit (Figure 1). When the
voltage across the master controller’s current-sense resistor (V
LIMIT
- V ) exceeds the
CM-
CM+
current-limit threshold (V /10), the MAX1887/MAX1897 pulls LIMIT low.
ILIM
Detailed Description
Table 1. Component Selection for Standard
Applications
The MAX1887/MAX1897 step-down slave controllers
are intended for low-voltage, high-current, multiphase
DC-to-DC applications. The MAX1887/MAX1897 slave
controllers can be combined with any of Maxim’s
Quick-PWM step-down controllers to form a multiphase
DC-to-DC converter. When compared to single-phase
operation, multiphase conversion lowers the peak
inductor current by distributing the load current
between parallel power paths. This simplifies compo-
nent selection, power distribution to the load, and ther-
mal layout. Existing Quick-PWM controllers, such as the
MAX1718, function as the master controller, providing
accurate output voltage regulation, fast transient
response, and multiple fault protection features.
Synchronized to the master’s low-side gate driver, the
MAX1887/MAX1897 include a constant on-time con-
troller, synchronous rectifier gate drive, active current
balancing, and precision current-limit circuitry.
COMPONENT
Output Voltage
CIRCUIT OF FIGURE 1
0.6V to 1.75V
7V to 24V
Input Voltage Range
Maximum Load Current
40A
0.6µH
Sumida CDEP134H-0R6 or
Panasonic ETQP6F0R6BFA
Inductor (each phase)
Frequency
300kHz (TON = float)
High-Side MOSFET
(N , each phase)
H
International Rectifier
(2) IRF7811W
International Rectifier
(2) IRF7822 or
Fairchild (3) FDS7764A or
Low-Side MOSFET
(N , each phase)
L
On-Time Control and Active
Current Balancing
(6) 10µF 25V
Taiyo Yuden
TMK432BJ106KM or
TDK C4532X5R1E106M
Input Capacitor (C
)
IN
The MAX1887/MAX1897 slave controller uses a con-
stant on-time, voltage feed-forward architecture similar
to Maxim’s Quick-PWM controllers (Figure 2). The con-
trol algorithm is simple: the high-side switch on-time is
determined solely by a one-shot whose period is
inversely proportional to input voltage and directly pro-
(8) 270µF 2V
Panasonic EEFUE0E271R
Output Capacitor (C
)
OUT
Current-Sense Resistors
(R and R
1.5mΩ
portional to the compensation voltage (V
).
COMP
)
CM
CS
Another one-shot sets a minimum off-time (130ns typi-
cal). The on-time one-shot is triggered when the follow-
ing conditions are satisfied: The slave detects a
Voltage Positioning Gain
(A
2
)
VPS
______________________________________________________________________________________ 11
Quick-PWM Slave Controllers for
Multiphase, Step-Down Supplies
Table 2. Component Suppliers
PHONE
MANUFACTURER
WEBSITE
[COUNTRY CODE]
MOSFETS
Fairchild Semiconductor
International Rectifier
Siliconix
[1] 888-522-5372
[1] 310-322-3331
[1] 203-268-6261
www.fairchildsemi.com
www.irf.com
www.vishay.com
CAPACITORS
Kemet
[1] 408-986-0424
[1] 847-468-5624
www.kemet.com
Panasonic
www.panasonic.com
[65] 281-3226 (Singapore)
[1] 408-749-9714
Sanyo
www.secc.co.jp
[03] 3667-3408 (Japan)
[1] 408-573-4150
Taiyo Yuden
www.t-yuden.com
INDUCTORS
Coilcraft
[1] 800-322-2645
[1] 561-752-5000
[1] 408-982-9660
www.coilcraft.com
www.coiltronics.com
www.sumida.com
Coiltronics
Sumida
transition on the TRIG input, the slave controller’s
inductor current is below its current-limit threshold, and
the minimum off time has expired. For the MAX1887, a
rising edge on the trigger input (TRIG) initiates a new
cycle. For the MAX1897, the trigger input’s polarity is
to CS-) become unbalanced, the transconductance
amplifiers adjust the slave controller’s on time, allowing
the slave inductor current to increase or decrease until
the current-sense signals are properly balanced.
V
selected by connecting POL to V
GND (falling edge).
(rising edge) or to
CC
COMP
t
= K
= K
ON
V
IN
At the slave controller’s core is the one-shot that sets
the high-side switch’s on-time. This fast, low-jitter one-
shot adjusts the on-time in response to the input volt-
age and the difference between the inductor currents in
the master and the slave. Two identical transconduc-
V
I
Z
OUT
COMP C
+K
V
V
IN
IN
= (Master’s on time) + (Slave’s on-time
correction due to current imbalance)
tance amplifiers (G
= G ) integrate the difference
MS
MM
between the master and slave current-sense signals.
The summed output is connected to COMP, allowing
adjustment of the integration time constant with a com-
pensation capacitor connected at COMP. The resulting
compensation current and voltage may be determined
by the following equations:
This control algorithm results in balanced inductor cur-
rents with the slave switching frequency synchronized
to the master. Since the master operates at nearly con-
stant frequency, the slave will as well. The benefits of a
constant switching frequency are twofold: first, the fre-
quency can be selected to avoid noise-sensitive
regions of the spectrum; second, the inductor ripple-
current operating point remains relatively constant,
resulting in easy design methodology and predictable
output voltage ripple.
I
= G
V
−V
− G
V
− V
(
)
(
)
COMP
MM CM+ CM−
MS CS+ CS−
V
= V
+I
Z
COMP
OUT COMP COMP
where Z
is the impedance at the COMP output.
Multiple phase switching effectively distributes the load
among the external components, thereby improving the
overall efficiency. Distributing the load current between
multiple phases lowers the peak inductor current by the
COMP
The PWM controller uses this integrated signal (V
)
COMP
to set the slave controller’s on time. When the master
and slave current-sense signals (CM+ to CM- and CS+
12 ______________________________________________________________________________________
Quick-PWM Slave Controllers for
Multiphase, Step-Down Supplies
R6
10Ω
C2
0.22µF
5V BIAS
SUPPLY
C1
1µF
V
CC
VGATE
D0
V
DD
TO LOGIC
INPUT
8V TO 24V
C
IN
D1
D2
D3
D4
V+
DAC
INPUTS
(6) 10µF 25V CERAMIC
DM
BST
C
BST(M)
0.1µF
DH
LX
DL
N
N
H(M)
L(M)
L
R
CM
S0
S1
SUSPEND
INPUTS
M
0.6µF
1.5mΩ
ZMODE
SUS
MUX CONTROL
C
CC
47pF
R5
GND
OVP
CC
5V BIAS
SUPPLY
510Ω
R13
0Ω
C
REF
0.22µF
REF
R8
53.6kΩ
R
FB
100Ω
MAX1718
FLOAT
(300kHz)
FB
TON
C
FB
1000pF
SKP/SDN
ON
OFF
NEG
POS
R9
100kΩ
R3
1kΩ
R4
1kΩ
R
TIME
62kΩ
ILIM
C5
470pF
TIME
R2
2.8kΩ
R10
34.8kΩ
DS
R1
301kΩ
TRIG
V+
BST
5V BIAS
SUPPLY
V
DD
C
BST(S)
0.1µF
C3
SHDN
R7
10Ω
1µF
MAX1897
LIMIT
N
N
DH
LX
DL
H(S)
V
CC
C4
OUTPUT
L
S
0.22µF
POL
R
CS
1.5mΩ
0.6µH
C
OUT
L(S)
(8) 270µF
FLOAT
(300kHz)
TON
C
COMP
470pF
R
COMP
10kΩ
PGND
CS+
FB
COMP
R13
200Ω
(MASTER)
REF
(MAX1718)
R14
200Ω
C7
R11
113kΩ
4700pF
CS-
POWER GROUND
I
LIM
C6
100pF
ANALOG GROUND
(MASTER)
CM+
R12
R15
200Ω
C8
4700pF
30.1kΩ
ANALOG GROUND
(SLAVE)
CM-
GND
R16
200Ω
Figure 1. Standard Application Circuit
______________________________________________________________________________________ 13
Quick-PWM Slave Controllers for
Multiphase, Step-Down Supplies
Q
TRIG
MAX1887
(MAX1897)*
TOFF
ONE-SHOT
BST
DH
LX
R
S
Q
Q
(V )*
CC
TRIG
TON
Q
CONTROLLER
BIAS
V
DD
(SHDN)*
ONE-SHOT
DL
(TON)*
ON-TIME
COMPUTE
PGND
V+
COMP
TRIG
CS-
Q
TRIG
(POL)*
EDGE
DETECTOR
GMS
NEGATIVE
CS LIMIT
POSITIVE
CS LIMIT
CS+
CM+
GMM
ILIM
CM-
17R
R
LIMIT
2R
GND
POSITIVE
CM LIMIT
Figure 2. Functional Diagram
number of phases (1/η) when compared to a single-
phase converter. This significantly reduces the I2R loss-
es across the inductor’s series resistance, the
MOSFETs on-resistance, and the board resistance.
In-Phase and Out-of-Phase Operation
Multiphase systems can stagger the on times of each
phase (out-of-phase operation) or simultaneously turn on
all phases at the beginning of a new cycle (in-phase
operation). When configured for out-of-phase operation,
high input-to-output differential voltages (V > ηV
)
IN
OUT
14 ______________________________________________________________________________________
Quick-PWM Slave Controllers for
Multiphase, Step-Down Supplies
prevent the on times from overlapping. Therefore, the
put voltage. Another benefit of forced-PWM operation,
the switching frequency remains relatively constant
over the full load and input voltage ranges.
instantaneous input current peaks of each phase do
not overlap, resulting in reduced input and output volt-
age ripple and RMS ripple current. This lowers the
input and output capacitor requirements, which allows
fewer or less expensive capacitors, and decreases
shielding requirements for EMI. When the on-times
5V Bias Supply (V
and V
)
CC
DD
The MAX1887/MAX1897 require an external 5V bias
supply in addition to the battery. Typically this 5V bias
supply is the notebook’s 95% efficient 5V system sup-
ply. Keeping the bias supply external to the IC
improves efficiency, eliminates power dissipation limita-
tions, and removes the cost associated with the inter-
nal, 5V linear regulator that would otherwise be needed
to supply the PWM circuit and gate drivers. If stand-
alone capability is needed, the 5V supply can be gen-
erated with an external linear regulator.
overlap at low input-to-output differential voltages (V
IN
< ηV
OUT
), the input currents of the overlapping phases
may sum together, increasing the total input and output
ripple voltage and RMS ripple current.
During in-phase operation, the input capacitors must
support large, instantaneous input currents when the
high-side MOSFETs turn on simultaneously, resulting in
increased ripple voltage and current when compared
to out-of-phase operation. The higher RMS ripple cur-
rent degrades efficiency due to power loss associated
with the input capacitor’s effective series resistance
(ESR). This typically requires a large number of low-
ESR input capacitors in parallel to meet input ripple
current ratings or minimize ESR-related losses.
The 20-pin MAX1897 has a separate analog PWM sup-
ply voltage input (V ) and gate-driver supply input
CC
(V ). For the 16-pin MAX1887 device, the analog
DD
PWM supply voltage input and the gate-driver supply
voltage input are internally connected and named V
.
DD
and
The battery input (V+) and 5V bias inputs (V
CC
V
) can be tied together if the input source is a fixed
DD
For the MAX1897, the polarity select input (POL) deter-
mines whether rising edges (POL = V ) or falling
CC
4.5V to 5.5V supply.
The maximum current required from the 5V bias supply
edges (POL = GND) trigger a new cycle. For low duty-
cycle applications (duty factor < 50%), triggering on
the rising edge of the master’s low-side gate driver pre-
vents both high-side MOSFETs from turning on at the
same time. Staggering the phases in this way lowers
the input ripple current, thereby reducing the input
capacitor requirements. For applications operating with
approximately a 50% duty factor, out-of-phase opera-
to power V
power) is:
(PWM controller) and V
(gate-drive
DD
CC
I
= I + f (Q + Q ) = 10mA to 45mA (typ)
CC SW G1 G2
BIAS
where I
is 525µA typical, f
is the switching
SW
CC
frequency, and Q
and Q
are the MOSFET data
G2
G1
sheets’ total gate charge specification limits at
= 5V.
tion (POL = V ) causes the slave controller to com-
CC
V
GS
plete an on-pulse coincident to the master controller
determining when to initiate its next on-time. The noise
generated when the slave controller turns off its high-
side MOSFET could compromise the master controller’s
feedback voltage and current-sense inputs, causing
inaccurate decisions that lead to more jitter in the
switching waveforms. Under these conditions, trigger-
ing off of the falling edge (POL = GND) of the master’s
low-side gate driver forces the controllers to operate in-
phase, improving the system’s noise immunity.
Shutdown (MAX1897 only)
When SHDN is driven low, the MAX1897 enters the
micropower shutdown mode (Table 3). Shutdown
immediately forces DL high, pulls DH low, and shuts
down the PWM controller so the total supply current
(I
+ I
+ I+) drops below 1µA. When SHDN is dri-
ven high, the MAX1897 operates normally with the
PWM controller enabled.
CC
DD
Table 3. Approximate K-Factor Errors
Forced-PWM Mode
The MAX1887/MAX1897 controllers do not allow light-
load pulse skipping. Therefore, the master controller
must be configured for forced-PWM operation. This
PWM control scheme forces the low-side gate drive
waveform to be the complement of the high-side gate
drive waveform, allowing the inductor current to
reverse. During negative load and downward output
voltage transitions, forced-PWM operation allows the
converter to sink current, rapidly pulling down the out-
MAX
TON
CONNECTION
(MAX1897)*
FREQUENCY
SETTING
(kHz)
K-FACTOR
(µs)
K-FACTOR
ERROR
(%)
V
200
300
550
5
10
10
10
CC
Float
GND
3.3
1.8
*The MAX1887 is internally preset for 300kHz operation.
______________________________________________________________________________________ 15
Quick-PWM Slave Controllers for
Multiphase, Step-Down Supplies
Table 4. Operating Mode Truth Table
SHDN
ILIM
DL
MODE
COMMENTS
Micropower, shutdown mode (I +I < 1µA typ). DL forced high,
CC DD
GND
X
High
Shutdown
DH forced low, and the PWM controller disabled.
Low-power, standby mode (I + I = 20µA typ). DL forced high,
CC
DD
GND
(< 0.25V)
DH forced low, and the PWM controller disabled. However, the bias
and fault protection circuitry remain active so the MAX1887/MAX1897
can continuously monitor the ILIM input.
V
V
High
Standby
CC
High
(> 0.25V)
Normal
Operation
Low-noise, fixed-frequency, PWM operation. The inductor current
reverses with light loads.
Switching
CC
X = Don’t Care
Several Quick-PWM converters that may be used as the
master controller ramp down the output voltage at a
controlled slew rate when shut down. When combined
with these master controllers, the MAX1897 must not be
deactivated until the output voltage is fully discharged.
Otherwise the slave’s low side switch will turn on while
the master is still attempting to regulate the output. In
these applications, delay the shutdown input signal to
side gate driver, the slave cannot initiate a new on-time
pulse so the slave’s inductor current ramps down as
well, maintaining the current balance. Therefore, the
slave’s valley current limit only needs to protect the
slave controller if the current-balance circuitry or the
master current limit fails. The slave’s ILIM input voltage
should be selected to properly adjust the master’s cur-
rent-limit threshold.
the MAX1897 or permanently connect SHDN to V
and use standby mode to conserve power (see the
Standby Mode section).
CC
Dual-Mode ILIM Input
The current-limit input (ILIM) features dual-mode opera-
tion, serving as both the standby mode control input
and the current-limit threshold adjustment. The slave
controller enters a low-power standby mode when the
Standby Mode
The MAX1887/MAX1897 slave controllers enter a low-
power standby mode when the ILIM voltage (V
)
ILIM voltage (V
) is pulled below 250mV. For ILIM
ILIM
ILIM
drops below 250mV (Table 4). Similar to shutdown
mode, standby forces DL high, pulls DH low, and dis-
ables the PWM controller to inhibit switching; however,
the bias and fault protection circuitry remain active so
the MAX1887/MAX1897 can continuously monitor the
voltages from 400mV to 1.5V, the current-limit threshold
voltage is precisely 0.1 ✕ V . The current-limit volt-
age may be accurately set with a resistive voltage-
divider between the master controller’s reference and
GND, allowing the MAX1887/MAX1897 to automatically
enter the low-power standby mode.
ILIM
ILIM input. When V
is driven above 250mV, the
ILIM
PWM controller is enabled.
Slave Current Limit
The slave current-limit circuit employs a unique “valley”
current-sensing algorithm. If the current-sense signal is
above the current-limit threshold, the MAX1887/ MAX1897
will not initiate a new cycle (Figure 3). The actual peak
inductor current is greater than the current-limit threshold
by an amount equal to the inductor ripple current.
Therefore, the exact current-limit characteristic and maxi-
mum load capability are a function of the current-limit
threshold, inductor value, and input voltage. The reward
for this uncertainty is robust, overcurrent sensing. When
combined with master controllers that contain output
undervoltage protection circuits, this current-limit method
is effective in almost every circumstance.
When the slave controller’s current-limit voltage (V
)
ILIM
is set through a resistive divider between the master
controller’s reference and GND (see the Current-Limit
Circuitry section), the MAX1887/MAX1897 automatically
enters low-power standby mode when the master con-
troller shuts down. As the master’s reference powers
down, the resistive divider pulls ILIM below 250mV,
automatically activating the MAX1887/MAX1897’s low-
power standby mode.
Current-Limit Circuitry
When the master’s inductor current exceeds its valley
current limit, the master extends its off time by forcing
DL high until the inductor current falls below the current-
limit threshold. Without a transition on the master’s low-
16 ______________________________________________________________________________________
Quick-PWM Slave Controllers for
Multiphase, Step-Down Supplies
The slave includes a precision current-limit comparator
that supplements the master’s current-limit circuitry.
The MAX1887/MAX1897 uses CM+ and CM- to differ-
I
I
I
PEAK
LOAD
LIMIT
entially sense the master’s inductor current across a
current-sense resistor, providing a more accurate cur-
rent limit. When the master’s current-sense voltage
exceeds the current limit set by ILIM in the slave (see
the Dual-Mode ILIM Input section), the open-drain cur-
rent-limit comparator pulls LIMIT low (Figure 2). Once
the master triggers the current limit, a pulse-width mod-
ulated output signal appears at LIMIT. This signal is fil-
tered and used to adjust the master’s current-limit
threshold.
2 - LIR
2η
I
= I
LIMIT(VALLEY) LOAD(MAX)
( )
High-Side, Gate Driver Supply (BST)
The gate drive voltage for the high-side, N-channel
MOSFET is generated by the flying capacitor boost cir-
cuit (Figure 4). The capacitor between BST and LX is
alternately charged from the external 5V bias supply
0
TIME
Figure 3. “Valley” Current-Limit Threshold Point
(V ) and placed in parallel with the high-side MOSFET’s
DD
There also is a negative current limit that prevents
excessive reverse inductor currents when V
ing current. The negative current-limit threshold is set to
approximately 150% of the positive current-limit thresh-
old, and tracks the positive current limit when ILIM is
adjusted.
gate-source terminals.
is sink-
OUT
On startup, the synchronous rectifier (low-side MOSFET)
forces LX to ground and charges the boost capacitor to
5V. On the second half of each cycle, the switch-mode
power supply turns on the high-side MOSFET by closing
an internal switch between BST and DH. This provides
the necessary gate-to-source voltage to turn on the high-
side switch, an action that boosts the 5V gate drive signal
above the system’s main supply voltage (V+).
The MAX1887/MAX1897 uses CS+ and CS- to differen-
tially measure the current across an external sense
resistor (R ) connected between the inductor and out-
CS
put capacitors. This configuration provides precise cur-
rent balancing, current limiting, and voltage positioning
with a 1% current-sense resistor. Reducing the sense
voltage decreases power dissipation but increases the
relative measurement error.
INPUT
(V
)
IN
C
BYP
Carefully observe the PC board layout guidelines to
ensure that noise and DC errors don’t corrupt the current-
sense signals measured at CS+ and CS-. The IC should
be mounted relatively close to the current-sense resistor
with short, direct traces making a Kelvin sense connec-
tion.
V+
D
BST
(R )*
BST
BST
DH
LX
C
BST
N
H
Master Current-Limit Adjustment (LIMIT)
The Quick-PWM controllers that may be used as the
master controller typically use the low-side MOSFET’s
on-resistance as its current-sense element. This depen-
dence on a loosely specified resistance with a large
temperature coefficient causes inaccurate current limit-
ing. As a result, high current-limit thresholds are need-
ed to guarantee full-load operation under worst-case
conditions. Furthermore, the inaccurate current limit
mandates the use of MOSFETs and inductors with
excessively high current and power dissipation ratings.
L
MAX1887
MAX1897
( )* OPTIONAL–THE RESISTOR REDUCES
THE SWITCHING-NODE RISE TIME.
Figure 4. High-Side Gate Driver Boost Circuitry
______________________________________________________________________________________ 17
Quick-PWM Slave Controllers for
Multiphase, Step-Down Supplies
MOSFET Gate Drivers (DH, DL)
Thermal-Fault Protection
The DH and DL drivers are optimized for driving moder-
ately sized, high-side and larger, low-side power
MOSFETs. This is consistent with the low duty factor
seen in the notebook CPU environment, where a large
The MAX1887/MAX1897 feature a thermal fault-protec-
tion circuit. When the junction temperature rises above
+160°C, a thermal sensor activates the standby logic,
forces the DL low-side gate driver high, and pulls the
DH high-side gate driver low. This quickly discharges
the output capacitors, tripping the master controller’s
undervoltage lockout protection. The thermal sensor
reactivates the slave controller after the junction tem-
perature cools by 15°C.
V
- V
differential exists. An adaptive dead-time
OUT
IN
circuit monitors the DL output and prevents the high-
side FET from turning on until DL is fully off. There must
be a low resistance, low inductance path from the DL
driver to the MOSFET gate in order for the adaptive
dead-time circuit to work properly. Otherwise, the sense
circuitry in the MAX1887/MAX1897 will interpret the
MOSFET gate as “off” while there is actually charge still
left on the gate. Use very short, wide traces (50mils to
100mils wide if the MOSFET is 1 inch from the device).
The dead time at the other edge (DH turning off) is
determined by a fixed 35ns internal delay.
Design Procedure
Firmly establish the input voltage range and maximum
load current before choosing a switching frequency
and inductor operating point (ripple-current ratio). The
primary design trade-off lies in choosing a good switch-
ing frequency and inductor operating point, and the fol-
lowing four factors dictate the rest of the design:
The internal pulldown transistor that drives DL low is
robust, with a 0.4Ω (typ) on-resistance. This helps pre-
vent DL from being pulled up during the fast rise-time of
the LX node, due to capacitive coupling from the drain
to the gate of the low-side synchronous-rectifier MOS-
FET. However, for high-current applications, some com-
binations of high- and low-side FETs may cause
excessive gate-drain coupling, leading to poor efficien-
cy, EMI, and shoot-through currents. This is often reme-
died by adding a resistor less than 5Ω in series with
BST, which increases the turn-on time of the high-side
FET without degrading the turn-off time (Figure 4).
Input Voltage Range: The maximum value (V
)
IN(MAX)
must accommodate the worst-case high AC adapter
voltage. The minimum value (V ) must account for
IN(MIN)
the lowest input voltage after drops due to connectors,
fuses, and battery selector switches. If there is a choice
at all, lower input voltages result in better efficiency.
Maximum Load Current: There are two values to con-
sider. The peak load current (I
) determines
LOAD(MAX)
the instantaneous component stresses and filtering
requirements, and thus drives output capacitor selec-
tion, inductor saturation rating, and the design of the
current-limit circuit. The continuous load current (I
)
LOAD
Undervoltage Lockout
undervoltage lockout (UVLO)
determines the thermal stresses and thus drives the
selection of input capacitors, MOSFETs, and other criti-
cal heat-contributing components. Modern notebook
During startup, the V
CC
circuitry forces the DL gate driver high and the DH gate
driver low, inhibiting switching until an adequate supply
CPUs generally exhibit I
= I
✕ 80%.
LOAD
LOAD(MAX)
voltage is reached. Once V
rises above 3.75V, valid
CC
For multiphase systems, each phase supports a frac-
tion of the load, depending on the current balancing.
The highly accurate current sensing and balancing
implemented by the MAX1887/MAX1897 slave con-
troller evenly distributes the load among each phase:
transitions detected at the trigger input initiate a corre-
sponding on-time pulse (see the On-Time Control and
Active Current Balancing section). To ensure correct
startup, the MAX1887/MAX1897 slave controller’s
undervoltage lockout voltage must be lower than the
master controller’s undervoltage lockout voltage.
If the V
voltage drops below 3.75V, it is assumed that
I
CC
LOAD
η
I
= I
=
LOAD(SLAVE)
LOAD(MASTER)
there is not enough supply voltage to make valid deci-
sions. To protect the output from overvoltage faults, DL
is forced high in this mode to force the output to
ground. This results in large negative inductor current
where η is the number of phases.
Switching Frequency: This choice determines the
basic trade-off between size and efficiency. The opti-
mal frequency is largely a function of maximum input
voltage, due to MOSFET switching losses that are pro-
and possibly small negative output voltages. If V
is
CC
likely to drop in this fashion, the output can be clamped
with a Schottky diode to PGND to reduce the negative
excursion.
portional to frequency and V 2. The optimum frequen-
IN
cy also is a moving target, due to rapid improvements
18 ______________________________________________________________________________________
Quick-PWM Slave Controllers for
Multiphase, Step-Down Supplies
in MOSFET technology that are making higher frequen-
Find a low-loss inductor having the lowest possible DC
resistance that fits in the allotted dimensions. Ferrite
cores are often the best choice, although powdered
iron is inexpensive and can work well at 200kHz. The
core must be large enough not to saturate at the peak
cies more practical.
Setting Switch On Time: The constant on-time control
algorithm in the master results in a nearly constant
switching frequency despite the lack of a fixed-frequen-
cy clock generator. In the slave, the high-side switch on
time is inversely proportional to V+ and directly propor-
inductor current (I
):
PEAK
2 + LIR
2η
tional to the compensation voltage (V
):
COMP
I
= I
LOAD(MAX)
PEAK
V
COMP
t
=K
ON
where η is the number of phases.
V
IN
Transient Response
where K is internally preset to 3.3µs for the MAX1887 or
externally set by the TON pin-strap connection for the
MAX1897 (Table 3)
The inductor ripple current affects transient-response
performance, especially at low V - V
differentials.
OUT
IN
Low inductor values allow the inductor current to slew
faster, replenishing charge removed from the output fil-
ter capacitors by a sudden load step. The amount of
output sag also is a function of the maximum duty fac-
tor, which can be calculated from the on time and mini-
mum off time:
Set the nominal on time in the slave to match the on
time in the master. An exact match is not necessary
because the MAX1887/MAX1897 have wide t
adjust-
ON
ment ranges ( 40%). For example, if t
in the master
ON
is set to 250kHz, the slave can be set to either 200kHz
or 300kHz and still achieve good performance. Care
should be taken to ensure that the COMP voltage
remains within its output voltage range (0.42V to
2.80V).
V
K
2
OUT
L ∆I
+ t
(
)
(
LOAD(MAX)
OFF(MIN)
V
IN
V
=
SAG
Inductor Operating Point: This choice provides trade-
offs between size vs. efficiency and transient response
vs. output noise. Low inductor values provide better
transient response and smaller physical size, but also
result in lower efficiency and higher output noise due to
increased ripple current. The minimum practical induc-
tor value is one that causes the circuit to operate at the
edge of critical conduction (where the inductor current
just touches zero with every cycle at maximum load).
Inductor values lower than this grant no further size-
reduction benefit. The optimum operating point is usu-
ally found between 20% and 50% ripple current.
V
− V
OUT
K
)
IN
2ηC
V
OUT OUT
OFF(MIN)
− t
V
IN
where t
is the minimum off time (see the
OFF(MIN)
Electrical Characteristics section), η is the number of
phases, and K is from Table 3.
The amount of overshoot due to stored inductor energy
can be calculated as:
2
∆I
L
(
)
LOAD(MAX)
V
≈
SOAR
2ηC
V
OUT OUT
Inductor Selection
The switching frequency and operating point (% ripple
or LIR) determine the inductor value as follows:
Setting the Current Limits
The master and slave current-limit thresholds must be
great enough to support the maximum load current,
even under worst-case operating conditions. Since the
master’s current limit determines the maximum load
(see the Current-Limit Circuitry section), the procedure
for setting the current limit is sequential. First, the mas-
ter’s current limit is set based on the operating condi-
tions and the characteristics of the low-side MOSFETs.
Then the slave controller is configured to adjust the
master’s current-limit threshold based on the precise
current-sense resistor value and variation in the MOS-
FET characteristics. Finally, the resulting valley current
limit for the slave’s inductor occurs above the master’s
V
x V − V
xη
xLIR
(
)
OUT
IN
OUT
L =
V xf xI
IN SW LOAD(MAX)
where η is the number of phases. Example: η = 2,
= 40A, V = 12V, V = 1.3V, f = 300kHz,
I
LOAD
IN
OUT
SW
30% ripple current or LIR = 0.3:
1.3Vx 12V −1.3V x2
(
)
L =
= 0.64µH
12Vx300kHzx40Ax0.3
______________________________________________________________________________________ 19
Quick-PWM Slave Controllers for
Multiphase, Step-Down Supplies
SLAVE
CONTROLLER
MASTER
CONTROLLER
R
C
1
R
B
V
=
=
V
REF
ILIM
REF
ITHM(HIGH)
10 R +R
A
B
C
REF
R
D
1
R //R
B LIMIT
MAX1887
MAX1897
MAX1718
V
V
REF
ITHM(HIGH)
10 R + R //R
(
)
A
B
LIMIT
R
R
A
B
R
LIMIT
LIMIT
ILIM
1
R
D
10 R +R
V
=
V
REF
ITHS
C
LIMIT
C
D
Figure 5. Setting the Adjustable Current Limits
current-limit threshold. This is acceptable since the
slave’s inductor current limit only serves as a fail-safe in
case the master and slave inductor currents become
significantly unbalanced during a transient.
to support the maximum load current for the maximum
and minimum current-limit tolerance value:
R
DS(ON)
V
≥ (I
)R
ITHM(HIGH)
LIMIT(VALLEY) DS(ON)(MAX)
where V
, the master’s current-limit threshold, is typ-
ITHM
The basic operating conditions are determined using
the same calculations provided in any Quick-PWM reg-
ulator data sheet. The valley of the inductor current
ically 1/10th the voltage seen at the master’s ILIM input
(V = 0.1 x V , see the master con-
ITHM
LIM(MASTER)
troller’s data sheet). Connect a resistive voltage-divider
from the master controller’s internal reference to GND,
with the master’s ILIM input connected to the center tap
(Figure 5). Use 1% tolerance resistors in the divider with
10µA to 20µA DC bias current to prevent significant
errors due to the ILIM pin’s input current:
(I
) occurs at I
divided by the
LOAD(MAX)
LIMIT(VALLEY)
number of phases minus half of the peak-to-peak
inductor current:
I
∆I
LOAD(MAX)
INDUCTOR
I
≥
LIMIT(VALLEY)
−
η
2
V
V
ILIM(MASTER)
ILIM(MASTER)
≤R ≤
B
where the peak-to-peak inductor current may be deter-
mined by the following equation:
20µA
10µA
V
REF(MASTER)
−1 R
B
R
=
A
V
V
− V
(
)
V
OUT IN OUT
ILIM(MASTER)
∆I
=
INDUCTOR
V f
L
IN SW
Configure the slave controller so its LIMIT output begins
to roll off after the master current-limit threshold occurs:
The master’s high current-limit threshold must be set
high enough to support the maximum load current,
even when the master’s current-limit threshold is at its
minimum tolerance value, as described in the master
controller’s data sheet. Most Quick-PWM controllers
that may be chosen as the master controller use the
low-side MOSFET’s on-resistance to sense the inductor
current. In these applications, the worst-case maximum
V
ITHM(HIGH)
V
≥ R
+ ∆I
INDUCTOR
ITHS
CM
R
DS(ON)(MAX)
where V
, the slave’s current-limit threshold, is pre-
ITHS
cisely one-tenth the voltage seen at the slave’s ILIM
input (V = 0.1 ✕ V ). Connect a second
ITHS
ILIM(SLAVE)
value for R
DS(ON)
plus some margin for the rise in
DS(ON)
resistive voltage-divider from the master controller’s
internal reference to GND, with the slave’s ILIM input
connected to the center tap (Figure 5). The external
adjustment range of 400mV to 1.5V corresponds to a
R
over temperature must be used to determine
the master’s current-limit threshold. A good general rule
is to allow 0.5% additional resistance for each °C of
temperature rise. Set the master current-limit threshold
20 ______________________________________________________________________________________
Quick-PWM Slave Controllers for
Multiphase, Step-Down Supplies
current-limit threshold of 40mV to 150mV. Use 1% toler-
2) Determine the master’s current-limit threshold from
the valley current limit and low-side MOSFETs’ max-
imum on-resistance over temperature:
ance resistors in the divider with 10µA to 20µA DC bias
current to prevent significant errors due to the ILIM
pin’s input current. Reducing the current-limit threshold
voltage lowers the sense resistor’s power dissipation,
but this also increases the relative measurement error:
V
≥ 21.8A ✕ 6mΩ = 130mV
ITH(MASTER)
Now select the resistive-divider values (R and R
A
B
V
V
ILIM(SLAVE)
in Figure 5) to set the appropriate voltage at the
ILIM(SLAVE)
≤R
≤
D
master’s ILIM input:
20µA
10µA
V
10x130mV
10x130mV
REF(MASTER)
−1 R
D
R
=
R =
to
= 65kΩ to130kΩ
C
B
V
20µA
10µA
ILIM(SLAVE)
Selecting R = 100kΩ 1% provides the following
Now, set the current-limit adjustment ratio (A
=
B
ADJ
value for R :
V
/V
) greater than the maximum to
A
ITHM(HIGH) ITHM(LOW)
minimum on-resistance ratio (A
= R
/
DS(ON)(MAX)
RDS
R
):
2V
DS(ON)(MIN)
R
=
−1 x100kΩ≈54kΩ
A
10x130mV
A
≥ A
ADJ
ROS
R
R //R
DS(ON)(MAX)
A
B
3) Determine the slave’s current-limit threshold:
1+
≥
R
R
DS(ON)(MIN)
LIMIT
130mV
6mΩ
V
≥ 1.5mΩ x
+ 6.4A ≈ 42mV
Increasing A
improves the master’s current-limit
ADJ
ITHS
accuracy but also increases the current limit’s noise
sensitivity. Therefore, R
following equation:
may be selected using the
LIMIT
Select the resistive-divider values (R and R in
Figure 5) to set the appropriate voltage at the
C
D
slave’s ILIM input:
R //R R
(
)
A
B
DS(ON)(MIN)
−R
R
≤
LIMIT
R
DS(ON)(MAX)
DS(ON)(MIN)
10x42mV
10x42mV
R
=
to
= 21kΩ to42kΩ
D
20µA
10µA
Finally, verify that the total load on the master’s refer-
ence does not exceed 50µA:
Selecting R = 30.1kΩ 1% provides the following
D
A
value for R :
V
V
REF
REF
I
=
+
≤ 50µA
BIAS(TOTAL)
R
+ R
D
R
+ R //R
(
)
C
A
B
LIMIT
2V
R
=
−1 x30.1kΩ≈113kΩ
C
10x42mV
Current Limit Design Example
For the typical application circuit shown in Figure 1: V
IN
LOAD(MAX)
= 6mΩ, R
DS(ON)(MIN )
4) Determine R
(Figure 5) from the above equation:
LIMIT
= 12V, V
= 1.3V, f
= 300kHz, η = 2, I
OUT
SW
= 50A, L = 0.6µH, R
= 3mΩ
DS(ON)(MAX)
53.6kΩ //100kΩ x3mΩ
(
)
R
≤
≈ 35kΩ
LIMIT
6mΩ − 3mΩ
1) Determine the peak-to-peak inductor current and
the valley current limit:
5) Finally, verify that that the total bias currents do not
exceed the 50µA maximum load of the master’s ref-
erence:
1.3Vx 12V −1.3V
(
)
∆I
=
= 6.4A
INDUCTOR
12Vx300kHzx0.6µH
2V
50A
2
1
2
−
I
=
+
BIAS(TOTAL)
I
=
x6.4A = 21.8A
LIMIT(VALLEY)
54kΩ + 100kΩ//34.8kΩ
(
)
2V
30.1kΩ +113kΩ
= 36µA
______________________________________________________________________________________ 21
Quick-PWM Slave Controllers for
Multiphase, Step-Down Supplies
SLAVE CURRENT-LIMIT VOLTAGES
vs. AVERAGE INDUCTOR CURRENT
160
V
ITHS
I
= I
=
ADJ(MIN) PEAK
R
140
120
100
80
CM
V
ITHM(HIGH)
MASTER
CONTROLLER
V
ITHM(LOW)
R
R
V
I
= R
I
CS LS(PEAK)
60
CM LM(PEAK)
SLAVE
CONTROLLER
I
= R
I
CS LS(VALLEY)
CM LM(VALLEY)
40
ITHS
20
V
(V - V
IN SW
)
OUT
OUT IN
∆I - ∆I
ADJ
=
INDUCTOR
[
]
V
f
L
0
0
10
20
30
40
50
AVERAGE INDUCTOR CURRENT (A)
MASTER CURRENT-LIMIT VOLTAGES
vs. AVERAGE INDUCTOR CURRENT
160
140
120
100
80
A
- 1
RDS
UNADJUSTED ∆I
≤ ∆I
= V
LIMIT ITHM(HIGH)
LIMIT
(
R
)
DS(ON)(MAX)
V
ITHM(HIGH)
ADJUSTED ∆I
≤ ∆I
INDUCTOR
LIMIT
V
R
ITHM(LOW)
60
= L
= L
DS(ON)(MIN)
LM(VALLEY)
LM(VALLEY)
40
R
DS(ON)(MIN)
20
0
0
10
20
30
40
50
AVERAGE INDUCTOR CURRENT (A)
Figure 6. Master/Slave Current-Limit Thresholds
When unadjusted, the on-resistance variation of the
low-side MOSFETs results in a maximum current-limit
rent-limit variation from 21.7A (unadjusted) to less than
6.4A (adjusted).
variation (∆I
) determined by the following equation:
LIMIT
Output Capacitor Selection
The output filter capacitor must have low enough effec-
tive series resistance (ESR) to meet output ripple and
load-transient requirements, yet have high enough ESR
to satisfy stability requirements.
A
−1
RDS
Unadjusted∆I
= V
LIMIT
ITHM(HIGH)
R
DS(ON)(MAX)
where A
= R
/R
. Using the
RDS
DS(ON)(MAX) DS(ON)(MIN)
In CPU V
converters and other applications where
CORE
MAX1887/MAX1897 to adjust the master’s current-limit
threshold results in a maximum current-limit variation
less than the peak-to-peak inductor current:
the output is subject to large load transients, the output
capacitor selection typically depends on how much
ESR is needed to prevent the output from dipping too
low under a load transient. Ignoring the sag due to
finite capacitance:
Adjusted ∆I
≤ ∆I
INDUCTOR
LIMIT
As shown in Figure 6, the resulting current-limit varia-
tion of the master is dramatically reduced. For the
above example, this control scheme reduces the cur-
V
STEP
LOAD(MAX)
R
≤
ESR
∆I
22 ______________________________________________________________________________________
Quick-PWM Slave Controllers for
Multiphase, Step-Down Supplies
In non-CPU applications, the output capacitor selection
Output Capacitor Stability Considerations
For Quick-PWM controllers, stability is determined by
the value of the ESR zero relative to the switching fre-
quency. The boundary of instability is given by the fol-
lowing equation:
often depends on how much ESR is needed to maintain
an acceptable level of output ripple voltage. The output
ripple voltage of a step-down controller equals the total
inductor ripple current multiplied by the output capaci-
tor’s ESR. When operating multiphase systems out-of-
phase, the peak inductor currents of each phase are
staggered, resulting in lower output ripple voltage by
reducing the total inductor ripple current. For out-of-
phase operation, the maximum ESR to meet ripple
requirements is:
fSW
π
fESR
≤
1
where:
fESR
=
2πRESRCOUT
V
RIPPLE
R
≤
ESR
For a standard 300kHz application, the ESR zero fre-
quency must be well below 95kHz, preferably below
50kHz. Tantalum, Sanyo POSCAP, and Panasonic SP
capacitors in wide-spread use at the time of publication
have typical ESR zero frequencies below 30kHz. In the
standard application used for inductor selection, the
η
L
V
− ηV
V
IN
OUT
OUT
− η−1 V
OUT TRIG
t
(
)
f
V
IN
SW
This equation may be rewritten as the single phase rip-
ple current minus a correction due to the additional
phases:
ESR needed to support a 30mV
ripple is 30mV/(40A
P-P
x 0.3) = 2.5mΩ. Eight 270µF/2V Panasonic SP capaci-
tors in parallel provide 1.9mΩ (max) ESR. Their typical
combined ESR results in a zero at 39kHz.
V
RIPPLE
R
≤
ESR
V
OUT
I
LIR− η η−1
t
+ t
ON TRIG
(
)
(
)
LOAD(MAX)
L
Don’t put high-value ceramic capacitors directly across
the output without taking precautions to ensure stability.
Ceramic capacitors have a high ESR zero frequency
and may cause erratic, unstable operation. However,
it’s easy to add enough series resistance by placing
the capacitors a couple of centimeters downstream
from the junction of the inductor and FB pin.
where t
is the MAX1887/MAX1897’s trigger propa-
TRIG
gation delay, η is the number of phases, and K is from
Table 3. When operating the MAX1897 in-phase (POL
= GND), the high-side MOSFETs turn on together, so
the output capacitors must simultaneously support the
combined inductor ripple currents of each phase. For
in-phase operation, the maximum ESR to meet ripple
requirements is:
Unstable operation manifests itself in two related but
distinctly different ways: double-pulsing and feedback
loop instability. Double-pulsing occurs due to noise on
the output or because the ESR is so low that there isn’t
enough voltage ramp in the output voltage signal. This
“fools” the error comparator into triggering a new cycle
immediately after the minimum off-time period has
expired. Double-pulsing is more annoying than harmful,
resulting in nothing worse than increased output ripple.
However, it can indicate the possible presence of loop
instability due to insufficient ESR. Loop instability can
result in oscillations at the output after line or load
steps. Such perturbations are usually damped, but can
cause the output voltage to rise above or fall below the
tolerance limits.
V
V
RIPPLE
RIPPLE
R
≤
=
ESR
I
LIR
η
V
LOAD(MAX)
OUT
V
IN
V
− V
OUT
(
)
IN
f
L
SW
The actual capacitance value required relates to the
physical size needed to achieve low ESR, as well as to
the chemistry of the capacitor technology. Thus, the
capacitor is usually selected by ESR and voltage rating
rather than by capacitance value (this is true of tanta-
lums, OS-CONs, and other electrolytics).
When using low-capacity filter capacitors such as
ceramic or polymer types, capacitor size is usually
The easiest method for checking stability is to apply a
very fast zero-to-max load transient and carefully
observe the output voltage ripple envelope for over-
shoot and ringing. It can help to simultaneously monitor
determined by the capacity needed to prevent V
SAG
and V
from causing problems during load tran-
SOAR
sients. Generally, once enough capacitance is added to
meet the overshoot requirement, undershoot at the ris-
the switching waveforms (V and/or I
). Don’t
INDUCTOR
LX
ing load edge is no longer a problem (see the V
and
allow more than one cycle of ringing after the initial
step-response under/overshoot.
SAG
V
SOAR
equations in the Transient Response section).
______________________________________________________________________________________ 23
Quick-PWM Slave Controllers for
Multiphase, Step-Down Supplies
the minimum power dissipation occurs where the resis-
Input Capacitor Selection
tive losses equal the switching losses.
The input capacitor must meet the ripple current
requirement (I
) imposed by the switching currents.
RMS
Choose a low-side MOSFET that has the lowest possi-
The MAX1887/MAX1897 multiphase slave controllers
operate out-of-phase (MAX1897 POL = V or float),
ble on-resistance (R
), comes in a moderate-
DS(ON)
CC
sized package (i.e., one or two SO-8s, DPAK or
D2PAK), and is reasonably priced. Make sure that the
DL gate driver can supply sufficient current to support
the gate charge and the current injected into the para-
sitic gate-to-drain capacitor caused by the high-side
MOSFET turning on; otherwise, cross-conduction prob-
lems may occur.
staggering the turn-on times of each phase. This mini-
mizes the input ripple current by dividing the load cur-
rent among independent phases:
V
V
− V
OUT
(
)
I
OUT IN
LOAD
I
=
RMS
η
V
IN
MOSFET Power Dissipation
Worst-case conduction losses occur at the duty factor
for out-of-phase operation.
extremes. For the high-side MOSFET (N ), the worst-
H
case power dissipation due to resistance occurs at the
minimum input voltage:
When operating the MAX1897 in-phase (POL = GND),
the high-side MOSFETs turn on simultaneously, so
input capacitors must support the combined input rip-
ple currents of each phase:
2
V
V
I
LOAD
OUT
PD(N Resistive) =
R
DS(ON)
H
η
IN
V
V
− V
OUT
(
)
OUT IN
Generally, a small high-side MOSFET is desired to
reduce switching losses at high input voltages.
I
=I
RMS LOAD
V
IN
However, the R
required to stay within package
DS(ON)
power-dissipation often limits how small the MOSFET
can be. Again, the optimum occurs when the switching
for in-phase operation.
losses equal the conduction (R
) losses. High-
DS(ON)
For most applications, nontantalum chemistries (ceram-
ic, aluminum, or OS-CON) are preferred because of
their resistance to inrush surge currents typical of sys-
tems with a mechanical switch or connector in series
with the input. If the MAX1887/MAX1897 is operated as
the second stage of a two-stage power-conversion sys-
tem, tantalum input capacitors are acceptable. In either
configuration, choose an input capacitor that exhibits
less than +10°C temperature rise at the RMS input cur-
rent for optimal circuit longevity.
side switching losses don’t usually become an issue
until the input is greater than approximately 15V.
Calculating the power dissipation of the high-side
MOSFET (N ) due to switching losses is difficult since it
H
must allow for difficult quantifying factors that influence
the turn-on and turn-off times. These factors include the
internal gate resistance, gate charge, threshold volt-
age, source inductance, and PC board layout charac-
teristics. The following switching-loss calculation
provides only a very rough estimate and is no substi-
tute for breadboard evaluation, preferably including
Power MOSFET Selection
Most of the following MOSFET guidelines focus on the
challenge of obtaining high load-current capability
when using high-voltage (>20V) AC adapters. Low-cur-
rent applications usually require less attention.
verification using a thermocouple mounted on N :
H
2
V
C
f I
RSS SW LOAD
(
)
IN(MAX)
PD(N Switching) =
H
I
η
GATE
The high-side MOSFET (N ) must be able to dissipate
H
the resistive losses plus the switching losses at both
where C
and I
is the reverse transfer capacitance of N
H
RSS
V
and V
. Calculate both of these sums.
IN(MAX)
is the peak gate-drive source/sink current
IN(MIN)
Ideally, the losses at V
GATE
should be roughly equal
IN(MIN)
(1A typ).
to losses at V
, with lower losses in between. If
IN(MIN)
IN(MAX)
Switching losses in the high-side MOSFET can become
an insidious heat problem when maximum AC adapter
the losses at V
are significantly higher than the
losses at V
, consider increasing the size of N .
IN(MAX)
H
voltages are applied, due to the squared term in the C
2
Conversely, if the losses at V
are significantly
IN(MAX)
✕ V
✕ f
switching-loss equation. If the high-side
SW
IN
higher than the losses at V
, consider reducing
IN(MIN)
MOSFET chosen for adequate R
voltages becomes extraordinarily hot when biased from
at low battery
DS(ON)
the size of N . If V does not vary over a wide range,
H
IN
24 ______________________________________________________________________________________
Quick-PWM Slave Controllers for
Multiphase, Step-Down Supplies
V
, consider choosing another MOSFET with
Balancing section). To reduce noise pick-up in applica-
tions that have a widely distributed layout, it is some-
times helpful to connect the compensation network to
IN(MAX)
lower parasitic capacitance.
For the low-side MOSFET (N ), the worst-case power
L
dissipation always occurs at maximum input voltage:
quiet analog ground rather than V
.
OUT
2
Applications Information
V
I
LOAD
OUT
R
DS(ON)
L
PD(N Resistive) = 1−
Voltage Positioning and
Effective Efficiency
V
η
IN(MAX)
Powering new mobile processors requires careful
attention to detail to reduce cost, size, and power dissi-
pation. As CPUs became more power hungry, it was
recognized that even the fastest DC-DC converters
were inadequate to handle the transient power require-
ments. After a load transient, the output instantly
The worst case for MOSFET power dissipation occurs
under heavy overloads that are greater than
LOAD(MAX)
the current limit and cause the fault latch to trip. To pro-
tect against this possibility, “overdesign” the circuit to
tolerate:
I
but are not quite high enough to exceed
changes by ESR
✕ ∆I
. Conventional DC-DC
LOAD
COUT
I
LIR
converters respond by regulating the output voltage
back to its nominal state after the load transient occurs
(Figure 7). However, the CPU only requires that the out-
put voltage remain above a specified minimum value.
Dynamically positioning the output voltage to this lower
limit allows the use of fewer output capacitors and
reduces power consumption under load.
LOAD(MAX)
I
= ηI
+
LOAD
VALLEY(MAX)
2
where I
is the maximum valley current
VALLEY(MAX)
allowed by the current-limit circuit, including threshold
tolerance and on-resistance variation. The MOSFETs
must have a good-sized heatsink to handle the over-
load power dissipation.
For a conventional (nonvoltage-positioned) circuit, the
total voltage change is:
Choose a Schottky diode (D1) with a forward voltage
low enough to prevent the low-side MOSFET body
diode from turning on during the dead time. As a gen-
eral rule, select a diode with a DC current rating equal
to 1/(3η) of the load current. This diode is optional and
can be removed if efficiency is not critical.
V
P-P
1 = 2 ✕ (ESR
✕ ∆I
) + V + V
LOAD SAG SOAR
COUT
where V
and V
are defined in Figure 8. Setting
SOAR
SAG
the converter to regulate at a lower voltage when under
load allows a larger voltage step when the output cur-
rent suddenly decreases (Figure 7). So the total voltage
change for a voltage-positioned circuit is:
Current Balance Compensation (COMP)
The current balance compensation capacitor (C
)
COMP
integrates the difference of the master and slave cur-
rent-sense signals, while the compensation resistor
improves transient response by increasing the phase
margin. This allows the user to optimize the dynamics
of the current balance loop. Excessively large capacitor
values increase the integration time constant, resulting
in larger current differences between the phases during
transients. Excessively small capacitor values allow the
current loop to respond cycle by cycle but can result in
small DC current variations between the phases.
Likewise, excessively large series resistance can also
cause DC current variations between the phases. Small
series resistance reduces the phase margin, resulting
in marginal stability in the current balance loop. For
most applications, a 470pF capacitor and 10kΩ series
resistor from COMP to the converter’s output voltage
works well.
V
2 = (ESR
✕ ∆I
) + V
+ V
P-P
COUT
LOAD
SAG SOAR
where V
and V
are defined in the Design
SOAR
SAG
Procedure section. Since the amplitudes are the same
for both circuits (V 1 = V 2), the voltage-positioned
P-P
P-P
circuit tolerates twice the ESR. Since the ESR specifica-
tion is achieved by paralleling several capacitors, fewer
units are needed for the voltage-positioned circuit.
An additional benefit of voltage positioning is reduced
power consumption at high load currents. Since the
output voltage is lower under load, the CPU draws less
current. The result is lower power dissipation in the
CPU, although some extra power is dissipated in
R
. For a nominal 1.6V, 22A output (R
=
LOAD
SENSE
72.7mΩ), reducing the output voltage 2.9% gives an
output voltage of 1.55V and an output current of 21.3A.
Given these values, CPU power consumption is
reduced from 35.2W to 33.03W. The additional power
The compensation network can be tied to V
to
OUT
consumption of R
is:
include the feed-forward term due to the master’s on
time (see the On-time Control and Active Current
SENSE
______________________________________________________________________________________ 25
Quick-PWM Slave Controllers for
Multiphase, Step-Down Supplies
CAPACITIVE SOAR
(dV/dt = I /C
VOLTAGE POSITIONING THE OUTPUT
)
OUT OUT
ESR VOLTAGE STEP
(I x R
)
ESR
STEP
A
B
1.4V
1.4V
V
OUT
CAPACITIVE SAG
(dV/dt = I /C
)
RECOVERY
OUT OUT
A. CONVENTIONAL CONVERTER (50mV/div)
B. VOLTAGE-POSITIONED OUTPUT (50mV/div)
I
LOAD
Figure 7. Voltage Positioning the Output
Figure 8. Transient Response Regions
50mV x 21.3A = 1.06W,
current, I
.
NP
The effective efficiency of voltage-positioned circuits is
shown in the Typical Operating Characteristics.
which results in an overall power savings of:
35.2W - (33.03W + 1.06W) = 1.10W.
One-Stage (Battery Input) Versus
Two-Stage (5V Input) Applications
The MAX1887/MAX1897 can be used with a direct bat-
tery connection (one stage) or can obtain power from a
regulated 5V supply (two-stage). Each approach has
advantages, and careful consideration should go into
the selection of the final design.
In effect, 2.2W of CPU dissipation is saved and the
power supply dissipates much of the savings, but both
the net savings and the transfer of dissipation away
from the hot CPU are beneficial. Effective efficiency is
defined as the efficiency required of a nonvoltage-posi-
tioned circuit to equal the total dissipation of a voltage-
positioned circuit for a given CPU operating condition.
The one-stage approach offers smaller total inductor
size and fewer capacitors overall due to the reduced
demands on the 5V supply. Due to the high input volt-
age, the one-stage approach requires lower DC input
currents, reducing input connection/bus requirements
and power dissipation due to input resistance. The
transient response of the single stage is better due to
the ability to ramp the inductor current faster. The total
efficiency of a single stage is better than the two-stage
approach.
Calculate effective efficiency as follows:
1) Start with the efficiency data for the positioned cir-
cuit (V , I , V
, I
).
IN IN OUT OUT
2) Model the load resistance for each data point:
R
= V / I
LOAD
OUT OUT
3) Calculate the output current that would exist for each
data point in a nonpositioned application:
R
LOAD
The two-stage approach allows flexible placement due
to smaller circuit size and reduced local power dissipa-
tion. The power supply can be placed closer to the
CPU for better regulation and lower I2R losses from PC
board traces. Although the two-stage design has slow-
er transient response than the single stage, this can be
offset by the use of a voltage-positioned converter.
I
= V / R
NP LOAD
NP
where V = 1.6V (in this example).
NP
4) Calculate effective efficiency as:
Effective efficiency = (V
culated nonpositioned power output divided by the
measured voltage-positioned power input.
✕ I ) / (V ✕ I ) = cal-
NP IN IN
NP
5) Plot the efficiency data point at the nonpositioned
26 ______________________________________________________________________________________
Quick-PWM Slave Controllers for
Multiphase, Step-Down Supplies
the master to the analog ground in the slave to pre-
vent ground offsets. A low value (≤10Ω) resistor is
sufficient to link the two grounds.
Ceramic Output Capacitor Applications
Ceramic capacitors have advantages and disadvan-
tages. They have ultra-low ESR and are noncom-
bustible, relatively small, and nonpolarized. However,
they are also expensive and brittle, and their ultra-low
ESR characteristic can result in excessively high ESR
zero frequencies. In addition, their relatively low capac-
itance value can cause output overshoot when step-
ping from full-load to no-load conditions, unless a small
inductor value is used (high switching frequency), or
there are some bulk tantalum or electrolytic capacitors
in parallel to absorb the stored inductor energy. In
some cases, there may be no room for electrolytics,
creating a need for a DC-DC design that uses nothing
but ceramics.
4) Keep the power traces and load connections short.
This is essential for high efficiency. The use of thick
copper PC boards (2oz vs. 1oz) can enhance full-load
efficiency by 1% or more. Correctly routing PC board
traces is a difficult task that must be approached in
terms of fractions of centimeters, where a single mΩ
of excess trace resistance causes a measurable effi-
ciency penalty.
5) Keep the high-current gate-driver traces (DL, DH,
LX, and BST) short and wide to minimize trace
resistance and inductance. This is essential for
high-power MOSFETs that require low-impedance
gate drivers to avoid shoot-through currents.
The MAX1887/MAX1897 can take full advantage of the
small size and low ESR of ceramic output capacitors in
a voltage-positioned circuit. The addition of the posi-
tioning resistor increases the ripple at FB, lowering the
effective ESR zero frequency of the ceramic output
capacitor.
6) CS+, CS-, CM+, and CM- connections for current
limiting and balancing must be made using Kelvin
sense connections to guarantee the current-sense
accuracy.
7) When trade-offs in trace lengths must be made, it’s
preferable to allow the inductor charging path to be
made longer than the discharge path. For example,
it’s better to allow some extra distance between the
input capacitors and the high-side MOSFET than to
allow distance between the inductor and the low-side
MOSFET or between the inductor and the output filter
capacitor.
Output overshoot (V
) determines the minimum
SOAR
output capacitance requirement (see the Output
Capacitor Selection section). Often the switching fre-
quency is increased to 550kHz, and the inductor value
is reduced to minimize the energy transferred from
inductor to capacitor during load-step recovery. The
efficiency penalty for operating at 550kHz is about 3%
when compared to the 300kHz circuit, primarily due to
the high-side MOSFET switching losses.
8) Route high-speed switching nodes away from sen-
sitive analog areas (COMP, ILIM). Make all pin-
strap control input connections (SHDN, ILIM, POL)
PC Board Layout Guidelines
Careful PC board layout is critical to achieve low
switching losses and clean, stable operation. The
switching power stage requires particular attention
(Figure 9). If possible, mount all of the power compo-
nents on the top side of the board with their ground ter-
minals flush against one another. Follow these
guidelines for good PC board layout:
to analog ground or V
rather than power ground
CC
or V
.
DD
Layout Procedure
1) Place the power components first, with ground termi-
nals adjacent (low-side MOSFET source, C , C
,
IN OUT
and D1 anode). If possible, make all these connec-
tions on the top layer with wide, copper-filled areas.
1) Keep the high-current paths short, especially at the
ground terminals. This is essential for stable, jitter-
free operation
2) Mount the controller IC adjacent to the low-side
MOSFET. The DL gate trace must be short and
wide (50mils to 100mils wide if the MOSFET is 1
inch from the controller IC).
2) Connect all analog grounds to a separate solid
copper plane, which connects to the GND pin of
3) Group the gate-drive components (BST diode and
the MAX1887/MAX1897. This includes the V
bypass capacitor, COMP components, and the
resistive-divider connected to ILIM.
CC
capacitor, V
bypass capacitor) together near the
DD
controller IC.
4) Make the DC-DC controller ground connections as
shown in Figure 1. This diagram can be viewed as
having four separate ground planes: input/output
ground, where all the high-power components go;
the power ground plane, where the PGND pin and
3) The master controller also should have a separate
analog ground. Return the appropriate noise sensi-
tive components to this plane. Since the reference
in the master is sometimes connected to the slave,
it may be necessary to couple the analog ground in
______________________________________________________________________________________ 27
Quick-PWM Slave Controllers for
Multiphase, Step-Down Supplies
MAX1718
(MASTER)
MAX1897
(SLAVE)
CONNECT THE EXPOSED
PAD TO GND
VIA TO POWER
GROUND
VIA TO POWER
GROUND
CONNECT GND AND PGND
BENEATH THE CONTROLLER AT
ONE POINT ONLY AS SHOWN
≤10Ω
MASTER
SLAVE
LM
DM
DS
LS
VIA TO CM+
AND FB
VIA TO CS+
C
C
C
C
C
C
C
C
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
VIA TO CM-
VIA TO CS-
POWER
GROUND
TOP LAYER
OUTPUT
MASTER
SLAVE
INPUT (V+)
C
C
C
C
C
C
C
C
IN
IN
IN
IN
IN
IN
IN
IN
POWER
GROUND
BOTTOM LAYER
Figure 9. Power-Stage PC Board Layout Example
28 ______________________________________________________________________________________
Quick-PWM Slave Controllers for
Multiphase, Step-Down Supplies
Typical Operating Circuit
5V BIAS
SUPPLY
V
DD
INPUT
V+
(V )*
CC
BST
(POL)*
DH
LX
OUTPUT
SHDN
ILIM
REF
(MASTER)
DL
MAX1887
(MAX1897)*
(TON)*
FLOAT
(300kHz)
PGND
CS+
ILIM
(MASTER)
LIMIT
CS-
FB
(MASTER)
CM+
COMP
MASTER CURRENT
SENSE RESISTOR
CM-
TRIG
MASTER LOW-SIDE GATE DRIVER
GND
( )* MAX1897 PINS ONLY
V
bypass capacitor go; the master’s analog
DD
Pin Configurations (continued)
ground plane where sensitive analog components,
the master’s GND pin and V bypass capacitor
CC
TOP VIEW
go; and the slave’s analog ground plane where the
slave’s GND pin, and V bypass capacitor go.
CC
ILIM
TRIG
CM+
CM-
1
2
3
4
5
6
7
8
16 LIMIT
15 V+
The master’s GND plane must meet the PGND
plane only at a single point directly beneath the IC.
Similarly, the slave’s GND plane must meet the
PGND plane only at a single point directly beneath
the IC. The respective master and slave ground
planes should connect to the high-power output
ground with a short metal trace from PGND to the
source of the low-side MOSFET (the middle of the
star ground). This point must also be very close to
the output capacitor ground terminal.
14 BST
13 LX
MAX1887
CS-
12 DH
CS+
11
10 DL
PGND
V
DD
COMP
GND
9
5) Connect the output power planes (V
and sys-
QSOP
CORE
tem ground planes) directly to the output filter
capacitor positive and negative terminals with multi-
ple vias. Place the entire DC-DC converter circuit
as close to the CPU as is practical.
Chip Information
TRANSISTOR COUNT: 1422
PROCESS: BiCMOS
______________________________________________________________________________________ 29
Quick-PWM Slave Controllers for
Multiphase, Step-Down Supplies
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
30 ______________________________________________________________________________________
Quick-PWM Slave Controllers for
Multiphase, Step-Down Supplies
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
______________________________________________________________________________________ 31
Quick-PWM Slave Controllers for
Multiphase, Step-Down Supplies
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
32 ______________________________________________________________________________________
Quick-PWM Slave Controllers for
Multiphase, Step-Down Supplies
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
D2
0.15
C A
D
b
0.10 M
C A B
C
L
D2/2
D/2
k
PIN # 1
I.D.
0.15
C
B
PIN # 1 I.D.
0.35x45
E/2
E2/2
C
(NE-1) X
e
L
E2
E
k
L
DETAIL A
e
(ND-1) X
e
C
C
L
L
L
L
e
e
0.10
C
A
0.08
C
C
A3
A1
PROPRIETARY INFORMATION
TITLE:
PACKAGE OUTLINE
16, 20, 28, 32L, QFN THIN, 5x5x0.8 mm
APPROVAL
DOCUMENT CONTROL NO.
REV.
1
21-0140
C
2
COMMON DIMENSIONS
EXPOSED PAD VARIATIONS
NOTES:
1. DIMENSIONING & TOLERANCING CONFORM TO ASME Y14.5M-1994.
2. ALL DIMENSIONS ARE IN MILLIMETERS. ANGLES ARE IN DEGREES.
3. N IS THE TOTAL NUMBER OF TERMINALS.
4. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL CONFORM TO JESD 95-1
SPP-012. DETAILS OF TERMINAL #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE
ZONE INDICATED. THE TERMINAL #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE.
5. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.25 mm AND 0.30 mm
FROM TERMINAL TIP.
6. ND AND NE REFER TO THE NUMBER OF TERMINALS ON EACH D AND E SIDE RESPECTIVELY.
7. DEPOPULATION IS POSSIBLE IN A SYMMETRICAL FASHION.
8. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS.
9. DRAWING CONFORMS TO JEDEC MO220.
PROPRIETARY INFORMATION
TITLE:
PACKAGE OUTLINE
10. WARPAGE SHALL NOT EXCEED 0.10 mm.
16, 20, 28, 32L, QFN THIN, 5x5x0.8 mm
APPROVAL
DOCUMENT CONTROL NO.
REV.
2
21-0140
C
2
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 33
© 2002 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
相关型号：
MAX1889ETE+
Switching Regulator, Current-mode, 2.8A, 1250kHz Switching Freq-Max, BICMOS, 5 X 5 MM, 0.80 MM HEIGHT, ULTRA THIN, QFN-16
MAXIM
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