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MAX17115ETJ+C32 [MAXIM]

Analog Circuit, 1 Func, BICMOS, 5 X 5 MM, ROHS COMPLIANT, TQFN-32;
MAX17115ETJ+C32
型号： MAX17115ETJ+C32
厂家： MAXIM INTEGRATED PRODUCTS    MAXIM INTEGRATED PRODUCTS
描述：

Analog Circuit, 1 Func, BICMOS, 5 X 5 MM, ROHS COMPLIANT, TQFN-32

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中文：  中文翻译
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19-4756; Rev 1; 4/10  
Internal-Switch Boost Regulator and High-Voltage,  
Low-Dropout Linear Regulator for TFT LCDs  
General Description  
Features  
Sꢀ2.5V_to_5.5V_Input_Supply_Range  
The MAX17115 includes a high-performance step-up  
regulator, a high-accuracy, high-voltage, low-dropout  
linear regulator (LDO), a high-performance buffer ampi-  
fier, and a logic-controlled high-voltage switch block.  
SꢀPin-Programmable_640kHz/1.2MHz_Switching_  
Frequency  
SꢀCurrent-Mode_Step-Up_Converter  
Fast-Transient_Response_to_Pulsed_Load_  
High-Accuracy_Output_Voltage_(0.8%)_  
Built-In_20V,_4.6A,_0.1I_n-Channel_Power_MOSFET  
Cycle-by-Cycle_Current_Limit_  
The DC-DC converter is a high-frequency (1.2MHz/  
640kHz) current-mode step-up regulator with a built-in  
power MOSFET. It provides fast-transient response to  
pulsed loads while producing efficiencies over 88%. The  
built-in power MOSFET allows output voltages as high as  
18V from inputs from 2.5V to 5.5V. A programmable soft-  
start function controls startup inrush currents.  
High_Efficiency_(88%)  
SꢀProgrammable_Soft-Start  
SꢀHigh-Performance_Operational_Amplifier  
200mA_Output_Short-Circuit_Current_  
45V/µs_Slew_Rate_  
The operational amplifier, typically used to drive the LCD  
backplane (VCOM), features high-output short-circuit  
current (200mA), fast slew rate (45V/Fs), and wide band-  
width (20MHz). Its rail-to-rail input and output maximize  
application flexibility. The high-voltage LDO is adjustable  
and has a high accuracy of Q0.5%. It is typically used to  
drive a gamma reference divider string. The high-voltage  
switch control block modulates the shape of the gate-on  
supply and provides an adjustable delay for power-up  
sequencing.  
20MHz_-3dB_Bandwidth_  
Rail-to-Rail_Input_and_Output  
SꢀHigh-Voltage_LDO  
High_ 0.5%_Accuracy_  
40mA_Guaranteed_Output_Current  
SꢀLogic-Controlled_High-Voltage_Switch_with_  
Adjustable_Delay  
SꢀHigh-Voltage_Stress_Mode  
SꢀBuilt-In_Sequencing  
SꢀThermal-Overload_Protection  
The high-voltage stress (HVS) function is used to tem-  
porarily increase the source-driver supply voltage of the  
LCD panel for aging tests. The HVS digital input controls  
an open-drain internal switch, which is typically used to  
change the feedback divider of the step-up regulator.  
SꢀGate_Driver_for_Input-Side_True_Shutdown™_  
Switch  
SꢀLogic-Level_Shutdown_Input  
SꢀTimer-Delayed_Fault_Shutdown_for_Boost-  
Regulator_Output  
The MAX17115 is available in a lead-free, 32-pin, thin  
QFN package. The package is a 5mm x 5mm square  
with a maximum thickness of 0.8mm for thin LCD panel  
design.  
True Shutdown is a trademark of Maxim Integrated Products, Inc.  
Pin Configuration  
TOP VIEW  
Applications  
24 23 22 21 20 19 18 17  
LCD Monitors  
LCD TVs  
16  
15  
COMP 25  
AGND 26  
IN  
IN  
14 AGND  
27  
28  
29  
30  
31  
32  
SS  
N.C.  
Ordering Information  
EN  
13  
12  
MAX17115  
VDPM  
VGH  
FREQ  
PART  
TEMP_RANGE  
PIN-PACKAGE  
11 HVS_EN  
MAX17115ETJ+  
-40NC to +85NC  
32 TQFN  
10  
9
VDET  
XAO  
VGHM  
DRN  
+Denotes a lead(Pb)-free/RoHS-compliant package.  
1
2
3
4
5
6
7
8
THIN QFN  
5mm x 5mm  
_ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ _Maxim Integrated Products_ _ 1  
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,  
or visit Maxim’s website at www.maxim-ic.com.  
Internal-Switch Boost Regulator and High-Voltage,  
Low-Dropout Linear Regulator for TFT LCDs  
ABSOLUTE_MAXIMUM_RATINGS  
IN, VFLK, EN to AGND.........................................-0.3V to +7.5V  
VDET, XAO, HVS_EN, RHVS, VREF_FB,  
VGHM to DRN .......................................................-0.3V to +40V  
OPI, OPO to OPGND .............................. -0.3V to (V + 0.3V)  
VOP  
FREQ to AGND .................................................-0.3V to +7.5V  
VDPM, FB, COMP, GATE,  
OPO Maximum Continuous Output Current.................... Q75mA  
LX, PGND RMS Current Rating (per pin).............................1.6A  
SS to AGND............................................-0.3V to (V + 0.3V)  
PGND, OPGND to AGND.....................................-0.3V to +0.3V  
IN  
Continuous Power Dissipation (T = +70NC)  
A
32-Pin TQFN (derate 34.5mW/NC above +70NC) ......2758mW  
Operating Temperature Range.......................... -40NC to +85NC  
Junction Temperature .....................................................+150NC  
Storage Temperature Range............................ -65NC to +160NC  
Lead Temperature (soldering, 10s) ................................+300NC  
Soldering Temperature (reflow) ......................................+260NC  
VREF_O to AGND................................-0.3V to (V  
+ 0.3V)  
VREF_I  
LX to PGND...........................................................-0.3V to +22V  
VOP, VREF_I to AGND.........................................-0.3V to +22V  
VGH to AGND .......................................................-0.3V to +40V  
VGHM, DRN to AGND............................ -0.3V to (V  
+ 0.3V)  
VGH  
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional  
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute  
maximum rating conditions for extended periods may affect device reliability.  
ELECTRICAL_CHARACTERISTICS  
(V = V = +5V, Circuit of Figure 1, V  
= +16V, V  
= 30V, T _=_0°C_to_+85°C, unless otherwise noted. Typical values are at  
VGH A  
IN  
EN  
VOP  
T
= +25°C.)  
A
PARAMETER  
CONDITIONS  
MIN  
TYP  
MAX  
UNITS  
SUPPLY  
IN Input-Supply Range  
IN Undervoltage Lockout  
(Note 1)  
2.5  
2.0  
6.0  
2.49  
1
V
V
V
V
V
rising, hysteresis = 200mV  
= 1.3V, LX not switching  
= 1.2V, switching  
2.25  
0.5  
IN  
FB  
FB  
IN Quiescent Current  
Thermal Shutdown  
mA  
°C  
2.5  
5
Temperature rising  
Hysteresis  
+160  
15  
HIGH-VOLTAGE_LDO  
VREF_I Input Voltage Range  
VREF_I Undervoltage Lockout  
VREF_I Input-Bias Current  
VREF_O Dropout Voltage  
10  
18  
5.8  
V
V
V
rising  
5.4  
100  
VREF_I  
No load  
VREF_I - VREF_O; I  
250  
0.5  
µA  
V
= 30mA  
0.25  
1.240  
VREF_O  
1mA ≤ I  
≤ 30mA  
1.234  
-0.9  
1.246  
+0.9  
V
VREF_FB  
Regulation Voltage  
VREF_O  
VREF_I  
10V < V  
< 18V, I  
= 20mA, V  
= 9V  
mV/V  
VREF_O  
VREF_O  
VREF_O Maximum  
Output Current  
40  
mA  
STEP-UP_REGULATOR  
Output-Voltage Range  
FB Regulation Voltage  
FB Fault Trip Level  
FB Fault Delay  
V
18  
V
V
IN  
No load  
1.228  
1.24  
1.00  
55  
1.252  
Falling edge  
= 0.95V  
V
V
FB  
ms  
%
FB Load Regulation  
FB Line Regulation  
FB Input-Bias Current  
FB Transconductance  
LX Current Limit  
1mA < I  
< 0.5A  
-0.1  
0.05  
120  
250  
4.6  
LOAD  
V
V
= 2.5V to 6V  
0.15  
250  
500  
5.4  
%/V  
nA  
µS  
A
IN  
= 1.24V; T = +25°C  
FB  
A
I
= +2.5µA  
100  
3.9  
COMP  
V
= 1.2V, duty cycle = 75%  
FB  
2_ _ _ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ  
Internal-Switch Boost Regulator and High-Voltage,  
Low-Dropout Linear Regulator for TFT LCDs  
ELECTRICAL_CHARACTERISTICS_(continued)  
(V = V = +5V, Circuit of Figure 1, V  
= +16V, V  
= 30V, T _=_0°C_to_+85°C, unless otherwise noted. Typical values are at  
VGH A  
IN  
EN  
VOP  
T
= +25°C.)  
A
PARAMETER  
CONDITIONS  
MIN  
TYP  
0.10  
0.13  
10  
MAX  
0.2  
UNITS  
V
IN  
V
IN  
V
LX  
V
IN  
= 5V  
= 3V  
W
LX On-Resistance  
0.26  
25  
LX Bias Current  
= 20V, T = +25°C  
A
µA  
Current-Sense Transresistance  
OSCILLATOR  
= 5V  
0.08  
0.15  
0.25  
V/A  
V
V
V
V
= 0V  
500  
1000  
3
640  
1200  
6
780  
1400  
9
FREQ  
FREQ  
FREQ  
FREQ  
Frequency  
kHz  
= 5V  
FREQ Pulldown Current  
Maximum Duty Cycle  
Minimum On-Time  
SOFT-START  
= 5V  
µA  
%
= 0V or 5V  
89  
93  
96  
100  
ns  
I
µA  
V
SS Reset Resistance  
SS Charge Current  
SS Done Threshold  
SS Time  
V
V
= 0V, I = 10mA  
SS  
10  
4
20  
6
EN  
= 1.2V  
2
SS  
SS voltage rising  
33nF on SS pin  
1.4  
6.6  
ms  
POSITIVE_GATE-DRIVER_TIMING_AND_CONTROL_SWITCHES  
VDPM Capacitor Charge Current MLG startup, V = 0V  
4
5
6
µA  
V
VDPM  
VDPM Turn-On Threshold  
VDPM Pulldown Resistance  
VFLK Input Low Voltage  
VDPM rising  
=10mA  
1.21  
1.24  
10  
1.27  
20  
I
I
VDPM  
V
IN  
= 2.5V to 6V  
0.7  
V
V
2.5V < V < 4.5V  
1.9  
2.3  
-1  
IN  
VFLK Input High Voltage  
4.5V < V < 6V  
IN  
VFLK Input Leakage Current  
V
VFLK  
= 0V or 5V, T = +25°C  
+1  
µA  
ns  
V
A
VFLK-to-VGH Propagation Delay VFLK rising and falling  
VGH Input-Voltage Range  
200  
35  
450  
350  
15  
V
V
V
V
= 1.5V, V  
= 1.5V, V  
= 1.5V, V  
= 1.5V, V  
= 5V  
300  
200  
8
µA  
µA  
I
VDPM  
VDPM  
VDPM  
VDPM  
VFLK  
VFLK  
VFLK  
VFLK  
VGH Input Current  
= 0V  
VGH-to-VGHM Resistance  
VGHM-to-DRN Resistance  
= 5V, I = 10mA  
= 0V, I = 10mA  
I
30  
60  
INPUT_SERIES_SWITCH_GATE_DRIVER  
V
V
= 5V  
8
10  
20  
12  
µA  
mA  
V
GATE  
GATE  
GATE Output Sink Current  
= 0.2V  
10  
GATE Done Voltage Threshold  
GATE Output Voltage Low  
GATE falling  
0.3  
0.01  
0.5  
I
= 1mA  
0.05  
V
GATE  
V
0.05  
-
V
0.02  
-
IN  
IN  
GATE Output Voltage High  
I
= -1mA, V = 0V  
V
GATE  
EN  
OPERATIONAL_AMPLIFIER  
VOP Supply Range  
6
18  
21  
5
V
V
VOP Overvoltage Threshold  
VOP Supply Current  
VOP rising  
No load  
19  
20  
3
mA  
ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ_ _ 3  
Internal-Switch Boost Regulator and High-Voltage,  
Low-Dropout Linear Regulator for TFT LCDs  
ELECTRICAL_CHARACTERISTICS_(continued)  
(V = V = +5V, Circuit of Figure 1, V  
= +16V, V  
= 30V, T _=_0°C_to_+85°C, unless otherwise noted. Typical values are at  
VGH A  
IN  
EN  
VOP  
T
= +25°C.)  
A
PARAMETER  
CONDITIONS  
/2, T = +25°C  
MIN  
-14  
-50  
TYP  
MAX  
+14  
+50  
UNITS  
mV  
VOP Input Offset Voltage  
OPI Input-Bias Current  
V
V
= V  
/2  
OPI  
VOP  
, V  
OPO OPI  
= V  
nA  
VOP  
A
Input Common-Mode  
Voltage Range  
0
V
V
VOP  
V
- 100  
V
VOP  
VOP  
- 40  
OPO Output Voltage High  
I
I
= +5mA, V  
= V  
VOP  
mV  
OPO  
OPI  
OPO Output Voltage Low  
Slew Rate  
= -5mA, V  
= 0V  
, C  
40  
45  
100  
mV  
V/µs  
MHz  
OPO  
OPI  
20% to 80% of V  
= 10pF, R  
= 10kW  
VOP LOAD  
LOAD  
-3dB Bandwidth  
C
= 10pF, R  
= 10kW  
20  
LOAD  
LOAD  
Sourcing, V  
= V  
- 3V, V  
= V - 4V  
VOP  
100  
100  
60  
200  
200  
OPI  
VOP  
OPO  
Short-Circuit Current  
mA  
dB  
Sinking, V  
= 3V, V  
= 4V  
OPI  
OPO  
Power-Supply Rejection Ratio  
XAO_FUNCTION  
DC,10V P V  
P 18V  
VOP  
VDET Threshold  
VDET falling, V = 5V  
1.22  
-1  
1.24  
50  
1.26  
V
mV  
µA  
V
IN  
VDET Hysteresis  
VDET Input-Bias Current  
XAO Output Voltage  
V
V
= 0V or 5V, T = +25°C  
+1  
VDET  
A
= 0V, I  
= 10mA  
0.1  
0.4  
VDET  
XAO  
HIGH-VOLTAGE_STRESS_MODE  
HVS_EN Input Low Voltage  
HVS_EN Input High Voltage  
HVS_EN Pulldown Resistance  
RHVS Output Voltage  
0.8  
V
V
2.1  
300  
6
kI  
V
(Note 1)  
6
RHVS Leakage Current  
RHVS On-Resistance  
V
V
= 6V, V  
= 0V, T = +25°C  
µA  
W
RHVS  
HVS_EN  
A
= 5V, I  
= 10mA  
20  
0.6  
HVS_EN  
RHVS  
CONTROL_INPUTS  
Input Low Voltage [EN, FREQ]  
V
IN  
V
IN  
V
IN  
= 2.5V to 6V  
V
V
= 4.5V to 6V  
= 2.5V to 4.5V  
2.4  
Input High Voltage [EN, FREQ]  
1.9  
-1  
Hysteresis [EN, FREQ]  
Input-Bias Current [EN]  
0.15  
V
T
A
= +25°C  
+1  
µA  
ELECTRICAL_CHARACTERISTICS  
(V = V = +5V, Circuit of Figure 1, V  
= +16V, V = 30V, T _=_-40°C_to_+85°C, unless otherwise noted.) (Note 2)  
VGH A  
IN  
EN  
VOP  
PARAMETER  
CONDITIONS  
MIN  
TYP  
MAX  
UNITS  
SUPPLY  
IN Input Supply Range  
IN Undervoltage Lockout  
(Note 1)  
2.5  
2.0  
6.0  
2.5  
1
V
V
V
V
V
rising, hysteresis = 200mV  
= 1.3V, LX not switching  
= 1.2V, switching  
IN  
FB  
FB  
IN Quiescent Current  
mA  
5
4_ _ _ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ  
Internal-Switch Boost Regulator and High-Voltage,  
Low-Dropout Linear Regulator for TFT LCDs  
ELECTRICAL_CHARACTERISTICS_(continued)  
(V = V = +5V, Circuit of Figure 1, V  
= +16V, V = 30V, T _=_-40°C_to_+85°C, unless otherwise noted.) (Note 2)  
VGH A  
IN  
EN  
VOP  
PARAMETER  
CONDITIONS  
MIN  
TYP  
MAX  
UNITS  
HIGH-VOLTAGE_LDO  
VREF_I Input-Voltage Range  
VREF_I Undervoltage Lockout  
VREF_I Input-Bias Current  
VREF_O Dropout Voltage  
10  
18  
5.8  
V
V
VREF_I rising  
No load  
250  
0.5  
µA  
V
I
= 30mA, VREFI - VREFO  
VREF_O  
1mA ≤ I  
≤ 30mA  
1.23  
-0.9  
1.25  
+0.9  
V
VREF_FB  
Regulation Voltage  
VREF_O  
VREF_I  
10V < V  
< 18V, I  
= 20mA, V  
= 9V  
mV/V  
VREF_O  
VREF_O  
VREF_O Maximum Output  
Current  
40  
mA  
STEP-UP_REGULATOR  
Output-Voltage Range  
FB Regulation Voltage  
FB Line Regulation  
FB Transconductance  
LX_SWITCH  
V
18  
1.252  
0.15  
550  
V
V
IN  
No load  
1.228  
V
= 2.5V to 6V  
%/V  
µS  
IN  
I
= ±2.5µA  
80  
COMP  
LX Current Limit  
V
FB  
V
IN  
V
IN  
= 1.2V, duty cycle = 75%  
3.9  
5.4  
0.2  
A
= 5V  
= 3V  
W
LX On-Resistance  
0.26  
0.25  
Current-Sense Transresistance  
0.08  
V/A  
OSCILLATOR  
V
V
V
V
= 0V  
500  
1000  
3
780  
1400  
9
FREQ  
FREQ  
FREQ  
FREQ  
Frequency  
kHz  
= 5V  
FREQ Pulldown Current  
Maximum Duty Cycle  
SOFT-START  
= 5V  
µA  
%
= 0V or 5V  
89  
96  
W
SS Reset Resistance  
SS Charge Current  
V
V
= 0V, I = 10mA  
SS  
20  
6
EN  
SS  
= 1.2V  
2
µA  
POSITIVE_GATE-DRIVER_TIMING_AND_CONTROL_SWITCHES  
VDPM Capacitor Charge Current MLG startup, V = 0V  
4
6
µA  
V
W
VDPM  
VDPM Turn-On Threshold  
VDPM Pulldown Resistance  
VFLK Input Low Voltage  
VDPM rising  
= 10mA  
1.21  
1.27  
20  
I
VDPM  
V
= 2.5V to 6V  
0.7  
V
IN  
2.5V < V < 4.5V  
1.9  
2.3  
IN  
VFLK Input High Voltage  
VGH Input-Voltage Range  
VGH Input Current  
V
4.5V < V < 6V  
IN  
35  
450  
350  
15  
V
V
V
V
V
= 1.5V, VFLK = IN  
VDPM  
VDPM  
VDPM  
VDPM  
µA  
= 1.5V, VFLK = AGND  
W
W
VGH-to-VGHM Resistance  
VGHM-to-DRN Resistance  
= 1.5V, V  
= 1.5V, V  
= 5V, I = 10mA  
VFLK  
VFLK  
= 0V, I = 10mA  
60  
ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ_ _ 5  
Internal-Switch Boost Regulator and High-Voltage,  
Low-Dropout Linear Regulator for TFT LCDs  
ELECTRICAL_CHARACTERISTICS_(continued)  
(V = V = +5V, Circuit of Figure 1, V  
= +16V, V = 30V, T _=_-40°C_to_+85°C, unless otherwise noted.) (Note 2)  
VGH A  
IN  
EN  
VOP  
PARAMETER  
INPUT_SERIES_SWITCH_GATE_DRIVER  
CONDITIONS  
MIN  
TYP  
MAX  
UNITS  
V
V
= 5V  
= 0V  
8
12  
µA  
mA  
V
GATE  
GATE  
GATE Output Sink Current  
10  
GATE Done Voltage Threshold  
GATE Output Voltage Low  
GATE falling  
0.5  
I
= 1mA  
0.05  
V
GATE  
V
0.05  
-
IN  
GATE Output Voltage High  
I
= -1mA, V = 0V  
V
GATE  
EN  
OPERATIONAL_AMPLIFIER  
VOP Supply Range  
6
18  
21  
5
V
V
VOP Overvoltage Threshold  
VOP Supply Current  
VOP rising  
No load  
19  
mA  
mV  
VOP Input Offset Voltage  
V
= V  
/2  
-14  
0
+14  
OPI  
VOP  
Input Common-Mode  
Voltage Range  
V
V
VOP  
V
- 100  
VOP  
OPO Output Voltage High  
OPO Output Voltage Low  
Short-Circuit Current  
I
I
= +5mA, V  
= V  
VOP  
mV  
mV  
mA  
dB  
OPO  
OPO  
OPI  
= -5mA, V  
= 0V  
- 3V, V  
100  
OPI  
Sourcing, V  
= V  
= V - 4V  
VOP  
100  
100  
60  
OPI  
VOP  
OPO  
Sinking, V  
= 3V, V  
= 4V  
OPI  
OPO  
Power-Supply Rejection Ratio  
XAO_FUNCTION  
DC, 10V P V  
P 18V  
VOP  
VDET Threshold  
VDET falling, V = 5V  
1.22  
1.26  
0.4  
V
V
IN  
XAO Output Voltage  
V
= 0V, I  
= 10mA  
VDET  
XAO  
HIGH-VOLTAGE_STRESS_MODE  
HVS_EN Input Low Voltage  
HVS_EN Input High Voltage  
HVS_EN Pulldown Resistance  
0.8  
V
V
2.1  
300  
kI  
(Note 1)  
6
RHVS Output Voltage  
V
W
RHVS On-Resistance  
V
= 5V, I  
= 10mA  
20  
0.6  
HVS_EN  
RHVS  
CONTROL_INPUTS  
Input Low Voltage [EN, FREQ]  
V
V
V
= 2.5V to 6V  
= 4.5V to 6V  
= 2.5V to 4.5V  
V
V
IN  
IN  
IN  
2.4  
1.9  
Input High Voltage [EN, FREQ]  
Note_1: For 5.5V < V < 6.0V, use IC for no longer than 1% of IC lifetime. For continuous operation, input voltage should not  
IN  
exceed 5.5V.  
Note_2:_Specifications to T = -40NC are guaranteed by design, not production tested.  
A
6_ _ _ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ  
Internal-Switch Boost Regulator and High-Voltage,  
Low-Dropout Linear Regulator for TFT LCDs  
Typical Operating Characteristics  
(Circuit of Figure 1, V = 5V, V  
= 16V, T = +25NC, unless otherwise noted.)  
A
IN  
MAIN  
STEP-UP REGULATOR EFFICIENCY  
vs. LOAD CURRENT  
POWER-UP SEQUENCE  
MAX17115 toc02  
90  
85  
80  
75  
A
0V  
B
V
= 5.0V  
SUP  
R
LOAD  
= 47I  
V
= 3.3V  
SUP  
0V  
C
70  
65  
60  
0V  
D
0V  
0V E  
F
55  
50  
45  
40  
0V  
10  
100  
LOAD CURRENT (mA)  
1000  
10ms/div  
D: V  
A: V , 5V/div  
, 10V/div  
, 20V/div  
SUP  
VREF_O  
B: V , 10V/div  
E: V  
VDPM  
VGHM  
, 2V/div  
LX  
C: V  
, 10V/div F: V  
MAIN  
IN SUPPLY QUIESCENT CURRENT  
vs. IN VOLTAGE  
STEP-UP REGULATOR OUTPUT  
LOAD REGULATION vs. LOAD CURRENT  
3
2
0.4  
0.2  
V
= 5V  
SUP  
SWITCHING  
0
-0.2  
-0.4  
-0.6  
-0.8  
1
0
NONSWITCHING  
-1.0  
2.5  
3.0  
3.5  
4.0  
4.5  
5.0  
5.5  
10  
100  
1000  
IN VOLTAGE (V)  
LOAD CURRENT (mA)  
REFERENCE VOLTAGE OUTPUT  
LOAD REGULATION vs. LOAD CURRENT  
REFERENCE VOLTAGE OUTPUT  
LINE REGULATION (%)  
0.40  
0.20  
0
0.10  
0.05  
0
-0.20  
-0.40  
-0.05  
-0.10  
-0.60  
-0.80  
0
20  
40  
60  
80  
15  
17  
18  
19  
20  
16  
LOAD CURRENT (mA)  
V
VOLTAGE (V)  
VREF_I  
ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ_ _ 7  
Internal-Switch Boost Regulator and High-Voltage,  
Low-Dropout Linear Regulator for TFT LCDs  
Typical Operating Characteristics (continued)  
(Circuit of Figure 1, V = 5V, V  
= 16V, T = +25NC, unless otherwise noted.)  
A
IN  
MAIN  
STEP-UP REGULATOR SOFT-START  
(HEAVY LOAD)  
STEP-UP REGULATOR PULSED  
LOAD-TRANSIENT RESPONSE  
MAX17115 toc07  
MAX17115 toc08  
LOAD CURRENT  
1A/div  
50mA  
V
SUP  
2V/div  
0V  
V
GATE  
0V  
2V/div  
0V  
V
MAIN  
(AC-COUPLED)  
200mV/div  
V
MAIN  
10V/div  
0V  
INDUCTOR  
CURRENT  
INDUCTOR  
CURRENT  
1A/div  
0A  
1A/div  
0A  
R
LOAD  
= 47I  
2ms/div  
10µs/div  
STEP-UP REGULATOR  
LOAD-TRANSIENT RESPONSE  
POWER-UP SEQUENCE  
MAX17115 toc09  
MAX17115 toc10  
A
0V  
B
R
= 47I  
LOAD  
LOAD CURRENT  
500mA/div  
50mA  
0V  
C
0V  
D
0V  
0V  
MAIN  
(AC-COUPLED)  
200mV/div  
V
INDUCTOR  
CURRENT  
2A/div  
0V E  
F
0A  
0V  
100µs/div  
10ms/div  
A: V , 5V/div  
D: V  
E: V  
, 10V/div  
VREF_O  
SUP  
B: V , 10V/div  
, 2V/div  
LX  
VDPM  
C: V , 10V/div F: V , 20V/div  
MAIN VGHM  
OPERATIONAL AMPLIFIER  
FREQUENCY RESPONSE  
OPERATIONAL AMPLIFIER  
LARGE-SIGNAL STEP RESPONSE  
MAX17115 toc12  
4
V
= 10V  
VOP  
2
0
V
OPI  
2V/div  
NO LOAD  
-2  
-4  
2V  
V
100pF LOAD  
OPO  
2V/div  
-6  
-8  
2V  
-10  
100  
1000  
10,000  
100,000  
100ns/div  
FREQUENCY (Hz)  
8_ _ _ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ  
Internal-Switch Boost Regulator and High-Voltage,  
Low-Dropout Linear Regulator for TFT LCDs  
Typical Operating Characteristics (continued)  
(Circuit of Figure 1, V = 5V, V  
= 16V, T = +25NC, unless otherwise noted.)  
A
IN  
MAIN  
OPERATIONAL AMPLIFIER  
OPERATIONAL AMPLIFIER  
RAIL-TO-RAIL INPUT/OUTPUT  
SMALL-SIGNAL STEP RESPONSE  
MAX17115 toc14  
MAX17115 toc13  
V
= 10V  
V
OPI  
VOP  
100mV/div  
(AC-COUPLED)  
V
OPI  
5V/div  
0V  
0V  
V
0V  
OPO  
5V/div  
V
OPO  
100mV/div  
(AC-COUPLED)  
0V  
4µs/div  
40ns/div  
OPERATIONAL AMPLIFIER  
LOAD-TRANSIENT RESPONSE  
MAX17115 toc15  
V
OPO  
(AC-COUPLED)  
1V/div  
0V  
0mA  
I
OPO  
100mA/div  
400ns/div  
ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ_ _ 9  
Internal-Switch Boost Regulator and High-Voltage,  
Low-Dropout Linear Regulator for TFT LCDs  
Pin Description  
PIN  
NAME  
FUNCTION  
High-Voltage LDO Regulator Feedback Input. Connect VREF_FB to the center of a resistive voltage-  
1
VREF_FB divider between VREF_O and AGND to set the LDO output voltage. Place the resistive voltage-divid-  
er within 5mm of VREF_FB.  
High-Voltage LDO Regulator Output. Bypass VREF_O to AGND with a minimum 2.2FF capacitor  
within 5mm of the pin.  
2
3
4
VREF_O  
High-Voltage LDO Regulator Supply Input. Bypass VREF_I to AGND with a minimum 1FF capacitor  
within 5mm of the pin.  
VREF_I  
Operational Amplifier Supply Input. Typically connected to the output of the step-up regulator.  
Bypass VOP to OPGND with a minimum 1FF capacitor within 5mm of the pin.  
VOP  
5
6
7
OPO  
OPI  
Operational Amplifier Output. OPO is high impedance in shutdown.  
Operational Amplifier Noninverting Input  
OPGND  
Operational Amplifier Ground  
High-Voltage Switch Control Input. When VFLK is high, the high-voltage switch between VGH and  
VGHM is on and the high-voltage switch between VGHM and DRN is off. When VFLK is low, the  
switch between VGH and VGHM is off and the switch between VGHM and DRN is on. VFLK is inhib-  
ited by the IN UVLO and when the voltage on VDPM is less than 1.24V.  
8
VFLK  
9
XAO  
Reset and XAO Function Output  
Voltage-Detection Input. Connect VDET to the center of a resistive voltage-divider between IN and  
AGND to set the threshold voltage for the XAO function.  
10  
VDET  
High-Voltage Stress Control Input. When HVS_EN is high, the internal switch between RHVS and  
AGND is on. When HVS_EN is low, RHVS is high impedance.  
11  
12  
HVS_EN  
FREQ  
Frequency-Select Input. Connect FREQ to AGND to select the step-up regulator’s 640kHz operating  
frequency. Connect FREQ to IN to select the step-up regulator’s 1.2MHz operating frequency. This  
input has 6FA pulldown current.  
Shutdown Control Input. Connect EN to AGND to disable the boost operation. Connect EN to IN to  
enable the boost operation.  
13  
EN  
14, 26  
AGND  
Analog Ground  
Power-Supply Input. IN supplies the internal reference and other internal circuitry. Connect IN to the  
input supply voltage and bypass IN to AGND with a minimum 1FF ceramic capacitor. (Pin 15 sup-  
plies current to internal analog circuits. Using an RC filter on pin 15 improves noise performance of  
the IC. Minimum resistor should be used on pin 16 due to high current through pin 16.)  
15, 16  
IN  
External p-Channel MOSFET Gate-Drive Output. If used, connect GATE to the gate of an external  
p-channel MOSFET between the input supply and the step-up converter’s inductor (see Figure 1). If  
not used, leave GATE unconnected.  
17  
GATE  
LX  
Step-Up Regulator Switching Node. Drain of the internal n-channel MOSFET between LX and PGND.  
Connect the inductor and catch diode here and minimize trace area for lowest EMI.  
18, 19  
20, 21  
22, 28  
PGND  
N.C.  
Power Ground. Source of the internal n-channel MOSFET between LX and PGND.  
No Connection. Not internally connected.  
Open-Drain Output of the Internal n-Channel MOSFET to AGND. Connect RHVS to FB through a  
resistor to adjust the step-up converter’s output to a higher voltage. If unused, leave RHVS uncon-  
nected. When HVS_EN is low, RHVS is high impedance. When HVS_EN is logic-high, RHVS con-  
nects to AGND.  
23  
24  
RHVS  
FB  
Step-Up Regulator Feedback Input. Connect FB to the center of a resistive voltage-divider between  
the step-up regulator output and AGND to set the regulator’s output voltage. Place the resistive  
voltage-divider within 5mm of FB.  
10_ _ _ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ  
Internal-Switch Boost Regulator and High-Voltage,  
Low-Dropout Linear Regulator for TFT LCDs  
Pin Description (continued)  
PIN  
NAME  
FUNCTION  
Compensation Pin for Error Amplifier. Connect a series RC from COMP to AGND. Typical values are  
47.5kI and 560pF.  
25  
COMP  
Soft-Start Control Pin. Connect a capacitor (C ) to this pin. Leave SS unconnected if a slow soft-start is  
SS  
not desired. The soft-start capacitor is charged by a 4FA current source. The full current limit is reached  
27  
SS  
after around t = C x 200Fs/nF. The soft-start capacitor is discharged to AGND when EN is low. On EN’s  
SS  
rise, the soft-start capacitor is quickly charged to 0.4V, after which, soft-start begins.  
High-Voltage Switch Delay Input. Connect a capacitor from VDPM to AGND to set the high-voltage  
switch startup delay.  
29  
30  
31  
VDPM  
VGH  
High-Voltage Switch Supply Input. Source of the internal high-voltage p-channel MOSFET between  
VGH and VGHM. Bypass VGH to PGND with a minimum of 0.1FF capacitor within 5mm of VGH.  
High-Voltage Switch Output. VGHM is the common junction of the internal high-voltage MOSFETs.  
VGHM is typically used to power the gate-driver IC’s positive supply input.  
VGHM  
High-Voltage Switch Input. Drain of the internal high-voltage MOSFET switch between DRN and  
VGHM.  
32  
—
DRN  
EP  
Exposed Pad. Connect EP to AGND.  
ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ_ _ 11  
Internal-Switch Boost Regulator and High-Voltage,  
Low-Dropout Linear Regulator for TFT LCDs  
390ω  
V
V
GON  
30V/20mA  
0.1µF  
0.1µF  
GOFF  
-6.8V/20mA  
6.8V  
0.1µF  
0.1µF  
0.1µF  
V
SUP  
4.5V TO 5.5V  
D2  
D3  
C1  
10µF  
6.3V  
L1  
3µH  
Q1  
D1  
V
MAIN  
16V/500mA  
C4  
10µF  
25V  
C3  
10µF  
25V  
C2  
10µF  
6.3V  
R1  
137kω  
GATE  
LX  
FB  
R4  
5.6ω  
V
IN  
R2  
11.5kω  
IN  
C5  
1µF  
PGND  
AGND  
R4  
47.5kω  
COMP  
560pF  
OPEN  
EN  
SS  
R3  
150kω  
33nF  
FREQ  
V
IN  
RHVS  
VOP  
HVS_EN  
VGH  
V
MAIN  
V
GON  
0.1µF  
1µF  
MAX17115  
VGHM  
DRN  
OPGND  
OPO  
1kω  
TO VCOM  
BACKPLANE  
150kω  
100kω  
FROM  
TCON  
VFLK  
OPI  
VREF_I  
V
MAIN  
VDPM  
1µF  
33nF  
V
VREF_O  
GAMMA  
V
IN  
15V/20mA  
R5  
10kω  
2.2µF  
20kω  
VREF_FB  
TO GATE  
DRIVER  
V
SUP  
XAO  
R6  
10kω  
110kω  
100kω  
VDET  
EP  
Figure 1. Typical Operating Circuit  
12_ _ _ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ  
Internal-Switch Boost Regulator and High-Voltage,  
Low-Dropout Linear Regulator for TFT LCDs  
Table_1._Component_List  
REFERENCE_  
DESIGNATION  
REFERENCE_  
DESIGNATION  
DESCRIPTION  
DESCRIPTION  
10FF, 6.3V X5R ceramic capacitors  
(0805)  
TDK C2012X5R0J106K  
200mA, 100V dual diodes (SOT23)  
Fairchild MMBD4148SE  
D2, D3  
L1  
C1, C2  
3.0FH, 3A inductor  
Sumida CDRH6D28-3R0  
10FF, 25V X5R ceramic capacitors  
(1206)  
TDK C3216X5R1E106M  
C3, C4  
D1  
SC-70 SiA443DJ, p-channel MOSFET,  
-20V/63mI  
Vishay PowerPak  
Q1  
3A, 30V Schottky diode (M-flat)  
Toshiba CMS02  
Table_2._Component_Suppliers  
SUPPLIER  
Fairchild Semiconductor  
Sumida Corp.  
PHONE  
FAX  
WEBSITE  
847-803-6100  
408-822-2000  
847-545-6700  
949-455-2000  
402-563-6866  
847-390-4405  
408-822-2102  
www.fairchildsemi.com  
www.sumida.com  
TDK Corp.  
847-545-6720  
949-859-3963  
402-563-6296  
www.component.tdk.com  
www.toshiba.com/taec  
www.vishay.com  
Toshiba America Electronic Components, Inc.  
Vishay  
Step-Up Regulator  
Typical Operating Circuit  
The main step-up regulator employs a current-mode,  
fixed-frequency (1.2MHz/640kHz-selectable) PWM archi-  
tecture to maximize loop bandwidth and provides fast-  
transient response to pulsed loads typical of TFT-LCD  
panel source drivers. High switching frequency opera-  
tion allows the use of low-profile inductors and ceramic  
capacitors to minimize the thickness of LCD panel  
designs. A current-control external capacitor-controlled  
programmable soft-start minimizes inrush currents. The  
The MAX17115 typical operating circuit (Figure 1) is a  
complete power-supply system for TFT LCD displays.  
The circuit generates a +16V/500mA source-driver sup-  
ply and +30V/20mA and -6.8V/20mA gate-driver sup-  
plies. The input-voltage range for the IC is from +2.5V to  
+6.0V. The listed load currents in Figure 1 are available  
from a +4.5V to +5.5V supply. Table 1 lists some rec-  
ommended components, and Table 2 lists the contact  
information of component suppliers.  
output voltage can be set from V to 18V with an exter-  
IN  
nal resistive voltage-divider.  
Detailed Description  
The regulator controls the output voltage and the power  
delivered to the output by modulating the duty cycle (D)  
of the internal power MOSFET in each switching cycle.  
The duty cycle of the MOSFET is approximated by:  
The MAX17115 contains a high-voltage step-up regula-  
tor, a high-accuracy linear regulator, a high-performance  
amplifier, a high-voltage switch control block for gate-  
driver supply modulation, and a logic-controlled open-  
drain MOSFET switch to AGND for high-voltage stress  
aging tests. Figure 2 shows the MAX17115 functional  
diagram.  
V
-V  
MAIN IN  
V
D ≈  
MAIN  
ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ_ _ 13  
Internal-Switch Boost Regulator and High-Voltage,  
Low-Dropout Linear Regulator for TFT LCDs  
V
V
GON  
GOFF  
V
IN  
V
MAIN  
LX  
GATE  
FB  
STEP-UP  
CONTROLLER  
IN  
PGND  
AGND  
EN  
COMP  
IN  
FREQ  
SS  
OSCILLATOR  
SOFT-START  
RHVS  
HVS_EN  
VGH  
VOP  
SWITCH  
CONTROL  
VGHM  
OPO  
DRN  
OPGND  
VFLK  
OPI  
VREF_I  
VDPM  
XAO  
VREF_O  
LINEAR  
REGULATOR  
MAX17115  
VREF_FB  
REF  
VDET  
EP  
Figure 2. MAX17115 Functional Diagram  
14_ _ _ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ  
Internal-Switch Boost Regulator and High-Voltage,  
Low-Dropout Linear Regulator for TFT LCDs  
Figure 3 shows the functional diagram of the step-up  
regulator. An error amplifier compares the signal at FB  
to 1.24V and changes the COMP output. The voltage at  
COMP sets the peak inductor current. As the load var-  
ies, the error amplifier sources or sinks current to the  
COMP output accordingly to produce the inductor peak  
current necessary to service the load. To maintain stabil-  
ity at high duty cycles, a slope-compensation signal is  
summed with the current-sense signal.  
the MOSFET. Since the inductor current is continuous,  
a transverse potential develops across the inductor that  
turns on the boost diode (D1). The voltage across the  
inductor then becomes the difference between the out-  
put voltage and the input voltage. This discharge condi-  
tion forces the current through the inductor to ramp back  
down, transferring the energy stored in the magnetic  
field to the output capacitor and the load. The MOSFET  
remains off for the rest of the clock cycle.  
On the rising edge of the internal clock, the controller sets  
a flip-flop, turning on the n-channel MOSFET and apply-  
ing the input voltage across the inductor. The current  
through the inductor ramps up linearly, storing energy in  
its magnetic field. Once the sum of the current-feedback  
signal and the slope compensation exceeds the COMP  
voltage, the controller resets the flip-flop and turns off  
Operational Amplifier  
The MAX17115 has one operational amplifier. The buffer  
amplifier is typically used to drive the LCD backplane  
voltage (VCOM) in TFT LCDs. It features high output cur-  
rent, 45V/Fs slew rate, and 20MHz/3dB bandwidth. The  
rail-to-rail input and output capability maximizes system  
flexibility.  
LX  
CLOCK  
LOGIC  
AND  
DRIVER  
PGND  
ILIM  
COMPARATOR  
IN  
SS  
SOFT-START  
SLOPE COMP  
PWM  
COMPARATOR  
CURRENT  
SENSE  
C
FREQ  
OSCILLATOR  
TO FAULT  
LOGIC  
ERROR AMP  
1.00V  
FB  
FAULT  
COMPARATOR  
1.24V  
COMP  
Figure 3. Step-Up Regulator Functional Diagram  
ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ_ _ 15  
Internal-Switch Boost Regulator and High-Voltage,  
Low-Dropout Linear Regulator for TFT LCDs  
Short-Circuit Current Limit  
The operational amplifier limits short-circuit current to  
approximately Q200mA if the output is directly shorted to  
VOP or to OPGND. If the short-circuit condition persists,  
the junction temperature of the IC rises until it reaches  
the thermal-shutdown threshold (+160NC typ) and acti-  
vates the thermal-fault protection, shutting off all the IC’s  
outputs. The IC restarts automatically when the device  
cools down by approximately 15NC.  
Power-Up Sequence and Soft-Start  
Once IN exceeds its UVLO (2.25V typ) and EN is above  
its logic-high threshold, the startup procedure begins.  
GATE is initially high and pulled low to turn on the exter-  
nal p-channel MOSFET if no output fault is detected.  
After GATE reaches its GATE-done threshold, the main  
step-up regulator’s soft-start begins. With the main step-  
up regulator’s soft-start, the voltage on VOP and VREF_I  
rises. Once VOP or VREF_I exceeds the UVLO, the  
relative buffer amplifier and LDO are enabled. Figure 4  
shows the power-up sequence.  
Driving a Pure Capacitive Load  
In general, the LCD backplane (VCOM) consists of a dis-  
tributed series capacitance and resistance, a load that  
can be easily driven by the buffer. However, if the buffer  
is used in an application with a pure capacitive load,  
steps must be taken to ensure stable operation.  
The IC employs a current-based, external-capacitor  
adjustable soft-start for the step-up regulator to control  
inrush current and voltage overshoot and to ensure a  
well-defined startup behavior. The voltage level on the  
SS pin directly controls an internal current limit. The cur-  
rent limit reaches its full current limit at approximately:  
As the buffer amplifier’s capacitive load increases, the  
amplifier’s bandwidth decreases and gain peaking  
increases. A 5I to 50I small resistor placed between  
OPO and the capacitive load reduces peaking, but also  
reduces the gain. An alternative method of reducing  
peaking is to place a series RC network (snubber) in par-  
allel with the capacitive load. The RC network does not  
continuously load the output or reduce the gain. Typical  
values of the resistor are between 100I and 200I, and  
the typical value of the capacitor is 10nF.  
t = C x 200Fs/nF  
SS  
The step-up regulator output voltage usually reaches  
regulation before C reaches its fully charged state.  
SS  
A capacitor (CVDPM) from VDPM to AGND determines  
the switch-control-block startup delay. After the soft-start  
routine is complete, a 5FA current source starts charging  
CVDPM. Once the capacitor voltage exceeds 1.24V (typ),  
the switch-control block is enabled as shown in Figure  
4. After the switch-control block is enabled, VGHM can  
be connected to VGH or DRN through the internal high-  
voltage p-channel switches, depending upon the state of  
VFLK. Before startup (EN is low) or when IN is less than its  
UVLO, both VGHM switches are turned off and VDPM is  
internally connected to AGND to discharge CVDPM. Select  
CVDPM to set the delay time using the following equation:  
Undervoltage Lockout (UVLO)  
The UVLO circuit compares the input voltage at IN with  
the UVLO threshold (2.25V typ) to ensure the input  
voltage is high enough for reliable operation. The wide  
200mV (typ) hysteresis prevents supply transients from  
causing a restart. The startup procedure begins when  
the input voltage exceeds the UVLO rising threshold and  
EN goes above threshold. During normal operation, if  
the input voltage falls below the UVLO falling threshold,  
the controller turns off the main step-up regulator, turns  
off the linear regulator, pulls GATE high to turn off the  
external p-channel MOSFET, disables the buffer, plac-  
ing its output into a high-impedance state, and disables  
the switch control block, placing VGHM into a high-  
impedance state.  
5FA  
1.24V  
C
=DELAY_TIME ×  
VDPM  
Switch-Control Block  
The switch-control block is not activated until all four of  
the following conditions are satisfied:  
U The input voltage exceeds its UVLO.  
U The soft-start routine of the boost regulator is  
High-Accuracy High-Voltage  
LDO Regulator  
The LDO features high output accuracy (Q0.5%) and  
low-dropout (LDO) voltage (0.25V typ) and can supply at  
least 40mA. The LDO is typically used to drive a gamma  
buffer reference resistor string and its output voltage is  
adjustable through a resistor-divider.  
complete.  
U No fault condition is detected.  
U V  
exceeds its turn-on threshold. VDPM begins  
VDPM  
charging when SS reaches the internal threshold.  
Once activated, if VFLK is high, the 5I (typ) internal  
p-channel switch between VGH and VGHM turns on  
and the 30I (typ) p-channel switch between VGHM  
16_ _ _ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ  
Internal-Switch Boost Regulator and High-Voltage,  
Low-Dropout Linear Regulator for TFT LCDs  
V
IN  
IN UVLO  
TIME  
V
EN  
V
TH  
> 2.1V  
TIME  
V
GATE  
TIME  
V
SS  
SS DONE  
0.4V  
TIME  
V
MAIN  
V
V
GON  
TIME  
GOFF  
V
VREF_O  
5.4V  
TIME  
VGHM DEPENDS ON VFLK  
V
V
VGHM  
VGHM IS FLOATING  
VDPM  
1.24V  
SOFT-START SOFT-START  
STARTUP  
PROCEDURE  
BEGINS  
TIME  
BEGINS  
ENDS  
Figure 4. Power-Up Sequence  
ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ_ _ 17  
Internal-Switch Boost Regulator and High-Voltage,  
Low-Dropout Linear Regulator for TFT LCDs  
and DRN turns off. If VFLK is low, the 5I (typ) internal  
p-channel switch between VGH and VGHM turns off  
and the 30I (typ) p-channel switch between VGHM  
and DRN turns on. Before activation, neither switch is  
turned on and VGHM is in a high-impedance state.  
Conversely, when HVS_EN is low, the switch is turned  
off and the output remains in its original voltage setting.  
XAO Function  
XAO is an open-drain output that connects to AGND when-  
ever VIN is below its UVLO threshold (2.25V typ) or VVDET is  
below its detection threshold (1.24V typ). In the meantime,  
VGHM is tied to VGH. XAO is guaranteed to remain low  
until VIN falls below the XAO UVLO level (1.7V max).  
Fault Protection  
During steady-state operation, if the output of the main  
regulator does not exceed its respective fault-detection  
threshold, the MAX17115 activates an internal fault timer.  
If the continuous fault exceeds the fault-timer duration  
(55ms typ), the MAX17115 sets the fault latch to shut  
down all the outputs and turn off the external p-channel  
MOSFET (GATE is pulled high). Once the fault condition  
is removed, cycle the input voltage to clear the fault latch  
and reactivate the device.  
Design Procedure  
Step-Up Regulator  
Inductor Selection  
The minimum inductance value, peak current rating, and  
series resistance are factors to consider when select-  
ing the inductor. These factors influence the converter’s  
efficiency, maximum output load capability, transient-  
response time, and output-voltage ripple. Size and cost  
are also important factors to consider.  
The MAX17115 also provides OVP for the output of the  
step-up regulator by monitoring the voltage on the VOP  
pin. During normal operation, if VOP is higher than the  
VOP overvoltage threshold (20V typ), the step-up con-  
verter stops switching to prevent excessive voltage from  
damaging the MAX17115. Once VOP drops below the  
threshold voltage, the step-up regulator resumes switch-  
ing and regulates the needed output voltage.  
The maximum output current, input voltage, output volt-  
age, and switching frequency determine the inductor  
value. Very high inductance values minimize the current  
ripple and therefore reduce the peak current, which  
decreases core losses in the inductor and conduction  
losses in the entire power path. However, large induc-  
tor values also require more energy storage and more  
turns of wire, which increase size and can increase con-  
duction losses in the inductor. Low-inductance values  
decrease the size, but increase the current ripple and  
peak current. Finding the best inductor involves choos-  
ing the best compromise between circuit efficiency,  
inductor size, and cost.  
Thermal-Overload Protection  
Thermal-overload protection prevents excessive power  
dissipation from overheating the MAX17115. When the  
junction temperature exceeds TJ = +160NC (typ), a ther-  
mal sensor immediately activates the fault protection to  
shut down all outputs and turns off the external p-chan-  
nel MOSFET (GATE is pulled high), allowing the device  
to cool down. Once the device cools down by approxi-  
mately 15NC, the MAX17115 starts up automatically. The  
thermal-overload protection protects the controller in the  
event of fault conditions. For continuous operation, do  
not exceed the absolute maximum junction temperature  
rating of TJ = +150NC.  
The equations used here include a constant, LIR, which  
is the ratio of the inductor peak-to-peak ripple current  
to the average DC inductor current at the full-load cur-  
rent. The best trade-off between inductor size and circuit  
efficiency for step-up regulators generally has an LIR  
between 0.3 and 0.6. However, depending on the AC  
characteristics of the inductor core material and ratio  
of inductor resistance to other power-path resistances,  
the best LIR can shift up or down. If the inductor resis-  
tance is relatively high, more ripple can be accepted to  
reduce the number of turns required and increase the  
wire diameter. If the inductor resistance is relatively low,  
increasing inductance to lower the peak current can  
decrease losses throughout the power path. If extremely  
thin high-resistance inductors are used, as is common  
for LCD panel applications, the best LIR can increase to  
between 0.5 and 1.0.  
High-Voltage Stress (HVS) Mode  
The HVS mode is used to increase the supply voltage  
of TFT LCD for aging tests. The MAX17115 provides an  
internal open-drain switch to AGND that is typically used  
to change the feedback divider impedance of the step-  
up regulator (FB). Connect an appropriate resistor from  
RHVS to FB to implement this feature.  
A control input (HVS_EN) determines when the switch  
is turned on. When HVS_EN is high, the internal switch  
is turned on and the output voltage is adjusted accord-  
ing to the resistor connected to the feedback input.  
18_ _ _ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ  
Internal-Switch Boost Regulator and High-Voltage,  
Low-Dropout Linear Regulator for TFT LCDs  
Once a physical inductor is chosen, higher and lower  
values of the inductor should be evaluated for efficiency  
improvements in typical operating regions.  
The inductor’s saturation current rating and the  
MAX17115’s LX current limit (I ) should exceed I  
,
PEAK  
LIM  
and the inductor’s DC current rating should exceed  
. For good efficiency, choose an inductor  
I
IN(DC,MAX)  
In Figure 1, the LCD’s gate-on and gate-off supply  
voltages are generated from two unregulated charge  
pumps driven by the step-up regulator’s LX node. The  
additional load on LX must therefore be considered in  
the inductance and current calculations. The effective  
with less than 0.1I series resistance.  
Considering Figure 1, the maximum load current  
(I ) is 500mA, with a 16V output and a typical  
MAIN(MAX)  
input voltage of 5V. The effective full-load step-up cur-  
rent is:  
maximum output current, I  
becomes the sum  
MAIN(EFF)  
of the maximum load current of the step-up regulator’s  
output plus the contributions from the positive and nega-  
tive charge pumps:  
I
= 500mA + 1O 20mA +  
(1+1) O 20mA = 560mA  
MAIN(EFF)  
Considering the typical operating circuit, the switching  
frequency is set to 1.2MHz, the maximum load current  
MAIN(MAX)  
I
= I  
+ E  
x I  
+
MAIN(EFF)  
MAIN(MAX)  
NEG  
+ 1) x I  
POS  
NEG  
(E  
POS  
(I  
) is 500mA with a 16V output and a typical  
where I  
is the maximum step-up output cur-  
is the number of negative charge-pump stag-  
input voltage of 5V. Choosing an LIR of 0.5 and estimat-  
ing efficiency 88% at this operating point:  
MAIN(MAX)  
rent, E  
NEG  
es, E  
is the number of positive charge-pump stages,  
is the negative charge-pump output current, and  
is the positive charge-pump output current, assum-  
POS  
5V  
16V - 5V  
0.88  
2
I
I
NEG  
POS  
L=(  
) (  
)(  
) ≈ 3.0FH  
16V 0.56A ×1.2MHz 0.5  
ing the initial pump source for IPOS is V  
.
MAIN  
Using the circuit’s minimum input voltage (4.5V) and esti-  
mating efficiency of 83% at that operating point:  
Using the typical operating circuit of Figure 1, calculate  
the approximate inductor value using the typical input  
voltage (V  
the expected efficiency (E  
curve in the Typical Operating Characteristics section,  
), the maximum output current (I  
),  
SUP  
MAIN(EFF)  
0.56A ×16V  
4.5V × 0.83  
IIN(DC,MAX)  
=
= 2.40A  
) taken from an appropriate  
TYP  
and an estimate of LIR based on the above discussion:  
The ripple current and the peak current are:  
V
V
-V  
η
TYP  
LIR  
SUP  
MAIN SUP  
4.5V ×(16V-4.5V)  
3.0FH×16V ×1.2MHz  
L=(  
)(  
)(  
)
IRIPPLE  
=
≈ 0.90A  
V
I
× f  
MAIN MAIN(EFF) OSC  
Choose an available inductor value from an appropriate  
inductor family. Calculate the maximum DC input current  
0.90A  
IPEAK=2.40A +  
= 2.85A  
2
at the minimum input voltage (V  
) using con-  
SUP(MIN)  
servation of energy and the expected efficiency at that  
operating point (EMIN) taken from the appropriate curve  
in the Typical Operating Characteristics:  
Output-Capacitor Selection  
The total output voltage ripple has two components: the  
capacitive ripple caused by the charging and discharg-  
ing of the output capacitance, and the ohmic ripple due  
to the capacitor’s ESR:  
I
× V  
MAIN  
MAIN(EFF)  
I
=
IN(DC,MAX)  
V
× η  
MIN  
SUP(MIN)  
VRIPPLE = VRIPPLE(C) + VRIPPLE(ESR)  
Calculate the ripple current at that operating point and  
the peak current required for the inductor:  
I
C
V
V
− V  
MAIN  
MAIN IN  
VRIPPLE(C)  
≈
× f  
V
(MIN) ×(VMAIN - V  
)
OUT MAIN  
OSC  
SUP  
IN(MIN)  
IRIPPLE  
=
L × VMAIN × fOSC  
and:  
VRIPPLE(ESR) ≈ IPEAK ×RESR(COUT)  
is the peak inductor current (see the  
IRIPPLE  
where I  
PEAK  
IPEAK=IIN(DC,MAX)  
+
2
Inductor Selection section). For ceramic capacitors,  
ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ_ _ 19  
Internal-Switch Boost Regulator and High-Voltage,  
Low-Dropout Linear Regulator for TFT LCDs  
Loop Compensation  
to set the high-frequency integrator gain  
the output-voltage ripple is typically dominated by  
. The voltage rating and temperature charac-  
Choose R  
V
COMP  
RIPPLE(C)  
for fast-transient response. Choose C  
to set the  
teristics of the output capacitor must also be considered.  
COMP  
integrator zero to maintain loop stability. For low-ESR  
output capacitors, use the following equations to obtain  
stable performance and good transient response:  
Input-Capacitor Selection  
The input capacitor (C ) reduces the current peaks  
IN  
drawn from the input supply and reduces noise injection  
into the IC. Two 10FF ceramic capacitors are used in the  
typical operating circuit (Figure 1) because of the high  
source impedance seen in typical lab setups. Actual  
applications usually have much lower source impe-  
dance since the step-up regulator often runs directly  
from the output of another regulated supply. Typically,  
253 × VSUP × VOUT × COUT  
RCOMP  
CCOMP  
≈
≈
L ×IMAIN(MAX)  
VOUT × COUT  
10 ×IMAIN(MAX) ×RCOMP  
C
can be reduced below the values used in the typi-  
IN  
To further optimize transient response, vary R  
in  
COMP  
cal operating circuit. Ensure a low-noise supply at IN by  
using adequate C . Alternatively, greater voltage varia-  
20% steps and C  
in 50% steps while observing  
COMP  
IN  
transient-response waveforms.  
tion can be tolerated on C if IN is decoupled from C  
IN  
IN  
High-Voltage LDO Linear Regulator  
using an RC lowpass filter (see R4 and C5 in Figure 1).  
Output-Voltage Selection  
The output voltage of the high-accuracy LDO is set by  
connecting a resistive voltage-divider from the output  
(VREF_O) to AGND with the center tap connected to  
VREF_FB (see Figure 1). Select R6 in the 10kI to 50kI  
range. Calculate R5 with the following equation:  
Rectifier Diode  
The MAX17115’s high switching frequency demands a  
high-speed rectifier. Schottky diodes are recommended  
for most applications because of their fast recovery time  
and low forward voltage. In general, a 3A Schottky diode  
complements the internal MOSFET well.  
V
Step-Up Regulator Output-Voltage Selection  
The output voltage of the main step-up regulator is set  
by connecting a resistive voltage-divider from the output  
VREF_O  
R5=R6×(  
-1)  
V
VREF_FB  
(V  
) to AGND with the center tap connected to FB  
(see Figure 1). Select R2 in the 10kI to 50kI range.  
Calculate R1 with the following equation:  
MAIN  
where V  
, the LDO’s feedback set point, is 1.24V.  
VREF_FB  
Place R5 and R6 close to the IC.  
Input and Output Capacitor Selection  
V
R1=R2×( MAIN-1)  
To ensure stability of the LDO, use a minimum of 1FF on  
the regulator’s input (VREF_I) and a minimum of 2.2FF  
on the regulator’s output (VREF_O). Place the capaci-  
tors near the pins and connect their ground connections  
directly together.  
V
FB  
where V , the step-up regulator’s feedback set point, is  
FB  
1.24V. Place R1 and R2 close to the IC.  
High-Voltage Stress (HVS)  
Mode Output-Voltage Setting  
Applications Information  
See Figure 1 for the typical operating circuit. R3 is con-  
nected to FB to change the output voltage whenever  
HVS_EN is high. The required value for R3 can be calcu-  
lated with the following equation:  
Power Dissipation  
An IC’s maximum power dissipation depends on the  
thermal resistance from the die to the ambient environ-  
ment and the ambient temperature. The thermal resis-  
tance depends on the IC package, PCB copper area,  
other thermal mass, and airflow. More PCB copper, cool-  
er ambient air, and more airflow increase the possible  
dissipation, while less copper or warmer air decreases  
the IC’s dissipation capability. The major components  
of power dissipation include the power dissipated in the  
step-up regulator and the power dissipated by the buffer  
amplifier and high-voltage LDO.  
R1  
R3=  
V
R1  
R2  
MAIN_HVS  
− (1+  
)
V
FB  
20_ _ _ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ  
Internal-Switch Boost Regulator and High-Voltage,  
Low-Dropout Linear Regulator for TFT LCDs  
Step-Up Regulator  
The largest portions of power dissipation in the step-  
up regulator are the internal MOSFET, the inductor,  
and the output diode. If the step-up regulator has 90%  
efficiency, approximately 3% to 5% of the power is lost  
in the internal MOSFET, approximately 3% to 4% in the  
inductor, and approximately 1% in the output diode.  
The remaining 1% to 3% is distributed among the input  
and output capacitors and the PCB traces. If the input  
power is approximately 5W, the power loss in the internal  
MOSFET is approximately 150mW to 250mW. The follow-  
ing formula can be used to estimate the power loss in  
the internal power MOSFET (excluding switching losses):  
positive terminal of the input capacitor to the induc-  
tor, to the IC’s LX pin, out of PGND, and to the input  
capacitor’s negative terminal. The high-current output  
loop is from the positive terminal of the input capaci-  
tor to the inductor, to the output diode (D1), and to the  
positive terminal of the output capacitors, reconnect-  
ing between the output capacitor and input capacitor  
ground terminals. Connect these loop components  
with short, wide connections. Avoid using vias in the  
high-current paths. If vias are unavoidable, use many  
vias in parallel to reduce resistance and inductance.  
Create a power-ground island (PGND) consisting  
of the input and output capacitor grounds, PGND  
pin, and any charge-pump components. Connect  
all these together with short, wide traces or a small  
ground plane. Maximizing the width of the power  
ground traces improves efficiency and reduces out-  
put voltage ripple and noise spikes. Create an analog  
ground plane (AGND) consisting of the AGND pin, all  
the feedback-divider ground connections, the opera-  
tional amplifier divider ground connection, the COMP,  
VDPM and SS capacitor ground connections, and the  
device’s exposed backside pad. Connect the AGND  
and PGND islands by connecting the PGND pin  
directly to the exposed backside pad. Make no other  
connections between these separate ground planes.  
2
P
= I  
×R  
×D  
DSON  
LX_ON  
IN(DC,MAX)  
where RDSON is the on-resistance for the internal power  
MOSFET.  
Operational Amplifiers  
The power dissipated in the buffer amplifier depends on  
the output current, the output voltage, and the supply  
voltage:  
PD  
= I  
× V - V  
VOP OPO  
(
)
SOURCE  
PD  
OPO_SOURCE  
= I  
× V  
OPO_SINK OPO  
SINK  
U Place all feedback voltage-divider resistors within  
5mm of their respective feedback pins. The divider’s  
center trace should be kept short. Placing the resis-  
tors far away causes their FB traces to become  
antennas that can pick up switching noise. Take care  
to avoid running any feedback trace near LX or the  
switching nodes in the charge pumps, or provide a  
ground shield.  
where I  
the amplifier, and I  
the amplifier sinks.  
is the output current sourced by  
OPO_SOURCE  
is the output current that  
OPO_SINK  
High-Voltage LDO Regulator  
The power dissipation of the high-voltage LDO depends  
on load current and the voltage drop between VREF_I and  
VREF_O. It can be estimated by the following formula:  
U Place the IN pin bypass capacitors as close as pos-  
sible to the device. The ground connection of the IN  
bypass capacitor should be connected directly to the  
AGND pin with a wide trace.  
P
=I  
× V  
LR LOAD DROP  
where I  
is the output current from the LDO and  
LOAD  
U Minimize the length and maximize the width of the  
traces between the output capacitors and the load for  
best transient response.  
V
is the voltage drop between VREF_I and VREF_O.  
DROP  
PCB Layout and Grounding  
Careful PCB layout is important for proper operation. Use  
the following guidelines for good PCB layout:  
U Minimize the size of the LX node while keeping it wide  
and short. Keep the LX node away from feedback  
nodes (FB) and analog ground. Use DC traces to  
shield necessary.  
U Minimize the area of high-current loops by placing  
the inductor, the output diode, and the output capaci-  
tors near the input capacitors and near the LX and  
PGND pins. The high-current input loop goes from the  
Refer to the MAX17115 evaluation kit for an example of  
proper PCB layout.  
ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ_ _ 21  
Internal-Switch Boost Regulator and High-Voltage,  
Low-Dropout Linear Regulator for TFT LCDs  
Chip Information  
Package Information  
PROCESS: BiCMOS  
For the latest package outline information and land patterns,  
go to www.maxim-ic.com/packages. Note that a “+”, “#”, or  
“-” in the package code indicates RoHS status only. Package  
drawings may show a different suffix character, but the drawing  
pertains to the package regardless of RoHS status.  
PACKAGE_TYPE PACKAGE_CODE DOCUMENT_NO.  
32 TQFN  
T-3255+4  
21-0140  
22_ _ _ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ  
Internal-Switch Boost Regulator and High-Voltage,  
Low-Dropout Linear Regulator for TFT LCDs  
Revision History  
REVISION  
NUMBER  
REVISION  
DATE  
PAGES  
CHANGED  
DESCRIPTION  
0
1
7/09  
4/10  
Initial release  
Added reflow temperature and removed a line in the fault-protection description  
0
2, 4, 6, 18, 22  
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied.  
Maxim reserves the right to change the circuitry and specifications without notice at any time.  
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600  
23  
©
2010 Maxim Integrated Products  
Maxim is a registered trademark of Maxim Integrated Products, Inc.  

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