MAX16998AAUA/V+T [MAXIM]
Timer or RTC, CMOS,;
| 型号： | MAX16998AAUA/V+T |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Timer or RTC, CMOS, 高压 |
| 文件： | 总16页 (文件大小：149K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-4000; Rev 1; 4/09
High-Voltage Watchdog Timers with
Adjustable Timeout Delay
7/MAX1698
General Description
Features
The MAX16997/MAX16998 are microprocessor (µP)
supervisory circuits for high-input-voltage and low-qui-
escent-current applications. These devices detect
downstream circuit failures and provide switchover to
redundant circuitry. See the Selector Guide for the dif-
ferent versions of this product family.
o Wide 5V to 40V Input Voltage Range
o 18µA Quiescent Current (Typical at +125°C)
o Capacitor-Adjustable Timeout Period for
Watchdog and Reset
o Windowed Watchdog Timer Options
The MAX16997/MAX16998 family has four independent
inputs for reset and watchdog functions. SWT and SRT
inputs independently set the timeout periods of watch-
dog and reset timers through external capacitors.
RESETIN/EN monitor voltages at respective inputs. A
resistive voltage-divider sets the reset threshold.
(MAX16998B/D)
o External Voltage Monitoring (RESETIN for the
MAX16998A/B/D and EN for the MAX16997A)
o Car Battery-Compatible EN Input
o TTL- and CMOS-Compatible Open-Drain Outputs
o 18V Maximum Open-Drain Reset Output Voltage
o 28V Maximum Open-Drain Enable Output Voltage
The MAX16998A/B/D generate two output signals,
RESET and ENABLE. RESET asserts whenever
RESETIN drops below its threshold voltage or when the
watchdog timer detects a timing fault at WDI. Once
asserted, and after all reset conditions are removed,
o Power-On/Power-Off Reset Functionality
RESET remains low for the reset timeout period, t
,
RESET
(MAX16998A/B/D Only)
and then goes high. The MAX16997A generates one
output signal (ENABLE) based on the voltage level at
EN and the signal at WDI.
o AECQ-100 Qualified
o -40°C to +125°C Operating Temperature Range
o Small (3mm x 3mm) µMAX Package
o WDI Narrow Pulse Immunity
The MAX16997A does not have a RESET output. The
watchdog is disabled if the voltage at EN is below its
threshold. The MAX16997A watchdog timer starts tim-
ing when the voltage at EN becomes higher than the
preset threshold voltage level. Each time EN rises
above the preset threshold voltage, the initial watchdog
timeout period is 8 times the normal watchdog timeout
Ordering Information
PART
TEMP RANGE
-40°C to +125°C
-40°C to +125°C
-40°C to +125°C
-40°C to +125°C
PIN-PACKAGE
period (t ).
WP
MAX16997AAUA+
MAX16998AAUA+
MAX16998BAUA+
MAX16998DAUA+
8 µMAX
The MAX16997/MAX16998 are available in 8-pin lead-
®
free µMAX packages and are fully specified over the
8 µMAX
-40°C to +125°C automotive temperature range.
8 µMAX
8 µMAX
Applications
+Denotes a lead(Pb)-free/RoHS-compliant package.
Automotive
Industrial
Selector Guide
WATCHDOG
WINDOW SIZE (%)
PART
ENABLE
RESET
EN
RESETIN
MAX16997A
MAX16998A
MAX16998B
MAX16998D
100
100
50
✓
✓
✓
✓
—
✓
✓
✓
✓
—
✓
✓
✓
—
—
—
75
Pin Configurations appear at end of data sheet.
µMAX is a registered trademark of Maxim Integrated Products, Inc.
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
High-Voltage Watchdog Timers with
Adjustable Timeout Delay
ABSOLUTE MAXIMUM RATINGS
(All pins referenced to GND, unless otherwise noted.)
Junction-to-Case Thermal Resistance (θ ) (Note 1)......42°C/W
JC
IN, ENABLE ............................................................-0.3V to +45V
WDI, RESET, EN.....................................................-0.3V to +20V
RESETIN.................................................................-0.3V to +20V
SRT, SWT................................................................-0.3V to +12V
Maximum Current (all pins).................................................30mA
Junction-to-Ambient Thermal Resistance (θ ) (Note 1).....206.3°C/W
JA
Operating Temperature Range (T )..................-40°C to +125°C
A
Junction Temperature (T )...............................................+150°C
J
Storage Temperature Range.............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Continuous Power Dissipation (T = +70°C)
A
8-Pin µMAX (derate 4.8mW/°C above +70°C)..........387.8mW
Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-
layer board. For detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V = 14V, T = T = -40°C to +125°C, unless otherwise noted. Typical values are at T = +25°C.) (Note 2)
IN
A
J
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
40.0
30
UNITS
7/MAX1698
Operating Voltage Range
V
5.0
V
IN
T
T
= -40°C to +85°C
18
18
A
Supply Current
I
µA
IN
= -40°C to +125°C
60
A
SWT Ramp Current
SRT Ramp Current
I
V
V
= 1.0V
= 1.0V
450
410
500
500
550
600
nA
nA
RAMP_SWT
SWT
SRT
I
RAMP_SRT
SWT/SRT Ramp Threshold
Voltage
V
1.115
1.235
1.363
V
RAMP
RESET TIMER
V
V
V
rising
falling
= 2V
1.135
1.115
1.255
1.235
0.1
1.383
1.363
Power-On Reset Input Threshold
Voltage
RESETIN
RESETIN
RESETIN
V
V
PON
RESETIN Input Leakage Current
I
µA
LPON
RESET asserted, I
= 1mA
0.9
0.4
0.4
SINK
RESET Output Low Voltage
V
V
V
= 1.1V, I
= 160µA, RESET asserted
OLRST
IN
SINK
RESET asserted, I
= 0.4mA
SINK
RESET Leakage Current
ENABLE Output Low Voltage
ENABLE Leakage Current
Minimum Reset Timeout Period
Reset Timeout Period
I
V
= 20V, RESET not asserted
RESET
0.1
µA
V
LKGR
V
ENABLE asserted, I
= 5mA
SINK
0.4
OLEN
LKGE
I
V
= 14V, ENABLE not asserted
= 390pF (Note 3)
= 2000pF (Note 3)
= 47nF
0.1
1
µA
ms
ms
ms
µs
ENABLE
t
C
C
C
RESETmin
SRT
SRT
SRT
t
5
RESET
Maximum Reset Time Period
RESET to ENABLE Delay
t
116.09
1.5
RESETmax
t
REDL
RESETIN falling below V
falling edge
to RESET
PON
RESETIN to RESET Delay
t
1
µs
RRDL
2
_______________________________________________________________________________________
High-Voltage Watchdog Timers with
Adjustable Timeout Delay
7/MAX1698
ELECTRICAL CHARACTERISTICS (continued)
(V = 14V, T = T = -40°C to +125°C, unless otherwise noted. Typical values are at T = +25°C.) (Note 2)
IN
A
J
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
WATCHDOG TIMER
V
2.25
IH
WDI Input Threshold
V
V
0.9
IL
WDI Input Hysteresis
WDI
200
mV
µs
HYST
WDI Minimum Pulse Width
WDI Input Current
t
(Note 4)
6.5
WDImin
I
WDI = 0 or 14V
0.1
6.8
µA
ms
ms
ms
WDI
Minimum Watchdog Timeout
t
C
C
C
= 680pF (Note 3)
WPmin
SWT
SWT
SWT
Watchdog Timeout Period
t
= 1200pF (Note 3)
= 22nF
12
WP
Maximum Watchdog Timeout
t
217.36
50
WPmax
MAX16998B
45
55
Watchdog Window
D
%t
WP
WDI
MAX16998D
67.5
75
82.5
WDI to ENABLE Output Delay
Start from WDI third wrong trigger
100
µs
RESET Pullup Resistor Supply
Voltage
(Note 5)
(Note 5)
2.25
2.25
2.5
18.00
28.00
V
V
ENABLE Pullup Resistor Supply
Voltage
2.5
Note 2: R
and R
are external pullup resistors for open-drain outputs. Connect R
and R
to a minimum 2.5V
RESET
ENABLE
RESET
ENABLE
voltage. Connect R
to a maximum voltage of 18V and connect R
to a maximum voltage of 28V.
RESET
ENABLE
Note 3: Calculated based on V
= 1.235V and I
= 500nA.
RAMP
RAMP
Note 4: WDI pulses narrower than 1µs will be ignored. WDI pulses wider than 6.5µs will be recognized.
Note 5: Not production tested, guaranteed by design.
Typical Operating Characteristics
(C
= C
= 1500pF, T = +25°C, unless otherwise noted.)
SRT A
SWT
WATCHDOG TIMEOUT PERIOD
RESET TIMEOUT PERIOD
SUPPLY CURRENT
vs. SUPPLY VOLTAGE
vs. C
vs. C
SWT
SRT
10,000
1000
100
10
10,000
1000
100
10
26
24
22
20
18
16
14
12
10
I = 500nA
RAMP
I
= 500nA
RAMP
RESET AND ENABLE NOT
ASSERTED
1
1
0.1
0.1
1
10
100
1000
0.1
1
10
(nF)
100
1000
0
10
20
30
40
50
C
(nF)
C
SUPPLY VOLTAGE (V)
SWT
SRT
_______________________________________________________________________________________
3
High-Voltage Watchdog Timers with
Adjustable Timeout Delay
Typical Operating Characteristics (continued)
(C
= C
= 1500pF, T = +25°C, unless otherwise noted.)
SWT
SRT
A
SUPPLY CURRENT
vs. TEMPERATURE
RESETIN/EN THRESHOLD VOLTAGE
vs. TEMPERATURE
RESETIN/EN THRESHOLD VOLTAGE
vs. SUPPLY VOLTAGE
20.0
19.5
19.0
18.5
18.0
17.5
17.0
16.5
16.0
15.5
15.0
1.35
1.33
1.30
1.28
1.25
1.23
1.20
1.18
1.15
1.13
1.10
1.50
1.45
1.40
1.35
1.30
1.25
1.20
1.15
1.10
1.05
1.00
RESET AND ENABLE NOT
ASSERTED
RISING
RISING
FALLING
FALLING
-40 -25 -10
5
20 35 50 65 80 95 110 125
TEMPERATURE (°C)
-40 -25 -10
5
20 35 50 65 80 95 110 125
4
8
12 16 20 24 28 32 36 40
SUPPLY VOLTAGE (V)
TEMPERATURE (°C)
7/MAX1698
RESETIN TO RESET DELAY
vs. TEMPERATURE
RESETIN/WATCHDOG PERIOD
vs. SUPPLY VOLTAGE
RESETIN/WATCHDOG PERIOD
vs. SUPPLY VOLTAGE
2.00
1.75
1.50
1.25
1.00
0.75
0.50
0.25
0
8
7
6
5
4
3
2
1
0
110
100
90
80
70
60
50
40
30
20
10
RESETIN FROM 2V TO 0V
100mV OVERDRIVE
WATCHDOG TIMEOUT
WATCHDOG TIMEOUT
PERIOD (C
= 10nF)
SWT
PERIOD (C
= 680pF)
SWT
RESET TIMEOUT
PERIOD (C = 680pF)
SRT
RESET TIMEOUT
50mV OVERDRIVE
PERIOD (C = 10nF)
SRT
-40 -25 -10
5
20 35 50 65 80 95 110 125
TEMPERATURE (°C)
4
8
12 16 20 24 28 32 36 40
SUPPLY VOLTAGE (V)
4
8
12 16 20 24 28 32 36 40
SUPPLY VOLTAGE (V)
I
RESET OUTPUT VOLTAGE
vs. SINK CURRENT
ENABLE OUTPUT VOLTAGE
vs. SINK CURRENT
RAMP
vs. TEMPERATURE
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
520
515
510
505
500
495
490
485
480
475
470
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
0
5
10
15
20
25
30
-40 -25 -10
5
20 35 50 65 80 95 110 125
0
0.5
1.0
1.5
2.0
2.5
3.0
SINK CURRENT (mA)
TEMPERATURE (°C)
SINK CURRENT (mA)
4
_______________________________________________________________________________________
High-Voltage Watchdog Timers with
Adjustable Timeout Delay
7/MAX1698
Pin Description
PIN
NAME
IN
FUNCTION
MAX16997A MAX16998A/B/D
1
1
Power-Supply Input. Bypass IN to GND with a 0.1µF capacitor.
High-Impedance Input to the Enable Comparator. Depending on the voltage level
at EN, the internal watchdog timer is turned on or off (see the EN Input section).
2
—
—
EN
3, 7
N.C.
No Connection. Not internally connected.
Watchdog Timeout Adjustment Input. Connect a capacitor between SWT and GND
to set the basic watchdog timeout period. Connect SWT to ground to disable the
watchdog timer function. See the Selecting the Watchdog Timeout Capacitor
section.
4
5
4
5
SWT
GND
Ground
Watchdog Input.
MAX16997A/MAX16998A (Timeout Watchdog): Two consecutive WDI falling
edges must occur at WDI within the watchdog timeout period or RESET asserts.
The watchdog timer clears when a falling edge occurs on WDI or whenever RESET
is asserted. ENABLE asserts if three consecutive watchdog timeout periods have
expired without a falling edge at WDI. WDI is a high-impedance input. Leaving
WDI unconnected will cause improper operation of the watchdog timer.
MAX16998B/D (Window Watchdog): WDI falling transitions within periods shorter
than the closed window width or longer than the basic watchdog timeout period
force RESET to assert low for the reset timeout period. The watchdog timer begins
to count after RESET is deasserted. The watchdog timer clears when a WDI falling
edge occurs or whenever RESET is asserted. ENABLE asserts if three consecutive
watchdog timeout periods have expired without a falling edge at WDI. WDI is a
high-impedance input. Leaving WDI unconnected will cause improper operation of
the watchdog timer.
6
6
WDI
Open-Drain Enable Output. ENABLE asserts when three consecutive WDI faults
occur. ENABLE remains low until three consecutive good WDI falling edges occur.
ENABLE does not assert if the voltage at RESETIN (EN) is below its threshold.
These devices are guaranteed to be in correct ENABLE output logic state when
8
8
ENABLE
V
remains greater than 1.1V.
IN
Reset Input. High-impedance input to the reset comparator. When V
falls
RESETIN
below 1.235V, RESET asserts. RESET remains asserted as long as V
RESETIN
RESETIN and for the reset timeout period after RESETIN goes high. Connect V
RESETIN
is low
to the
—
—
—
2
3
7
center point of an external resistive divider to set the threshold for the externally
monitored voltage. Connect RESETIN to a defined voltage logic-level.
Reset Timeout Adjustment Input. Connect a capacitor between SRT and GND to
set the reset timeout period. See the Selecting the Reset Timeout Capacitor
section.
SRT
Open-Drain Reset Output. RESET asserts whenever RESETIN drops below the
selected reset threshold voltage (V
). RESET remains low for the reset timeout
PON
RESET
period after all reset conditions are removed, and then goes high. RESET asserts
for a period of t whenever a WDI fault occurs. Connect RESET to a pullup
RESET
resistor connected to a voltage higher than 2.5V (typ).
_______________________________________________________________________________________
5
High-Voltage Watchdog Timers with
Adjustable Timeout Delay
Functional Diagram
IN
MAX16997/MAX16998
PREG
RESET
V
BG
RESETIN (MAX16998)
EN (MAX16997)
WDI
BUFFER
ENABLE
MAX16997A/
MAX16998A/B/D
LOGIC
I
RAMP
7/MAX1698
V
BG
SRT
(MAX16998)
I
RAMP
V
BG
SWT
GND
6
_______________________________________________________________________________________
High-Voltage Watchdog Timers with
Adjustable Timeout Delay
7/MAX1698
Timing Diagrams
V
EN
V
HYST
V
PON
t
WP
t
WD
t
WDI
t
t
t
t
t
t
WDI
t
t
WP
WP
WP
WP
WDI
WDI
WP INITIAL
WDI
1
3
1
2
2
3
ENABLE
t
= WATCHDOG TIMEOUT PERIOD x 8
t
= WATCHDOG TIMEOUT PERIOD
t
= WDI TRIGGER PERIOD
WDI
WP INITIAL
WP
3 CONSECUTIVE t WITHOUT TRIGGER ENABLE GOES LOW
3 CONSECUTIVE WATCHDOG TRIGGER (WDI) ENABLE GOES ACTIVE HIGH
WP
Figure 1. MAX16997A Timing Diagram
V
RESETIN
V
HYST
V
PON
t
t
t
WDI
t
t
t
t
t
WP
WDI
WDI
RESET
WDI
WP
WP
WDI
t
WP
1
3
2
1
2
3
RESET
ENABLE
t
= RESET TIMEOUT PERIOD
t
= WATCHDOG TIMEOUT PERIOD
t
= WDI TRIGGER PERIOD
WDI
RESET
WP
3 CONSECUTIVE RESETS ENABLE GOES ACTIVE LOW
3 CONSECUTIVE WATCHDOG TRIGGER (WDI) ENABLE GOES ACTIVE HIGH
Figure 2. MAX16998A Timing Diagram
_______________________________________________________________________________________
7
High-Voltage Watchdog Timers with
Adjustable Timeout Delay
Timing Diagrams (continued)
V
RESETIN
V
HYST
V
PON
PROPER WATCHDOG TRIGGER RESETS THE INTERNAL ENABLE COUNTER
t
t
t
t
t
t
t
t
t
t
WDI
RESET
OW
WDI
CW
WP
WP
WP
WDI
WDI
WDI
t
WP
1
2
3
1
3
2
RESET
ENABLE
7/MAX1698
t
= RESET TIMEOUT PERIOD
t
= T OPEN WINDOW
t
= T CLOSED WINDOW
t = t + t
WP CW OW
t
= WDI TRIGGER PERIOD
WDI
RESET
OW
CW
3 CONSECUTIVE RESETS ENABLE GOES ACTIVE LOW
3 CONSECUTIVE WATCHDOG TRIGGER (WDI) ENABLE GOES ACTIVE HIGH
Figure 3. MAX16998B/D Timing Diagram
V
RESETIN
V
HYST
V
PON
t
t
t
RESET
RESET
RESET
t
RRDL
RESET
V
= ENABLE
1.1V
IN
t
WP
t
≤ t ≤ t
CW WDI WP
ENABLE DOES NOT GET ASSERTED IF THE VOLTAGE
AT RESETIN IS BELOW ITS THRESHOLD.
t
WDI
t
WDI
t
t
t
t
t
t
WDI WDI WDI WDI WDI WDI
WDI
THE WATCHDOG TIMER CLEARS
WHENEVER RESET IS ASSERTED.
t
≤ t ≤ t
CW WDI WP
t
t
WP
CW
t = 0
t
OW
Figure 4. RESETIN, RESET, V , ENABLE, and WDI Voltage Monitoring
IN
8
_______________________________________________________________________________________
High-Voltage Watchdog Timers with
Adjustable Timeout Delay
7/MAX1698
For the MAX16998A/B/D, RESET asserts whenever
Detailed Description
RESETIN drops below the selected reset threshold volt-
The MAX16997/MAX16998 are µP supervisory circuits
for high-input-voltage and low-quiescent-current appli-
cations. These devices improve system reliability by
monitoring the sub-system for software code execution
errors. The MAX16997A/MAX16998A/B/D detect down-
stream circuit failures, and provide switchover to
redundant circuitry. These devices provide complete
adjustability for reset and watchdog functions.
age (V
). RESET remains low for the reset timeout
PON
period after RESETIN exceeds the selected threshold
voltage, and then goes high.
The MAX16998A asserts RESET for a period of t
RESET
when two consecutive WDI falling edges do not occur
within the adjusted watchdog timeout period. The
MAX16998B/D also assert RESET for a period of t
RESET
when a WDI falling edge does not occur within the
open window period.
The MAX16998A/B/D generate two output signals,
RESET and ENABLE, that depend on the voltage level
at RESETIN and the signal at WDI. RESET asserts
whenever RESETIN drops below the selected reset
threshold voltage. RESET remains low for the reset
timeout period after all reset conditions are deasserted,
and then goes high. RESET also asserts for a period of
Anytime reset asserts, the watchdog timer clears. At
the end of the reset timeout period, RESET goes high,
and the watchdog timer is restarted from zero (see the
Selecting the Watchdog Timeout Capacitor section).
Enable Output (ENABLE)
If the µC fails to operate correctly (e.g., the software
execution is stuck in a loop), WDI does not trigger any
more and RESET pulls low, resetting the µC. If the µC
does not work properly in the next loop either, the
device asserts RESET again. After three watchdog
timeout periods elapse with no falling edges at WDI,
ENABLE asserts and flags a backup circuit that can
take over the operation.
t
whenever a WDI fault occurs. The MAX16997A
RESET
generates one output signal (ENABLE) based on the
voltage level at EN and the signal at WDI.
The MAX16997A/MAX16998A provide watchdog time-
out adjustability with an external capacitor. The
MAX16998A asserts RESET when two consecutive WDI
falling edges do not occur within the watchdog timeout
period. This device also asserts ENABLE if three con-
secutive watchdog timeout periods have elapsed with-
out a falling edge at WDI. ENABLE remains low until
three consecutive good WDI falling edges occur.
ENABLE does not assert if the voltage at RESETIN (EN)
is below its threshold. For the MAX16997A, the watch-
dog timer starts timing if the voltage at EN is higher
than a preset threshold level. Each time the voltage at
EN rises from below to above the preset threshold volt-
age, the initial watchdog timeout period is 8 times the
ENABLE remains low until three consecutive WDI
falling edges with periods shorter than the watchdog
timeout occur. ENABLE does not assert if the voltage at
RESETIN (EN) is below its threshold. These devices are
guaranteed to be in correct ENABLE output logic state
when V remains greater than 1.1V.
IN
Power-On/Power-Off Sequence
Figure 5 shows the power-up and power-down
sequence for RESET and ENABLE for the
MAX16998A/B/D.
normal watchdog timeout period (t ). Other than
WP
described above, the MAX16997A behaves the same
as the MAX16998A.
On power-up, once V reaches 1.1V, RESET goes
IN
The MAX16998B/MAX16998D contain a window watch-
dog timer that looks for activity outside an expected
window of operation. The window size is factory-set to
50% (MAX16998B) or 75% (MAX16998D) of the adjust-
ed watchdog timeout period.
logic-low. As RESETIN rises, RESET remains low. When
RESETIN rises above V , the reset timer starts and
PON
RESET remains low. When the reset timeout period
ends, RESET goes high.
On power-down, once RESETIN goes below V
,
PON
RESET goes low and remains low until V drops below
Reset Output (RESET) (MAX16998A/B/D)
The reset output is typically connected to the reset
input of the µC to start or restart it in a known state. The
MAX16998A/B/D provide an active-low open-drain
reset logic to prevent code execution errors.
IN
1.1V. Figure 6 shows the detailed power-up sequence
for the MAX16998A/B/D.
_______________________________________________________________________________________
9
High-Voltage Watchdog Timers with
Adjustable Timeout Delay
V
IN
V
= 1.1V
IN
V
RESETIN
V
HYST
V
PON
t
RESET
t
RESET
t
t
RESET
RESET
RESET
ENABLE
t
t
t
WP
WP
WP
t
≤ t ≤ t
CW WDI WP
t
t
t
t
t
t
t
t
WDI
WDI WDI WDI WDI WDI WDI
WDI WDI
THE THREE CONSECUTIVE RESET COULD BE CAUSED BY THREE
TIMEOUTS AS SHOWN HERE OR BY THREE WDI FALLING EDGE
OUTSIDE THE OPEN WINDOW, OR A COMBINATION OF ANY RESET
t
≤ t ≤ t
CW WDI WP
t
t
CONDITIONS EXCEPT V
DROPS TOO LOW.
CW
WP
RESETIN
7/MAX1698
t
OW
t = 0
RESET
WDI
WDT CLEARS AND
STARTS COUNTING
FROM O
Figure 5. Power-On Reset and Power-Down Reset for the MAX16998A/B/D
V
= V
ENABLE
IN
V
= 1.1V
IN
V
V
PON
HYST
V
RESETIN
t
RESET
V
RESET
Figure 6. Detailed Power-Up Sequence for the MAX16998A/B/D
10 ______________________________________________________________________________________
High-Voltage Watchdog Timers with
Adjustable Timeout Delay
7/MAX1698
RESETIN Input (MAX16998A/B/D)
V
IN
The MAX16998A/B/D monitor the voltage at RESETIN
using an adjustable reset threshold, set with an external
resistive divider (see Figure 7). RESET asserts when
V
CC
V
is below 1.235V.
RESETIN
MAX16998A/B/D
Use the following equations to calculate the externally
monitored voltage (V ).
R1
R2
CC
RESETIN
⎡
⎢
⎣
⎤
R
1
V
= V
+1
⎥
⎦
TH
PON
R
2
where V
PON
is the desired reset threshold voltage, and
TH
V
= 1.235V. To simplify the resistor selection,
Figure 7. Setting RESETIN Voltage for the MAX16998A/B/D
choose a value for R (< than 1MΩ) and calculate R .
2
1
⎡
⎢
⎣
⎤
V
MAX16998A
TH
R = R
−1
⎥
⎦
1
2
The MAX16998A asserts RESET when two consecutive
V
PON
WDI falling edges do not occur within the adjusted
watchdog timeout period (t ). RESET remains assert-
WP
EN Input
ed for the reset timeout period (t
) and then goes
RESET
The MAX16997A provides a high-impedance input (EN)
to the enable comparator. Based on the voltage level at
EN, the watchdog timer is turned on or off. The watch-
dog timer starts timing if the voltage level at EN is high-
high. This device also asserts ENABLE if three consec-
utive watchdog timeout periods have elapsed without a
falling edge at WDI. ENABLE remains low until three
consecutive WDI falling edges with periods shorter
than the watchdog timeout period occur (see Figure 2).
er than a preset threshold voltage (V
). Each time
PON
the voltage at EN rises from below to above the preset
threshold voltage, the initial watchdog timeout period is
The internal watchdog timer is cleared by a RESET ris-
ing edge or by a falling edge at WDI. The watchdog
timer remains cleared while RESET is asserted; as soon
as RESET is released, the timer starts counting. WDI
falling edges are ignored when RESET is low. If no WDI
falling edge occurs within the watchdog timeout period,
RESET immediately goes low and stays low for the
adjusted reset timeout period.
8 times the normal watchdog timeout period (t ).
WP
Watchdog Timer
MAX16997A
The watchdog circuit monitors the µC’s activity. For the
MAX16997A, the watchdog timer starts timing once the
voltage at EN is higher than a preset threshold voltage.
ENABLE asserts if three consecutive watchdog timeout
periods have elapsed without a falling edge at WDI.
ENABLE remains low until three consecutive WDI falling
edges with periods shorter than the watchdog timeout
period occur.
MAX16998B/D
The MAX16998B/D have a windowed watchdog timer.
The watchdog timeout period (t ) is the sum of a
WP
closed window period (t ) and an open window period
CW
(t ). If the µC issues a WDI falling edge within the open
OW
window period, RESET stays high. Once a WDI falling
edge occurs within the closed window period, RESET
immediately goes low and stays low for the adjusted
reset timeout period (see Figure 3). If no WDI falling
edge occurs within the watchdog timeout period, RESET
immediately goes low and stays low for the adjusted
reset timeout period. The open window size is factory-set
to 50% of the watchdog timeout period for the
MAX16998B and 75% for the MAX16998D.
Each time the voltage at EN rises from below to above
the preset threshold voltage, the first watchdog timeout
period extends by a factor of 8 (8 x t ). If a WDI falling
WP
edge occurs during that time, then the watchdog time-
out period is immediately switched over to a single t
.
WP
If no watchdog falling edge occurs during this pro-
longed watchdog timeout period, ENABLE goes low at
the end of this period and stays low. After this, the first
falling edge at WDI switches the watchdog timeout
period to a single t . See Figure 1. The MAX16997A
WP
Figure 8 shows a WDI falling edge identified as a good or
a bad WDI signal edge. In case 1, the WDI falling edge
occurs within the closed window period and is considered
a bad WDI falling edge (early fault); therefore, it asserts
RESET. Case 2 also shows another fault. In this case, no
watchdog timeout period (t ) is adjustable by a single
WP
capacitor at SWT.
______________________________________________________________________________________ 11
High-Voltage Watchdog Timers with
Adjustable Timeout Delay
WDI falling edge occurs within the watchdog timeout
Leakage currents and stray capacitance (e.g., a scope
period (t ) and is considered a late fault that asserts
WP
probe, which induces both) at SRT may cause errors in
the reset timeout period. If precise time control is
required, use capacitors with low leakage current and
high stability.
RESET. In case 3, the WDI falling edge occurs within the
open window period and is considered a good WDI sig-
nal falling edge. In this case, RESET stays high. In case
4, the WDI falling edge occurs within the indeterminate
region. In this case, the RESET state is indeterminate.
Selecting the Watchdog
Timeout Capacitor
These devices assert ENABLE after three consecutive
bad WDI falling edges. ENABLE returns high after three
consecutive good WDI signal falling edges (see Figure 3).
The watchdog timeout period is adjustable to accom-
modate a variety of µP applications. With this feature,
the watchdog timeout can be optimized for software
execution. The programmer determines how often the
watchdog timer should be serviced. Adjust the watch-
Either a rising edge at RESET or a falling edge at WDI
clears the internal watchdog timer. The watchdog timer
remains cleared while RESET is asserted. The watch-
dog timer begins counting when RESET goes high.
WDI falling edges are ignored when RESET is low.
dog timeout period (t ) by connecting a capacitor
WP
(C
) between SWT and GND. For normal mode
SWT
operation, calculate the watchdog timeout capacitance
using the following equation:
Applications Information
Selecting the Reset Timeout Capacitor
The reset timeout period is adjustable to accommodate a
variety of µP applications. Adjust the reset timeout period
I
RAMP
C
= t
×
SWT
WP
4 × V
RAMP
where V
is in volts, t
is in seconds, I
is in nA,
RAMP
WP
RAMP
7/MAX1698
(t
) by connecting a capacitor (C
) between SRT
RESET
SRT
and C
is in nF. See the Watchdog Timeout Period vs.
SWT
and ground. See the Reset Timeout Period vs. C
SRT
C
graph in the Typical Operating Characteristics.
SWT
graph in the Typical Operating Characteristics. Calculate
the reset timeout capacitance using the equation below:
For the MAX16998B/MAX16998D, the open window size
is factory-set to 50% (MAX16998B) or 75% (MAX16998D)
of the watchdog period. Leakage currents and stray
capacitance (e.g., a scope probe, which induces both) at
SWT may cause errors in the watchdog timeout period. If
precise time control is required, use capacitors with low
leakage current and high stability. To disable the watch-
dog timer function, connect SWT to ground and connect
WDI to either the high- or low-logic state.
I
V
RAMP
C
= t
×
RESET
SRT
RAMP
where V
is in volts, t
is in nF.
is in seconds, I
is
RAMP
RESET
RAMP
in nA, and C
SRT
(50% or 75%) x t
WDImin
WP
t
RESET RISING EDGE
t
t
WP
WDImax
CLOSED WINDOW
INDETERMINATE
OPEN WINDOW
CASE 1 (FAST FAULT)
CASE 2 (SLOW FAULT)
CASE 3 (GOOD WDI)
CASE 4 (INDETERMINATE)
Figure 8. The MAX16998B/D Window Watchdog Diagram
12 ______________________________________________________________________________________
High-Voltage Watchdog Timers with
Adjustable Timeout Delay
7/MAX1698
RESETIN is a high-impedance input and a high-imped-
ance resistive divider (e.g., 100kΩ to 1MΩ) sets the
threshold level. Minimize coupling to transient signals
by keeping the connections to this input short. Any DC
leakage current at RESETIN (e.g., a scope probe)
causes errors in the programmed reset threshold.
Interfacing to Other Voltages for
Logic Compatibility
As shown in Figure 9, the open-drain RESET output can
operate in the 2.5V to 18V range. This allows the device
to interface a µP with other logic levels.
WDI Glitch Immunity
For additional glitch immunity, connect an RC lowpass
filter as close as possible to WDI (see Figure 10).
Typical Operating Circuits
RESET remains asserted as long as RESETIN is below
the regulated voltage and for the reset timeout period
after RESETIN goes high to assure that the monitored
LDO voltage is settled. Then, the µC starts operating
and triggers WDI.
For example, for glitches with duration of 1µs, a 12kΩ
resistor and a 47pF capacitor will provide immunity.
Layout Considerations
SRT and SWT are connected to internal precision cur-
rent sources. When developing the layout for the appli-
cation, minimize stray capacitance attached to SRT
and SWT as well as leakage currents that can reach
those nodes. SRT and SWT traces should be as short
as possible. Route traces carrying high-speed digital
signals and traces with large voltage potentials as far
from SRT and SWT as possible. Leakage currents and
stray capacitance (e.g., a scope probe, which induces
both) at these pins may cause errors in the reset and/or
watchdog timeout period. When evaluating these parts,
use clean prototype boards to ensure accurate reset
and watchdog timeout periods.
If the µC fails to operate correctly (e.g., the software
execution is stuck in a loop), the WDI signal does not
trigger the watchdog timer any more, and RESET is
pulled low, resetting the µC. If the µC does not work
properly in the next loop either, the device asserts
RESET again. After three watchdog timeout periods
with no WDI falling edges, ENABLE asserts and flags
backup or safety circuits that take over the operation.
5V TO 40V
2.5V TO 18V
IN
IN
10kΩ
V
CC
MAX16998A/B/D
V
CC
MAX16998A/B/D
RESET
RESET
R
µP
I/O
WDI
µP
N
C
GND
GND
GND
GND
Figure 10. Additional WDI Glitch Immunity Circuit
Figure 9. Interfacing to Other Voltage Levels
______________________________________________________________________________________ 13
High-Voltage Watchdog Timers with
Adjustable Timeout Delay
V
BATT
IN
SRT
EN
BACKUP CIRCUITRY,
PERIPHERAL
ENABLE
V
CC
5V
REGULATOR
MAX16998A/B/D
V
CC
R1
RESET
WDI
RESET
RESETIN
SWT
µC
R2
I/O
GND
GND
7/MAX1698
Figure 11. MAX16998A/B/D Switch Over to Backup Circuitry
V
BATT
BACKUP
CIRCUITRY FLAGS
IN
BACKUP CIRCUITRY,
PERIPHERAL
ENABLE
5V
V
CC
REGULATOR
MAX16997A
LDO
R1
EN
µC
R2
RESET
SWT
WATCHDOG
5V
I/O
WDI
I/O
GND
GND
SEPARATE
WATCHDOG
Figure 12. MAX16997A Application Diagram
14 ______________________________________________________________________________________
High-Voltage Watchdog Timers with
Adjustable Timeout Delay
7/MAX1698
Pin Configurations
TOP VIEW
+
+
IN
RESETIN
SRT
1
2
3
4
8
7
6
5
ENABLE
RESET
WDI
IN
EN
1
2
3
4
8
7
6
5
ENABLE
N.C.
MAX16998A/B/D
MAX16997A
N.C.
SWT
WDI
SWT
GND
GND
µMAX
µMAX
Package Information
Chip Information
For the latest package outline information and land patterns, go
PROCESS: BiCMOS
to www.maxim-ic.com/packages.
PACKAGE TYPE PACKAGE CODE DOCUMENT NO.
8 µMAX
U8-1
21-0036
______________________________________________________________________________________ 15
High-Voltage Watchdog Timers with
Adjustable Timeout Delay
Revision History
REVISION
NUMBER
REVISION
DATE
PAGES
CHANGED
DESCRIPTION
0
1
2/08
3/09
Initial release
Added bullet to Features section, revised Electrical Characteristics table.
—
1, 2, 3
7/MAX1698
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
16 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2009 Maxim Integrated Products
Maxim is a registered trademark of Maxim Integrated Products, Inc.
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